From patchwork Fri Feb 8 08:08:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 157812 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1664479jaa; Fri, 8 Feb 2019 00:10:41 -0800 (PST) X-Google-Smtp-Source: AHgI3IYYxMizpaSJyHqD8+XccHEzulIEaM4UUCme+hh/0Gx/qyvvh5iWTTH6aSf9ZIIfKyo/ibxK X-Received: by 2002:a62:5910:: with SMTP id n16mr20693106pfb.128.1549613441591; Fri, 08 Feb 2019 00:10:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549613441; cv=none; d=google.com; s=arc-20160816; b=ec+FxatIhowB2CdNsAcPNZKdMxTCmD6sKJM/pY6Dmj4U6FORezAKcYhMTi8ktioz4U HOJsTsgwo+/hjrTkM/C9I5EwL9tj+Phb9ulzFrAvm2o8qovqaWJ2lVVRh77wVUUHRCu+ HsAmkUbNYRx9R21kktN1ttXzO86oUpY4iytq1DHNGZmHA1SCciE76JQfVSq+km5EdP/2 +PensQ9WHuWu/vnreV7PdRltjQt/6g7QvARb4UB/9qwVWF0Z4QAdcjCN98DaTpim1Pec 1DSQR4hho8DeFsjlJiodtiyaL4vd+3a6lw568MtbhKA4s5VMpTUU2tTGqVx8CGDtydL7 m+pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=fsbAy+mNjv6UN7W3uZeIwWQhvQaZQGjUQy8lvIRZ8wo=; b=b83vHpJXWfIrOQVWnFr22p/mB025UoqaHUXFrZy6NnJSZohLCFdPD/GJu7ADOafqLK 0Ku9UFMnMiYpunZnVr+KeztU58S0N/3NX/M7E08U+hNpXjag9B9SqOtOIqVZqn6Fa29m WBEfxhzptEbRpcOBFmzYcZlU1mUpZIYUi2YsyetDbLB+WCvJOT8HegX6cAt5kG53/WmB OjQy2NySK4+++RxQyim8JVXu2J0u+Qp9J92vWg60aiLpwUvrrQaBxsN6O3WdAPqqKpPc l2D3/ol5hsSb9V7Apz5STioQZm7UGeQiPvWXwE7/SnpX3tvzjrBcRVWYY8YRnSmXWO14 Mo5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=tP1BdhGb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o61si1643307pld.246.2019.02.08.00.10.41; Fri, 08 Feb 2019 00:10:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=tP1BdhGb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727297AbfBHIKP (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:15 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:61678 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726915AbfBHIKO (ORCPT ); Fri, 8 Feb 2019 03:10:14 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902B007241; Fri, 8 Feb 2019 17:09:03 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902B007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613343; bh=fsbAy+mNjv6UN7W3uZeIwWQhvQaZQGjUQy8lvIRZ8wo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tP1BdhGbS/YxDLaXdHvSFTkuNrMLLO44by59iKNGytXi8IS3q1WwIpgOnwD7yBDTv /rLfbVwoMhuN2+7X0rHSAQIQDbjHR6tbfwFTGe1KHxEr9c6y5Tumim8DETob9Odwf/ Nheg4xKXyGaGh5+kd+mGZzvjZL/gyJeTAzh15VnSpKB2l8IUx5EuFpsZ/HQUrv1Kvw oaaMtSEJDWkg4p9x7C9N0hJiEd7AaPlByl5h9aLnbxThYBs3+6G5EOx8yq+482kbgT PwFKQI/kLBv4s1bsnRUHG9HBXAWiLhaisJLA3YCvbOTd3QDJ2jSpksFbi27MR8h7UM /XfU/3bfoLmpw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH 02/11] mtd: rawnand: denali: refactor syndrome layout handling for raw access Date: Fri, 8 Feb 2019 17:08:46 +0900 Message-Id: <1549613335-30319-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Denali IP adopts the syndrome page layout (payload and ECC are interleaved). The *_page_raw() and *_oob() callbacks are complicated because they must hide the underlying layout used by the hardware, and always return contiguous in-band and out-of-band data. Currently, similar code is duplicated to reorganize the data layout. For example, denali_read_page_raw() and denali_write_page_raw() look almost the same. The idea for refactoring is to split the code into two parts: [1] conversion of page layout [2] what to do at every ECC chunk boundary For [1], I wrote denali_raw_payload_op() and denali_raw_oob_op(). They manipulate data for the Denali controller's specific page layout of in-band, out-of-band, respectively. The difference between write and read is just the operation at ECC chunk boundaries. For example, denali_read_oob() calls nand_change_read_column_op(), whereas denali_write_oob() calls nand_change_write_column_op(). So, I implemented [2] as a callback passed into [1]. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 354 +++++++++++++++++++----------------------- 1 file changed, 163 insertions(+), 191 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 4ac1314..9287f4f 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -608,159 +608,210 @@ static int denali_data_xfer(struct nand_chip *chip, void *buf, size_t size, return denali_pio_xfer(denali, buf, size, page, write); } -static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip, - int page, int write) +typedef int denali_change_column_callback(void *buf, unsigned int offset, + unsigned int len, void *priv); + +static int denali_raw_payload_op(struct nand_chip *chip, void *buf, + denali_change_column_callback *cb, void *priv) { - struct denali_nand_info *denali = mtd_to_denali(mtd); + struct denali_nand_info *denali = to_denali(chip); + struct mtd_info *mtd = nand_to_mtd(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int writesize = mtd->writesize; + int oob_skip = denali->oob_skip_bytes; + int ret, i, pos, len; + + for (i = 0; i < ecc->steps; i++) { + pos = i * (ecc->size + ecc->bytes); + len = ecc->size; + + if (pos >= writesize) { + pos += oob_skip; + } else if (pos + len > writesize) { + /* This chunk overwraps the BBM area. Must be split */ + ret = cb(buf, pos, writesize - pos, priv); + if (ret) + return ret; + + buf += writesize - pos; + len -= writesize - pos; + pos = writesize + oob_skip; + } + + ret = cb(buf, pos, len, priv); + if (ret) + return ret; + + buf += len; + } + + return 0; +} + +static int denali_raw_oob_op(struct nand_chip *chip, void *buf, + denali_change_column_callback *cb, void *priv) +{ + struct denali_nand_info *denali = to_denali(chip); + struct mtd_info *mtd = nand_to_mtd(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; int writesize = mtd->writesize; int oobsize = mtd->oobsize; - uint8_t *bufpoi = chip->oob_poi; - int ecc_steps = chip->ecc.steps; - int ecc_size = chip->ecc.size; - int ecc_bytes = chip->ecc.bytes; int oob_skip = denali->oob_skip_bytes; - size_t size = writesize + oobsize; - int i, pos, len; + int ret, i, pos, len; /* BBM at the beginning of the OOB area */ - if (write) - nand_prog_page_begin_op(chip, page, writesize, bufpoi, - oob_skip); - else - nand_read_page_op(chip, page, writesize, bufpoi, oob_skip); - bufpoi += oob_skip; + ret = cb(buf, writesize, oob_skip, priv); + if (ret) + return ret; - /* OOB ECC */ - for (i = 0; i < ecc_steps; i++) { - pos = ecc_size + i * (ecc_size + ecc_bytes); - len = ecc_bytes; + buf += oob_skip; - if (pos >= writesize) - pos += oob_skip; - else if (pos + len > writesize) - len = writesize - pos; + for (i = 0; i < ecc->steps; i++) { + pos = ecc->size + i * (ecc->size + ecc->bytes); - if (write) - nand_change_write_column_op(chip, pos, bufpoi, len, - false); + if (i == ecc->steps - 1) + /* The last chunk includes OOB free */ + len = writesize + oobsize - pos - oob_skip; else - nand_change_read_column_op(chip, pos, bufpoi, len, - false); - bufpoi += len; - if (len < ecc_bytes) { - len = ecc_bytes - len; - if (write) - nand_change_write_column_op(chip, writesize + - oob_skip, bufpoi, - len, false); - else - nand_change_read_column_op(chip, writesize + - oob_skip, bufpoi, - len, false); - bufpoi += len; + len = ecc->bytes; + + if (pos >= writesize) { + pos += oob_skip; + } else if (pos + len > writesize) { + /* This chunk overwraps the BBM area. Must be split */ + ret = cb(buf, pos, writesize - pos, priv); + if (ret) + return ret; + + buf += writesize - pos; + len -= writesize - pos; + pos = writesize + oob_skip; } + + ret = cb(buf, pos, len, priv); + if (ret) + return ret; + + buf += len; } - /* OOB free */ - len = oobsize - (bufpoi - chip->oob_poi); - if (write) - nand_change_write_column_op(chip, size - len, bufpoi, len, - false); - else - nand_change_read_column_op(chip, size - len, bufpoi, len, - false); + return 0; +} + +static int denali_memcpy_in(void *buf, unsigned int offset, unsigned int len, + void *priv) +{ + memcpy(buf, priv + offset, len); + return 0; } static int denali_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { + struct denali_nand_info *denali = to_denali(chip); struct mtd_info *mtd = nand_to_mtd(chip); - struct denali_nand_info *denali = mtd_to_denali(mtd); - int writesize = mtd->writesize; - int oobsize = mtd->oobsize; - int ecc_steps = chip->ecc.steps; - int ecc_size = chip->ecc.size; - int ecc_bytes = chip->ecc.bytes; void *tmp_buf = denali->buf; - int oob_skip = denali->oob_skip_bytes; - size_t size = writesize + oobsize; - int ret, i, pos, len; + size_t size = mtd->writesize + mtd->oobsize; + int ret; + + if (!buf) + return -EINVAL; ret = denali_data_xfer(chip, tmp_buf, size, page, 1, 0); if (ret) return ret; - /* Arrange the buffer for syndrome payload/ecc layout */ - if (buf) { - for (i = 0; i < ecc_steps; i++) { - pos = i * (ecc_size + ecc_bytes); - len = ecc_size; - - if (pos >= writesize) - pos += oob_skip; - else if (pos + len > writesize) - len = writesize - pos; - - memcpy(buf, tmp_buf + pos, len); - buf += len; - if (len < ecc_size) { - len = ecc_size - len; - memcpy(buf, tmp_buf + writesize + oob_skip, - len); - buf += len; - } - } - } + ret = denali_raw_payload_op(chip, buf, denali_memcpy_in, tmp_buf); + if (ret) + return ret; if (oob_required) { - uint8_t *oob = chip->oob_poi; - - /* BBM at the beginning of the OOB area */ - memcpy(oob, tmp_buf + writesize, oob_skip); - oob += oob_skip; - - /* OOB ECC */ - for (i = 0; i < ecc_steps; i++) { - pos = ecc_size + i * (ecc_size + ecc_bytes); - len = ecc_bytes; - - if (pos >= writesize) - pos += oob_skip; - else if (pos + len > writesize) - len = writesize - pos; - - memcpy(oob, tmp_buf + pos, len); - oob += len; - if (len < ecc_bytes) { - len = ecc_bytes - len; - memcpy(oob, tmp_buf + writesize + oob_skip, - len); - oob += len; - } - } - - /* OOB free */ - len = oobsize - (oob - chip->oob_poi); - memcpy(oob, tmp_buf + size - len, len); + ret = denali_raw_oob_op(chip, chip->oob_poi, denali_memcpy_in, + tmp_buf); + if (ret) + return ret; } return 0; } -static int denali_read_oob(struct nand_chip *chip, int page) +static int denali_memcpy_out(void *buf, unsigned int offset, unsigned int len, + void *priv) +{ + memcpy(priv + offset, buf, len); + return 0; +} + +static int denali_write_page_raw(struct nand_chip *chip, const uint8_t *buf, + int oob_required, int page) { + struct denali_nand_info *denali = to_denali(chip); struct mtd_info *mtd = nand_to_mtd(chip); + void *tmp_buf = denali->buf; + size_t size = mtd->writesize + mtd->oobsize; + int ret; - denali_oob_xfer(mtd, chip, page, 0); + if (!buf) + return -EINVAL; - return 0; + /* + * Fill the buffer with 0xff first except the full page transfer. + * This simplifies the logic. + */ + if (!oob_required) + memset(tmp_buf, 0xff, size); + + ret = denali_raw_payload_op(chip, (void *)buf, denali_memcpy_out, + tmp_buf); + if (ret) + return ret; + + if (oob_required) { + ret = denali_raw_oob_op(chip, chip->oob_poi, denali_memcpy_out, + tmp_buf); + if (ret) + return ret; + } + + return denali_data_xfer(chip, tmp_buf, size, page, 1, 1); +} + +static int denali_change_read_column_op(void *buf, unsigned int offset, + unsigned int len, void *priv) +{ + return nand_change_read_column_op(priv, offset, buf, len, false); +} + +static int denali_read_oob(struct nand_chip *chip, int page) +{ + int ret; + + ret = nand_read_page_op(chip, page, 0, NULL, 0); + if (ret) + return ret; + + return denali_raw_oob_op(chip, chip->oob_poi, + denali_change_read_column_op, chip); +} + +static int denali_change_write_column_op(void *buf, unsigned int offset, + unsigned int len, void *priv) +{ + return nand_change_write_column_op(priv, offset, buf, len, false); } static int denali_write_oob(struct nand_chip *chip, int page) { - struct mtd_info *mtd = nand_to_mtd(chip); + int ret; - denali_oob_xfer(mtd, chip, page, 1); + ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); + if (ret) + return ret; + + ret = denali_raw_oob_op(chip, chip->oob_poi, + denali_change_write_column_op, chip); + if (ret) + return ret; return nand_prog_page_end_op(chip); } @@ -798,85 +849,6 @@ static int denali_read_page(struct nand_chip *chip, uint8_t *buf, return stat; } -static int denali_write_page_raw(struct nand_chip *chip, const uint8_t *buf, - int oob_required, int page) -{ - struct mtd_info *mtd = nand_to_mtd(chip); - struct denali_nand_info *denali = mtd_to_denali(mtd); - int writesize = mtd->writesize; - int oobsize = mtd->oobsize; - int ecc_steps = chip->ecc.steps; - int ecc_size = chip->ecc.size; - int ecc_bytes = chip->ecc.bytes; - void *tmp_buf = denali->buf; - int oob_skip = denali->oob_skip_bytes; - size_t size = writesize + oobsize; - int i, pos, len; - - /* - * Fill the buffer with 0xff first except the full page transfer. - * This simplifies the logic. - */ - if (!buf || !oob_required) - memset(tmp_buf, 0xff, size); - - /* Arrange the buffer for syndrome payload/ecc layout */ - if (buf) { - for (i = 0; i < ecc_steps; i++) { - pos = i * (ecc_size + ecc_bytes); - len = ecc_size; - - if (pos >= writesize) - pos += oob_skip; - else if (pos + len > writesize) - len = writesize - pos; - - memcpy(tmp_buf + pos, buf, len); - buf += len; - if (len < ecc_size) { - len = ecc_size - len; - memcpy(tmp_buf + writesize + oob_skip, buf, - len); - buf += len; - } - } - } - - if (oob_required) { - const uint8_t *oob = chip->oob_poi; - - /* BBM at the beginning of the OOB area */ - memcpy(tmp_buf + writesize, oob, oob_skip); - oob += oob_skip; - - /* OOB ECC */ - for (i = 0; i < ecc_steps; i++) { - pos = ecc_size + i * (ecc_size + ecc_bytes); - len = ecc_bytes; - - if (pos >= writesize) - pos += oob_skip; - else if (pos + len > writesize) - len = writesize - pos; - - memcpy(tmp_buf + pos, oob, len); - oob += len; - if (len < ecc_bytes) { - len = ecc_bytes - len; - memcpy(tmp_buf + writesize + oob_skip, oob, - len); - oob += len; - } - } - - /* OOB free */ - len = oobsize - (oob - chip->oob_poi); - memcpy(tmp_buf + size - len, oob, len); - } - - return denali_data_xfer(chip, tmp_buf, size, page, 1, 1); -} - static int denali_write_page(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page) { From patchwork Fri Feb 8 08:08:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 157811 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1664237jaa; Fri, 8 Feb 2019 00:10:26 -0800 (PST) X-Google-Smtp-Source: AHgI3IbSMCrTuiuzdX7TuZS0ohKyDu9buItSgnDIoOqHyBibdB3aPrMWT8lD9BQHStR1ZNCXPhMa X-Received: by 2002:a65:4807:: with SMTP id h7mr2738505pgs.15.1549613426043; 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[209.132.180.67]) by mx.google.com with ESMTP id d25si1600302pgd.88.2019.02.08.00.10.25; Fri, 08 Feb 2019 00:10:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=olVwhAsp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727383AbfBHIKY (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:24 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:61726 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727174AbfBHIKP (ORCPT ); Fri, 8 Feb 2019 03:10:15 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902E007241; Fri, 8 Feb 2019 17:09:05 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902E007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613346; bh=FWcCJjEq8f/6i4xahnidBxZk+rUMKWgh+Bly4jpfp0o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=olVwhAspSguC9wwqWq2B51Gt4JLcqpKdPCzHgVByZ+2JUdyZPlxBB/hDLea1kytp6 FstQkB/ReKmGXLuxencnsxsS6T+Pfg2JBxsuupXK41Ev+IsO/QpzW8b0Q9oBMbR4Sg ZM91WfyHzKNzgDLuHp2pHbck9rAIfXwtbMoNa6tTyzDtFChq/hRcsCHNPfb33cuZDb glULfOnRdlUbYDSAQJ0agDI92GfLAVRUp081RrhouPZpJ4D0/SOdaEmNdzzh3cfI3r rzEb2EWRyD7XNCZPwkG/pI8EzHmUDI2pIn9YrOKNylY10xz41HaPM1+307KZgxa/qD 9En1x9qqcBnmA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH 05/11] mtd: rawnand: denali: rename irq_status to irq_stat Date: Fri, 8 Feb 2019 17:08:49 +0900 Message-Id: <1549613335-30319-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I will add the third argument to denali_wait_for_irq() in the following commit. Then, some lines will exceed 80 columns. Rename 'irq_status' to 'irq_stat'. Saving two characters will avoid line-wrapping in some places, and keep the code clean. I replaced uint32_t with u32 in the touched lines. This will reduce the reports from 'scripts/checkpatch.pl --strict'. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 60 +++++++++++++++++++++---------------------- drivers/mtd/nand/raw/denali.h | 4 +-- 2 files changed, 32 insertions(+), 32 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index bd7df25..9e63cbd 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -121,10 +121,10 @@ static void denali_disable_irq(struct denali_nand_info *denali) } static void denali_clear_irq(struct denali_nand_info *denali, - int bank, uint32_t irq_status) + int bank, u32 irq_stat) { /* write one to clear bits */ - iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); + iowrite32(irq_stat, denali->reg + INTR_STATUS(bank)); } static void denali_clear_irq_all(struct denali_nand_info *denali) @@ -139,24 +139,24 @@ static irqreturn_t denali_isr(int irq, void *dev_id) { struct denali_nand_info *denali = dev_id; irqreturn_t ret = IRQ_NONE; - uint32_t irq_status; + u32 irq_stat; int i; spin_lock(&denali->irq_lock); for (i = 0; i < DENALI_NR_BANKS; i++) { - irq_status = ioread32(denali->reg + INTR_STATUS(i)); - if (irq_status) + irq_stat = ioread32(denali->reg + INTR_STATUS(i)); + if (irq_stat) ret = IRQ_HANDLED; - denali_clear_irq(denali, i, irq_status); + denali_clear_irq(denali, i, irq_stat); if (i != denali->active_bank) continue; - denali->irq_status |= irq_status; + denali->irq_stat |= irq_stat; - if (denali->irq_status & denali->irq_mask) + if (denali->irq_stat & denali->irq_mask) complete(&denali->complete); } @@ -170,7 +170,7 @@ static void denali_reset_irq(struct denali_nand_info *denali) unsigned long flags; spin_lock_irqsave(&denali->irq_lock, flags); - denali->irq_status = 0; + denali->irq_stat = 0; denali->irq_mask = 0; spin_unlock_irqrestore(&denali->irq_lock, flags); } @@ -179,16 +179,16 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) { unsigned long time_left, flags; - uint32_t irq_status; + u32 irq_stat; spin_lock_irqsave(&denali->irq_lock, flags); - irq_status = denali->irq_status; + irq_stat = denali->irq_stat; - if (irq_mask & irq_status) { + if (irq_mask & irq_stat) { /* return immediately if the IRQ has already happened. */ spin_unlock_irqrestore(&denali->irq_lock, flags); - return irq_status; + return irq_stat; } denali->irq_mask = irq_mask; @@ -203,7 +203,7 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, return 0; } - return denali->irq_status; + return denali->irq_stat; } static void denali_select_target(struct nand_chip *chip, int cs) @@ -294,7 +294,7 @@ static int denali_sw_ecc_fixup(struct nand_chip *chip, unsigned int err_byte, err_sector, err_device; uint8_t err_cor_value; unsigned int prev_sector = 0; - uint32_t irq_status; + u32 irq_stat; denali_reset_irq(denali); @@ -349,8 +349,8 @@ static int denali_sw_ecc_fixup(struct nand_chip *chip, * Once handle all ECC errors, controller will trigger an * ECC_TRANSACTION_DONE interrupt. */ - irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); - if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) + irq_stat = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); + if (!(irq_stat & INTR__ECC_TRANSACTION_DONE)) return -EIO; return max_bitflips; @@ -408,7 +408,7 @@ static int denali_pio_read(struct denali_nand_info *denali, u32 *buf, size_t size, int page) { u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; - uint32_t irq_status, ecc_err_mask; + u32 irq_stat, ecc_err_mask; int i; if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) @@ -421,21 +421,21 @@ static int denali_pio_read(struct denali_nand_info *denali, u32 *buf, for (i = 0; i < size / 4; i++) buf[i] = denali->host_read(denali, addr); - irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); - if (!(irq_status & INTR__PAGE_XFER_INC)) + irq_stat = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); + if (!(irq_stat & INTR__PAGE_XFER_INC)) return -EIO; - if (irq_status & INTR__ERASED_PAGE) + if (irq_stat & INTR__ERASED_PAGE) memset(buf, 0xff, size); - return irq_status & ecc_err_mask ? -EBADMSG : 0; + return irq_stat & ecc_err_mask ? -EBADMSG : 0; } static int denali_pio_write(struct denali_nand_info *denali, const u32 *buf, size_t size, int page) { u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; - uint32_t irq_status; + u32 irq_stat; int i; denali_reset_irq(denali); @@ -443,9 +443,9 @@ static int denali_pio_write(struct denali_nand_info *denali, const u32 *buf, for (i = 0; i < size / 4; i++) denali->host_write(denali, addr, buf[i]); - irq_status = denali_wait_for_irq(denali, + irq_stat = denali_wait_for_irq(denali, INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); - if (!(irq_status & INTR__PROGRAM_COMP)) + if (!(irq_stat & INTR__PROGRAM_COMP)) return -EIO; return 0; @@ -464,7 +464,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, size_t size, int page, int write) { dma_addr_t dma_addr; - uint32_t irq_mask, irq_status, ecc_err_mask; + u32 irq_mask, irq_stat, ecc_err_mask; enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; int ret = 0; @@ -501,17 +501,17 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, denali_reset_irq(denali); denali->setup_dma(denali, dma_addr, page, write); - irq_status = denali_wait_for_irq(denali, irq_mask); - if (!(irq_status & INTR__DMA_CMD_COMP)) + irq_stat = denali_wait_for_irq(denali, irq_mask); + if (!(irq_stat & INTR__DMA_CMD_COMP)) ret = -EIO; - else if (irq_status & ecc_err_mask) + else if (irq_stat & ecc_err_mask) ret = -EBADMSG; iowrite32(0, denali->reg + DMA_ENABLE); dma_unmap_single(denali->dev, dma_addr, size, dir); - if (irq_status & INTR__ERASED_PAGE) + if (irq_stat & INTR__ERASED_PAGE) memset(buf, 0xff, size); return ret; diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index c8c2620..46296f2 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -299,9 +299,9 @@ struct denali_nand_info { void __iomem *reg; /* Register Interface */ void __iomem *host; /* Host Data/Command Interface */ struct completion complete; - spinlock_t irq_lock; /* protect irq_mask and irq_status */ + spinlock_t irq_lock; /* protect irq_mask and irq_stat */ u32 irq_mask; /* interrupts we are waiting for */ - u32 irq_status; /* interrupts that have happened */ + u32 irq_stat; /* interrupts that have happened */ int irq; void *buf; /* for syndrome layout conversion */ int dma_avail; /* can support DMA? */ From patchwork Fri Feb 8 08:08:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 157810 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1664187jaa; Fri, 8 Feb 2019 00:10:22 -0800 (PST) X-Google-Smtp-Source: AHgI3IZTaIDKDoIqbhRsX462+FhBjxEGhsiyCb6FkA72pLjQbkFwwneJM34OKBEQ8Xlo/ojp80mZ X-Received: by 2002:a17:902:8e8b:: with SMTP id bg11mr21658140plb.332.1549613422853; Fri, 08 Feb 2019 00:10:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549613422; cv=none; d=google.com; s=arc-20160816; b=L3PpwBADRU/ib2lCGLaN9eE1SNRB9xlg484Tpw3VzFRtyEblyjawro81ZcQk49kggu gO8RjAT/+J+y8s/znXxlI7gdB6q0wQNzJXM8A/jluszPVedVpDv2PmrhDeanXxmTXRXA GcOKUU9SnonpBy/Ioizn7DoQ85XR8WNFImUV6Ib1Y0XZq6SjFVkcEUhwOfHljEL4U0G8 fQ5zW6yd2fVM/MzVgIhFYTQQ7YadNP5A3rXTMzVcq/qK5Q88BmB/xkXarDmwgXRLzW79 Iqj+uXetu0IUqH5ovL030RZ83j5LDWkNOr+a2bIgYq7SpN/PGZBAWuFHKl3gi5VXQdle KtoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=ws0rfNY0AqZ3Gauy1XWKRiE8n2TnorcpmKdkHThTkHk=; b=juyeoKq5z0rPX01EMLKtSBa2/Egw2xMsJ/WmkIzufVQ1v6pJE9oFq3nkoWzMErJB+Z GacY1ur0y6xqxAqI7yJ5AxsW5Z6h69tnaJW/z5VNCpk45UL6r5TzIBkj48HGKvF9t3IO tDKZLLJw+tNOgZ1KxQsVRK5GTP+B0ZznowkEHogfQaK3No6HCNGjHfMmUmYujXsmK5ux 7u8iC3wPlLuJZIHHmbqceRtlb13lLkqSazj/l4sV2/2NHItoZOqeCQ/+6GTzzq9pyl6c LoMdINESpTSMIzWabkbciQFS8RlKHsKqlK5MQg8zcfisRYOO85L0tovt1oG1cySpr+VQ 3n8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=rxsLx+JI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n10si1587962pgd.57.2019.02.08.00.10.22; Fri, 08 Feb 2019 00:10:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=rxsLx+JI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727361AbfBHIKU (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:20 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:61757 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727247AbfBHIKP (ORCPT ); Fri, 8 Feb 2019 03:10:15 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902G007241; Fri, 8 Feb 2019 17:09:07 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902G007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613348; bh=ws0rfNY0AqZ3Gauy1XWKRiE8n2TnorcpmKdkHThTkHk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rxsLx+JIjfJicShCqTX0Jz73s0MTfV43OGVjEN4xxS3ctswj6f/NpiPw3bhGSGNsw OChqCR/uuJlonTMWoFBMoAKk9uFI9VKLvpVBry9k/jGBUyW3ToogsnoaTsG+8rgCEk YsOaI6P6t5QuceXjJc+2Dyl+QBTEy/nVbVDkQO3VSC26/X77KZD3TwwcBULD2u6vhd RbPQOX69zuiDbQqVM/I+I2/lo+Qmhpev/9XVCIruTOrbumYeKIqIk244Uv73NbIrsp FW3V6kb+Xn19LYaCbFj6jZkNYDnc6cKmiPhjDwnwcP4CF2CMQupAxo7efjRZsU8ywI nBp5rN7aGhYkA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH 07/11] mtd: rawnand: denali: use bool type instead of int where appropriate Date: Fri, 8 Feb 2019 17:08:51 +0900 Message-Id: <1549613335-30319-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use 'bool' type for some function arguments. - write (write or read?) - raw (the raw access mode or not?) It is true that denali_nand_info::dma_avail is also boolean, but I am keeping it as 'int' because 'scripts/checkpatch --strict' would report the following: CHECK: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 I do not think it is a matter here, but I am sticking to the suggestion. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 23 ++++++++++++----------- drivers/mtd/nand/raw/denali.h | 2 +- 2 files changed, 13 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 514d189..748711e 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -357,7 +357,7 @@ static int denali_sw_ecc_fixup(struct nand_chip *chip, } static void denali_setup_dma64(struct denali_nand_info *denali, - dma_addr_t dma_addr, int page, int write) + dma_addr_t dma_addr, int page, bool write) { uint32_t mode; const int page_count = 1; @@ -371,7 +371,8 @@ static void denali_setup_dma64(struct denali_nand_info *denali, * burst len = 64 bytes, the number of pages */ denali->host_write(denali, mode, - 0x01002000 | (64 << 16) | (write << 8) | page_count); + 0x01002000 | (64 << 16) | + (write ? BIT(8) : 0) | page_count); /* 2. set memory low address */ denali->host_write(denali, mode, lower_32_bits(dma_addr)); @@ -381,7 +382,7 @@ static void denali_setup_dma64(struct denali_nand_info *denali, } static void denali_setup_dma32(struct denali_nand_info *denali, - dma_addr_t dma_addr, int page, int write) + dma_addr_t dma_addr, int page, bool write) { uint32_t mode; const int page_count = 1; @@ -392,7 +393,7 @@ static void denali_setup_dma32(struct denali_nand_info *denali, /* 1. setup transfer type and # of pages */ denali->host_write(denali, mode | page, - 0x2000 | (write << 8) | page_count); + 0x2000 | (write ? BIT(8) : 0) | page_count); /* 2. set memory high address bits 23:8 */ denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); @@ -453,7 +454,7 @@ static int denali_pio_write(struct denali_nand_info *denali, const u32 *buf, } static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, - size_t size, int page, int write) + size_t size, int page, bool write) { if (write) return denali_pio_write(denali, buf, size, page); @@ -462,7 +463,7 @@ static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, } static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, - size_t size, int page, int write) + size_t size, int page, bool write) { dma_addr_t dma_addr; u32 irq_mask, irq_stat, ecc_err_mask; @@ -519,7 +520,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, } static int denali_data_xfer(struct nand_chip *chip, void *buf, size_t size, - int page, int raw, int write) + int page, bool raw, bool write) { struct denali_nand_info *denali = to_denali(chip); @@ -644,7 +645,7 @@ static int denali_read_page_raw(struct nand_chip *chip, uint8_t *buf, if (!buf) return -EINVAL; - ret = denali_data_xfer(chip, tmp_buf, size, page, 1, 0); + ret = denali_data_xfer(chip, tmp_buf, size, page, true, false); if (ret) return ret; @@ -700,7 +701,7 @@ static int denali_write_page_raw(struct nand_chip *chip, const uint8_t *buf, return ret; } - return denali_data_xfer(chip, tmp_buf, size, page, 1, 1); + return denali_data_xfer(chip, tmp_buf, size, page, true, true); } static int denali_change_read_column_op(void *buf, unsigned int offset, @@ -752,7 +753,7 @@ static int denali_read_page(struct nand_chip *chip, uint8_t *buf, int stat = 0; int ret; - ret = denali_data_xfer(chip, buf, mtd->writesize, page, 0, 0); + ret = denali_data_xfer(chip, buf, mtd->writesize, page, false, false); if (ret && ret != -EBADMSG) return ret; @@ -782,7 +783,7 @@ static int denali_write_page(struct nand_chip *chip, const uint8_t *buf, struct mtd_info *mtd = nand_to_mtd(chip); return denali_data_xfer(chip, (void *)buf, mtd->writesize, page, - 0, 1); + false, true); } static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 46296f2..8e91438 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -314,7 +314,7 @@ struct denali_nand_info { u32 (*host_read)(struct denali_nand_info *denali, u32 addr); void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, - int page, int write); + int page, bool write); }; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) From patchwork Fri Feb 8 08:08:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 157815 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1664642jaa; Fri, 8 Feb 2019 00:10:54 -0800 (PST) X-Google-Smtp-Source: AHgI3IaEdAfDJFk6iqu811jRc5Z9fZ0aAaVsz/Dnl5iahMh6WmEodJjKoP6MeTfUuUv8Owlq9csJ X-Received: by 2002:a17:902:8643:: with SMTP id y3mr8728297plt.80.1549613454054; Fri, 08 Feb 2019 00:10:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549613454; cv=none; d=google.com; s=arc-20160816; b=gFGcvEOLkdkQx2rrlNhuMYo8ZQy7Q+ly5o3omIqDBeptFae9bCLoPBBYUKu9yBLr13 5mKJdD34mKdk5Jd/edc40A8g+auKX78coF4aQOwlgoYu4yIuLEjpMd/1l/znTvCbvzEv bmgavIrCKVyokVde+bguAQ6brpk0ugPEsZUObXt/4SicSCD+7xfQtCd3qmPebSVzDjxB J9M7U+DEjh8yndkef9jqqwN/NkiLrcFVDK1L8jzPaxOgKGCvqp5MYZ8xDh36F34qyiFp 1VTtHJEPcnZGrlU0zR3sG/OAdzFbxAxQdlDNbV3bqHEc20PVOl80zGL5R2L60Ci94zc2 OoSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=mmmNIad85Z00UT/gAne8xw5tDTiobUiwOXN0ahE1tag=; b=AvzXzUud3rVYRWKvv1kZ1ghOCItAo6p2c6rBlumLnrzAQYhYwmC9k+rg7AsJfRgZPt 1Ft1GWYBzsegoOSRZM+gdaXB+sDGGMbQJF9e0LG9vlCwU9+A5ZsnB91XpuBv1fCDIt5j FXL+h6h2N0KoZXP45klhobO13X/HN2ftO8d8c8Kooaf8BbJCAxI0XhJiLX2fM1zNAvGq zUYoRBW1Q5IiXT0bP/BNXxFqWhXOjWhQfHGKusGPq90Ar0v/RsfB2hsdiMNcWoeWjZA0 E/nnoUCVpE5E2OBv5NaYUeMetibAre8E9XwiWpd2FFnLekNkDTw7o0GAcJlPiaASCWCH LKig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=P2+WA9+4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g10si1547771plq.371.2019.02.08.00.10.53; Fri, 08 Feb 2019 00:10:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=P2+WA9+4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727491AbfBHIKw (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:52 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:62750 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727442AbfBHIKr (ORCPT ); Fri, 8 Feb 2019 03:10:47 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902H007241; Fri, 8 Feb 2019 17:09:08 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902H007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613349; bh=mmmNIad85Z00UT/gAne8xw5tDTiobUiwOXN0ahE1tag=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P2+WA9+4GBQPvmz7S5k2va4Jc7H4O347SObQ8GUdNwe+sgiOHZG7j/PhlH/UP0h+P DG2p8WAwEwJAQRrur+GDv+hvEjJMiA5BICFMLPS2OZFHO6fRBNWjVPr5BeG67l24iS dwEabo0aK16ToeihD/4FjmV9l5GKbpExgKtP8/qI8zJ424cBs/u7shCetoadla93NK N6xp8/R9vGtpE99uVv18X/jTAm/yQfWiqnlhBUVoql4j1IDo/rxkmC14HItD/9PyqI AIIQUPwbkqIAYpbNs1JJrmVgtovReWWoCSq/wUjwjNlf9gik0SsqlTwGCUbHj8lTzb wa4sA5Tt+7k9g== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH 08/11] mtd: rawnand: denali_pci: rename goto labels Date: Fri, 8 Feb 2019 17:08:52 +0900 Message-Id: <1549613335-30319-9-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As Documentation/process/coding-style.rst says, choose label names which say what the goto does. The out_ label style is already used in denali_dt.c. Rename likewise for denali_pci.c Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali_pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali_pci.c b/drivers/mtd/nand/raw/denali_pci.c index 48e9ac5..02eb599 100644 --- a/drivers/mtd/nand/raw/denali_pci.c +++ b/drivers/mtd/nand/raw/denali_pci.c @@ -84,20 +84,20 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) if (!denali->host) { dev_err(&dev->dev, "Spectra: ioremap_nocache failed!"); ret = -ENOMEM; - goto failed_remap_reg; + goto out_unmap_reg; } ret = denali_init(denali); if (ret) - goto failed_remap_mem; + goto out_unmap_host; pci_set_drvdata(dev, denali); return 0; -failed_remap_mem: +out_unmap_host: iounmap(denali->host); -failed_remap_reg: +out_unmap_reg: iounmap(denali->reg); return ret; } From patchwork Fri Feb 8 08:08:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 157814 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1664572jaa; Fri, 8 Feb 2019 00:10:48 -0800 (PST) X-Google-Smtp-Source: AHgI3IbAPKBSKZGakq1kMH8zMYMAke9hSnu4CFRbfl4qGhF2n4swdN6XM68nP7qqTGO5EG10rGob X-Received: by 2002:a63:5902:: with SMTP id n2mr9102044pgb.354.1549613448411; Fri, 08 Feb 2019 00:10:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549613448; cv=none; d=google.com; s=arc-20160816; b=NJaKexjf21g0QVA7V/6ZwjLv7szcAvGyFi5ih1/6YmSzxjVi6cPBa5lFVQNo5/ih0Z S0ApBV3+ieAFb/qeMBP42FtTBlfaXjPJaHgBq2c8CxULbc6d0hXPcEexr0KH/lSpCHHA lcvXg74ps6jHJ0hqGPsqcMYirQaS9p2bEPV6/vf51wjU9vsDroBH6jAd/hKvGnOeoFyM CaAKn6LKz0N2PZM5/opEIc7v+hLCsaSzpz+Z474VcCSv+hNSzX3irdX2nWrXvsKsnR13 4y17PfEnrum0bLgKfbvCWHteOvInmrqHsvIFZybAnc2ADN/s+LBBKci08IdDL4OGgTcy KfEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=UxYR+cc8C2q+yzzg3Z0RLmZOO4LCkDOJl9DmGy/UAGw=; b=YGpvHeKE3Eqq537CY2vvcoLzwbuSlstDy0qUtnqMStyaCOh4ZfJ2IEOLVJx/3ciF5K XvAEGsvmZrpk3bIJiJ3m1+snyEkOWHd9qaedSYFC+MuCrhDCK2v0Cguc5kGI69RZnfCo hBP6WqPlW2m47LOnhEoZDmVwNEMFZnQCF8qikcOITjqm9SDR2Dyc4o/5ckmahJn4eEu/ c7y5SQkUK9X6Fc3aFFUbLs0FH2ox74je/E9OzgGwpIkXqa/ij/+AA3c63ypUO/N3tYri SIdgwWVwpL0c7PNn45Rvva7Flt20Kroja9V/0QFPcKBoz+hg3l3iwujUJS454ASg5/r9 ilKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=cUlKsgsl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o61si1643307pld.246.2019.02.08.00.10.48; Fri, 08 Feb 2019 00:10:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=cUlKsgsl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727453AbfBHIKq (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:46 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:62371 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727231AbfBHIKo (ORCPT ); Fri, 8 Feb 2019 03:10:44 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902I007241; Fri, 8 Feb 2019 17:09:09 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902I007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613350; bh=UxYR+cc8C2q+yzzg3Z0RLmZOO4LCkDOJl9DmGy/UAGw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cUlKsgslEquFLknRUSjJVoVbuNccWdMse+tcOV/zxqQH6cQbeEi8MZWbRX5S7muAu gQyMaDkODDw5bqPT6CbyiNyudmm9JZhOVxBvVtcZWGzrEKhMvInpZ89BjmkYojIMeV SduOz/IBV47DvkZZnmOTXszgKMQubbPaweu4u9wbz495kD376dJOqDuHukXl+fAAQL 5lEi2k8dhBkeN43/QspNzHI1HTLHv8Lcx6WWL4pCCjpwBZ0JK5hQ6WCiRahNXudcc0 LyJ/y8jkGU1vA3cZri/D2JKH0ycZaVr4V6u42W7w27xF2PA9S7LhYT75o1wUD9E4Eq WdX0nxnJ3KI8A== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , devicetree@vger.kernel.org, Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse , Rob Herring , Mark Rutland Subject: [PATCH 09/11] mtd: rawnand: denali: decouple controller and NAND chips Date: Fri, 8 Feb 2019 17:08:53 +0900 Message-Id: <1549613335-30319-10-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, this driver sticks to the legacy NAND model because denali_dt.c was up streamed before commit 2d472aba15ff ("mtd: nand: document the NAND controller/NAND chip DT representation"). However, relying on the dummy_controller is already deprecated. Switch over to the new controller/chip representation. The struct denali_nand_info has been split into denali_controller and denali_chip, to contain the controller data, per-chip data, respectively. One problem is, this would change the DT binding. So, as always, the backward compatibility must be taken into consideration. In the new binding, the controller node expects #address-cells = <1>; #size-cells = <0>; ... since the child nodes represent NAND chips. In the old binding, the controller node may have subnodes, but they are just MTD partitions. The denali_dt_is_legacy_binding() exploits it to distinguish old/new platforms. Of course, the old binding is allowed only for existing DT files. Update the binding document. Signed-off-by: Masahiro Yamada --- .../devicetree/bindings/mtd/denali-nand.txt | 39 +- drivers/mtd/nand/raw/denali.c | 455 ++++++++++++--------- drivers/mtd/nand/raw/denali.h | 117 +++++- drivers/mtd/nand/raw/denali_dt.c | 98 ++++- drivers/mtd/nand/raw/denali_pci.c | 30 +- 5 files changed, 501 insertions(+), 238 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index f33da87..de4ddff 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -7,34 +7,47 @@ Required properties: "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b) - reg : should contain registers location and length for data and reg. - reg-names: Should contain the reg names "nand_data" and "denali_reg" + - #address-cells: should be 1. The cell encodes the chip select connection. + - #size-cells : should be 0. - interrupts : The interrupt number. - clocks: should contain phandle of the controller core clock, the bus interface clock, and the ECC circuit clock. - clock-names: should contain "nand", "nand_x", "ecc" -Optional properties: - - nand-ecc-step-size: see nand.txt for details. If present, the value must be - 512 for "altr,socfpga-denali-nand" - 1024 for "socionext,uniphier-denali-nand-v5a" - 1024 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-strength: see nand.txt for details. Valid values are: - 8, 15 for "altr,socfpga-denali-nand" - 8, 16, 24 for "socionext,uniphier-denali-nand-v5a" - 8, 16 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-maximize: see nand.txt for details - -The device tree may optionally contain sub-nodes describing partitions of the +Sub-nodes: + Sub-nodes represent available NAND chips. + + Required properties: + - reg: should contain the bank ID of the controller to which each chip + select is connected. + + Optional properties: + - nand-ecc-step-size: see nand.txt for details. If present, the value must be + 512 for "altr,socfpga-denali-nand" + 1024 for "socionext,uniphier-denali-nand-v5a" + 1024 for "socionext,uniphier-denali-nand-v5b" + - nand-ecc-strength: see nand.txt for details. Valid values are: + 8, 15 for "altr,socfpga-denali-nand" + 8, 16, 24 for "socionext,uniphier-denali-nand-v5a" + 8, 16 for "socionext,uniphier-denali-nand-v5b" + - nand-ecc-maximize: see nand.txt for details + +The chip nodes may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. Examples: nand: nand@ff900000 { #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; compatible = "altr,socfpga-denali-nand"; reg = <0xff900000 0x20>, <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; interrupts = <0 144 4>; + + nand@0 { + reg = <0>; + } }; diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 748711e..84dac9f 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -3,7 +3,7 @@ * NAND Flash Controller Device Driver * Copyright © 2009-2010, Intel Corporation and its suppliers. * - * Copyright (c) 2017 Socionext Inc. + * Copyright (c) 2017-2019 Socionext Inc. * Reworked by Masahiro Yamada */ @@ -42,14 +42,15 @@ #define DENALI_INVALID_BANK -1 #define DENALI_NR_BANKS 4 -static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) +static struct denali_chip *to_denali_chip(struct nand_chip *chip) { - return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); + return container_of(chip, struct denali_chip, chip); } -static struct denali_nand_info *to_denali(struct nand_chip *chip) +static struct denali_controller *to_denali_controller(struct nand_chip *chip) { - return container_of(chip, struct denali_nand_info, nand); + return container_of(chip->controller, struct denali_controller, + controller); } /* @@ -57,12 +58,12 @@ static struct denali_nand_info *to_denali(struct nand_chip *chip) * type, bank, block, and page address). The slave data is the actual data to * be transferred. This mode requires 28 bits of address region allocated. */ -static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr) +static u32 denali_direct_read(struct denali_controller *denali, u32 addr) { return ioread32(denali->host + addr); } -static void denali_direct_write(struct denali_nand_info *denali, u32 addr, +static void denali_direct_write(struct denali_controller *denali, u32 addr, u32 data) { iowrite32(data, denali->host + addr); @@ -74,35 +75,20 @@ static void denali_direct_write(struct denali_nand_info *denali, u32 addr, * control information and transferred data are latched by the registers in * the translation module. */ -static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr) +static u32 denali_indexed_read(struct denali_controller *denali, u32 addr) { iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); return ioread32(denali->host + DENALI_INDEXED_DATA); } -static void denali_indexed_write(struct denali_nand_info *denali, u32 addr, +static void denali_indexed_write(struct denali_controller *denali, u32 addr, u32 data) { iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); iowrite32(data, denali->host + DENALI_INDEXED_DATA); } -/* - * Use the configuration feature register to determine the maximum number of - * banks that the hardware supports. - */ -static void denali_detect_max_banks(struct denali_nand_info *denali) -{ - uint32_t features = ioread32(denali->reg + FEATURES); - - denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features); - - /* the encoding changed from rev 5.0 to 5.1 */ - if (denali->revision < 0x0501) - denali->max_banks <<= 1; -} - -static void denali_enable_irq(struct denali_nand_info *denali) +static void denali_enable_irq(struct denali_controller *denali) { int i; @@ -111,7 +97,7 @@ static void denali_enable_irq(struct denali_nand_info *denali) iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); } -static void denali_disable_irq(struct denali_nand_info *denali) +static void denali_disable_irq(struct denali_controller *denali) { int i; @@ -120,14 +106,14 @@ static void denali_disable_irq(struct denali_nand_info *denali) iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); } -static void denali_clear_irq(struct denali_nand_info *denali, - int bank, u32 irq_stat) +static void denali_clear_irq(struct denali_controller *denali, int bank, + u32 irq_stat) { /* write one to clear bits */ iowrite32(irq_stat, denali->reg + INTR_STATUS(bank)); } -static void denali_clear_irq_all(struct denali_nand_info *denali) +static void denali_clear_irq_all(struct denali_controller *denali) { int i; @@ -137,7 +123,7 @@ static void denali_clear_irq_all(struct denali_nand_info *denali) static irqreturn_t denali_isr(int irq, void *dev_id) { - struct denali_nand_info *denali = dev_id; + struct denali_controller *denali = dev_id; irqreturn_t ret = IRQ_NONE; u32 irq_stat; int i; @@ -165,7 +151,7 @@ static irqreturn_t denali_isr(int irq, void *dev_id) return ret; } -static void denali_reset_irq(struct denali_nand_info *denali) +static void denali_reset_irq(struct denali_controller *denali) { unsigned long flags; @@ -175,8 +161,8 @@ static void denali_reset_irq(struct denali_nand_info *denali) spin_unlock_irqrestore(&denali->irq_lock, flags); } -static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, - u32 irq_mask, unsigned int timeout_ms) +static u32 denali_wait_for_irq(struct denali_controller *denali, u32 irq_mask, + unsigned int timeout_ms) { unsigned long time_left, flags; u32 irq_stat; @@ -208,13 +194,45 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, static void denali_select_target(struct nand_chip *chip, int cs) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_controller *denali = to_denali_controller(chip); + struct denali_chip_sel *sel = &to_denali_chip(chip)->sels[cs]; + struct mtd_info *mtd = nand_to_mtd(chip); - denali->active_bank = cs; + denali->active_bank = sel->bank; + + iowrite32(1 << (chip->phys_erase_shift - chip->page_shift), + denali->reg + PAGES_PER_BLOCK); + iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, + denali->reg + DEVICE_WIDTH); + iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); + iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); + iowrite32(chip->options & NAND_ROW_ADDR_3 ? + 0 : TWO_ROW_ADDR_CYCLES__FLAG, + denali->reg + TWO_ROW_ADDR_CYCLES); + iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | + FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), + denali->reg + ECC_CORRECTION); + iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); + iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); + iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS); + + if (chip->options & NAND_KEEP_TIMINGS) + return; + + /* update timing registers unless NAND_KEEP_TIMINGS is set */ + iowrite32(sel->hwhr2_and_we_2_re, denali->reg + TWHR2_AND_WE_2_RE); + iowrite32(sel->tcwaw_and_addr_2_data, + denali->reg + TCWAW_AND_ADDR_2_DATA); + iowrite32(sel->re_2_we, denali->reg + RE_2_WE); + iowrite32(sel->acc_clks, denali->reg + ACC_CLKS); + iowrite32(sel->rdwr_en_lo_cnt, denali->reg + RDWR_EN_LO_CNT); + iowrite32(sel->rdwr_en_hi_cnt, denali->reg + RDWR_EN_HI_CNT); + iowrite32(sel->cs_setup_cnt, denali->reg + CS_SETUP_CNT); + iowrite32(sel->re_2_re, denali->reg + RE_2_RE); } static int denali_check_erased_page(struct nand_chip *chip, - struct denali_nand_info *denali, u8 *buf, + struct denali_controller *denali, u8 *buf, unsigned long uncor_ecc_flags, unsigned int max_bitflips) { @@ -248,7 +266,7 @@ static int denali_check_erased_page(struct nand_chip *chip, } static int denali_hw_ecc_fixup(struct nand_chip *chip, - struct denali_nand_info *denali, + struct denali_controller *denali, unsigned long *uncor_ecc_flags) { struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; @@ -283,7 +301,7 @@ static int denali_hw_ecc_fixup(struct nand_chip *chip, } static int denali_sw_ecc_fixup(struct nand_chip *chip, - struct denali_nand_info *denali, + struct denali_controller *denali, unsigned long *uncor_ecc_flags, uint8_t *buf) { struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; @@ -356,7 +374,7 @@ static int denali_sw_ecc_fixup(struct nand_chip *chip, return max_bitflips; } -static void denali_setup_dma64(struct denali_nand_info *denali, +static void denali_setup_dma64(struct denali_controller *denali, dma_addr_t dma_addr, int page, bool write) { uint32_t mode; @@ -381,7 +399,7 @@ static void denali_setup_dma64(struct denali_nand_info *denali, denali->host_write(denali, mode, upper_32_bits(dma_addr)); } -static void denali_setup_dma32(struct denali_nand_info *denali, +static void denali_setup_dma32(struct denali_controller *denali, dma_addr_t dma_addr, int page, bool write) { uint32_t mode; @@ -405,7 +423,7 @@ static void denali_setup_dma32(struct denali_nand_info *denali, denali->host_write(denali, mode | 0x14000, 0x2400); } -static int denali_pio_read(struct denali_nand_info *denali, u32 *buf, +static int denali_pio_read(struct denali_controller *denali, u32 *buf, size_t size, int page) { u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; @@ -432,7 +450,7 @@ static int denali_pio_read(struct denali_nand_info *denali, u32 *buf, return irq_stat & ecc_err_mask ? -EBADMSG : 0; } -static int denali_pio_write(struct denali_nand_info *denali, const u32 *buf, +static int denali_pio_write(struct denali_controller *denali, const u32 *buf, size_t size, int page) { u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; @@ -453,7 +471,7 @@ static int denali_pio_write(struct denali_nand_info *denali, const u32 *buf, return 0; } -static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, +static int denali_pio_xfer(struct denali_controller *denali, void *buf, size_t size, int page, bool write) { if (write) @@ -462,7 +480,7 @@ static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, return denali_pio_read(denali, buf, size, page); } -static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, +static int denali_dma_xfer(struct denali_controller *denali, void *buf, size_t size, int page, bool write) { dma_addr_t dma_addr; @@ -522,7 +540,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, static int denali_data_xfer(struct nand_chip *chip, void *buf, size_t size, int page, bool raw, bool write) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_controller *denali = to_denali_controller(chip); denali_select_target(chip, chip->cur_cs); @@ -542,7 +560,7 @@ typedef int denali_change_column_callback(void *buf, unsigned int offset, static int denali_raw_payload_op(struct nand_chip *chip, void *buf, denali_change_column_callback *cb, void *priv) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_controller *denali = to_denali_controller(chip); struct mtd_info *mtd = nand_to_mtd(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; int writesize = mtd->writesize; @@ -579,7 +597,7 @@ static int denali_raw_payload_op(struct nand_chip *chip, void *buf, static int denali_raw_oob_op(struct nand_chip *chip, void *buf, denali_change_column_callback *cb, void *priv) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_controller *denali = to_denali_controller(chip); struct mtd_info *mtd = nand_to_mtd(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; int writesize = mtd->writesize; @@ -636,9 +654,9 @@ static int denali_memcpy_in(void *buf, unsigned int offset, unsigned int len, static int denali_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_chip *dchip = to_denali_chip(chip); struct mtd_info *mtd = nand_to_mtd(chip); - void *tmp_buf = denali->buf; + void *tmp_buf = dchip->buf; size_t size = mtd->writesize + mtd->oobsize; int ret; @@ -673,9 +691,9 @@ static int denali_memcpy_out(void *buf, unsigned int offset, unsigned int len, static int denali_write_page_raw(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_chip *dchip = to_denali_chip(chip); struct mtd_info *mtd = nand_to_mtd(chip); - void *tmp_buf = denali->buf; + void *tmp_buf = dchip->buf; size_t size = mtd->writesize + mtd->oobsize; int ret; @@ -747,8 +765,8 @@ static int denali_write_oob(struct nand_chip *chip, int page) static int denali_read_page(struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { + struct denali_controller *denali = to_denali_controller(chip); struct mtd_info *mtd = nand_to_mtd(chip); - struct denali_nand_info *denali = mtd_to_denali(mtd); unsigned long uncor_ecc_flags = 0; int stat = 0; int ret; @@ -789,7 +807,8 @@ static int denali_write_page(struct nand_chip *chip, const uint8_t *buf, static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, const struct nand_data_interface *conf) { - struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip)); + struct denali_controller *denali = to_denali_controller(chip); + struct denali_chip_sel *sel; const struct nand_sdr_timings *timings; unsigned long t_x, mult_x; int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; @@ -818,6 +837,8 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) return 0; + sel = &to_denali_chip(chip)->sels[chipnr]; + /* tREA -> ACC_CLKS */ acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); @@ -825,7 +846,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + ACC_CLKS); tmp &= ~ACC_CLKS__VALUE; tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); - iowrite32(tmp, denali->reg + ACC_CLKS); + sel->acc_clks = tmp; /* tRWH -> RE_2_WE */ re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); @@ -834,7 +855,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + RE_2_WE); tmp &= ~RE_2_WE__VALUE; tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); - iowrite32(tmp, denali->reg + RE_2_WE); + sel->re_2_we = tmp; /* tRHZ -> RE_2_RE */ re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); @@ -843,7 +864,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + RE_2_RE); tmp &= ~RE_2_RE__VALUE; tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); - iowrite32(tmp, denali->reg + RE_2_RE); + sel->re_2_re = tmp; /* * tCCS, tWHR -> WE_2_RE @@ -857,7 +878,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); - iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); + sel->hwhr2_and_we_2_re = tmp; /* tADL -> ADDR_2_DATA */ @@ -872,7 +893,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); - iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); + sel->tcwaw_and_addr_2_data = tmp; /* tREH, tWH -> RDWR_EN_HI_CNT */ rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), @@ -882,7 +903,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); tmp &= ~RDWR_EN_HI_CNT__VALUE; tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); - iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); + sel->rdwr_en_hi_cnt = tmp; /* tRP, tWP -> RDWR_EN_LO_CNT */ rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); @@ -895,7 +916,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); tmp &= ~RDWR_EN_LO_CNT__VALUE; tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); - iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); + sel->rdwr_en_lo_cnt = tmp; /* tCS, tCEA -> CS_SETUP_CNT */ cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, @@ -906,39 +927,11 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, tmp = ioread32(denali->reg + CS_SETUP_CNT); tmp &= ~CS_SETUP_CNT__VALUE; tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); - iowrite32(tmp, denali->reg + CS_SETUP_CNT); + sel->cs_setup_cnt = tmp; return 0; } -static void denali_hw_init(struct denali_nand_info *denali) -{ - /* - * The REVISION register may not be reliable. Platforms are allowed to - * override it. - */ - if (!denali->revision) - denali->revision = swab16(ioread32(denali->reg + REVISION)); - - /* - * Set how many bytes should be skipped before writing data in OOB. - * If a non-zero value has already been set (by firmware or something), - * just use it. Otherwise, set the driver default. - */ - denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES); - if (!denali->oob_skip_bytes) { - denali->oob_skip_bytes = DENALI_DEFAULT_OOB_SKIP_BYTES; - iowrite32(denali->oob_skip_bytes, - denali->reg + SPARE_AREA_SKIP_BYTES); - } - - denali_detect_max_banks(denali); - iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); - iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); - - iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); -} - int denali_calc_ecc_bytes(int step_size, int strength) { /* BCH code. Denali requires ecc.bytes to be multiple of 2 */ @@ -949,10 +942,10 @@ EXPORT_SYMBOL(denali_calc_ecc_bytes); static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { - struct denali_nand_info *denali = mtd_to_denali(mtd); struct nand_chip *chip = mtd_to_nand(mtd); + struct denali_controller *denali = to_denali_controller(chip); - if (section) + if (section > 0) return -ERANGE; oobregion->offset = denali->oob_skip_bytes; @@ -964,10 +957,10 @@ static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, static int denali_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { - struct denali_nand_info *denali = mtd_to_denali(mtd); struct nand_chip *chip = mtd_to_nand(mtd); + struct denali_controller *denali = to_denali_controller(chip); - if (section) + if (section > 0) return -ERANGE; oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; @@ -983,7 +976,7 @@ static const struct mtd_ooblayout_ops denali_ooblayout_ops = { static int denali_multidev_fixup(struct nand_chip *chip) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_controller *denali = to_denali_controller(chip); struct mtd_info *mtd = nand_to_mtd(chip); /* @@ -1034,38 +1027,11 @@ static int denali_multidev_fixup(struct nand_chip *chip) static int denali_attach_chip(struct nand_chip *chip) { + struct denali_controller *denali = to_denali_controller(chip); + struct denali_chip *dchip = to_denali_chip(chip); struct mtd_info *mtd = nand_to_mtd(chip); - struct denali_nand_info *denali = mtd_to_denali(mtd); int ret; - if (ioread32(denali->reg + FEATURES) & FEATURES__DMA) - denali->dma_avail = 1; - - if (denali->dma_avail) { - int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32; - - ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit)); - if (ret) { - dev_info(denali->dev, - "Failed to set DMA mask. Disabling DMA.\n"); - denali->dma_avail = 0; - } - } - - if (denali->dma_avail) { - chip->options |= NAND_USE_BOUNCE_BUFFER; - chip->buf_align = 16; - if (denali->caps & DENALI_CAP_DMA_64BIT) - denali->setup_dma = denali_setup_dma64; - else - denali->setup_dma = denali_setup_dma32; - } - - chip->bbt_options |= NAND_BBT_USE_FLASH; - chip->bbt_options |= NAND_BBT_NO_OOB; - chip->ecc.mode = NAND_ECC_HW_SYNDROME; - chip->options |= NAND_NO_SUBPAGE_WRITE; - ret = nand_ecc_choose_conf(chip, denali->ecc_caps, mtd->oobsize - denali->oob_skip_bytes); if (ret) { @@ -1077,33 +1043,6 @@ static int denali_attach_chip(struct nand_chip *chip) "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); - iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | - FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), - denali->reg + ECC_CORRECTION); - iowrite32(mtd->erasesize / mtd->writesize, - denali->reg + PAGES_PER_BLOCK); - iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, - denali->reg + DEVICE_WIDTH); - iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG, - denali->reg + TWO_ROW_ADDR_CYCLES); - iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); - iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); - - iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); - iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); - /* chip->ecc.steps is set by nand_scan_tail(); not available here */ - iowrite32(mtd->writesize / chip->ecc.size, - denali->reg + CFG_NUM_DATA_BLOCKS); - - mtd_set_ooblayout(mtd, &denali_ooblayout_ops); - - chip->ecc.read_page = denali_read_page; - chip->ecc.read_page_raw = denali_read_page_raw; - chip->ecc.write_page = denali_write_page; - chip->ecc.write_page_raw = denali_write_page_raw; - chip->ecc.read_oob = denali_read_oob; - chip->ecc.write_oob = denali_write_oob; - ret = denali_multidev_fixup(chip); if (ret) return ret; @@ -1113,8 +1052,8 @@ static int denali_attach_chip(struct nand_chip *chip) * use devm_kmalloc() because the memory allocated by devm_ does not * guarantee DMA-safe alignment. */ - denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); - if (!denali->buf) + dchip->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); + if (!dchip->buf) return -ENOMEM; return 0; @@ -1122,13 +1061,12 @@ static int denali_attach_chip(struct nand_chip *chip) static void denali_detach_chip(struct nand_chip *chip) { - struct mtd_info *mtd = nand_to_mtd(chip); - struct denali_nand_info *denali = mtd_to_denali(mtd); + struct denali_chip *dchip = to_denali_chip(chip); - kfree(denali->buf); + kfree(dchip->buf); } -static void denali_exec_in8(struct denali_nand_info *denali, u32 type, +static void denali_exec_in8(struct denali_controller *denali, u32 type, u8 *buf, unsigned int len) { int i; @@ -1137,7 +1075,7 @@ static void denali_exec_in8(struct denali_nand_info *denali, u32 type, buf[i] = denali->host_read(denali, type | DENALI_BANK(denali)); } -static void denali_exec_in16(struct denali_nand_info *denali, u32 type, +static void denali_exec_in16(struct denali_controller *denali, u32 type, u8 *buf, unsigned int len) { u32 data; @@ -1151,7 +1089,7 @@ static void denali_exec_in16(struct denali_nand_info *denali, u32 type, } } -static void denali_exec_out8(struct denali_nand_info *denali, u32 type, +static void denali_exec_out8(struct denali_controller *denali, u32 type, const u8 *buf, unsigned int len) { int i; @@ -1160,7 +1098,7 @@ static void denali_exec_out8(struct denali_nand_info *denali, u32 type, denali->host_write(denali, type | DENALI_BANK(denali), buf[i]); } -static void denali_exec_out16(struct denali_nand_info *denali, u32 type, +static void denali_exec_out16(struct denali_controller *denali, u32 type, const u8 *buf, unsigned int len) { int i; @@ -1170,7 +1108,7 @@ static void denali_exec_out16(struct denali_nand_info *denali, u32 type, buf[i + 1] << 16 | buf[i]); } -static int denali_exec_waitrdy(struct denali_nand_info *denali, +static int denali_exec_waitrdy(struct denali_controller *denali, unsigned int timeout_ms) { u32 irq_stat; @@ -1187,7 +1125,7 @@ static int denali_exec_waitrdy(struct denali_nand_info *denali, static int denali_exec_instr(struct nand_chip *chip, const struct nand_op_instr *instr) { - struct denali_nand_info *denali = to_denali(chip); + struct denali_controller *denali = to_denali_controller(chip); bool width16 = chip->options & NAND_BUSWIDTH_16; switch (instr->type) { @@ -1239,7 +1177,7 @@ static int denali_exec_op(struct nand_chip *chip, * Some commands contain NAND_OP_WAITRDY_INSTR. * irq must be cleared here to catch the R/B# interrupt there. */ - denali_reset_irq(to_denali(chip)); + denali_reset_irq(to_denali_controller(chip)); for (i = 0; i < op->ninstrs; i++) { ret = denali_exec_instr(chip, &op->instrs[i]); @@ -1257,53 +1195,91 @@ static const struct nand_controller_ops denali_controller_ops = { .setup_data_interface = denali_setup_data_interface, }; -int denali_init(struct denali_nand_info *denali) +int denali_chip_init(struct denali_controller *denali, + struct denali_chip *dchip) { - struct nand_chip *chip = &denali->nand; + struct nand_chip *chip = &dchip->chip; struct mtd_info *mtd = nand_to_mtd(chip); - u32 features = ioread32(denali->reg + FEATURES); - int ret; + struct denali_chip *dchip2; + unsigned int chip_cnt = 0; + int i, j, ret; - mtd->dev.parent = denali->dev; - denali_hw_init(denali); + chip->controller = &denali->controller; - init_completion(&denali->complete); - spin_lock_init(&denali->irq_lock); + /* sanity checks for bank numbers */ + for (i = 0; i < dchip->nsels; i++) { + unsigned int bank = dchip->sels[i].bank; - denali_clear_irq_all(denali); + if (bank >= denali->nbanks) { + dev_err(denali->dev, "unsupported bank %d\n", bank); + return -EINVAL; + } - ret = devm_request_irq(denali->dev, denali->irq, denali_isr, - IRQF_SHARED, DENALI_NAND_NAME, denali); - if (ret) { - dev_err(denali->dev, "Unable to request IRQ\n"); - return ret; - } + for (j = 0; j < i; j++) { + if (bank == dchip->sels[j].bank) { + dev_err(denali->dev, + "bank %d is assigned twice in the same chip\n", + bank); + return -EINVAL; + } + } - denali_enable_irq(denali); + list_for_each_entry(dchip2, &denali->chips, node) { + chip_cnt++; + for (j = 0; j < dchip2->nsels; j++) { + if (bank == dchip2->sels[j].bank) { + dev_err(denali->dev, + "bank %d is already used\n", + bank); + return -EINVAL; + } + } + } + } - denali->active_bank = DENALI_INVALID_BANK; + mtd->dev.parent = denali->dev; - nand_set_flash_node(chip, denali->dev->of_node); /* Fallback to the default name if DT did not give "label" property */ - if (!mtd->name) - mtd->name = "denali-nand"; + if (!mtd->name) { + if (chip_cnt) { + mtd->name = devm_kasprintf(denali->dev, GFP_KERNEL, + "denali-nand%d", chip_cnt); + if (!mtd->name) + return -ENOMEM; + } else { + /* + * "denali-nand" instead of "denali-nand0" + * for backward compatibility + */ + mtd->name = "denali-nand"; + } + } - if (features & FEATURES__INDEX_ADDR) { - denali->host_read = denali_indexed_read; - denali->host_write = denali_indexed_write; - } else { - denali->host_read = denali_direct_read; - denali->host_write = denali_direct_write; + if (denali->dma_avail) { + chip->options |= NAND_USE_BOUNCE_BUFFER; + chip->buf_align = 16; } /* clk rate info is needed for setup_data_interface */ if (!denali->clk_rate || !denali->clk_x_rate) chip->options |= NAND_KEEP_TIMINGS; - chip->legacy.dummy_controller.ops = &denali_controller_ops; - ret = nand_scan(chip, denali->max_banks); + chip->bbt_options |= NAND_BBT_USE_FLASH; + chip->bbt_options |= NAND_BBT_NO_OOB; + chip->options |= NAND_NO_SUBPAGE_WRITE; + chip->ecc.mode = NAND_ECC_HW_SYNDROME; + chip->ecc.read_page = denali_read_page; + chip->ecc.write_page = denali_write_page; + chip->ecc.read_page_raw = denali_read_page_raw; + chip->ecc.write_page_raw = denali_write_page_raw; + chip->ecc.read_oob = denali_read_oob; + chip->ecc.write_oob = denali_write_oob; + + mtd_set_ooblayout(mtd, &denali_ooblayout_ops); + + ret = nand_scan(chip, dchip->nsels); if (ret) - goto disable_irq; + return ret; ret = mtd_device_register(mtd, NULL, 0); if (ret) { @@ -1311,20 +1287,109 @@ int denali_init(struct denali_nand_info *denali) goto cleanup_nand; } + list_add_tail(&dchip->node, &denali->chips); + return 0; cleanup_nand: nand_cleanup(chip); -disable_irq: - denali_disable_irq(denali); return ret; } +EXPORT_SYMBOL_GPL(denali_chip_init); + +int denali_init(struct denali_controller *denali) +{ + u32 features = ioread32(denali->reg + FEATURES); + int ret; + + nand_controller_init(&denali->controller); + denali->controller.ops = &denali_controller_ops; + init_completion(&denali->complete); + spin_lock_init(&denali->irq_lock); + INIT_LIST_HEAD(&denali->chips); + denali->active_bank = DENALI_INVALID_BANK; + + /* + * The REVISION register may not be reliable. Platforms are allowed to + * override it. + */ + if (!denali->revision) + denali->revision = swab16(ioread32(denali->reg + REVISION)); + + denali->nbanks = 1 << FIELD_GET(FEATURES__N_BANKS, features); + + /* the encoding changed from rev 5.0 to 5.1 */ + if (denali->revision < 0x0501) + denali->nbanks <<= 1; + + if (features & FEATURES__DMA) + denali->dma_avail = 1; + + if (denali->dma_avail) { + int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32; + + ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit)); + if (ret) { + dev_info(denali->dev, + "Failed to set DMA mask. Disabling DMA.\n"); + denali->dma_avail = 0; + } + } + + if (denali->dma_avail) { + if (denali->caps & DENALI_CAP_DMA_64BIT) + denali->setup_dma = denali_setup_dma64; + else + denali->setup_dma = denali_setup_dma32; + } + + if (features & FEATURES__INDEX_ADDR) { + denali->host_read = denali_indexed_read; + denali->host_write = denali_indexed_write; + } else { + denali->host_read = denali_direct_read; + denali->host_write = denali_direct_write; + } + + /* + * Set how many bytes should be skipped before writing data in OOB. + * If a non-zero value has already been set (by firmware or something), + * just use it. Otherwise, set the driver's default. + */ + denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES); + if (!denali->oob_skip_bytes) { + denali->oob_skip_bytes = DENALI_DEFAULT_OOB_SKIP_BYTES; + iowrite32(denali->oob_skip_bytes, + denali->reg + SPARE_AREA_SKIP_BYTES); + } + + iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED); + iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); + iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); + + denali_clear_irq_all(denali); + + ret = devm_request_irq(denali->dev, denali->irq, denali_isr, + IRQF_SHARED, DENALI_NAND_NAME, denali); + if (ret) { + dev_err(denali->dev, "Unable to request IRQ\n"); + return ret; + } + + denali_enable_irq(denali); + + return 0; +} EXPORT_SYMBOL(denali_init); -void denali_remove(struct denali_nand_info *denali) +void denali_remove(struct denali_controller *denali) { - nand_release(&denali->nand); + struct denali_chip *dchip; + + list_for_each_entry(dchip, &denali->chips, node) + nand_release(&dchip->chip); + denali_disable_irq(denali); } EXPORT_SYMBOL(denali_remove); diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h index 8e91438..711a13d 100644 --- a/drivers/mtd/nand/raw/denali.h +++ b/drivers/mtd/nand/raw/denali.h @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -290,30 +291,100 @@ #define CHNL_ACTIVE__CHANNEL2 BIT(2) #define CHNL_ACTIVE__CHANNEL3 BIT(3) -struct denali_nand_info { - struct nand_chip nand; - unsigned long clk_rate; /* core clock rate */ - unsigned long clk_x_rate; /* bus interface clock rate */ - int active_bank; /* currently selected bank */ +/** + * struct denali_chip_sel - per-CS data of Denali NAND + * + * @bank: bank id of the controller this CS is connected to + * @hwhr2_and_we_2_re: value of timing register HWHR2_AND_WE_2_RE + * @tcwaw_and_addr_2_data: value of timing register TCWAW_AND_ADDR_2_DATA + * @re_2_we: value of timing register RE_2_WE + * @acc_clks: value of timing register ACC_CLKS + * @rdwr_en_lo_cnt: value of timing register RDWR_EN_LO_CNT + * @rdwr_en_hi_cnt: value of timing register RDWR_EN_HI_CNT + * @cs_setup_cnt: value of timing register CS_SETUP_CNT + * @re_2_re: value of timing register RE_2_RE + */ +struct denali_chip_sel { + int bank; + u32 hwhr2_and_we_2_re; + u32 tcwaw_and_addr_2_data; + u32 re_2_we; + u32 acc_clks; + u32 rdwr_en_lo_cnt; + u32 rdwr_en_hi_cnt; + u32 cs_setup_cnt; + u32 re_2_re; +}; + +/** + * struct denali_chip - per-chip data of Denali NAND + * + * @chip: base NAND chip structure + * @buf: internal buffer for syndrome layout conversion + * @node: node to be used to associate this chip with the controller + * @nsels: the number of CS lines of this chip + * @sels: the array of per-cs data + */ +struct denali_chip { + struct nand_chip chip; + void *buf; + struct list_head node; + unsigned int nsels; + struct denali_chip_sel sels[0]; +}; + +/** + * struct denali_controller - Denali NAND controller data + * + * @controller: base NAND controller structure + * @dev: device + * @chips: the list of chips attached to this controller + * @clk_rate: frequency of core clock + * @clk_x_rate: frequency of bus interface clock + * @reg: base of Register Interface + * @host: base of Host Data/Command interface + * @complete: completion used to wait for interrupts + * @irq: interrupt number + * @irq_mask: interrupt bits the controller is waiting for + * @irq_status: interrupt bits of events that have happened + * @irq_lock: lock to protect @irq_mask and @irq_status + * @dma_avail: 1 if DMA engine is available, 0 otherwise + * @devs_per_cs: number of devices connected in parallel + * @oob_skip_bytes: number of bytes in OOB skipped by the ECC engine + * @active_bank: active bank id + * @nbanks: the number of banks supported by this controller + * @revision: IP revision + * @caps: controller capabilities that cannot be detected run-time + * @ecc_caps: ECC engine capabilities + * @host_read: callback for read access of Host Data/Command Interface + * @host_write: callback for write access of Host Data/Command Interface + * @setup_dma: callback for setup of the Data DMA + */ +struct denali_controller { + struct nand_controller controller; struct device *dev; - void __iomem *reg; /* Register Interface */ - void __iomem *host; /* Host Data/Command Interface */ + struct list_head chips; + unsigned long clk_rate; + unsigned long clk_x_rate; + void __iomem *reg; + void __iomem *host; struct completion complete; - spinlock_t irq_lock; /* protect irq_mask and irq_stat */ - u32 irq_mask; /* interrupts we are waiting for */ - u32 irq_stat; /* interrupts that have happened */ int irq; - void *buf; /* for syndrome layout conversion */ - int dma_avail; /* can support DMA? */ - int devs_per_cs; /* devices connected in parallel */ - int oob_skip_bytes; /* number of bytes reserved for BBM */ - int max_banks; - unsigned int revision; /* IP revision */ - unsigned int caps; /* IP capability (or quirk) */ + u32 irq_mask; + u32 irq_stat; + spinlock_t irq_lock; + int dma_avail; + int devs_per_cs; + int oob_skip_bytes; + int active_bank; + int nbanks; + unsigned int revision; + unsigned int caps; const struct nand_ecc_caps *ecc_caps; - u32 (*host_read)(struct denali_nand_info *denali, u32 addr); - void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); - void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, + u32 (*host_read)(struct denali_controller *denali, u32 addr); + void (*host_write)(struct denali_controller *denali, u32 addr, + u32 data); + void (*setup_dma)(struct denali_controller *denali, dma_addr_t dma_addr, int page, bool write); }; @@ -321,7 +392,9 @@ struct denali_nand_info { #define DENALI_CAP_DMA_64BIT BIT(1) int denali_calc_ecc_bytes(int step_size, int strength); -int denali_init(struct denali_nand_info *denali); -void denali_remove(struct denali_nand_info *denali); +int denali_chip_init(struct denali_controller *denali, + struct denali_chip *dchip); +int denali_init(struct denali_controller *denali); +void denali_remove(struct denali_controller *denali); #endif /* __DENALI_H__ */ diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 0b5ae24..5e14836 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -18,7 +18,7 @@ #include "denali.h" struct denali_dt { - struct denali_nand_info denali; + struct denali_controller controller; struct clk *clk; /* core clock */ struct clk *clk_x; /* bus interface clock */ struct clk *clk_ecc; /* ECC circuit clock */ @@ -71,19 +71,92 @@ static const struct of_device_id denali_nand_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, denali_nand_dt_ids); +static int denali_dt_chip_init(struct denali_controller *denali, + struct device_node *chip_np) +{ + struct denali_chip *dchip; + u32 bank; + int nsels, i, ret; + + nsels = of_property_count_u32_elems(chip_np, "reg"); + if (nsels < 0) + return nsels; + + dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), + GFP_KERNEL); + if (!dchip) + return -ENOMEM; + + dchip->nsels = nsels; + + for (i = 0; i < nsels; i++) { + ret = of_property_read_u32_index(chip_np, "reg", i, &bank); + if (ret) + return ret; + + dchip->sels[i].bank = bank; + + nand_set_flash_node(&dchip->chip, chip_np); + } + + return denali_chip_init(denali, dchip); +} + +/* Backward compatibility for old platforms */ +static int denali_dt_legacy_chip_init(struct denali_controller *denali) +{ + struct denali_chip *dchip; + int nsels, i; + + nsels = denali->nbanks; + + dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), + GFP_KERNEL); + if (!dchip) + return -ENOMEM; + + dchip->nsels = nsels; + + for (i = 0; i < nsels; i++) + dchip->sels[i].bank = i; + + nand_set_flash_node(&dchip->chip, denali->dev->of_node); + + return denali_chip_init(denali, dchip); +} + +/* + * Check the DT binding. + * The new binding expects chip subnodes in the controller node. + * So, #address-cells = <1>; #size-cells = <0>; are required. + * Check the #size-cells to distinguish the binding. + */ +static bool denali_dt_is_legacy_binding(struct device_node *np) +{ + u32 cells; + int ret; + + ret = of_property_read_u32(np, "#size-cells", &cells); + if (ret) + return true; + + return cells != 0; +} + static int denali_dt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *res; struct denali_dt *dt; const struct denali_dt_data *data; - struct denali_nand_info *denali; + struct denali_controller *denali; + struct device_node *np; int ret; dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL); if (!dt) return -ENOMEM; - denali = &dt->denali; + denali = &dt->controller; data = of_device_get_match_data(dev); if (data) { @@ -140,9 +213,26 @@ static int denali_dt_probe(struct platform_device *pdev) if (ret) goto out_disable_clk_ecc; + if (denali_dt_is_legacy_binding(dev->of_node)) { + ret = denali_dt_legacy_chip_init(denali); + if (ret) + goto out_remove_denali; + } else { + for_each_child_of_node(dev->of_node, np) { + ret = denali_dt_chip_init(denali, np); + if (ret) { + of_node_put(np); + goto out_remove_denali; + } + } + } + platform_set_drvdata(pdev, dt); + return 0; +out_remove_denali: + denali_remove(denali); out_disable_clk_ecc: clk_disable_unprepare(dt->clk_ecc); out_disable_clk_x: @@ -157,7 +247,7 @@ static int denali_dt_remove(struct platform_device *pdev) { struct denali_dt *dt = platform_get_drvdata(pdev); - denali_remove(&dt->denali); + denali_remove(&dt->controller); clk_disable_unprepare(dt->clk_ecc); clk_disable_unprepare(dt->clk_x); clk_disable_unprepare(dt->clk); diff --git a/drivers/mtd/nand/raw/denali_pci.c b/drivers/mtd/nand/raw/denali_pci.c index 02eb599..d62aa52 100644 --- a/drivers/mtd/nand/raw/denali_pci.c +++ b/drivers/mtd/nand/raw/denali_pci.c @@ -29,10 +29,11 @@ NAND_ECC_CAPS_SINGLE(denali_pci_ecc_caps, denali_calc_ecc_bytes, 512, 8, 15); static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) { - int ret; resource_size_t csr_base, mem_base; unsigned long csr_len, mem_len; - struct denali_nand_info *denali; + struct denali_controller *denali; + struct denali_chip *dchip; + int nsels, ret, i; denali = devm_kzalloc(&dev->dev, sizeof(*denali), GFP_KERNEL); if (!denali) @@ -64,7 +65,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) denali->dev = &dev->dev; denali->irq = dev->irq; denali->ecc_caps = &denali_pci_ecc_caps; - denali->nand.ecc.options |= NAND_ECC_MAXIMIZE; denali->clk_rate = 50000000; /* 50 MHz */ denali->clk_x_rate = 200000000; /* 200 MHz */ @@ -91,10 +91,32 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) if (ret) goto out_unmap_host; + nsels = denali->nbanks; + + dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), + GFP_KERNEL); + if (!dchip) { + ret = -ENOMEM; + goto out_remove_denali; + } + + dchip->chip.ecc.options |= NAND_ECC_MAXIMIZE; + + dchip->nsels = nsels; + + for (i = 0; i < nsels; i++) + dchip->sels[i].bank = i; + + ret = denali_chip_init(denali, dchip); + if (ret) + goto out_remove_denali; + pci_set_drvdata(dev, denali); return 0; +out_remove_denali: + denali_remove(denali); out_unmap_host: iounmap(denali->host); out_unmap_reg: @@ -104,7 +126,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) static void denali_pci_remove(struct pci_dev *dev) { - struct denali_nand_info *denali = pci_get_drvdata(dev); + struct denali_controller *denali = pci_get_drvdata(dev); denali_remove(denali); iounmap(denali->reg); From patchwork Fri Feb 8 08:08:54 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id g10si1547771plq.371.2019.02.08.00.10.56; Fri, 08 Feb 2019 00:10:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=1AlivkQe; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727475AbfBHIKu (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:50 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:62766 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727447AbfBHIKr (ORCPT ); Fri, 8 Feb 2019 03:10:47 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902J007241; Fri, 8 Feb 2019 17:09:10 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902J007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613351; bh=4zRVCkg/JqYATaz8w/n52lDPh+nyy/86YNhKn3aIKXA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=1AlivkQeB0sqZjn/QVpg2ses5Md81TmQiFxy8v0qYX8DNda0iSLNKnKh/BdUGS/Ng PvioLXEseYNivXfAcgoozn/yul2ZYHBdVfoo42iXYIRSZZ4rhGwWF1e+0hfpPbyYW4 LvhAIhhdgCAMvPTWnSuJ2M/shuqrOwZ09PyzljFReunCDc0Y30DXikWlqjXdsVZc2n M2d8BmpHSMUQNwiUp70osAcftlAbskNGvQIln1uPI9DtVe7qwLCZOenNFAik4vGTIo absSn3pdCamgM+dPVuZ+whP71kTt3gmkd2fm1CoIWiZZPwumXFnuodI9eETzo6nDea +qLQzggiCgelw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH 10/11] mtd: rawnand: denali: remove DENALI_NR_BANKS macro Date: Fri, 8 Feb 2019 17:08:54 +0900 Message-Id: <1549613335-30319-11-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the runtime-detected denali->nbanks instead of hard-coded DENALI_NR_BANKS (=4). The actual number of banks depends on the IP configuration, and can be less than DENALI_NR_BANKS. It is pointless to touch registers of unsupported banks. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index 84dac9f..ce3a4bb 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -40,7 +40,6 @@ #define DENALI_BANK(denali) ((denali)->active_bank << 24) #define DENALI_INVALID_BANK -1 -#define DENALI_NR_BANKS 4 static struct denali_chip *to_denali_chip(struct nand_chip *chip) { @@ -92,7 +91,7 @@ static void denali_enable_irq(struct denali_controller *denali) { int i; - for (i = 0; i < DENALI_NR_BANKS; i++) + for (i = 0; i < denali->nbanks; i++) iowrite32(U32_MAX, denali->reg + INTR_EN(i)); iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); } @@ -101,7 +100,7 @@ static void denali_disable_irq(struct denali_controller *denali) { int i; - for (i = 0; i < DENALI_NR_BANKS; i++) + for (i = 0; i < denali->nbanks; i++) iowrite32(0, denali->reg + INTR_EN(i)); iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); } @@ -117,7 +116,7 @@ static void denali_clear_irq_all(struct denali_controller *denali) { int i; - for (i = 0; i < DENALI_NR_BANKS; i++) + for (i = 0; i < denali->nbanks; i++) denali_clear_irq(denali, i, U32_MAX); } @@ -130,7 +129,7 @@ static irqreturn_t denali_isr(int irq, void *dev_id) spin_lock(&denali->irq_lock); - for (i = 0; i < DENALI_NR_BANKS; i++) { + for (i = 0; i < denali->nbanks; i++) { irq_stat = ioread32(denali->reg + INTR_STATUS(i)); if (irq_stat) ret = IRQ_HANDLED; From patchwork Fri Feb 8 08:08:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 157817 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1664749jaa; Fri, 8 Feb 2019 00:11:01 -0800 (PST) X-Google-Smtp-Source: AHgI3IZSFqi4AYw9sg4kBYs4yQRHFWOZRhV7nxLI08iO81YTu1OLG0sD98qqjv2KXH+jf2xgwUXY X-Received: by 2002:a17:902:4324:: with SMTP id i33mr20987196pld.227.1549613461135; Fri, 08 Feb 2019 00:11:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549613461; cv=none; d=google.com; s=arc-20160816; b=VwJIMKSzL+P2mi+e/EBO23S41+wcbng6u+whBmn1Xz+pkJoz/RzhoOksUD9WUKBJns U2dDGG4IWxTTqqWSszJiS+XqXLmAkxQ5AI6sUKwrvpsjHsHcbwlCON1IeTv1PAY0VT3F k5aLKf2ll4y4rM7Gl5D9CjOuoCy1kxJqAmKVECjPqxx85CXIm5B4nUK8RRkooq4ngP/+ PAF2IiMQ1gpSle627slBmxjCWON+dDES8NQo6GTsF39W/EDvoQ5c0xz9WsBnbSiR9ET+ g6l8cVInEkZnBKtoPk+YImW7keR9l+17hiRQv58HNWLKCTkik1L7JiIvOg+N3cV0eILj o0Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter; bh=0G9+10Zia38HKdZABMcllan4CmkUVH2FwVxeSCvb9Uk=; b=tudWj68BItgK2Sx1+a5CygEJ6HDQ7rp4a+d2RUp4IAmCHY8U3VJIvroQaph15SC9bm 15v9FnrvRjJIXDqCwr739XA6Bz5W1qSeNXDQM8gks2eCSYrW+6m1Q6nUdMqMoOEJtOa0 U94WNUEY5T4R+N8HqXm2HUOn+d8kUZuRrnrikzQxMhparoen6gpfpcRc9TE1Z+3KvFj6 IFvAWkr9NlR0ZjDOxyMQk6K4glhFOktXns9WlkaH2IAZso1NTW6N6Xf93J3J3Cf7KRoo 0cpPVngukTN5uRKG8dgXkAmh8k96rYEMd63OwAt8ALFZyJNKXrghGd7Pu+k3LheCkZd6 expg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=OHjzn7Ja; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g10si1547771plq.371.2019.02.08.00.11.00; Fri, 08 Feb 2019 00:11:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=OHjzn7Ja; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727505AbfBHIK7 (ORCPT + 31 others); Fri, 8 Feb 2019 03:10:59 -0500 Received: from conuserg-07.nifty.com ([210.131.2.74]:63037 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727442AbfBHIK4 (ORCPT ); Fri, 8 Feb 2019 03:10:56 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x188902K007241; Fri, 8 Feb 2019 17:09:11 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x188902K007241 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1549613352; bh=0G9+10Zia38HKdZABMcllan4CmkUVH2FwVxeSCvb9Uk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OHjzn7JaxJRvQ6tvJWOXI1jqRmWlUSABKvdErsIkOg+I+K9lWKzNVB9tKo2Ahlyy7 TlWkl0oNBpaU8TsjSpH2SKF8Znisep/MYbkakSSqra1Z+zc1lFnul3rxB+E8w1Ao2Y pwvXr0DQSOs7qNnzVL8Tep4DHdtqfRdwDZqulnBOYszVxk1zFSzLakLTE1fM0zOaGL E9pE5e0mHaAlO9fk0VCfBRQMkJxArm7zozd3oReS0lhd+a2jz0wdQa4yoniNk0ktXt QJiVlPryCg/KCl1Mgg6QIzu+8KRDAyTz5783fuZ2nZovt/8y4oGyeEXNxyH6iNoyUt YamVtEkykteWA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Miquel Raynal Cc: Boris Brezillon , Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse Subject: [PATCH 11/11] mtd: rawnand: denali: clean up coding style Date: Fri, 8 Feb 2019 17:08:55 +0900 Message-Id: <1549613335-30319-12-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> References: <1549613335-30319-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Eliminate the following reports from 'scripts/checkpatch.pl --strict'. CHECK: Prefer kernel type 'u8' over 'uint8_t' CHECK: Prefer kernel type 'u32' over 'uint32_t' CHECK: Alignment should match open parenthesis I slightly changed denali_check_erased_page() to make it shorter. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/raw/denali.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index ce3a4bb..18d53dd 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -236,20 +236,17 @@ static int denali_check_erased_page(struct nand_chip *chip, unsigned int max_bitflips) { struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; - uint8_t *ecc_code = chip->oob_poi + denali->oob_skip_bytes; - int ecc_steps = chip->ecc.steps; - int ecc_size = chip->ecc.size; - int ecc_bytes = chip->ecc.bytes; + struct nand_ecc_ctrl *ecc = &chip->ecc; + u8 *ecc_code = chip->oob_poi + denali->oob_skip_bytes; int i, stat; - for (i = 0; i < ecc_steps; i++) { + for (i = 0; i < ecc->steps; i++) { if (!(uncor_ecc_flags & BIT(i))) continue; - stat = nand_check_erased_ecc_chunk(buf, ecc_size, - ecc_code, ecc_bytes, - NULL, 0, - chip->ecc.strength); + stat = nand_check_erased_ecc_chunk(buf, ecc->size, ecc_code, + ecc->bytes, NULL, 0, + ecc->strength); if (stat < 0) { ecc_stats->failed++; } else { @@ -257,8 +254,8 @@ static int denali_check_erased_page(struct nand_chip *chip, max_bitflips = max_t(unsigned int, max_bitflips, stat); } - buf += ecc_size; - ecc_code += ecc_bytes; + buf += ecc->size; + ecc_code += ecc->bytes; } return max_bitflips; @@ -270,7 +267,7 @@ static int denali_hw_ecc_fixup(struct nand_chip *chip, { struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; int bank = denali->active_bank; - uint32_t ecc_cor; + u32 ecc_cor; unsigned int max_bitflips; ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); @@ -301,15 +298,15 @@ static int denali_hw_ecc_fixup(struct nand_chip *chip, static int denali_sw_ecc_fixup(struct nand_chip *chip, struct denali_controller *denali, - unsigned long *uncor_ecc_flags, uint8_t *buf) + unsigned long *uncor_ecc_flags, u8 *buf) { struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; unsigned int ecc_size = chip->ecc.size; unsigned int bitflips = 0; unsigned int max_bitflips = 0; - uint32_t err_addr, err_cor_info; + u32 err_addr, err_cor_info; unsigned int err_byte, err_sector, err_device; - uint8_t err_cor_value; + u8 err_cor_value; unsigned int prev_sector = 0; u32 irq_stat; @@ -376,7 +373,7 @@ static int denali_sw_ecc_fixup(struct nand_chip *chip, static void denali_setup_dma64(struct denali_controller *denali, dma_addr_t dma_addr, int page, bool write) { - uint32_t mode; + u32 mode; const int page_count = 1; mode = DENALI_MAP10 | DENALI_BANK(denali) | page; @@ -401,7 +398,7 @@ static void denali_setup_dma64(struct denali_controller *denali, static void denali_setup_dma32(struct denali_controller *denali, dma_addr_t dma_addr, int page, bool write) { - uint32_t mode; + u32 mode; const int page_count = 1; mode = DENALI_MAP10 | DENALI_BANK(denali); @@ -650,7 +647,7 @@ static int denali_memcpy_in(void *buf, unsigned int offset, unsigned int len, return 0; } -static int denali_read_page_raw(struct nand_chip *chip, uint8_t *buf, +static int denali_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_required, int page) { struct denali_chip *dchip = to_denali_chip(chip); @@ -687,7 +684,7 @@ static int denali_memcpy_out(void *buf, unsigned int offset, unsigned int len, return 0; } -static int denali_write_page_raw(struct nand_chip *chip, const uint8_t *buf, +static int denali_write_page_raw(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { struct denali_chip *dchip = to_denali_chip(chip); @@ -761,7 +758,7 @@ static int denali_write_oob(struct nand_chip *chip, int page) return nand_prog_page_end_op(chip); } -static int denali_read_page(struct nand_chip *chip, uint8_t *buf, +static int denali_read_page(struct nand_chip *chip, u8 *buf, int oob_required, int page) { struct denali_controller *denali = to_denali_controller(chip); @@ -794,7 +791,7 @@ static int denali_read_page(struct nand_chip *chip, uint8_t *buf, return stat; } -static int denali_write_page(struct nand_chip *chip, const uint8_t *buf, +static int denali_write_page(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { struct mtd_info *mtd = nand_to_mtd(chip); @@ -813,7 +810,7 @@ static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; int addr_2_data_mask; - uint32_t tmp; + u32 tmp; timings = nand_get_sdr_timings(conf); if (IS_ERR(timings))