From patchwork Mon Aug 29 13:39:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 600950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EDE3C0502C for ; Mon, 29 Aug 2022 13:39:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230175AbiH2Nji (ORCPT ); Mon, 29 Aug 2022 09:39:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229958AbiH2Njg (ORCPT ); Mon, 29 Aug 2022 09:39:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED992915E9; Mon, 29 Aug 2022 06:39:35 -0700 (PDT) Received: from pan.home (unknown [IPv6:2a00:23c6:c311:3401:c9c8:35ca:a27e:68d0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: martyn) by madras.collabora.co.uk (Postfix) with ESMTPSA id EFEF56601EF8; Mon, 29 Aug 2022 14:39:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1661780374; bh=fl7+lflxCH9Rw0rOoUbIJKkLQbH0fp7tF0ZZogSLMl8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XWu7It+Y3R6i1jK0zlTO9mEQ5N1BRzolj3xJWDouS6D1y0nKw8sFTvMgIxFzp7UIk pbVenjrVt9+ySnAado7NKJmdH+UIibVF5QbYwSpOW8Yb+GDbaFlFTsKeUx6FyMaxKE 2lnu1ovyC19YSfNiGYOFdXkSc/nX92GnrIpSWaY9fD0SzDjHOlb4rlkyUg1JUt0R/B 7GgzNFJ5qPh8LIOmjc1HmUBarpjBWAwe4CsI2qJo7EzBc8DTofKmFY5uAsTqEyT8g2 AoYPb30Pz8ce3TdKSGpaeJCMGziXRLWQIeo+ksrRZeXt+lWpS658Bt0IB/iVSrhIkS KZg3gqQw/1CLQ== From: Martyn Welch To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski Cc: kernel@collabora.com, Martyn Welch , Krzysztof Kozlowski , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] dt-bindings: gpio: pca95xx: add entry for pcal6534 and PI4IOE5V6534Q Date: Mon, 29 Aug 2022 14:39:19 +0100 Message-Id: <20220829133923.1114555-2-martyn.welch@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220829133923.1114555-1-martyn.welch@collabora.com> References: <20220829133923.1114555-1-martyn.welch@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The NXP PCAL6534 is a 34-bit I2C I/O expander similar to the PCAL6524. The Diodes PI4IOE5V6534Q is a functionally identical chip provided by Diodes Inc. Signed-off-by: Martyn Welch --- Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml index 977b14db09b0..b8106348e025 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml @@ -16,6 +16,7 @@ description: |+ properties: compatible: enum: + - diodes,pi4ioe5v6534q - exar,xra1202 - maxim,max7310 - maxim,max7312 @@ -49,6 +50,7 @@ properties: - nxp,pca9698 - nxp,pcal6416 - nxp,pcal6524 + - nxp,pcal6534 - nxp,pcal9535 - nxp,pcal9554b - nxp,pcal9555a From patchwork Mon Aug 29 13:39:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 601296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D97D1C0502F for ; Mon, 29 Aug 2022 13:39:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229984AbiH2Njk (ORCPT ); Mon, 29 Aug 2022 09:39:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229972AbiH2Njh (ORCPT ); Mon, 29 Aug 2022 09:39:37 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B48091D0B; Mon, 29 Aug 2022 06:39:36 -0700 (PDT) Received: from pan.home (unknown [IPv6:2a00:23c6:c311:3401:c9c8:35ca:a27e:68d0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: martyn) by madras.collabora.co.uk (Postfix) with ESMTPSA id E0F706601EFD; Mon, 29 Aug 2022 14:39:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1661780375; bh=YPBC2ZGfDEC3siJavEeAXGqNt/bIFS7SELauum05Ixs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=meG8L5zNJOSYdEfGbfLU3hYjg7MKBQjnaz80UCWpzPuhQyzBfs9QrQjTJGXdvMcz1 1oCq9v2xOkS7mlahOJWdEuMUTMWFrHZHfpXEEHQPFT0X3lCWjtOk2lzTE3YRJPgL5u Qhj3VyrM+qTYo0mkQhEoC8g736YPA6LDMJ4VRzoCuviepZg93OB2JZX9XiQx5OmeiY ipQQCkPWahBV7yU2dFe0BQkDtU8tr32rjvdU+bNRldxCONKeZgRgals1WNn+xUuPP3 tjwUFNV7whPMlZBn+zaWmsPC4kDGaY5lSkHng+1PRa977sSDlrAKReeTsBARXLV7E7 b3ctpy72k4cfQ== From: Martyn Welch To: Linus Walleij , Bartosz Golaszewski Cc: kernel@collabora.com, Martyn Welch , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] gpio: pca953x: Fix pca953x_gpio_set_pull_up_down() Date: Mon, 29 Aug 2022 14:39:20 +0100 Message-Id: <20220829133923.1114555-3-martyn.welch@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220829133923.1114555-1-martyn.welch@collabora.com> References: <20220829133923.1114555-1-martyn.welch@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org A previous fix (dc87f6dd058a gpio: pca953x: Fix pca953x_gpio_set_config) identified that pinconf_to_config_param() needed to be used to isolate the config_param from the pinconf in pca953x_gpio_set_config(). This fix however did not consider that this would also be needed in pca953x_gpio_set_pull_up_down() to which it passes this config. Perform a similar call in pca953x_gpio_set_pull_up_down() to isolate the configuration parameter there as well, rather than passing it from pca953x_gpio_set_config() as the configuration argument may also be needed in pca953x_gpio_set_pull_up_down() at a later date. Signed-off-by: Martyn Welch Acked-by: Linus Walleij Reviewed-by: Andy Shevchenko --- drivers/gpio/gpio-pca953x.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index ecd7d169470b..41e7ff83a735 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -551,6 +551,7 @@ static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset); u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset); u8 bit = BIT(offset % BANK_SZ); + enum pin_config_param param = pinconf_to_config_param(config); int ret; /* @@ -563,9 +564,9 @@ static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, mutex_lock(&chip->i2c_lock); /* Configure pull-up/pull-down */ - if (config == PIN_CONFIG_BIAS_PULL_UP) + if (param == PIN_CONFIG_BIAS_PULL_UP) ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); - else if (config == PIN_CONFIG_BIAS_PULL_DOWN) + else if (param == PIN_CONFIG_BIAS_PULL_DOWN) ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); else ret = 0; @@ -573,7 +574,7 @@ static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, goto exit; /* Disable/Enable pull-up/pull-down */ - if (config == PIN_CONFIG_BIAS_DISABLE) + if (param == PIN_CONFIG_BIAS_DISABLE) ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); else ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); From patchwork Mon Aug 29 13:39:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 600949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1142ECAAD2 for ; Mon, 29 Aug 2022 13:39:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230168AbiH2Njl (ORCPT ); Mon, 29 Aug 2022 09:39:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229940AbiH2Nji (ORCPT ); Mon, 29 Aug 2022 09:39:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7264691D04; Mon, 29 Aug 2022 06:39:37 -0700 (PDT) Received: from pan.home (unknown [IPv6:2a00:23c6:c311:3401:c9c8:35ca:a27e:68d0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: martyn) by madras.collabora.co.uk (Postfix) with ESMTPSA id 163076601EF9; Mon, 29 Aug 2022 14:39:36 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1661780376; bh=MKi6iSuiyBrqjQ+i2iO51hvgrkrKFIHF32iimDWmvTo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bx7vGc1yg3TkyDEW0G0fd2HkIrZel9NQCGpm6VYa9lhNhKE5+ZnuWTizoKW4j0Sf1 f2ARunTW+xPlpKJN27H+Vk7U4tsvVjC0+3J4PSWJ1Db65gT/cxDIDxRpeL0CwmVuKD 2C4aZoEATMDd/LYRwRSC3UQEJ/1t61JFF9WvCNHxLlWvFObicyYyPyKxB9st35VCpQ UNoZE4X//QiQQuS3K6WdPIVXEezLmNKug23yaq7WpAeFxamhp8SmfNpSoRoHch3m1a SVMrLKz4m2zb55pvURr4hha1Iw4ycY23LYRJZTnYjRo/hz+73WDd8jFLlkESGpkhdd DMxuWSZ2nVUvw== From: Martyn Welch To: Linus Walleij , Bartosz Golaszewski Cc: kernel@collabora.com, Martyn Welch , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] gpio: pca953x: Swap if statements to save later complexity Date: Mon, 29 Aug 2022 14:39:21 +0100 Message-Id: <20220829133923.1114555-4-martyn.welch@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220829133923.1114555-1-martyn.welch@collabora.com> References: <20220829133923.1114555-1-martyn.welch@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org A later patch in the series adds support for a further chip type that shares some similarity with the PCA953X_TYPE. In order to keep the logic simple, swap over the if and else portions where checks are made against PCA953X_TYPE and instead check for PCA957X_TYPE. Signed-off-by: Martyn Welch Reviewed-by: Linus Walleij Reviewed-by: Andy Shevchenko --- drivers/gpio/gpio-pca953x.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 41e7ff83a735..19a8eb94a629 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -293,13 +293,13 @@ static bool pca953x_readable_register(struct device *dev, unsigned int reg) struct pca953x_chip *chip = dev_get_drvdata(dev); u32 bank; - if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { - bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | - PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; - } else { + if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; + } else { + bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | + PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; } if (chip->driver_data & PCA_PCAL) { @@ -316,12 +316,12 @@ static bool pca953x_writeable_register(struct device *dev, unsigned int reg) struct pca953x_chip *chip = dev_get_drvdata(dev); u32 bank; - if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { - bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | - PCA953x_BANK_CONFIG; - } else { + if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; + } else { + bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | + PCA953x_BANK_CONFIG; } if (chip->driver_data & PCA_PCAL) @@ -336,10 +336,10 @@ static bool pca953x_volatile_register(struct device *dev, unsigned int reg) struct pca953x_chip *chip = dev_get_drvdata(dev); u32 bank; - if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) - bank = PCA953x_BANK_INPUT; - else + if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) bank = PCA957x_BANK_INPUT; + else + bank = PCA953x_BANK_INPUT; if (chip->driver_data & PCA_PCAL) bank |= PCAL9xxx_BANK_IRQ_STAT; @@ -1069,13 +1069,12 @@ static int pca953x_probe(struct i2c_client *client, /* initialize cached registers from their original values. * we can't share this chip with another i2c master. */ - - if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) { - chip->regs = &pca953x_regs; - ret = device_pca95xx_init(chip, invert); - } else { + if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { chip->regs = &pca957x_regs; ret = device_pca957x_init(chip, invert); + } else { + chip->regs = &pca953x_regs; + ret = device_pca95xx_init(chip, invert); } if (ret) goto err_exit; From patchwork Mon Aug 29 13:39:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martyn Welch X-Patchwork-Id: 601295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94EC9ECAAD2 for ; Mon, 29 Aug 2022 13:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230211AbiH2Njn (ORCPT ); Mon, 29 Aug 2022 09:39:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230194AbiH2Njl (ORCPT ); Mon, 29 Aug 2022 09:39:41 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11D9B91D02; Mon, 29 Aug 2022 06:39:38 -0700 (PDT) Received: from pan.home (unknown [IPv6:2a00:23c6:c311:3401:c9c8:35ca:a27e:68d0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: martyn) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1ECC56601D96; Mon, 29 Aug 2022 14:39:37 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1661780377; bh=tqK6VyVv7nQ6cJ2oC9czqWTr/HZRWOMBA23Gw1mUxZA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mAE3AOYC+gswFsAlwxgQqkMa7Lu5QAHgau0zckD6S5UGl55KH8KJSEcD5SpbssP4M IkP6bqXULyUnIlOuZsRMef7Jlql32uyM3YsVrKws4rirXCs/3kgOGyQPQASP31FmtN HK2hnn63rNgkEc7bP/1XluHqJ4FrtUpO8al2JC29OyxlcUBQ99njxhVCga7UkUZ2S9 PMORd5qLhLxtrf4smDspvEpWT9n1U58ZfVGoNniqDuTwz4SO8tFEx+29qc7SXGzK82 hrKRlIGM0D6Ps2KQWAMNRPbuaUoxRp/nEHt8saKjFKZILZ5MnC9aYoU8Ox5AQGCSbB EMNtb8wxQbcWA== From: Martyn Welch To: Linus Walleij , Bartosz Golaszewski Cc: kernel@collabora.com, Martyn Welch , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] gpio: pca953x: Add support for PCAL6534 and compatible Date: Mon, 29 Aug 2022 14:39:22 +0100 Message-Id: <20220829133923.1114555-5-martyn.welch@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220829133923.1114555-1-martyn.welch@collabora.com> References: <20220829133923.1114555-1-martyn.welch@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support for the NXP PCAL6534 and Diodes Inc. PI4IOE5V6534Q. These devices, which have identical register layouts and features, are broadly a 34-bit version of the PCAL6524. However, whilst the registers are broadly what you'd expect for a 34-bit version of the PCAL6524, the spacing of the registers has been compacted. This has the unfortunate effect of breaking the bit shift based mechanism that is employed to work out register locations used by the other chips supported by this driver, resulting in special handling needing to be introduced in pca953x_recalc_addr() and pca953x_check_register(). Datasheet: https://www.nxp.com/docs/en/data-sheet/PCAL6534.pdf Datasheet: https://www.diodes.com/assets/Datasheets/PI4IOE5V6534Q.pdf Signed-off-by: Martyn Welch --- drivers/gpio/gpio-pca953x.c | 101 +++++++++++++++++++++++++++++++----- 1 file changed, 89 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 19a8eb94a629..ef1f0a603007 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -66,8 +66,10 @@ #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) #define PCA953X_TYPE BIT(12) #define PCA957X_TYPE BIT(13) +#define PCAL653X_TYPE BIT(14) #define PCA_TYPE_MASK GENMASK(15, 12) + #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) static const struct i2c_device_id pca953x_id[] = { @@ -91,6 +93,7 @@ static const struct i2c_device_id pca953x_id[] = { { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, + { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, @@ -107,6 +110,8 @@ static const struct i2c_device_id pca953x_id[] = { { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, { "xra1202", 8 | PCA953X_TYPE }, + + { "pi4ioe5v6534q", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, { } }; MODULE_DEVICE_TABLE(i2c, pca953x_id); @@ -261,20 +266,56 @@ static int pca953x_bank_shift(struct pca953x_chip *chip) * - Registers with bit 0x80 set, the AI bit * The bit is cleared and the registers fall into one of the * categories above. + * + * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow + * the same register layout as the PCAL6524, the spacing of the registers has + * been fundamentally altered by compacting them and thus does not obey the + * same rules, including being able to use bit shifting to determine bank. + * These chips hence need special handling here. */ static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, u32 checkbank) { - int bank_shift = pca953x_bank_shift(chip); - int bank = (reg & REG_ADDR_MASK) >> bank_shift; - int offset = reg & (BIT(bank_shift) - 1); + int bank; + int offset; + + if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) { + if (reg > 0x2f) { + /* + * Reserved block between 14h and 2Fh does not align on + * expected bank boundaries like other devices. + */ + int temp = reg - 0x30; + + bank = temp / NBANK(chip); + offset = temp - (bank * NBANK(chip)); + bank += 8; + } else if (reg > 0x53) { + /* Handle lack of reserved registers after output port + * configuration register to form a bank. + */ + int temp = reg - 0x54; + + bank = temp / NBANK(chip); + offset = temp - (bank * NBANK(chip)); + bank += 16; + } else { + bank = reg / NBANK(chip); + offset = reg - (bank * NBANK(chip)); + } + } else { + int bank_shift = pca953x_bank_shift(chip); - /* Special PCAL extended register check. */ - if (reg & REG_ADDR_EXT) { - if (!(chip->driver_data & PCA_PCAL)) - return false; - bank += 8; + bank = (reg & REG_ADDR_MASK) >> bank_shift; + offset = reg & (BIT(bank_shift) - 1); + + /* Special PCAL extended register check. */ + if (reg & REG_ADDR_EXT) { + if (!(chip->driver_data & PCA_PCAL)) + return false; + bank += 8; + } } /* Register is not in the matching bank. */ @@ -381,10 +422,42 @@ static const struct regmap_config pca953x_ai_i2c_regmap = { static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) { - int bank_shift = pca953x_bank_shift(chip); - int addr = (reg & PCAL_GPIO_MASK) << bank_shift; - int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; - u8 regaddr = pinctrl | addr | (off / BANK_SZ); + int addr; + int pinctrl; + u8 regaddr; + + if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) { + /* The PCAL6534 and compatible chips have altered bank alignment that doesn't + * fit within the bit shifting scheme used for other devices. + */ + addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); + + switch (reg) { + case PCAL953X_OUT_STRENGTH: + case PCAL953X_IN_LATCH: + case PCAL953X_PULL_EN: + case PCAL953X_PULL_SEL: + case PCAL953X_INT_MASK: + case PCAL953X_INT_STAT: + case PCAL953X_OUT_CONF: + pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; + break; + case PCAL6524_INT_EDGE: + case PCAL6524_INT_CLR: + case PCAL6524_IN_STATUS: + case PCAL6524_OUT_INDCONF: + case PCAL6524_DEBOUNCE: + pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; + break; + } + regaddr = pinctrl + addr + (off / BANK_SZ); + } else { + int bank_shift = pca953x_bank_shift(chip); + + addr = (reg & PCAL_GPIO_MASK) << bank_shift; + pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; + regaddr = pinctrl | addr | (off / BANK_SZ); + } return regaddr; } @@ -1215,6 +1288,7 @@ static int pca953x_resume(struct device *dev) #endif /* convenience to stop overlong match-table lines */ +#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) @@ -1239,6 +1313,7 @@ static const struct of_device_id pca953x_dt_ids[] = { { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, + { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, @@ -1261,6 +1336,8 @@ static const struct of_device_id pca953x_dt_ids[] = { { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, + + { .compatible = "diodes,pi4ioe5v6534q", .data = OF_653X(34, PCA_LATCH_INT), }, { } };