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The chips before that used APB DMA. This change works under the presumption that all chips apart from those supporting APB DMA is using GPCDMA. Signed-off-by: Akhil R Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 031c78ac42e6..954022c04cc4 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -443,11 +443,16 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) u32 *dma_buf; int err; - if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) + if (i2c_dev->is_vi) return 0; - if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { - dev_dbg(i2c_dev->dev, "DMA support not enabled\n"); + if (!i2c_dev->hw->has_apb_dma) { + if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { + dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); + return 0; + } + } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) { + dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); return 0; } From patchwork Tue Sep 6 14:47:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 603205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBBBAC6FA83 for ; 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Tue, 6 Sep 2022 07:47:50 -0700 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH v2 2/3] arm64: tegra: Add GPCDMA support for Tegra I2C Date: Tue, 6 Sep 2022 20:17:15 +0530 Message-ID: <20220906144716.16274-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220906144716.16274-1-akhilrajeev@nvidia.com> References: <20220906144716.16274-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 18263499-89f0-4be1-1d24-08da9016c8c1 X-MS-TrafficTypeDiagnostic: IA1PR12MB6601:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tGLvSLbc3p0+Dxm8PO6VuKPy3ec2wAWOqEunxhx5fK1nc9p8p8cdi6i7nOKEKF7R/zWYxHoft5Jj0zytGOJc8k8pGF2lM87N8ME2qhfXWCFYDfjtzCvntLP5EkmnfBYYWuNs4UEphQt22QvFibcDGIT6mJ9LOcoIbP7WxEivtuvdUKT21WTSmy5DhXSXjIlOwBLlNgEuULFm6uK2D8yXISQ9dcnDeiA59dgfti1bkP6KzwwJz00xsV29EYT8XSDRN5IAxojdzzGMc2oom7RqJCDS0Nmi0UNq6SopRok45+VEsIokoTgCn7VUfbUJOLgXg8LpNhZel2TGXjdSJa5UsEmSdVeKNOfHLLh8rRSqjjikSfAHdEOpAc5nyy1tRsjBDwnLH0IQ1nxTNLXQeX0gAIqg8+dS0J3eF9CMwxQJEcV6cMNXZAcMYNfqx2NIj0F9WE0lgavD1MLohSf1BZKlnSKbLv7eUCvsMw0Bvqe7VGH23ay9GbCxrhopt04rAuXBrrbtYxjaonAkT7JeYw1T8P8Q7Y5cnlkAnROTV4nua+A2IIbuc6OYOcYwYjn8n72UblxloHT23Pker0nSMTITtZpCzgZbLREqQg+450dqSI4FY+LqJIgF8MUs4RIl6vhf7x4VYnyarLn3hg0MPF6KH5T2a+jWDisX06ELkbcoYHscXAfmpjLTzejtD7BiiMfBwn0ex+Wg465P3mnWQhx953yAGlnF24n4vewefHgjxXY6KkIT1v1kVPAl4duMU/7l7D1rbb7Lw1WP3Yc7jJtYs6S4qhEfiPmlKP/l+UqRJUu1ocOwTgijaDAz0cqbFpvSibiAYl1r6fvFmYS7LIjRRzU5+dpNRJQXKYA/vre4xyRp1eCluRsTbLKtlaDRBReR X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(136003)(396003)(39860400002)(346002)(376002)(46966006)(40470700004)(36840700001)(8676002)(356005)(921005)(41300700001)(2906002)(36860700001)(1076003)(36756003)(7696005)(81166007)(2616005)(336012)(316002)(110136005)(82310400005)(186003)(82740400003)(83380400001)(107886003)(8936002)(5660300002)(47076005)(70586007)(40460700003)(426003)(70206006)(86362001)(26005)(4326008)(7416002)(6666004)(478600001)(40480700001)(36900700001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2022 14:47:55.6875 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18263499-89f0-4be1-1d24-08da9016c8c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6601 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 32 ++++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 32 ++++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 ++++++++++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 59a10fb184f8..3580fbf99091 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -672,6 +672,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C1>; reset-names = "i2c"; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 21>, <&gpcdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -685,6 +689,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C3>; reset-names = "i2c"; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 23>, <&gpcdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -702,6 +710,10 @@ pinctrl-names = "default", "idle"; pinctrl-0 = <&state_dpaux1_i2c>; pinctrl-1 = <&state_dpaux1_off>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 26>, <&gpcdma 26>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -733,6 +745,10 @@ pinctrl-names = "default", "idle"; pinctrl-0 = <&state_dpaux_i2c>; pinctrl-1 = <&state_dpaux_off>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 30>, <&gpcdma 30>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -746,6 +762,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C7>; reset-names = "i2c"; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 27>, <&gpcdma 27>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -759,6 +779,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C9>; reset-names = "i2c"; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 31>, <&gpcdma 31>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1176,6 +1200,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C2>; reset-names = "i2c"; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 22>, <&gpcdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1189,6 +1217,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C8>; reset-names = "i2c"; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 0>, <&gpcdma 0>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d0ed55e5c860..9176c4b27133 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -805,6 +805,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C1>; reset-names = "i2c"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 21>, <&gpcdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -830,6 +834,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C3>; reset-names = "i2c"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 23>, <&gpcdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -847,6 +855,10 @@ pinctrl-0 = <&state_dpaux1_i2c>; pinctrl-1 = <&state_dpaux1_off>; pinctrl-names = "default", "idle"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 26>, <&gpcdma 26>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -864,6 +876,10 @@ pinctrl-0 = <&state_dpaux0_i2c>; pinctrl-1 = <&state_dpaux0_off>; pinctrl-names = "default", "idle"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 30>, <&gpcdma 30>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -881,6 +897,10 @@ pinctrl-0 = <&state_dpaux2_i2c>; pinctrl-1 = <&state_dpaux2_off>; pinctrl-names = "default", "idle"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 27>, <&gpcdma 27>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -898,6 +918,10 @@ pinctrl-0 = <&state_dpaux3_i2c>; pinctrl-1 = <&state_dpaux3_off>; pinctrl-names = "default", "idle"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 31>, <&gpcdma 31>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1565,6 +1589,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C2>; reset-names = "i2c"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 22>, <&gpcdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1578,6 +1606,10 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C8>; reset-names = "i2c"; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + dmas = <&gpcdma 0>, <&gpcdma 0>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 81a0f599685f..5852e765ad90 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -737,6 +737,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C1>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 21>, <&gpcdma 21>; + dma-names = "rx", "tx"; }; cam_i2c: i2c@3180000 { @@ -752,6 +756,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C3>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 23>, <&gpcdma 23>; + dma-names = "rx", "tx"; }; dp_aux_ch1_i2c: i2c@3190000 { @@ -767,6 +775,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C4>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 26>, <&gpcdma 26>; + dma-names = "rx", "tx"; }; dp_aux_ch0_i2c: i2c@31b0000 { @@ -782,6 +794,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C6>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 30>, <&gpcdma 30>; + dma-names = "rx", "tx"; }; dp_aux_ch2_i2c: i2c@31c0000 { @@ -797,6 +813,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C7>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 27>, <&gpcdma 27>; + dma-names = "rx", "tx"; }; dp_aux_ch3_i2c: i2c@31e0000 { @@ -812,6 +832,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C9>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 31>, <&gpcdma 31>; + dma-names = "rx", "tx"; }; spi@3270000 { @@ -1109,6 +1133,10 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C2>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 22>, <&gpcdma 22>; + dma-names = "rx", "tx"; }; gen8_i2c: i2c@c250000 { @@ -1125,6 +1153,10 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C8>; reset-names = "i2c"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + dmas = <&gpcdma 0>, <&gpcdma 0>; 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This would avoid the potential long delay probe deferral can cause. Signed-off-by: Akhil R --- arch/arm64/configs/defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d5b2d2dd4904..9e8c532126aa 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -995,7 +995,7 @@ CONFIG_MV_XOR=y CONFIG_MV_XOR_V2=y CONFIG_OWL_DMA=y CONFIG_PL330_DMA=y -CONFIG_TEGRA186_GPC_DMA=m +CONFIG_TEGRA186_GPC_DMA=y CONFIG_TEGRA20_APB_DMA=y CONFIG_TEGRA210_ADMA=m CONFIG_QCOM_BAM_DMA=y