From patchwork Sat Sep 10 01:11:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 604599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBF63C6FA82 for ; Sat, 10 Sep 2022 01:11:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230181AbiIJBLp (ORCPT ); Fri, 9 Sep 2022 21:11:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230387AbiIJBLj (ORCPT ); Fri, 9 Sep 2022 21:11:39 -0400 Received: from mail-io1-xd2b.google.com (mail-io1-xd2b.google.com [IPv6:2607:f8b0:4864:20::d2b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9371FC678 for ; Fri, 9 Sep 2022 18:11:36 -0700 (PDT) Received: by mail-io1-xd2b.google.com with SMTP id i80so333082ioa.13 for ; Fri, 09 Sep 2022 18:11:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=8IhN48uB19RDEOY3f6Cdr9YhMwFwA3ArVNn1nzV0N/4=; b=O7S4EymRcbI05VmHJr6NW11/lwMC5FbhqvY2vAp2D5a0CQXnJkF2g0eu8QTvmxqQ7t zqMDTC70c/jZHx0eXfxXAieBYq9XfY9cvss7EKZerrMtHBUDdZ3tb4k20B8oFfqBNJFL DbgIM8cS18QF1p8gmQy4Qv3BMuRFH8f9LVzKCT+fvi+DcIcLMoI2faRDRYtNrTX+rp3n ++ZTQjyn5KNkK19xm/efSx5IBNmGDO8I0kmozVnw/JRbbMaWS5Q5UZ6k++oEPA0Hss3F HTwFX6qv90m50uRQIUXi7KLkATp0cefDZIMRXem6XsbzH/br9K6Btw+UZFs6Gx3qM03R shPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=8IhN48uB19RDEOY3f6Cdr9YhMwFwA3ArVNn1nzV0N/4=; b=VZil/8KVZ4XreBQu+ndpHtbPve5W3hCkCs40UM4Mbc1XChyU8H+2UJhckc3jUGBZC8 f173Wc3MZRBqlsNs8IsEB4ofckhzEExltm1go0O5lhfx4MrsJ+/QyciFGdzhuRuyFhuq Qa35N3i/eQXm6QBNTY6tuRxYhE1Y0W65PeH6yiQSHnUCA/Z/gBZUGbtz8uG6Ssvj4awM aTMT0O4nAqguhrxlqDoM/w8ZvhcRa0VdzJ+VGTKyXILM7lYOszDH7YUsCrveSO23WQRW oehEAQT9AtQDp0GeHjjfqDme6oypPFJCahEAVg6bfQvnZRTgtC8OSGxx13CSVqEINntL 3ymA== X-Gm-Message-State: ACgBeo1ya8lZDEdLtbq52TAgSscoPc8jFhiBN4UI9nM2UklPgmIce4QC ax8Cx0fBIZ3wC6RDYch6cDLnJw== X-Google-Smtp-Source: AA6agR4Nk1FGVTEk4Yco6UNP9NTI27B1EOIv+0+KFBhCKO/i6nfwF1gtuY+Vy1t4nU+K4oYnXcjssg== X-Received: by 2002:a05:6602:2d41:b0:688:e962:2b53 with SMTP id d1-20020a0566022d4100b00688e9622b53mr8001330iow.79.1662772295979; Fri, 09 Sep 2022 18:11:35 -0700 (PDT) Received: from presto.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id u133-20020a02238b000000b00348e1a6491asm733064jau.137.2022.09.09.18.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 18:11:35 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/6] net: ipa: don't define unneeded GSI register offsets Date: Fri, 9 Sep 2022 20:11:26 -0500 Message-Id: <20220910011131.1431934-2-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220910011131.1431934-1-elder@linaro.org> References: <20220910011131.1431934-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Each GSI execution environment (EE) is able to access many of the GSI registers associated with the other EEs. A block of GSI registers is contained within a region of memory, and an EE's register offset can be determined by adding the register's base offset to the product of the EE ID and a fixed constant. Despite this possibility, the AP IPA code *never* accesses any GSI registers other than its own. So there's no need to define the macros that compute register offsets for other EEs. Redefine the AP access macros to compute the offset the way the more general "any EE" macro would, and get rid of the unneeded macros. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi_reg.h | 208 ++++++++++---------------------------- 1 file changed, 52 insertions(+), 156 deletions(-) diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 5bd8b31656d30..b36fd10a57d69 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -55,14 +55,10 @@ /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ #define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \ - GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \ - (0x0000c020 + 0x1000 * (ee)) + (0x0000c020 + 0x1000 * GSI_EE_AP) #define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \ - GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ - (0x0000c024 + 0x1000 * (ee)) + (0x0000c024 + 0x1000 * GSI_EE_AP) /* All other register offsets are relative to gsi->virt */ @@ -81,9 +77,7 @@ enum gsi_channel_type { }; #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ - GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \ - (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) #define CHTYPE_DIR_FMASK GENMASK(3, 3) #define EE_FMASK GENMASK(7, 4) @@ -112,9 +106,7 @@ chtype_protocol_encoded(enum ipa_version version, enum gsi_channel_type type) } #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ - GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \ - (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) /* Encoded value for CH_C_CNTXT_1 register R_LENGTH field */ static inline u32 r_length_encoded(enum ipa_version version, u32 length) @@ -125,19 +117,13 @@ static inline u32 r_length_encoded(enum ipa_version version, u32 length) } #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ - GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \ - (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ - GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \ - (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c00c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define GSI_CH_C_QOS_OFFSET(ch) \ - GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \ - (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c05c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define WRR_WEIGHT_FMASK GENMASK(3, 0) #define MAX_PREFETCH_FMASK GENMASK(8, 8) #define USE_DB_ENG_FMASK GENMASK(9, 9) @@ -158,29 +144,19 @@ enum gsi_prefetch_mode { }; #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ - GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \ - (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c060 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ - GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \ - (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c064 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ - GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \ - (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c068 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ - GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \ - (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch)) + (0x0001c06c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \ - (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ #define EV_CHTYPE_FMASK GENMASK(3, 0) #define EV_EE_FMASK GENMASK(7, 4) @@ -190,9 +166,7 @@ enum gsi_prefetch_mode { #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \ - (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) /* Encoded value for EV_CH_C_CNTXT_1 register EV_R_LENGTH field */ static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length) { @@ -202,83 +176,53 @@ static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length) } #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \ - (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \ - (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d00c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \ - (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d010 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \ - (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d020 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define MODT_FMASK GENMASK(15, 0) #define MODC_FMASK GENMASK(23, 16) #define MOD_CNT_FMASK GENMASK(31, 24) #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \ - (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d024 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \ - (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d028 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \ - (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d02c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \ - (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d030 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \ - (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d034 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \ - (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d048 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \ - (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev)) + (0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ - GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP) -#define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \ - (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch)) + (0x0001e000 + 0x4000 * GSI_EE_AP + 0x08 * (ch)) #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ - GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP) -#define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \ - (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev)) + (0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev)) #define GSI_GSI_STATUS_OFFSET \ - GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP) -#define GSI_EE_N_GSI_STATUS_OFFSET(ee) \ - (0x0001f000 + 0x4000 * (ee)) + (0x0001f000 + 0x4000 * GSI_EE_AP) #define ENABLED_FMASK GENMASK(0, 0) #define GSI_CH_CMD_OFFSET \ - GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CH_CMD_OFFSET(ee) \ - (0x0001f008 + 0x4000 * (ee)) + (0x0001f008 + 0x4000 * GSI_EE_AP) #define CH_CHID_FMASK GENMASK(7, 0) #define CH_OPCODE_FMASK GENMASK(31, 24) @@ -293,9 +237,7 @@ enum gsi_ch_cmd_opcode { }; #define GSI_EV_CH_CMD_OFFSET \ - GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) -#define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \ - (0x0001f010 + 0x4000 * (ee)) + (0x0001f010 + 0x4000 * GSI_EE_AP) #define EV_CHID_FMASK GENMASK(7, 0) #define EV_OPCODE_FMASK GENMASK(31, 24) @@ -307,9 +249,7 @@ enum gsi_evt_cmd_opcode { }; #define GSI_GENERIC_CMD_OFFSET \ - GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) -#define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \ - (0x0001f018 + 0x4000 * (ee)) + (0x0001f018 + 0x4000 * GSI_EE_AP) #define GENERIC_OPCODE_FMASK GENMASK(4, 0) #define GENERIC_CHID_FMASK GENMASK(9, 5) #define GENERIC_EE_FMASK GENMASK(13, 10) @@ -326,9 +266,7 @@ enum gsi_generic_cmd_opcode { /* The next register is present for IPA v3.5.1 and above */ #define GSI_GSI_HW_PARAM_2_OFFSET \ - GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) -#define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ - (0x0001f040 + 0x4000 * (ee)) + (0x0001f040 + 0x4000 * GSI_EE_AP) #define IRAM_SIZE_FMASK GENMASK(2, 0) #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) @@ -357,13 +295,9 @@ enum gsi_iram_size { /* IRQ condition for each type is cleared by writing type-specific register */ #define GSI_CNTXT_TYPE_IRQ_OFFSET \ - GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ - (0x0001f080 + 0x4000 * (ee)) + (0x0001f080 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ - GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ - (0x0001f088 + 0x4000 * (ee)) + (0x0001f088 + 0x4000 * GSI_EE_AP) /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ enum gsi_irq_type_id { @@ -377,62 +311,38 @@ enum gsi_irq_type_id { }; #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ - GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \ - (0x0001f090 + 0x4000 * (ee)) + (0x0001f090 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ - GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \ - (0x0001f094 + 0x4000 * (ee)) + (0x0001f094 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ - GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \ - (0x0001f098 + 0x4000 * (ee)) + (0x0001f098 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ - GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ - (0x0001f09c + 0x4000 * (ee)) + (0x0001f09c + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ - GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \ - (0x0001f0a0 + 0x4000 * (ee)) + (0x0001f0a0 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ - GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ - (0x0001f0a4 + 0x4000 * (ee)) + (0x0001f0a4 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ - GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \ - (0x0001f0b0 + 0x4000 * (ee)) + (0x0001f0b0 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ - GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \ - (0x0001f0b8 + 0x4000 * (ee)) + (0x0001f0b8 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ - GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \ - (0x0001f0c0 + 0x4000 * (ee)) + (0x0001f0c0 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ - GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ - (0x0001f100 + 0x4000 * (ee)) + (0x0001f100 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ - GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ - (0x0001f108 + 0x4000 * (ee)) + (0x0001f108 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ - GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ - (0x0001f110 + 0x4000 * (ee)) + (0x0001f110 + 0x4000 * GSI_EE_AP) /* Values here are bit positions in the GLOB_IRQ_* registers */ enum gsi_global_irq_id { ERROR_INT = 0x0, @@ -442,17 +352,11 @@ enum gsi_global_irq_id { }; #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ - GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ - (0x0001f118 + 0x4000 * (ee)) + (0x0001f118 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ - GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ - (0x0001f120 + 0x4000 * (ee)) + (0x0001f120 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ - GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ - (0x0001f128 + 0x4000 * (ee)) + (0x0001f128 + 0x4000 * GSI_EE_AP) /* Values here are bit positions in the (general) GSI_IRQ_* registers */ enum gsi_general_id { BREAK_POINT = 0x0, @@ -462,15 +366,11 @@ enum gsi_general_id { }; #define GSI_CNTXT_INTSET_OFFSET \ - GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \ - (0x0001f180 + 0x4000 * (ee)) + (0x0001f180 + 0x4000 * GSI_EE_AP) #define INTYPE_FMASK GENMASK(0, 0) #define GSI_ERROR_LOG_OFFSET \ - GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP) -#define GSI_EE_N_ERROR_LOG_OFFSET(ee) \ - (0x0001f200 + 0x4000 * (ee)) + (0x0001f200 + 0x4000 * GSI_EE_AP) /* Fields below are present for IPA v3.5.1 and above */ #define ERR_ARG3_FMASK GENMASK(3, 0) @@ -501,14 +401,10 @@ enum gsi_err_type { }; #define GSI_ERROR_LOG_CLR_OFFSET \ - GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) -#define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \ - (0x0001f210 + 0x4000 * (ee)) + (0x0001f210 + 0x4000 * GSI_EE_AP) #define GSI_CNTXT_SCRATCH_0_OFFSET \ - GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP) -#define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \ - (0x0001f400 + 0x4000 * (ee)) + (0x0001f400 + 0x4000 * GSI_EE_AP) #define INTER_EE_RESULT_FMASK GENMASK(2, 0) #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) From patchwork Sat Sep 10 01:11:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 604598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89023C6FA82 for ; Sat, 10 Sep 2022 01:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229767AbiIJBLq (ORCPT ); Fri, 9 Sep 2022 21:11:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230423AbiIJBLj (ORCPT ); Fri, 9 Sep 2022 21:11:39 -0400 Received: from mail-il1-x136.google.com (mail-il1-x136.google.com [IPv6:2607:f8b0:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEB59FC67F for ; Fri, 9 Sep 2022 18:11:38 -0700 (PDT) Received: by mail-il1-x136.google.com with SMTP id h14so1662846ilh.10 for ; Fri, 09 Sep 2022 18:11:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=/KJRsDXkQlnFmQZPViyIwBLDjtPmSnCqlK5jU9YX2n0=; b=lQfqa/l/qX4f9tLNKKXIC1QFajURv47Df3DMvCOq88Z1BF0DcuiIlJzH7X3FkNAwDS L9AAXEx1oN911qhjxEsfgiJ7l/XL27k2QUuf+sl7dbpNyyOlzZHlOes6mf7GYBmKoSSW rLTRQJ4XzMQMCTKBjCDbn6URJzkFUxsceANAil1kbBGdXttBKck9OvrDkdSL6tk7kqMb 1N19EcCx/DtZ5Xe/QsxjbOc7HkqWr9rTFfHpnpBDGfprfICFLBjGDRPVM9gnHlwwqKZD Yr5XOMWBa1OKwNKR1vAv83KqF1JD70JdeeIAZoCmTpTzEZ+X26dylfAUoSBcwvQBY+CQ JtZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=/KJRsDXkQlnFmQZPViyIwBLDjtPmSnCqlK5jU9YX2n0=; b=AwJ09h5c8zbCY3TqAk5OYAJCvi45H/hUhP0kzVI/P8rKjfwsTkg2CVlBjSnl0FAXzp j/X3HdQfo5u9ByjRrnhhLtq+fsjzku65RBj4h42ic22Fx2bzY0Gl3pH39wJaOBfTEAzf IWvhvtzbh9T6HGHM9co0RjhjgPrzZBAJZ+FK5mvu4muq5EPigRFKx9Kcb5d8m9aaNUEo hAICPO7SDxuCmGMmlVG07ybwmu91MpWMk7U+ubjFMHiBmGQ0Qm9BHrbWqzHlLJ0lIVl8 /v9TVhuCFUfbNxvKkrQk1utpAfQFOrzapCJMAgOAMl0YbMK4dDTOwvytXUpWLh03/579 Sc8Q== X-Gm-Message-State: ACgBeo0ITj0CiCLVhN3D4S6O3KFm9+1zQNYWwmC4sZ24ZA1sokwReOM6 KXp7EMzq9MTUE0BpFxxM4n0Png== X-Google-Smtp-Source: AA6agR7t3Jdqc+4WFwfocgHR6svPY/UXN839YEsNqTRzYXeuzZOL69PYSS//B/NtZUS/MK6vWAxN/g== X-Received: by 2002:a05:6e02:667:b0:2e6:9b52:3426 with SMTP id l7-20020a056e02066700b002e69b523426mr5421635ilt.318.1662772298032; Fri, 09 Sep 2022 18:11:38 -0700 (PDT) Received: from presto.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id u133-20020a02238b000000b00348e1a6491asm733064jau.137.2022.09.09.18.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 18:11:37 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/6] net: ipa: move and redefine ipa_version_valid() Date: Fri, 9 Sep 2022 20:11:28 -0500 Message-Id: <20220910011131.1431934-4-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220910011131.1431934-1-elder@linaro.org> References: <20220910011131.1431934-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the definition of ipa_version_valid(), making it a static inline function defined together with the enumerated type in "ipa_version.h". Define a new count value in the type. Rename the function to be ipa_version_supported(), and have it return true only if the IPA version supplied is explicitly supported by the driver. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_main.c | 25 ++----------------------- drivers/net/ipa/ipa_version.h | 20 ++++++++++++++++++-- 2 files changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 32962d885acd5..9dfa7f58a207f 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -616,27 +616,6 @@ static void ipa_validate_build(void) field_max(AGGR_GRANULARITY_FMASK)); } -static bool ipa_version_valid(enum ipa_version version) -{ - switch (version) { - case IPA_VERSION_3_0: - case IPA_VERSION_3_1: - case IPA_VERSION_3_5: - case IPA_VERSION_3_5_1: - case IPA_VERSION_4_0: - case IPA_VERSION_4_1: - case IPA_VERSION_4_2: - case IPA_VERSION_4_5: - case IPA_VERSION_4_7: - case IPA_VERSION_4_9: - case IPA_VERSION_4_11: - return true; - - default: - return false; - } -} - /** * ipa_probe() - IPA platform driver probe function * @pdev: Platform device pointer @@ -678,8 +657,8 @@ static int ipa_probe(struct platform_device *pdev) return -ENODEV; } - if (!ipa_version_valid(data->version)) { - dev_err(dev, "invalid IPA version\n"); + if (!ipa_version_supported(data->version)) { + dev_err(dev, "unsupported IPA version %u\n", data->version); return -EINVAL; } diff --git a/drivers/net/ipa/ipa_version.h b/drivers/net/ipa/ipa_version.h index 852d6cbc87758..58f7b43b4db3b 100644 --- a/drivers/net/ipa/ipa_version.h +++ b/drivers/net/ipa/ipa_version.h @@ -19,10 +19,10 @@ * @IPA_VERSION_4_7: IPA version 4.7/GSI version 2.7 * @IPA_VERSION_4_9: IPA version 4.9/GSI version 2.9 * @IPA_VERSION_4_11: IPA version 4.11/GSI version 2.11 (2.1.1) + * @IPA_VERSION_COUNT: Number of defined IPA versions * * Defines the version of IPA (and GSI) hardware present on the platform. - * Please update ipa_version_valid() and ipa_version_string() whenever a - * new version is added. + * Please update ipa_version_string() whenever a new version is added. */ enum ipa_version { IPA_VERSION_3_0, @@ -36,8 +36,24 @@ enum ipa_version { IPA_VERSION_4_7, IPA_VERSION_4_9, IPA_VERSION_4_11, + IPA_VERSION_COUNT, /* Last; not a version */ }; +static inline bool ipa_version_supported(enum ipa_version version) +{ + switch (version) { + case IPA_VERSION_3_1: + case IPA_VERSION_3_5_1: + case IPA_VERSION_4_2: + case IPA_VERSION_4_5: + case IPA_VERSION_4_9: + case IPA_VERSION_4_11: + return true; + default: + return false; + } +} + /* Execution environment IDs */ enum gsi_ee_id { GSI_EE_AP = 0x0, From patchwork Sat Sep 10 01:11:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 604597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 011D1C6FA86 for ; Sat, 10 Sep 2022 01:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231365AbiIJBMR (ORCPT ); Fri, 9 Sep 2022 21:12:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230526AbiIJBLp (ORCPT ); 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Fri, 09 Sep 2022 18:11:40 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 6/6] net: ipa: fix two symbol names Date: Fri, 9 Sep 2022 20:11:31 -0500 Message-Id: <20220910011131.1431934-7-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220910011131.1431934-1-elder@linaro.org> References: <20220910011131.1431934-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All field mask symbols are defined with a "_FMASK" suffix, but EOT_COAL_GRANULARITY and DRBIP_ACL_ENABLE are defined without one. Fix that. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index b7b7fb553c445..3e24bddc682ef 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -254,7 +254,7 @@ static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, /* The next register is not present for IPA v4.5+ */ #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 /* The next field is not present for IPA v3.5+ */ -#define EOT_COAL_GRANULARITY GENMASK(3, 0) +#define EOT_COAL_GRANULARITY_FMASK GENMASK(3, 0) #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) /* The next register is present for IPA v3.5+ */ @@ -470,7 +470,7 @@ static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, /* The next field is not present for IPA v4.5+ */ #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) /* The next field is present for IPA v4.9+ */ -#define DRBIP_ACL_ENABLE GENMASK(30, 30) +#define DRBIP_ACL_ENABLE_FMASK GENMASK(30, 30) /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ enum ipa_mode {