From patchwork Sat Sep 10 14:32:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 604637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E19B2C6FA8B for ; Sat, 10 Sep 2022 14:32:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229587AbiIJOcS (ORCPT ); Sat, 10 Sep 2022 10:32:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229464AbiIJOcR (ORCPT ); Sat, 10 Sep 2022 10:32:17 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B4733BC6B; Sat, 10 Sep 2022 07:32:16 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id c2-20020a1c3502000000b003b2973dafb7so7069902wma.2; Sat, 10 Sep 2022 07:32:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=tfOkC7rAMPVTo8l6wnriy72fNtCnhfwJaZ8s4WJI0B8=; b=n8nSAEALjBXhAavns6HFURS85wmN13q1y+qmsxBjPJ43v0PqEFfsAxQuR5Iy8/x0zl cITDJVfWws8ULaiLz4tW7YHqAOq9+Bd7n3gCv1EPSjffN6Fcx2ct04zEVy6BQVgceuv9 N8ujhqW90A6JjdfxknLAJA7yMSIpEz3BUNw6uai9Yj+JcvxrSCGlDxz+OXQnyaC419Bb O6QV2S8ig6X0CoOrnH7pHGJde4ewvxTQ4d466DUW4Vn4GLoMtQ3mqlzHPw5I4vGpmzSP LjUoipfIO5s8MXvO3w0hyeOmxbg7jYN3xUjBKw3XxXuqZI5p5CsnYbGOSxoUqF29kQ7K CyJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=tfOkC7rAMPVTo8l6wnriy72fNtCnhfwJaZ8s4WJI0B8=; b=8Ce5IWwIojGPwVWlFkUzFvXTEifqD0hsi7kXThJ7cnHlf6wioDmiULsTS1yfW+JSAd bfAbx8xvBJ6s3Wm/8uP+0InPES1btupFQe6i1wSmy1XpP7TIwnbNtlxvpK9mdHeu64UH 7FXOhtZW9hEGEe1PkgUIqiYPPZyaIu5uGln9qoy8R6vhnJ6/wFGO81ovhWi5rvaPQ27s EIKB9M3Ki/dbi1qOSFaPXknWN57+IoVmWk/UDWGsTtXmzSbB00gCC7XF+vA1j+q/KPBo NbYkhbZMWV6y/w7YITF1At9w8yNO4QHjyMP/yF2At8PIYXsw5cfouqvTBmtgfSkzsW6C 8acQ== X-Gm-Message-State: ACgBeo0q3dybNvJtbrVDbQcN6K9SHuyb0e2jhu0Hi6uaEBo6+gxWzLyx b+o3WpcnFN+M/Syf0NZZO68= X-Google-Smtp-Source: AA6agR5SLFVky//jqgsiUiCiDK8+7Q9F7etZ5Dju4IdzM2C0i5p0RF+Jz0PV1oGZtEbYLqEXJujqQw== X-Received: by 2002:a05:600c:2181:b0:3b4:74e4:16f8 with SMTP id e1-20020a05600c218100b003b474e416f8mr1394617wme.174.1662820334801; Sat, 10 Sep 2022 07:32:14 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id v11-20020adff68b000000b0021e5adb92desm2939565wrp.60.2022.09.10.07.32.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Sep 2022 07:32:14 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Alim Akhtar , Avri Altman , Bart Van Assche , Krzysztof Kozlowski , linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/9] dt-bindings: ufs: qcom: Add sm6115 binding Date: Sat, 10 Sep 2022 17:32:05 +0300 Message-Id: <20220910143213.477261-2-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220910143213.477261-1-iskren.chernev@gmail.com> References: <20220910143213.477261-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SM6115 UFS to DT schema. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index f2d6298d926c..b517d76215e3 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -28,6 +28,7 @@ properties: - qcom,msm8998-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc + - qcom,sm6115-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - qcom,sm8250-ufshc @@ -178,6 +179,31 @@ allOf: minItems: 1 maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-ufshc + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: ice_core_clk + reg: + minItems: 2 + maxItems: 2 + # TODO: define clock bindings for qcom,msm8994-ufshc unevaluatedProperties: false From patchwork Sat Sep 10 14:32:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 604636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6E10C6FA8B for ; Sat, 10 Sep 2022 14:32:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229639AbiIJOc0 (ORCPT ); Sat, 10 Sep 2022 10:32:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229628AbiIJOcY (ORCPT ); Sat, 10 Sep 2022 10:32:24 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4ACAA3F1C0; Sat, 10 Sep 2022 07:32:22 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id n23-20020a7bc5d7000000b003a62f19b453so7065910wmk.3; Sat, 10 Sep 2022 07:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=EneIXY/B5LBT5BBbtyztaHF9mjVl7aiyd+xPwT0PgL0=; b=YxkJN1KztGkCir4zCR9DpON6tjppUXTo83/S4W1M+hgd6rBHAbU+/3dyadpRwNSbkp 5NUrEhvPAcp5hWXDKx+g+STrWre34p2OY+8QarZSsuMFqOy71TNJbhTpgVoutjZmqZQR x8QWqBMO0eMH01k63x/uKXsq9oSb8gwxtmcUJ+mvK7oAteQ6I+ziQH4o59eaMqWzN/0g VOulgjNxNwtol3qFCOmv40A7M3qcSo1hTOl4uHPl3S0UzwEkvF7RpMRiRo36y1lFlaW2 /y+5qiw48JvnNceppbWKKPZcdHkDHQ6w6/Fct47W5KNaT5+m2rb1Sv7t6uAIutZEvH/Z 1wFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=EneIXY/B5LBT5BBbtyztaHF9mjVl7aiyd+xPwT0PgL0=; b=prhcZXQsXB/mJPriP+ZZtUINGi64RnOpRHzSTa7KuYzhwBurHU0pcqgUBdBl4rpydD tcEablexeZwQ4d9YcP4qjaThhg/MigmTLRf0FAnPETupjD8cj9jOTaiQx5qLLrq+St6P vjUJ7pjaDfjQecv+Vry0QT9cmgk4lMOQmY7GLtXMKezQaJW+kuHy7goJAzu1eWooVdy4 SIHQ5KNIEsHVy2ES693aQ9XeJyMBOR7fX9Q8rj6o/KxycFL8DyhQxXuHACgoPQXgiCI2 jw8kfADjYOp7eJzaQ8g+pKNkiAz4SKcZu9Rq8AIhI57SytgBp4rYDLchLkJNhyjmo1sZ IqAQ== X-Gm-Message-State: ACgBeo3xnxu5UcDtlcTRtif7vPf/iztLBYawoqitlviIkpM0DTcWl7Rf quHiE3j2NGFaOjzE7U645kg= X-Google-Smtp-Source: AA6agR6FptnQU7TepK9E8qa/NAxIBA1fiR1Px3U3q7yEkMKOHZy+/eXvTspoHH7b+on/dmhvyZjH1g== X-Received: by 2002:a05:600c:4e92:b0:3a5:fd90:24e3 with SMTP id f18-20020a05600c4e9200b003a5fd9024e3mr8795831wmq.59.1662820340712; Sat, 10 Sep 2022 07:32:20 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id p3-20020a05600c430300b003a5dbdea6a8sm4354253wme.27.2022.09.10.07.32.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Sep 2022 07:32:20 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Caleb Connolly , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v3 3/9] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Date: Sat, 10 Sep 2022 17:32:07 +0300 Message-Id: <20220910143213.477261-4-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220910143213.477261-1-iskren.chernev@gmail.com> References: <20220910143213.477261-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org oneplus,billie2 (OnePlus Nord N100) is based on QualComm Snapdragon SM4250 SoC. Add support for the same in dt-bindings. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Caleb Connolly --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 9cd798810eff..377bfb21cbc8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -54,6 +54,8 @@ description: | sdm845 sdx55 sdx65 + sm4250 + sm6115 sm6125 sm6350 sm7225 @@ -680,6 +682,11 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - oneplus,billie2 + - const: qcom,sm4250 + - items: - enum: - sony,pdx201 From patchwork Sat Sep 10 14:32:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 604635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B0E6C6FA86 for ; Sat, 10 Sep 2022 14:32:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229699AbiIJOcg (ORCPT ); Sat, 10 Sep 2022 10:32:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229668AbiIJOc3 (ORCPT ); Sat, 10 Sep 2022 10:32:29 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D0593C15B; Sat, 10 Sep 2022 07:32:26 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id e16so7846379wrx.7; Sat, 10 Sep 2022 07:32:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ri5En/fDJnZs9/fgpIxN7nIJmyjfgpQ1FdIzzVX5B3I=; b=GDmsmw1nMyyrhBDISv4WWbTZCjtK0xybNcqoP3gO8yYgIzH5fd/E1CgqTCsaplnVAv KcwOL0qju7hgMGKOFTpff9HDIkfnYOl5ty0Kc4dFV8KD6YA3KiK5DAR4EJ8OhjAiuZmz L0IIZwHajCuwIXt7uzuSiflExeX68kalvhdz1IN6Euw0mE7xNV3i4gH7WQl0Z4x3BRRh /HlztyT/ZnELNZRLcOoSJHS+HzgMygmG3ueSmS/QOQGAmY4L+4Vi70akS85+26hMu7dd /e4rbRmUf4YOoqcETGzGBN4k+isXEDwHJ32soLlc8R2oV+ILymKf4Y8p5/rUI5JOl9eO ZBJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ri5En/fDJnZs9/fgpIxN7nIJmyjfgpQ1FdIzzVX5B3I=; b=Jg+djW7EfRfLMhvqjd9ab68fpdaXEiRYwUPGYnZdUcoBNCO+R+Tl68IalVwXc0F1Ug r2X73UqkuaUj/c4Rp1r4hUst+q8KtnCeSaW8cEHWLx6GsSfVE3WmSx80AeGR8ilemlYY cBBavBpyIkL3eN55LI6ueVo6woS3ABlqyBtJbboVxpYVfuhvG9Gf6b0vyHAH133kLMzJ dSkTmaSZTzclF6ZbbSQnn4eHe4bWCeR8IgY1G9RDb1gd9mZOv30kxzLvUSVGmQ66t0DA GOSLcVzeNVTPQMF4IgfdfSfxgqyKVzvbq124LV0lcyMThUOVXtuNTqth2ul6nq9RJM63 YV+Q== X-Gm-Message-State: ACgBeo134jdRz2Xfvdl/WNlnnf9DmEajsXE2MjFF5TwzWwsA4ULgQ4ha jGuSwHph+4XCvqhJIq/WrXA= X-Google-Smtp-Source: AA6agR4zXW62zIwj6CaLhiyKEF4o4Y6C1vTVmUD3oqNKkWRtMjO1EAt931MwWTCnR1Uo38nyPfwoAw== X-Received: by 2002:a5d:5551:0:b0:228:d70a:102e with SMTP id g17-20020a5d5551000000b00228d70a102emr10390924wrw.446.1662820345380; Sat, 10 Sep 2022 07:32:25 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id i13-20020a05600c354d00b003a5c1e916c8sm4951251wmq.1.2022.09.10.07.32.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Sep 2022 07:32:25 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Ulf Hansson , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/9] dt-bindings: mmc: sdhci-msm: Add pinctrl-1 property Date: Sat, 10 Sep 2022 17:32:09 +0300 Message-Id: <20220910143213.477261-6-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220910143213.477261-1-iskren.chernev@gmail.com> References: <20220910143213.477261-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Most mmc blocks contain two pinctrls, default and sleep. But then dt-schema complains about pinctrl-1 not being defined. Signed-off-by: Iskren Chernev Acked-by: Krzysztof Kozlowski Reviewed-by: Bhupesh Sharma --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index a792fa5574a0..775476d7f9f0 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -97,6 +97,10 @@ properties: description: Should specify pin control groups used for this controller. + pinctrl-1: + description: + Should specify sleep pin control groups used for this controller. + resets: maxItems: 1 From patchwork Sat Sep 10 14:32:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 604634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8AE1C6FA86 for ; Sat, 10 Sep 2022 14:33:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229806AbiIJOdA (ORCPT ); Sat, 10 Sep 2022 10:33:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229546AbiIJOcj (ORCPT ); Sat, 10 Sep 2022 10:32:39 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1779D4CA2E; Sat, 10 Sep 2022 07:32:31 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id c11so7822179wrp.11; Sat, 10 Sep 2022 07:32:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ciTSseM0ZVhIoNLpfdtSKBndt9cSVhiI4lsKMZmSUUc=; b=BZLowzB0M3PJgeBqR88atC9wD/i7PSeZsbO3g+88wVfE4w3fn/rI9qMDK7iW9Msl73 nGUCyFDf8Cics/15bxx7zV5hd3hoHTcy0WYmOJbBzNbYqJcQvm7V2X2NYwKPR7rnFsWf 3qvG4c7Mul7AiXPoXvhuTrZestTEcwVstdGEicyH6/Nj4xh72Muj8uxiqjWPcuatJuG6 8tyADtyBWzO+YXFfp7qXr0rfT97MaIutnjqqBW/wVDb2q2WbgSZERJnWhIEFEIUJDbzG moGxiQA1S6SBjUz5TEim4d+p7cCPoprC44wFpddpm2q1Ykf7AmhzaVKfFA4uTVM6HdEq nvqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ciTSseM0ZVhIoNLpfdtSKBndt9cSVhiI4lsKMZmSUUc=; b=AfaGxol8tLxc7iYKeluUKLd3GjALwzGq1jbcx9+R0JfQI5DsYF3UFXYkizDKpKoMvG vQKxEtd0wV5Ld1LZatteA0Cn2jiA/v25zQHKDPm7TGLIZb3yNQNlub9Juw+OtVDndx4N Ypa3tPk7pzDRhV2gcomjFE2j7J84Xftd59rmGQ1b1tf9OpavWKwz4bQ9KXBq6IXMgqyM SiNmVcT7GEXwWSk0m/fbE3jSgscHOgUXEGChwzuqaOGXBSliBK0c2gKJLLTcReqqS65u OkIWGDgoJShAHhieZ8u1ErknZNdVwNNAyymIWCqiFuXmsnr5qbZzkBgFnDsJOig9i6VZ pdpg== X-Gm-Message-State: ACgBeo18JcDBzECJ+cOdZ+1ibm8M3fb7K9d6IwWsCy02gpXgBoI/e9xN EVZ0/Yn6dZq9nGlu0nIw6zQ= X-Google-Smtp-Source: AA6agR78tG/sLvNyUDfJFZwa5O1JC8qaoXGnLB0iI8sQnJNGaL61DR3UtpjnR3isAGWgArOURDfuVg== X-Received: by 2002:a5d:5c0a:0:b0:228:db53:22cc with SMTP id cc10-20020a5d5c0a000000b00228db5322ccmr10041594wrb.126.1662820351386; Sat, 10 Sep 2022 07:32:31 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id n2-20020a5d4c42000000b002250c35826dsm2926917wrt.104.2022.09.10.07.32.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Sep 2022 07:32:30 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v3 7/9] arm64: dts: qcom: sm6115: Add basic soc dtsi Date: Sat, 10 Sep 2022 17:32:11 +0300 Message-Id: <20220910143213.477261-8-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220910143213.477261-1-iskren.chernev@gmail.com> References: <20220910143213.477261-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Qualcomm SM6115 SoC. This includes: - GCC - Pinctrl - RPM (CC+PD) - USB - MMC - UFS Signed-off-by: Iskren Chernev --- pending issues with dtschema: - for some reason, using pinctrl phandles (in mmc) breaks the pinctrl schema (4 times) .output/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dtb: pinctrl@500000: sdc1-on-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'clk', 'cmd', 'data', 'rclk' do not match any of the regexes: 'pinctrl-[0-9]+' [[26]] is not of type 'object' From schema: /home/iskren/src/pmos/linux-postmarketos/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml - the ufs phy is actually a phy inside a phy, so the outher one requires #phy-cells (according to dtschema python package). Maybe rename the outer to phys@ because it's not used as a phy, only a holder of phys. arch/arm64/boot/dts/qcom/sm6115.dtsi | 857 +++++++++++++++++++++++++++ 1 file changed, 857 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi new file mode 100644 index 000000000000..8a9f98230d46 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: memory@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@46000000 { + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + }; + + cdsp_sec_mem: memory@46200000 { + reg = <0x0 0x46200000 0x0 0x1e00000>; + no-map; + }; + + pil_modem_mem: memory@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: memory@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: memory@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_cdsp_mem: memory@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_mem: memory@53800000 { + reg = <0x0 0x53800000 0x0 0x2800000>; + no-map; + }; + + pil_ipa_fw_mem: memory@56100000 { + reg = <0x0 0x56100000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@56110000 { + reg = <0x0 0x56110000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: memory@56115000 { + reg = <0x0 0x56115000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: memory@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: memory@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: memory@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x500000 0x400000>, <0x900000 0x400000>, <0xd00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 121>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc1_state_on: sdc1-on-state { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio88"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x1400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + hsusb_phy: phy@1613000 { + compatible = "qcom,sm6115-qusb2-phy"; + reg = <0x1613000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + + status = "disabled"; + }; + + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x340000 0x20000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x4744000 0x1000>, <0x4745000 0x1000>, <0x4748000 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x4804000 0x3000>, <0x4810000 0x8000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x100 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6115-qmp-ufs-phy"; + reg = <0x4807000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@4807400 { + reg = <0x4807400 0x098>, + <0x4807600 0x130>, + <0x4807c00 0x16c>; + #phy-cells = <0>; + }; + }; + + usb3: usb@4ef8800 { + compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; + reg = <0x04ef8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb3_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x04e00000 0xcd00>; + interrupts = ; + phys = <&hsusb_phy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; + reg = <0xc600000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,sm6115-apcs-hmss-global"; + reg = <0xf111000 0x1000>; + + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <19200000>; + + frame@f121000 { + reg = <0xf121000 0x1000>, <0xf122000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@f123000 { + reg = <0xf123000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@f124000 { + reg = <0xf124000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@f125000 { + reg = <0xf125000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@f126000 { + reg = <0xf126000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@f127000 { + reg = <0xf127000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = ; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0xf200000 0x10000>, <0xf300000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Sat Sep 10 14:32:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 604633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1323C6FA86 for ; Sat, 10 Sep 2022 14:33:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229853AbiIJOdN (ORCPT ); Sat, 10 Sep 2022 10:33:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229777AbiIJOc6 (ORCPT ); Sat, 10 Sep 2022 10:32:58 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A136F491FF; Sat, 10 Sep 2022 07:32:39 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id t7so7816356wrm.10; Sat, 10 Sep 2022 07:32:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=0KP4+DvPw8H2XraCq7DVmGrh+MmfdY68pVAk8xlOP9M=; b=SILmZi99yu35ydR0RYfV9tGeJ0qa/xOUYpNHbMggNP3vxL40vmgTVKf970KXUY9ayT AXL5v1ai5SU4NFCm0KaBkslJ1Ab6nRaK8cAUPYovN1m7UqYSdTb+Q1vvXtv6f9Itai9z tW2u91WHX+DCVu4ffsQcby6bFXeyDstSrVpmoUlNwk5OYSUOY22RxUCeGm4f23U20A9M /MCB/YHMOiL96e5844XVkTSOdgQU0HYIJbS7sePNMIfqtZzwwfuYPl1ETmP5cbyoKC4e hEnN9TeZY+H2RmJVGvlJwk6d+UvNo6gp3PHW/8hobmGwj9jdhEeb8LjR27NrtcB1pTqL 9b6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=0KP4+DvPw8H2XraCq7DVmGrh+MmfdY68pVAk8xlOP9M=; b=6knyNLeTmw6a2UwvwtgL2FTuYu00c+8dU85xaeoiVH5Qe+xeJJPHT02A8u5BIzAp1p SJKlURR2+74B9Nyny6lGU7LjodcGTGpiEYWMRSwqSJ5Jl4Tf3SXPYIBkqHifG68+Rd3Y ln8itN/hF62XT1Zq6HOKB6uMWuyeZP0T3glRBKhz8STmiw1cFqCX8ovtEhurwjXjZji3 +l9Pb2q8WxzJoh7Ssq854Li44RWYGPfJIi9FRtcrqxwdLGwVzppfjc4AIlxDlg2MVxgD NzgazGXKSQpdwGdnnB0PaoY3eUwHo70iViuWC1ULGGs9lZuDyRZ3zsD/tck1/4JIJO9D H4EQ== X-Gm-Message-State: ACgBeo2b6Imq0FiVJIi3VjgBssA1K5Qxh1X18gWUgah00HNBg6/uXbS0 1X/z8oJbspA/wOjz7Q9/b8g= X-Google-Smtp-Source: AA6agR4TQDpqBEIq9PShOGI/4/ptzgX6DungIY4QdXEVG/cVUMgnnDWQ6nDzqDo7dEXOcZaafiUaEQ== X-Received: by 2002:a05:6000:1ac8:b0:22a:4cd7:92bc with SMTP id i8-20020a0560001ac800b0022a4cd792bcmr1365822wry.230.1662820358722; Sat, 10 Sep 2022 07:32:38 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id q127-20020a1c4385000000b003a5f54e3bbbsm3933139wma.38.2022.09.10.07.32.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Sep 2022 07:32:38 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-kernel@vger.kernel.org Subject: [PATCH v3 9/9] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Date: Sat, 10 Sep 2022 17:32:13 +0300 Message-Id: <20220910143213.477261-10-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220910143213.477261-1-iskren.chernev@gmail.com> References: <20220910143213.477261-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial support for OnePlus Nord N100, based on SM4250. Currently working: - boots - usb - buildin flash storage (UFS) - SD card reader Signed-off-by: Iskren Chernev --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f4126f7e7640..5d2570b600e0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -137,6 +137,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts new file mode 100644 index 000000000000..b9094f1efca0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Iskren Chernev + */ + +/dts-v1/; + +#include "sm4250.dtsi" + +/ { + model = "OnePlus Nord N100"; + compatible = "oneplus,billie2", "qcom,sm4250"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; + qcom,board-id = <0x1000b 0x00>; + + aliases { + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (1600 * 720 * 4)>; + width = <720>; + height = <1600>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; +}; + +&xo_board { + clock-frequency = <19200000>; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&reserved_memory { + bootloader_log_mem: memory@5fff7000 { + reg = <0x00 0x5fff7000 0x00 0x8000>; + no-map; + }; + + ramoops@cbe00000 { + compatible = "ramoops"; + reg = <0x0 0xcbe00000 0x0 0x400000>; + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + }; + + param_mem: memory@cc200000 { + reg = <0x00 0xcc200000 0x00 0x100000>; + no-map; + }; + + mtp_mem: memory@cc300000 { + reg = <0x00 0xcc300000 0x00 0xb00000>; + no-map; + }; +}; + +&usb3 { + status = "okay"; +}; + +&hsusb_phy { + vdd-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vddp-ref-clk-supply = <&vreg_l18a>; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1456000>; + }; + + vreg_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; +};