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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id v62-20020a632f41000000b00430c6fd7ffbsm4705716pgv.84.2022.09.11.23.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 23:50:38 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v4 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Date: Mon, 12 Sep 2022 06:50:24 +0000 Message-Id: <20220912065029.1793-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220912065029.1793-1-zong.li@sifive.com> References: <20220912065029.1793-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li Suggested-by: Conor Dooley Suggested-by: Ben Dooks Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml similarity index 83% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index ca3b9be58058..bf3f07421f7e 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -2,18 +2,18 @@ # Copyright (C) 2020 SiFive, Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SiFive L2 Cache Controller +title: SiFive Composable Cache Controller maintainers: - Sagar Kadam - Paul Walmsley description: - The SiFive Level 2 Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Level 2 Cache Controller also + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this platform. @@ -22,6 +22,7 @@ select: compatible: contains: enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache @@ -33,6 +34,7 @@ properties: oneOf: - items: - enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache @@ -45,7 +47,7 @@ properties: const: 64 cache-level: - const: 2 + enum: [2, 3] cache-sets: enum: [1024, 2048] @@ -115,6 +117,22 @@ allOf: cache-sets: const: 1024 + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + additionalProperties: false required: From patchwork Mon Sep 12 06:50:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 605094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28326C6FA89 for ; Mon, 12 Sep 2022 06:50:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229934AbiILGux (ORCPT ); Mon, 12 Sep 2022 02:50:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229824AbiILGur (ORCPT ); Mon, 12 Sep 2022 02:50:47 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73E501BEAB for ; Sun, 11 Sep 2022 23:50:43 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id r17so7382851pgr.7 for ; Sun, 11 Sep 2022 23:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=5SuaG6Ukq0CemB7A8qUbJlhfLaxFef4FQZrGHxKHG2c=; b=YohP9yojEQcCRdLCat24x5Mj+IkjNQarsonI/1qPPwuLLmzv6sel9Y++kT6xXUu0Rm jq5tIXoHGn8iHLpkwMzfK5GVYmYmrDDWSRnDEKYDcT/XOdLr5LwLd2W1RT7f8PSaElV7 JAQty2nUjARKFLuOvvlsTdZhWYYG+/kcoUh4/znraCVqgH/5HpaW+FFagCvAHWz06Yyg JsdSO2Naw7fd8IflC3KmKwtHlPrfnuCrRLVHxoZrswePXQFhqPP8SlhogIllZcq6HEJd tDa9wNsw9E8vCZwFpLC72Ql/LgJ5NWa4XmoFxqN7bYYSjL23FVKut+LCpQvDOju2+6nz b3Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=5SuaG6Ukq0CemB7A8qUbJlhfLaxFef4FQZrGHxKHG2c=; b=L8I3MU6D+7yjbAtWBr2sPqf9DzM3wzrztws/ZJUuyG0bUKu6k0zlbEJ2JTZ73keZDd A5MGgP3BahzHVFyoDpJr5SQTi5Nn4v2/GobwJwT2jh16nKhYH9HfFc8s5+rzfXWg47Vz GkbTChHaw5V+HeGayv9Tfr5IfZ+l+3hZjnvX15v03MlWxzdLWAOt3uVCM6bpNqYiBCat ZpSUSPPRuuEeVHSRcOAKqj5wBvMkl2DSjY4zr9Zb3QMpYoYFuGW4qUI6XSMlFBGBcuBS SWpN95WvML2N0FpU80378QLQ7eoNDbcOzRz5oD65LJEsm4u3uq1NL90rMJ9nNxQlDS19 Mqmg== X-Gm-Message-State: ACgBeo2rGIpset49lgAuaWAKuJJbW2dFAOdaCS37YyKszF5LrFFBWzzv PLUV8AGCjiQkl+LGN8HBsH4QnA== X-Google-Smtp-Source: AA6agR5nbTXjpyILRFiRpPCefxdAB20Q7gXw4UZs9EWUdNMmOm1UJImwpvvIOiunYcDZVySVsEryWw== X-Received: by 2002:a05:6a00:2385:b0:544:c42d:8a72 with SMTP id f5-20020a056a00238500b00544c42d8a72mr834219pfc.84.1662965442181; Sun, 11 Sep 2022 23:50:42 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id v62-20020a632f41000000b00430c6fd7ffbsm4705716pgv.84.2022.09.11.23.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 23:50:41 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v4 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Date: Mon, 12 Sep 2022 06:50:25 +0000 Message-Id: <20220912065029.1793-3-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220912065029.1793-1-zong.li@sifive.com> References: <20220912065029.1793-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Greentime Hu Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu Signed-off-by: Zong Li Co-developed-by: Zong Li Reviewed-by: Conor Dooley --- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 +- drivers/soc/sifive/Kconfig | 6 +- drivers/soc/sifive/Makefile | 2 +- .../{sifive_l2_cache.c => sifive_ccache.c} | 174 +++++++++--------- .../{sifive_l2_cache.h => sifive_ccache.h} | 16 +- 6 files changed, 110 insertions(+), 102 deletions(-) rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (34%) rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 17562cf1fe97..456602d373b7 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC config EDAC_SIFIVE bool "Sifive platform EDAC driver" - depends on EDAC=y && SIFIVE_L2 + depends on EDAC=y && SIFIVE_CCACHE help Support for error detection and correction on the SiFive SoCs. diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index ee800aec7d47..b844e2626fd5 100644 --- a/drivers/edac/sifive_edac.c +++ b/drivers/edac/sifive_edac.c @@ -2,7 +2,7 @@ /* * SiFive Platform EDAC Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * * This driver is partially based on octeon_edac-pc.c * @@ -10,7 +10,7 @@ #include #include #include "edac_module.h" -#include +#include #define DRVNAME "sifive_edac" @@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr) p = container_of(this, struct sifive_edac_priv, notifier); - if (event == SIFIVE_L2_ERR_TYPE_UE) + if (event == SIFIVE_CCACHE_ERR_TYPE_UE) edac_device_handle_ue(p->dci, 0, 0, msg); - else if (event == SIFIVE_L2_ERR_TYPE_CE) + else if (event == SIFIVE_CCACHE_ERR_TYPE_CE) edac_device_handle_ce(p->dci, 0, 0, msg); return NOTIFY_OK; @@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev) goto err; } - register_sifive_l2_error_notifier(&p->notifier); + register_sifive_ccache_error_notifier(&p->notifier); return 0; @@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev) { struct sifive_edac_priv *p = platform_get_drvdata(pdev); - unregister_sifive_l2_error_notifier(&p->notifier); + unregister_sifive_ccache_error_notifier(&p->notifier); edac_device_del_device(&pdev->dev); edac_device_free_ctl_info(p->dci); diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index 58cf8c40d08d..ed4c571f8771 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -2,9 +2,9 @@ if SOC_SIFIVE -config SIFIVE_L2 - bool "Sifive L2 Cache controller" +config SIFIVE_CCACHE + bool "Sifive Composable Cache controller" help - Support for the L2 cache controller on SiFive platforms. + Support for the composable cache controller on SiFive platforms. endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile index b5caff77938f..1f5dc339bf82 100644 --- a/drivers/soc/sifive/Makefile +++ b/drivers/soc/sifive/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o +obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c similarity index 34% rename from drivers/soc/sifive/sifive_l2_cache.c rename to drivers/soc/sifive/sifive_ccache.c index 59640a1d0b28..949b824e89ad 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * SiFive L2 cache controller Driver + * SiFive composable cache controller Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * */ #include @@ -11,33 +11,33 @@ #include #include #include -#include +#include -#define SIFIVE_L2_DIRECCFIX_LOW 0x100 -#define SIFIVE_L2_DIRECCFIX_HIGH 0x104 -#define SIFIVE_L2_DIRECCFIX_COUNT 0x108 +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 -#define SIFIVE_L2_DIRECCFAIL_LOW 0x120 -#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124 -#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128 +#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 +#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 +#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 -#define SIFIVE_L2_DATECCFIX_LOW 0x140 -#define SIFIVE_L2_DATECCFIX_HIGH 0x144 -#define SIFIVE_L2_DATECCFIX_COUNT 0x148 +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 -#define SIFIVE_L2_DATECCFAIL_LOW 0x160 -#define SIFIVE_L2_DATECCFAIL_HIGH 0x164 -#define SIFIVE_L2_DATECCFAIL_COUNT 0x168 +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 -#define SIFIVE_L2_CONFIG 0x00 -#define SIFIVE_L2_WAYENABLE 0x08 -#define SIFIVE_L2_ECCINJECTERR 0x40 +#define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_WAYENABLE 0x08 +#define SIFIVE_CCACHE_ECCINJECTERR 0x40 -#define SIFIVE_L2_MAX_ECCINTR 4 +#define SIFIVE_CCACHE_MAX_ECCINTR 4 -static void __iomem *l2_base; -static int g_irq[SIFIVE_L2_MAX_ECCINTR]; -static struct riscv_cacheinfo_ops l2_cache_ops; +static void __iomem *ccache_base; +static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops ccache_cache_ops; enum { DIR_CORR = 0, @@ -49,83 +49,84 @@ enum { #ifdef CONFIG_DEBUG_FS static struct dentry *sifive_test; -static ssize_t l2_write(struct file *file, const char __user *data, - size_t count, loff_t *ppos) +static ssize_t ccache_write(struct file *file, const char __user *data, + size_t count, loff_t *ppos) { unsigned int val; if (kstrtouint_from_user(data, count, 0, &val)) return -EINVAL; if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR); + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); else return -EINVAL; return count; } -static const struct file_operations l2_fops = { +static const struct file_operations ccache_fops = { .owner = THIS_MODULE, .open = simple_open, - .write = l2_write + .write = ccache_write }; static void setup_sifive_debug(void) { - sifive_test = debugfs_create_dir("sifive_l2_cache", NULL); + sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL); debugfs_create_file("sifive_debug_inject_error", 0200, - sifive_test, NULL, &l2_fops); + sifive_test, NULL, &ccache_fops); } #endif -static void l2_config_read(void) +static void ccache_config_read(void) { u32 regval, val; - regval = readl(l2_base + SIFIVE_L2_CONFIG); + regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); val = regval & 0xFF; - pr_info("L2CACHE: No. of Banks in the cache: %d\n", val); + pr_info("CCACHE: No. of Banks in the cache: %d\n", val); val = (regval & 0xFF00) >> 8; - pr_info("L2CACHE: No. of ways per bank: %d\n", val); + pr_info("CCACHE: No. of ways per bank: %d\n", val); val = (regval & 0xFF0000) >> 16; - pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); val = (regval & 0xFF000000) >> 24; - pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - regval = readl(l2_base + SIFIVE_L2_WAYENABLE); - pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval); + regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); } -static const struct of_device_id sifive_l2_ids[] = { +static const struct of_device_id sifive_ccache_ids[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, - { /* end of table */ }, + { .compatible = "sifive,ccache0" }, + { /* end of table */ } }; -static ATOMIC_NOTIFIER_HEAD(l2_err_chain); +static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); -int register_sifive_l2_error_notifier(struct notifier_block *nb) +int register_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_register(&l2_err_chain, nb); + return atomic_notifier_chain_register(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); -int unregister_sifive_l2_error_notifier(struct notifier_block *nb) +int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_unregister(&l2_err_chain, nb); + return atomic_notifier_chain_unregister(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); -static int l2_largest_wayenabled(void) +static int ccache_largest_wayenabled(void) { - return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; + return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; } static ssize_t number_of_ways_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%u\n", l2_largest_wayenabled()); + return sprintf(buf, "%u\n", ccache_largest_wayenabled()); } static DEVICE_ATTR_RO(number_of_ways_enabled); @@ -139,99 +140,106 @@ static const struct attribute_group priv_attr_group = { .attrs = priv_attrs, }; -static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +static const struct attribute_group *ccache_get_priv_group(struct cacheinfo + *this_leaf) { - /* We want to use private group for L2 cache only */ + /* We want to use private group for composable cache only */ if (this_leaf->level == 2) return &priv_attr_group; else return NULL; } -static irqreturn_t l2_int_handler(int irq, void *device) +static irqreturn_t ccache_int_handler(int irq, void *device) { unsigned int add_h, add_l; if (irq == g_irq[DIR_CORR]) { - add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); - pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); + pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_CE, "DirECCFix"); } if (irq == g_irq[DIR_UNCORR]) { - add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW); + add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); /* Reading this register clears the DirFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_UE, "DirECCFail"); - panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); + panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); } if (irq == g_irq[DATA_CORR]) { - add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); - pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); + pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_CE, "DatECCFix"); } if (irq == g_irq[DATA_UNCORR]) { - add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH); - add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW); - pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); + add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); + pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_UE, "DatECCFail"); } return IRQ_HANDLED; } -static int __init sifive_l2_init(void) +static int __init sifive_ccache_init(void) { struct device_node *np; struct resource res; int i, rc, intr_num; - np = of_find_matching_node(NULL, sifive_l2_ids); + np = of_find_matching_node(NULL, sifive_ccache_ids); if (!np) return -ENODEV; if (of_address_to_resource(np, 0, &res)) return -ENODEV; - l2_base = ioremap(res.start, resource_size(&res)); - if (!l2_base) + ccache_base = ioremap(res.start, resource_size(&res)); + if (!ccache_base) return -ENOMEM; intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { - pr_err("L2CACHE: no interrupts property\n"); + pr_err("CCACHE: no interrupts property\n"); return -ENODEV; } for (i = 0; i < intr_num; i++) { g_irq[i] = irq_of_parse_and_map(np, i); - rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); + rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", + NULL); if (rc) { - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); return rc; } } - l2_config_read(); + ccache_config_read(); - l2_cache_ops.get_priv_group = l2_get_priv_group; - riscv_set_cacheinfo_ops(&l2_cache_ops); + ccache_cache_ops.get_priv_group = ccache_get_priv_group; + riscv_set_cacheinfo_ops(&ccache_cache_ops); #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif return 0; } -device_initcall(sifive_l2_init); + +device_initcall(sifive_ccache_init); diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_ccache.h similarity index 12% rename from include/soc/sifive/sifive_l2_cache.h rename to include/soc/sifive/sifive_ccache.h index 92ade10ed67e..4d4ed49388a0 100644 --- a/include/soc/sifive/sifive_l2_cache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * SiFive L2 Cache Controller header file + * SiFive Composable Cache Controller header file * */ -#ifndef __SOC_SIFIVE_L2_CACHE_H -#define __SOC_SIFIVE_L2_CACHE_H +#ifndef __SOC_SIFIVE_CCACHE_H +#define __SOC_SIFIVE_CCACHE_H -extern int register_sifive_l2_error_notifier(struct notifier_block *nb); -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); +extern int register_sifive_ccache_error_notifier(struct notifier_block *nb); +extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb); -#define SIFIVE_L2_ERR_TYPE_CE 0 -#define SIFIVE_L2_ERR_TYPE_UE 1 +#define SIFIVE_CCACHE_ERR_TYPE_CE 0 +#define SIFIVE_CCACHE_ERR_TYPE_UE 1 -#endif /* __SOC_SIFIVE_L2_CACHE_H */ +#endif /* __SOC_SIFIVE_CCACHE_H */ From patchwork Mon Sep 12 06:50:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 605550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5837ECAAD5 for ; Mon, 12 Sep 2022 06:50:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229967AbiILGuy (ORCPT ); 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id v62-20020a632f41000000b00430c6fd7ffbsm4705716pgv.84.2022.09.11.23.50.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 23:50:44 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v4 3/6] soc: sifive: ccache: determine the cache level from dts Date: Mon, 12 Sep 2022 06:50:26 +0000 Message-Id: <20220912065029.1793-4-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220912065029.1793-1-zong.li@sifive.com> References: <20220912065029.1793-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 949b824e89ad..b361b661ea09 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -38,6 +38,7 @@ static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; +static int level; enum { DIR_CORR = 0, @@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf) { /* We want to use private group for composable cache only */ - if (this_leaf->level == 2) + if (this_leaf->level == level) return &priv_attr_group; else return NULL; @@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void) if (!ccache_base) return -ENOMEM; + if (of_property_read_u32(np, "cache-level", &level)) + return -ENOENT; + intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("CCACHE: no interrupts property\n"); From patchwork Mon Sep 12 06:50:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 605549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF5FCECAAD5 for ; Mon, 12 Sep 2022 06:51:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229536AbiILGvK (ORCPT ); Mon, 12 Sep 2022 02:51:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229989AbiILGut (ORCPT ); Mon, 12 Sep 2022 02:50:49 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFB4C2A24B for ; Sun, 11 Sep 2022 23:50:48 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id r17so7383043pgr.7 for ; Sun, 11 Sep 2022 23:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=6Xe3R/apOfj9yPTgHstXk1duLFBJjDM/Rtwt0f9H5Eo=; b=LanQLFvf6RQo3FztPxAXUGZuOt8XUCf0383mzuu7l36i5lBuVM7bi3iPqfx+wzmfyi uAlDr3GoCXquZqHzwvBrhDMXi0YtylvsZwA7YId+/ApLY1U5XJj0rN/I5QmWb3MuF4mC m9sgzjS2xK2t+nt4fHR7dRPUE0LxTuedAV6S5+a94szVmhw/tch7jvfdX5N8jMUoRye8 xz0O7JnDIoV3PayCrYsZ7jYT5OP6Jd7Kh3ndLlupvIYW7p5AByJ1ucJyzKvsKrhNusWC NcDZRyT4fxBkMHfgo6RQKyXC7/+Yo59BMEgUpZLNG2E3VKWnxuV+cKwjSztuqIOtiR48 ElmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=6Xe3R/apOfj9yPTgHstXk1duLFBJjDM/Rtwt0f9H5Eo=; b=3kERzwxWZs06UbsBzObvlbuLtGUamfbyaDkqDXwVYhOcY0fz5YXKeRmaLfidi1UgM9 Hvy4vTTsfN4fQhi5wgxY7JlPUx0XF5AWDWxB/sePD7co8cLJbPVVqLBWAktSlq9qoMg+ mAruNTTDwQesEOL1OuEDUxGBYN3jI7YJVCYGTWFHiYfWsdaLotc5x3XvxXnc+zGkcyLq s/LFaOmdsBfUOGD6xOeiy11S4QClWYS8haaUgd/y+tywo6G5MsgZ3qYmM1bSMeAEh2ZS UBWz71cYzjnJM/Snw0PZcQQr7viQ6iRU4qgSu3Vd396G8QCDxhKmKywITMAPZUFksgkR snZA== X-Gm-Message-State: ACgBeo2BYrtEdUmk0+FtI8qze39z3E8VDmpYSL15InR+Eao0B7cTeRyE F8e2q5tPDv/fqIwmG0dyYy5MkA== X-Google-Smtp-Source: AA6agR4JOxDScrdlY2QeBhFk8ibiBQ+YL8tlBtJH7FnoTf9lRCe8Mq0poUexl6SesZaolsHcCoBjjA== X-Received: by 2002:a65:6cc4:0:b0:412:35fa:5bce with SMTP id g4-20020a656cc4000000b0041235fa5bcemr21758036pgw.466.1662965448405; Sun, 11 Sep 2022 23:50:48 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id v62-20020a632f41000000b00430c6fd7ffbsm4705716pgv.84.2022.09.11.23.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 23:50:47 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v4 4/6] soc: sifive: ccache: reduce printing on init Date: Mon, 12 Sep 2022 06:50:27 +0000 Message-Id: <20220912065029.1793-5-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220912065029.1793-1-zong.li@sifive.com> References: <20220912065029.1793-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ben Dooks The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index b361b661ea09..17080af7dfa0 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -81,20 +81,17 @@ static void setup_sifive_debug(void) static void ccache_config_read(void) { - u32 regval, val; - - regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - val = regval & 0xFF; - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); - val = (regval & 0xFF00) >> 8; - pr_info("CCACHE: No. of ways per bank: %d\n", val); - val = (regval & 0xFF0000) >> 16; - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val = (regval & 0xFF000000) >> 24; - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); + u32 cfg; + + cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); + + pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + (cfg & 0xff), (cfg >> 8) & 0xff, + BIT_ULL((cfg >> 16) & 0xff), + BIT_ULL((cfg >> 24) & 0xff)); + + cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = { From patchwork Mon Sep 12 06:50:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 605093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B713BC6FA89 for ; Mon, 12 Sep 2022 06:51:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229963AbiILGvN (ORCPT ); Mon, 12 Sep 2022 02:51:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229971AbiILGuy (ORCPT ); Mon, 12 Sep 2022 02:50:54 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B83381BEAB for ; Sun, 11 Sep 2022 23:50:52 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id n23-20020a17090a091700b00202a51cc78bso5141453pjn.2 for ; Sun, 11 Sep 2022 23:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=KI8GGOYVJ30lpXYNmzlWaq92ei+up8qB7deF01pAkE4=; b=GMSuU6wrb4gbfYf/Vc0tM7RnsBejNC2gtIIk2Qqm496IkB0U2XSIRA7/Jc4ugHnvJs OjneuLH3F3Tt6TL+fqiz9ZTMfWhaKcV8kS+Ks+EnFKBo9g/JouaqfyJYIgRBbtNcARKx TSXTQUnz4KJ0Ot9xsMK5tE25NnaQ5FR1FKCBlzmQEkAi7CY6TUQqxkaP1cuwrKiuK8gO WvbVra2LCBBnXAph5GtB+6dwcB9ZESeRqDMp90+XJi4IXC3bjqUICagf5lSjyhQxXrix +DVTC69T1Ux9AQNu1LPgcguNE5wRhBuCY30SLbS4F05NmeRNLvqBYo0Da8WUeWCnllaa ixmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=KI8GGOYVJ30lpXYNmzlWaq92ei+up8qB7deF01pAkE4=; b=GiPJlfyk4QW8MyrP480zoe3QELFdnX0zJdYoSoScvlN4Ip3dFGmDCelkmNi7P3nfga yg8KAcbOhUbEFPot2xMg88UOmrWQclc2MKxjps9HRBI+AoITgxeLZMLBf/871TbaPfZd qYiqlDUzexUhdwRuctnTP5wCJvOOlaZcH7Xj1ubYKsA6M1opp4wGr2SrJtHMnhaCbOs2 XX5i7U1EsJfKpLDPiGKJ96tQjiFcJ1JKBQEyAB7gf6iA+5BZuKjlnmWVewtZsBROlT+8 pRnPcOu2wSyjiq5P3BGVP3yMfeC+eVGpEhYvjufEAIpFPbyNCpPEbq2ZtqZCXassNuAH eDRA== X-Gm-Message-State: ACgBeo3m4V48edZideat6O6qYPVmfjps5pOObuxCb2VZlgkR1SWGsLc+ cseyrELn/TWP25sXG1EFjdwazw== X-Google-Smtp-Source: AA6agR6nGrzvFOlvlGJ8qouQVgLOiB7yFHWl4qEw+wEQhb08Q+u4R9GUJDn3p2gGJylOnOwQcAnDDQ== X-Received: by 2002:a17:90a:6a83:b0:200:9da5:d0e7 with SMTP id u3-20020a17090a6a8300b002009da5d0e7mr21960464pjj.187.1662965451415; Sun, 11 Sep 2022 23:50:51 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id v62-20020a632f41000000b00430c6fd7ffbsm4705716pgv.84.2022.09.11.23.50.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 23:50:50 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v4 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Date: Mon, 12 Sep 2022 06:50:28 +0000 Message-Id: <20220912065029.1793-6-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220912065029.1793-1-zong.li@sifive.com> References: <20220912065029.1793-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ben Dooks Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 17080af7dfa0..91f0c2b32ea2 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -5,6 +5,9 @@ * Copyright (C) 2018-2022 SiFive, Inc. * */ + +#define pr_fmt(fmt) "CCACHE: " fmt + #include #include #include @@ -85,13 +88,13 @@ static void ccache_config_read(void) cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", + pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", (cfg & 0xff), (cfg >> 8) & 0xff, BIT_ULL((cfg >> 16) & 0xff), BIT_ULL((cfg >> 24) & 0xff)); cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); + pr_info("Index of the largest way enabled: %u\n", cfg); } static const struct of_device_id sifive_ccache_ids[] = { @@ -155,7 +158,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DIR_CORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); - pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -175,7 +178,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DATA_CORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); - pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -185,7 +188,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device) if (irq == g_irq[DATA_UNCORR]) { add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); - pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -218,7 +221,7 @@ static int __init sifive_ccache_init(void) intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { - pr_err("CCACHE: no interrupts property\n"); + pr_err("No interrupts property\n"); return -ENODEV; } @@ -227,7 +230,7 @@ static int __init sifive_ccache_init(void) rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); if (rc) { - pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("Could not request IRQ %d\n", g_irq[i]); return rc; } } From patchwork Mon Sep 12 06:50:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 605548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 091E7C6FA82 for ; Mon, 12 Sep 2022 06:51:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230183AbiILGvP (ORCPT ); Mon, 12 Sep 2022 02:51:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230034AbiILGu4 (ORCPT ); Mon, 12 Sep 2022 02:50:56 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA4FD29CB0 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id v62-20020a632f41000000b00430c6fd7ffbsm4705716pgv.84.2022.09.11.23.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 23:50:53 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v4 6/6] soc: sifive: ccache: define the macro for the register shifts Date: Mon, 12 Sep 2022 06:50:29 +0000 Message-Id: <20220912065029.1793-7-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220912065029.1793-1-zong.li@sifive.com> References: <20220912065029.1793-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 91f0c2b32ea2..1c171150e878 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,11 @@ #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 #define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0) +#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8) +#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) +#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 @@ -87,11 +93,11 @@ static void ccache_config_read(void) u32 cfg; cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - - pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", - (cfg & 0xff), (cfg >> 8) & 0xff, - BIT_ULL((cfg >> 16) & 0xff), - BIT_ULL((cfg >> 24) & 0xff)); + pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n", + FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg), + FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg))); cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); pr_info("Index of the largest way enabled: %u\n", cfg);