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Fri, 15 Feb 2019 10:56:44 +0000 (GMT) X-AuditID: cbfec7f4-835ff700000010c6-11-5c669aec7e6e Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 31.19.04128.BEA966C5; Fri, 15 Feb 2019 10:56:43 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PMY000Q7RQFYR40@eusync4.samsung.com>; Fri, 15 Feb 2019 10:56:43 +0000 (GMT) From: Marek Szyprowski To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Szyprowski , Russell King , Nicolas Pitre , Kevin Hilman , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Marian Mihailescu , Seung-Woo Kim Subject: [PATCH v2] ARM: pm: fix HYP/SVC mode mismatch when MCPM is used Date: Fri, 15 Feb 2019 11:56:38 +0100 Message-id: <20190215105638.17476-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRmVeSWpSXmKPExsWy7djP87pvZqXFGGw6JWuxccZ6Vouf7VuY LM6f38BusenxNVaLy7vmsFnMOL+PyWLtkbvsFuun/WS1+PTsH7vFpf6JTBYzJr9kc+D2uHzt IrPH+xut7B47Z91l99i0qpPN4861PWwem5fUe/RtWcXo8XmTXABHFJdNSmpOZllqkb5dAlfG m9a/zAWzxCrW33jE2MB4SKiLkZNDQsBEYsbe2YxdjFwcQgIrGCVmX+thg3A+M0rcXHqIBabq wstLLBCJZYwSD5c9Z4dwGpgkti5oZgOpYhMwlOh62wVmiwi4SfxbdwhsFLNAO7PEiyfTwRLC Ah4S/Q+3MoHYLAKqEk29n1hBbF4BW4k1aw6xQayTl1i94QAzhL2ATWL3vCQI20Xix7tOVghb RuLy5G6wkyQEmhkl2mfMYodwehglts7ZATXJWuLw8YtgHcwCfBKTtk0HmsoBFOeV6GiDhoCH xOoL39lBbCGBWInv578zTmAUX8DIsIpRPLW0ODc9tdgoL7Vcrzgxt7g0L10vOT93EyMwLk// O/5lB+OuP0mHGAU4GJV4eFdkpMYIsSaWFVfmHmKU4GBWEuEtnJEWI8SbklhZlVqUH19UmpNa fIhRmoNFSZy3muFBtJBAemJJanZqakFqEUyWiYNTqoHR6JOeWWBg2fHt/woefvnatnn7XxMx rbg78/Mfl9p/dZLvED/QuCbmuFnvlO9Ne+XUns55cLLf9fz5B2qsu81rPScJp9U17nz2YcOS G8dmy25dxXnvqWrp4n2K9QubP69MDJzCf1W5ZtI5/7S2yPnBclGiq9Kcv795rTi7+OTaI/L7 OPgdK85lKrEUZyQaajEXFScCAGCsKgvHAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprELMWRmVeSWpSXmKPExsVy+t/xa7qvZ6XFGPw8omuxccZ6Vouf7VuY LM6f38BusenxNVaLy7vmsFnMOL+PyWLtkbvsFuun/WS1+PTsH7vFpf6JTBYzJr9kc+D2uHzt IrPH+xut7B47Z91l99i0qpPN4861PWwem5fUe/RtWcXo8XmTXABHFJdNSmpOZllqkb5dAlfG m9a/zAWzxCrW33jE2MB4SKiLkZNDQsBE4sLLSyxdjFwcQgJLGCVaP/5hhnCamCS2nDvIDlLF JmAo0fW2iw3EFhFwk/i37hAbSBGzQCezxLzpe1hAEsICHhL9D7cygdgsAqoSTb2fWEFsXgFb iTVrDrFBrJOXWL3hAPMERq4FjAyrGEVSS4tz03OLjfSKE3OLS/PS9ZLzczcxAkNq27GfW3Yw dr0LPsQowMGoxMO7IiM1Rog1say4MvcQowQHs5IIb+GMtBgh3pTEyqrUovz4otKc1OJDjNIc LErivOcNKqOEBNITS1KzU1MLUotgskwcnFINjAYNUt9EnvpNE1x1pe6x1/NlkyyXSjz5nGa4 3vkJm1FUT2X7xrXLpss95xd5t/CmZ+6S5WkTM4XmMivucw85wHRR5rj2TRl/ibPdtZ5VLite +WqJWYaGbp9n7tKtwlLrFMBxW0HsPluar+aLw3sO7nt/PHox29W64u6HNr8+qxyOiQ8z7DNZ ocRSnJFoqMVcVJwIAB6tt4YlAgAA X-CMS-MailID: 20190215105644eucas1p19d0bdab386354cff0a9a354b5e33f0fe CMS-TYPE: 201P X-CMS-RootMailID: 20190215105644eucas1p19d0bdab386354cff0a9a354b5e33f0fe References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MCPM does a soft reset of the CPUs and uses common cpu_resume() routine to perform low-level platform initialization. This results in a try to install HYP stubs for the second time for each CPU and results in false HYP/SVC mode mismatch detection. The HYP stubs are already installed at the beginning of the kernel initialization on the boot CPU (head.S) or in the secondary_startup() for other CPUs. To fix this issue MCPM code should use a cpu_resume() routine without HYP stubs installation. This change fixes HYP/SVC mode mismatch on Samsung Exynos5422-based Odroid XU3/XU4/HC1 boards. Fixes: 3721924c8154 ("ARM: 8081/1: MCPM: provide infrastructure to allow for MCPM loopback") Signed-off-by: Marek Szyprowski Acked-by: Nicolas Pitre --- v2: - fixed support for Thumb-mode kernel --- arch/arm/common/mcpm_entry.c | 2 +- arch/arm/include/asm/suspend.h | 1 + arch/arm/kernel/sleep.S | 12 ++++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c index ad574d20415c..1b1b82b37ce0 100644 --- a/arch/arm/common/mcpm_entry.c +++ b/arch/arm/common/mcpm_entry.c @@ -381,7 +381,7 @@ static int __init nocache_trampoline(unsigned long _arg) unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); phys_reset_t phys_reset; - mcpm_set_entry_vector(cpu, cluster, cpu_resume); + mcpm_set_entry_vector(cpu, cluster, cpu_resume_no_hyp); setup_mm_for_reboot(); __mcpm_cpu_going_down(cpu, cluster); diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h index 452bbdcbcc83..506314265c6f 100644 --- a/arch/arm/include/asm/suspend.h +++ b/arch/arm/include/asm/suspend.h @@ -10,6 +10,7 @@ struct sleep_save_sp { }; extern void cpu_resume(void); +extern void cpu_resume_no_hyp(void); extern void cpu_resume_arm(void); extern int cpu_suspend(unsigned long, int (*)(unsigned long)); diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index a8257fc9cf2a..5dc8b80bb693 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -120,6 +120,14 @@ ENDPROC(cpu_resume_after_mmu) .text .align +#ifdef CONFIG_MCPM + .arm +THUMB( .thumb ) +ENTRY(cpu_resume_no_hyp) +ARM_BE8(setend be) @ ensure we are in BE mode + b no_hyp +#endif + #ifdef CONFIG_MMU .arm ENTRY(cpu_resume_arm) @@ -135,6 +143,7 @@ ARM_BE8(setend be) @ ensure we are in BE mode bl __hyp_stub_install_secondary #endif safe_svcmode_maskall r1 +no_hyp: mov r1, #0 ALT_SMP(mrc p15, 0, r0, c0, c0, 5) ALT_UP_B(1f) @@ -163,6 +172,9 @@ ENDPROC(cpu_resume) #ifdef CONFIG_MMU ENDPROC(cpu_resume_arm) +#endif +#ifdef CONFIG_MCPM +ENDPROC(cpu_resume_no_hyp) #endif .align 2