From patchwork Wed Sep 14 07:53:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 606794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DCC2C6FA8A for ; Wed, 14 Sep 2022 07:54:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230192AbiINHyP (ORCPT ); Wed, 14 Sep 2022 03:54:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229472AbiINHyN (ORCPT ); Wed, 14 Sep 2022 03:54:13 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44A6872FCC for ; Wed, 14 Sep 2022 00:54:08 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id ge9so2217942pjb.1 for ; Wed, 14 Sep 2022 00:54:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=gbwg87hG3tf6Wqw8hsoPn0QdO74QME7etMAVFms+/pw=; b=ljDxR322JltyV7F/QZun8KlOd5owh+tpFy2pY0cKU+zKsqRc50k4t5cyHvkM6i0xo3 pq6ZR06hgYFaJfAHniPKBC0tFQAX6jWo4BLBjC+8MwffaTfyY5mRtUoc2MLbKB+EemR3 XspmcR19OZ0B02d8lswcBsROs4SX/Yp4UHWhPt1VDV8hJKZO0CJTBVHTL+Y+LZD6F7fi G+Ud256J3h+fp070+YqAApIwLDIWKyUOfr3OdFJWDpx/lA3BhIhRF6vNcokWCN+1LIfE d6UJRpyLQp2d9bP2FgYosUkCk7J9p7BjAKNrKP/gt+SYNUnjtuFO+FJJPbkkzDi2JYx2 kktg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=gbwg87hG3tf6Wqw8hsoPn0QdO74QME7etMAVFms+/pw=; b=MAowSZswhwgKrKIjeM6aRPjG6aBS3KI1yuO7eGgcaUM+Nq+x/xDF3RCL8DdnMRR0Fk yBylb1rytOrgw4esAuB39B+N5A8ThkWgLQFzds5msP5hxfK3G4bXdsDOpONpmai/TBG3 EL2KfzfEgbcTlFdxS8W0uOoFwftR3Y/94esMSSnRSv/YwP6GW5FcjNBu67MXjQnV7F/l wiMhBzkvGN5PcWk/IGfKVmergyGR+bU+3ZTsjKg8ah9zgHQIhp28sQacJTVDxhiYk/Kz 0ImgRYDfakh8U5zkXCSSNUf0OrNlwBvA7PTAvRHcQWuhQXobowAh4h+QR6qzvkwXWika Y2/Q== X-Gm-Message-State: ACgBeo3bwJA4m3SksTg1c32LJln3jj/SgujGa4S+n0+REXvNL0qhFux9 U5NY5IhX//IWGX5Hy8osa2Az X-Google-Smtp-Source: AA6agR687zf0LoatHaeWiGH4w815XItAduyFQasakKnQ/p68K4peAppr3Gu0UF/br24Pcir9Gx0E5A== X-Received: by 2002:a17:902:b217:b0:172:bd6c:814d with SMTP id t23-20020a170902b21700b00172bd6c814dmr35664854plr.55.1663142047255; Wed, 14 Sep 2022 00:54:07 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.122]) by smtp.gmail.com with ESMTPSA id p8-20020a1709027ec800b00174ea015ee2sm10119054plb.38.2022.09.14.00.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 00:54:06 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 01/12] PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure Date: Wed, 14 Sep 2022 13:23:39 +0530 Message-Id: <20220914075350.7992-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> References: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add kernel-doc for qcom_pcie_ep structure. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 9f92d53da81a..27b7c9710b5f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -140,6 +140,23 @@ static struct clk_bulk_data qcom_pcie_ep_clks[] = { { .id = "slave_q2a" }, }; +/** + * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller + * @pci: Designware PCIe controller struct + * @parf: Qualcomm PCIe specific PARF register base + * @elbi: Designware PCIe specific ELBI register base + * @perst_map: PERST regmap + * @mmio_res: MMIO region resource + * @core_reset: PCIe Endpoint core reset + * @reset: PERST# GPIO + * @wake: WAKE# GPIO + * @phy: PHY controller block + * @perst_en: Flag for PERST enable + * @perst_sep_en: Flag for PERST separation enable + * @link_status: PCIe Link status + * @global_irq: Qualcomm PCIe specific Global IRQ + * @perst_irq: PERST# IRQ + */ struct qcom_pcie_ep { struct dw_pcie pci; From patchwork Wed Sep 14 07:53:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 606793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83FE8ECAAD8 for ; Wed, 14 Sep 2022 07:54:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230216AbiINHya (ORCPT ); Wed, 14 Sep 2022 03:54:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230202AbiINHyV (ORCPT ); Wed, 14 Sep 2022 03:54:21 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9FCA72FE5 for ; Wed, 14 Sep 2022 00:54:19 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id jm11so14283375plb.13 for ; Wed, 14 Sep 2022 00:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=cXVSIoAXy4k6GvjO7JA/nhvOJMAK8QRnMR9+cTCkOGs=; b=qez3AqbemKhd2KHJlD1Y8nPiFRA2B4wpF2ojCVOvYEpgfYVqNisNl6VaQqbg1qFVKv 3qysIrPolQaIUaSd8GhD4gt+oVRuahoSSICPiIAukmbJnsfXdtSaEqpnK1mLBRKyyJWx RGsJT5EebaZI1/7zaA2ZiAtBfe9ZGR8fTfsJbT1R7L/gnPzoQ9eIQCKSwWdmTlRmrZ23 hXVZ7njIpcPNg9Z2InNNa/OzsF/xeDhAio+c5fFTgV0tmqXaJGFjmPGLtmxPmp8G9WEd q66Ki1HYnnx1wW7o9hPrk8Rl4GIcCoekQUk4koJS7wWk1za3rtMFRmfqciCSlkQYDokA K5yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=cXVSIoAXy4k6GvjO7JA/nhvOJMAK8QRnMR9+cTCkOGs=; b=FZyk+8nL56ZJECEStzahXO1za6j6j0UE8Vr9PAYvYNQGDBeTRz5uszp4z+GChrcmKS OZYEFPLniPzj9uLbKO70K1XQ9S++EP6Hz/bc9S48ZH/uue8jdpj3+qnFZk+v+NIoER1J 2/1s2zjrGz70NkasZmPxpq0HIWW+EUkjNlBUCBrTwWr0Diw2xkCW6sTzhN7QTXqovR4F JV4+2G8Bey7ihCFhsoc+msAERfIEYERnUlYEnyNIZycw3bOSGo8gbvlchlU8x58Ow+qY j1c6a5qI0Z2BOxyeEqNJv4OTMVReO1az8rYCS6cBRWs0frieMwhklDGXFDE2k0mGjVFS leAQ== X-Gm-Message-State: ACgBeo0pQrrIcn0tqYYtVPPvr/Sk/r3RoOYONCUb/+dbQx+UalJibUDQ A0lq89Iv8TTM1lwo4I7oftR8 X-Google-Smtp-Source: AA6agR4d+gm8VSzIVcCgMlF5CW7W94zSpFyFAlU9mNy7XgcL0NZIqXmaGst93x7L6Z/ZqsI3b4OthA== X-Received: by 2002:a17:902:bd05:b0:172:ae77:1eea with SMTP id p5-20020a170902bd0500b00172ae771eeamr35061464pls.158.1663142058990; Wed, 14 Sep 2022 00:54:18 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.122]) by smtp.gmail.com with ESMTPSA id p8-20020a1709027ec800b00174ea015ee2sm10119054plb.38.2022.09.14.00.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 00:54:18 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 03/12] PCI: qcom-ep: Make use of the cached dev pointer Date: Wed, 14 Sep 2022 13:23:41 +0530 Message-Id: <20220914075350.7992-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> References: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the qcom_pcie_ep_get_resources() function, dev pointer is already cached in a local variable. So let's make use of it instead of getting the dev pointer again from pdev struct. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 34c498d581de..1e09eca5b3b2 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -483,7 +483,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep); if (ret) { - dev_err(&pdev->dev, "Failed to get io resources %d\n", ret); + dev_err(dev, "Failed to get io resources %d\n", ret); return ret; } @@ -505,7 +505,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, if (IS_ERR(pcie_ep->wake)) return PTR_ERR(pcie_ep->wake); - pcie_ep->phy = devm_phy_optional_get(&pdev->dev, "pciephy"); + pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); if (IS_ERR(pcie_ep->phy)) ret = PTR_ERR(pcie_ep->phy); From patchwork Wed Sep 14 07:53:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 606792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A42A7C6FA89 for ; Wed, 14 Sep 2022 07:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230291AbiINHzH (ORCPT ); Wed, 14 Sep 2022 03:55:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230252AbiINHyj (ORCPT ); Wed, 14 Sep 2022 03:54:39 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 407A71155 for ; Wed, 14 Sep 2022 00:54:32 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id v4so13576409pgi.10 for ; Wed, 14 Sep 2022 00:54:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=BmOWU26gjLBIOonkKcZ0ILBj0OeiqDzaVAugyvdHpNQ=; b=ScM8Pi5xIEHRfZElpQvyLnPbEmuIDVDUfS64bTvorxQf3MQlJGCGSFwwhlTpQqXajY dEOnCFWcI8pMFn7nYJ7QR4JrW6WTQK9v5Nbyc/3pnDtdcmCOsDfe+LC+Ot5Olr/fQ/hW Ra9ZQceClL0Xh2ESP7pjfaGkI/Vo6aJHCOSIUi91jHDf5+7hDCP/CIYSPb7VwnU4j3J8 ALqMGXIk6bz7roWDxnyriH9XiqDPKxVbhoRFESq0VFhSIsInSok8Wepimlx/V7CyHLCK pyMmq+/37lUgTMduEQbKl6lIgwxdrRo6YCIF+qhiN7iwR9xf3IRF+Q8ILzSguc6ET2WB 1yuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=BmOWU26gjLBIOonkKcZ0ILBj0OeiqDzaVAugyvdHpNQ=; b=vZ47j0gg2PsvyBeVmXt/KGuMzJkkA/nqhh8ldJ3hxoYFgxUVK8ZPz5nAVxiY2Fp4M3 IWFKM/DmVvzAWqmLV3iTVLTNA2jR02Eihh/xUK5CuEyj8c7heyUI1FmQfnHhW0KCZ2+G M9kcf0ORXWpZ1WC7oc25/VuO/npSaapb08SrOvwoSNSKQTJ+OMV8zTL8DhbEcMOZvkUg L8xjyJYm2ujNE4hKWoAZrODg7WHGVFHdRIpZtz/2LnyZyH5Yu72S6g+wzXbwGjEaHyAT hcin6mUWI58lSvhNA7B5946KAZQdASsQUnHlFsZHW1QDpVWOXWgIvDK7uS5VSXMXXb/O PI5Q== X-Gm-Message-State: ACgBeo0sBJ7j8ilAIBlPLaqoj/WcUxCFSRi/xyvfSZXaI2VWOUY1KK7A +OICy7JgVN7Mu/GaUdH7h15i X-Google-Smtp-Source: AA6agR7J9lOpcH4DAcMCYZmGgbbWz6EuCww8Cg5abiUxwkNkJP96/s3sSYcJ793K0ntpPo/MN8xAmg== X-Received: by 2002:a63:847:0:b0:439:22e4:8e49 with SMTP id 68-20020a630847000000b0043922e48e49mr8965145pgi.165.1663142071017; Wed, 14 Sep 2022 00:54:31 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.122]) by smtp.gmail.com with ESMTPSA id p8-20020a1709027ec800b00174ea015ee2sm10119054plb.38.2022.09.14.00.54.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 00:54:30 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 05/12] PCI: qcom-ep: Expose link transition counts via debugfs Date: Wed, 14 Sep 2022 13:23:43 +0530 Message-Id: <20220914075350.7992-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> References: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm PCIe controllers have debug registers in the MMIO region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 72eb6cacdb3a..2dc6d4e44aff 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -45,6 +46,11 @@ #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 #define PARF_SRIS_MODE 0x644 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c +#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_CFG 0x2c00 @@ -135,12 +141,14 @@ enum qcom_pcie_ep_link_status { * @pci: Designware PCIe controller struct * @parf: Qualcomm PCIe specific PARF register base * @elbi: Designware PCIe specific ELBI register base + * @mmio: MMIO register base * @perst_map: PERST regmap * @mmio_res: MMIO region resource * @core_reset: PCIe Endpoint core reset * @reset: PERST# GPIO * @wake: WAKE# GPIO * @phy: PHY controller block + * @debugfs: PCIe Endpoint Debugfs directory * @clks: PCIe clocks * @num_clks: PCIe clocks count * @perst_en: Flag for PERST enable @@ -154,6 +162,7 @@ struct qcom_pcie_ep { void __iomem *parf; void __iomem *elbi; + void __iomem *mmio; struct regmap *perst_map; struct resource *mmio_res; @@ -161,6 +170,7 @@ struct qcom_pcie_ep { struct gpio_desc *reset; struct gpio_desc *wake; struct phy *phy; + struct dentry *debugfs; struct clk_bulk_data *clks; int num_clks; @@ -446,6 +456,9 @@ static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio"); + pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); + if (IS_ERR(pcie_ep->mmio)) + return PTR_ERR(pcie_ep->mmio); syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); if (!syscon) { @@ -629,6 +642,37 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, } } +static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data) +{ + struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *) + dev_get_drvdata(s->private); + + seq_printf(s, "L0s transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); + + seq_printf(s, "L1 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); + + seq_printf(s, "L1.1 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); + + seq_printf(s, "L1.2 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); + + seq_printf(s, "L2 transition count: %u\n", + readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); + + return 0; +} + +static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) +{ + struct dw_pcie *pci = &pcie_ep->pci; + + debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs, + qcom_pcie_ep_link_transition_count); +} + static const struct pci_epc_features qcom_pcie_epc_features = { .linkup_notifier = true, .core_init_notifier = true, @@ -661,6 +705,7 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qcom_pcie_ep *pcie_ep; + char *name; int ret; pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); @@ -686,8 +731,21 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) if (ret) goto err_disable_resources; + name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); + if (!name) { + ret = -ENOMEM; + goto err_disable_irqs; + } + + pcie_ep->debugfs = debugfs_create_dir(name, NULL); + qcom_pcie_ep_init_debugfs(pcie_ep); + return 0; +err_disable_irqs: + disable_irq(pcie_ep->global_irq); + disable_irq(pcie_ep->perst_irq); + err_disable_resources: qcom_pcie_disable_resources(pcie_ep); @@ -701,6 +759,8 @@ static int qcom_pcie_ep_remove(struct platform_device *pdev) disable_irq(pcie_ep->global_irq); disable_irq(pcie_ep->perst_irq); + debugfs_remove_recursive(pcie_ep->debugfs); + if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) return 0; From patchwork Wed Sep 14 07:53:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 606791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E557EECAAD3 for ; Wed, 14 Sep 2022 07:55:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230171AbiINHz2 (ORCPT ); Wed, 14 Sep 2022 03:55:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230286AbiINHzC (ORCPT ); Wed, 14 Sep 2022 03:55:02 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4480AE0B7 for ; Wed, 14 Sep 2022 00:54:43 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id e68so14136113pfe.1 for ; Wed, 14 Sep 2022 00:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=rmpTVMmLmv6UMsIzgv+O74eFW0TvLRItNBIUwPHHvPM=; b=W80PLz3cj7OTdR2xEOoF7e15KEc68u0lAxgpkr052tLq0DN9vxB+vD6435bBK7Outd PhwZauqjX4/X5LWYKbAlBMzpqSkNf9LEzzqxTXPFjIvU0jFBJkkpsCuqkGNvDIFAQXW+ Zjq0Q40DphcIvkqCkyx+tzNI4w59TGnztg7Y6OiaOGhiVL220eo5AOHg6RPzg5A+MxjU pSpLLDNwRAZPrrNGSQZmRMFpwU4nOsZib2PvmoZqYSjAkMxvS6neX4cOEx9vzICYQuua QYDGJ7Y1H6bCjS8PvR8oGFQN+1IBH8fv6yDPP+BQajL/G28f3gDtKVMeze/3PzIEHj7e +7fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=rmpTVMmLmv6UMsIzgv+O74eFW0TvLRItNBIUwPHHvPM=; b=g96MI6cZDloPxOF2Bh4HQZD8SHFma6OcSXBgxxJmgewjj7B3HSOR40ZxUfagwDdFEf VgGC9AaLL3Jn8n8K4dlAkqsL71KDU+qOqTJyL3Fk89iWV7p27wp1guMY64R44H/r5s1e o+X6k5L3+6Zxjjw5LhDNbxcs86M4+JMPwUkAkZ4HyL95b+ftPtRud8ibZcyeMLopuqSV zdC+ZGXSb8u8YVabgl5cIs1dBD2GiFaf1zace1mG34xBKIdJetOLyvteRY8qyN8E3QuU o60mhOWiQt15G/sKLJ1w8R2E+Jvb3vq3p4zp6OO7z0jouReA+Bo4hyL30yGkcjpG1L9A pFUw== X-Gm-Message-State: ACgBeo3dHQnNvv/oF5ln0zE4AvXhNR6wTu77MS3WD7OmEVEvr2dJZICm /3IYPBhD63uYGgT7Hyr9ADjM X-Google-Smtp-Source: AA6agR5CxdndaK0G7PKDFZZC4RRnzrbG3c3QW1kLROYUPhM/+vc97wH8N+DYutyDUHSyS3+JkDridA== X-Received: by 2002:a63:2c0b:0:b0:434:ebb6:7594 with SMTP id s11-20020a632c0b000000b00434ebb67594mr29028939pgs.245.1663142082905; Wed, 14 Sep 2022 00:54:42 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.122]) by smtp.gmail.com with ESMTPSA id p8-20020a1709027ec800b00174ea015ee2sm10119054plb.38.2022.09.14.00.54.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 00:54:42 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 07/12] PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic Date: Wed, 14 Sep 2022 13:23:45 +0530 Message-Id: <20220914075350.7992-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> References: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Master AXI clock can be disabled when it is not used i.e., when there is no traffic on the PCIe bus. This helps to save power during idle state. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 526e98ea23f6..40f75a6c55df 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -105,6 +105,7 @@ /* PARF_SYS_CTRL register fields */ #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4) #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6) +#define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10) #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11) /* PARF_DB_CTRL register fields */ @@ -341,8 +342,14 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) val &= ~PARF_Q2A_FLUSH_EN; writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH); - /* Disable DBI Wakeup, core clock CGC and enable AUX power */ + /* + * Disable Master AXI clock during idle + * Do not allow DBI access to take the core out of L1 + * Disable core clock gating that gates PIPE clock from propagating to core clock + * Report to the host that Vaux is present + */ val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL); + val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS; val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE | PARF_SYS_CTRL_CORE_CLK_CGC_DIS | PARF_SYS_CTRL_AUX_PWR_DET; From patchwork Wed Sep 14 07:53:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 606790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6DCBC6FA89 for ; Wed, 14 Sep 2022 07:55:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230261AbiINHzx (ORCPT ); Wed, 14 Sep 2022 03:55:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230266AbiINHzW (ORCPT ); Wed, 14 Sep 2022 03:55:22 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0159918B25 for ; Wed, 14 Sep 2022 00:54:56 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id v4so13577232pgi.10 for ; Wed, 14 Sep 2022 00:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=qIqmnnPPd/w9PevtCzz3I9Xl0se/j1JE8K0DzKiojlg=; b=xLwR1mJuVy34/JvHtpZKgmKBiqRV+MIFyUCk0n6BmwK5jdgtI2R7dz0OHzvYMo9DGO NW+Wg7NqwoiQmhHpAP/GA5xju3wTlWZDXOC+knC7yN7jw5qfECsSXRLbIjkO4joaoWtb 8sXIM/d7vKUjJfpv3ccDXHO3bUO0z+lEMOYJksUvp0MjW4hC7kw711ynHQf8IqguMPrd vv87xH8Tmxl3zK0w3SVgFZJmxnotad2NDOtnfLIkfZSuAUURbS9hkHyVoqTzfML+Stix T6tO35N2jQlNUUHwi5unIYHzzqhmOWCWb7hmIJHSG+eqL2VPd4U1z2AdC//3CNlSL0/t NgZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=qIqmnnPPd/w9PevtCzz3I9Xl0se/j1JE8K0DzKiojlg=; b=EKx5W+6HhOM4ntAhgXB/VcIKMNn3Ek8TKL/uMh4GbMhH/o1g0yw6s5fmcqSM2Yqv7u WcAlgbA6UYp35lbucAyQZGL0voYM+HYIHSo921x4FGVgGpwY6wEYeSOEyjZ3ih6wgdOx 4NwgDh9/mJ0U3dnDoFV2zOzaUez2KEkRvvD3TKvgmLkOQQgJFh3DCILXtHsB7x7uwwYU hbPCkLJVBapTK39QmCJB5oHcu3pVmZthdtlVucvA9Iw+FoPS7DoZW8dd73jS02gZx4mh QAgQUCD6oUSCnXZyh34ohE5uE6tl+V1n+bqf/yfqm+g/aIPnqRyG1wbUuAsF62g6gWn4 5Dug== X-Gm-Message-State: ACgBeo3FdfMPWQEPIRbeMwOx0zjpsZEIdVxVqgZVRm4sU8S7oelEnpeg AD7TfZzXRiVDqdr6NOtryN1n X-Google-Smtp-Source: AA6agR6CniLWKO3rP5PihB6hHOHcm/blzCTKeYPSDusx8T0u0JuJSFk8eJwnOtZcYkLjeMQ18NtkOw== X-Received: by 2002:a05:6a00:174f:b0:53a:a96b:10b0 with SMTP id j15-20020a056a00174f00b0053aa96b10b0mr36456123pfc.68.1663142095704; Wed, 14 Sep 2022 00:54:55 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.122]) by smtp.gmail.com with ESMTPSA id p8-20020a1709027ec800b00174ea015ee2sm10119054plb.38.2022.09.14.00.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 00:54:55 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 09/12] PCI: qcom-ep: Make PERST separation optional Date: Wed, 14 Sep 2022 13:23:47 +0530 Message-Id: <20220914075350.7992-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> References: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PERST separation is an optional debug feature used to collect the crash dump from the PCIe endpoint devices by the PCIe host when the endpoint crashes. This feature keeps the PCIe link up by separating the PCIe IP block from the SoC reset logic. Hence, make the property optional in the driver. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 40f75a6c55df..92140a09aac5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -220,8 +220,10 @@ static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) */ static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep) { - regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); - regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); + if (pcie_ep->perst_map) { + regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0); + regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0); + } } static int qcom_pcie_dw_link_up(struct dw_pcie *pci) @@ -478,8 +480,8 @@ static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); if (!syscon) { - dev_err(dev, "Failed to parse qcom,perst-regs\n"); - return -EINVAL; + dev_dbg(dev, "PERST separation not available\n"); + return 0; } pcie_ep->perst_map = syscon_node_to_regmap(syscon); From patchwork Wed Sep 14 07:53:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 606789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BC24ECAAD8 for ; Wed, 14 Sep 2022 07:56:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230302AbiINH41 (ORCPT ); Wed, 14 Sep 2022 03:56:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230197AbiINHzt (ORCPT ); Wed, 14 Sep 2022 03:55:49 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2411B4662B for ; Wed, 14 Sep 2022 00:55:09 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id w20so2249574ply.12 for ; Wed, 14 Sep 2022 00:55:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9mP9HJdXVQAxtsXYpKC+mSQmcqbaHq7yO4Fo8xLEceU=; b=wUYIypOhGADGriBI+bgSRel8LMXbpdGqu9/K77qWEwH64/UwapHSINwuixauatFQVk WMK2f7wAtaMNTmJ6LW0Z5QDYcOXpzm6SKnovPAZPUrrc+ylHK66rhmKzWDfaarZJ9rNz CuvtrZiYbgO3iDlkxqXAYuZGZV6d3iFjhOKokE6zrBj6Qx1S4QFOkCuBtLrQnhVjJM0S uU97M8xv7YoznAK8Kl+axyREUlhNamsPYT4vyAVDK1vV2TgimGoGlsXWqRG8tX4G8eYC YXG2hyhuDPRQbsjSG0W9FaHs4f3D07Puk0UgAJ/NEDqdRYMVToYuDCXqSjqQr8pzgwAM RKSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9mP9HJdXVQAxtsXYpKC+mSQmcqbaHq7yO4Fo8xLEceU=; b=UW4QMl3R5NwNIYBANEdyFALRFnW2hZhR95tgifqKUNzZ5qw2EVcJwSNx2vZ8s/j6s2 Q1a3tXHJDm1GOlC6zxL+UMPCFPifbJ4VyWlJ3OVUGOZSmd9j+4BwwbV8h0JczWPivMU2 W5qnisftODPiyBhYAmAg7JUNIf1DTj3qtM1/EgpiFFwzcCiar/tMeJSj0FirpSb6D78v 0/VBK9I5muNbc0uzwB5EWkxvwkg+Edex5HXLWLIs1Z2xF4iFjGYByymvQOG2FFn2R3G9 evL9n/Tb+GlZC5wd8rMxoGblL8w8/rkEhE+L5mldJx/d3EnTFdsd7EvJUxKaL85kdOVJ CCYQ== X-Gm-Message-State: ACrzQf1D+JHUUy2p6yhbPzIrWqALRf28U0ruW58ehHgjIpWAnJpew8ER hOIKlQZNCthkhkhZqMQZQBYT X-Google-Smtp-Source: AMsMyM40w4UYyHvFh7evE7z1F+eiJYVMfWYqChW7KmQX97jRbMwd47LDyQUEe+xCqqea0RKZyIe2Mw== X-Received: by 2002:a17:90b:306:b0:202:b9a4:b0aa with SMTP id ay6-20020a17090b030600b00202b9a4b0aamr3467801pjb.78.1663142108381; Wed, 14 Sep 2022 00:55:08 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.122]) by smtp.gmail.com with ESMTPSA id p8-20020a1709027ec800b00174ea015ee2sm10119054plb.38.2022.09.14.00.55.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 00:55:07 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v4 11/12] dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC Date: Wed, 14 Sep 2022 13:23:49 +0530 Message-Id: <20220914075350.7992-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> References: <20220914075350.7992-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree bindings support for SM8450 SoC. Only the clocks are different on this platform, rest is same as SDX55. Reviewed-by: Rob Herring Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++-- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index bb8e982e69be..977c976ea799 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: qcom,sdx55-pcie-ep + enum: + - qcom,sdx55-pcie-ep + - qcom,sm8450-pcie-ep reg: items: @@ -32,10 +34,12 @@ properties: - const: mmio clocks: - maxItems: 7 + minItems: 7 + maxItems: 8 clock-names: - maxItems: 7 + minItems: 7 + maxItems: 8 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -124,6 +128,35 @@ allOf: - const: sleep - const: ref + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Reference clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ref + - const: ddrss_sf_tbu + - const: aggre_noc_axi + unevaluatedProperties: false examples: