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[209.51.188.17]) by mx.google.com with ESMTPS id r13-20020a0562140c4d00b00496b42cd3f4si3180416qvj.456.2022.09.22.08.08.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 22 Sep 2022 08:08:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fFf1HjTj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obNol-0007Oj-Jf for patch@linaro.org; Thu, 22 Sep 2022 11:08:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obNex-0001Gv-TQ for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:39 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:40754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obNeu-0000vR-NY for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:39 -0400 Received: by mail-wr1-x431.google.com with SMTP id x18so9969924wrm.7 for ; Thu, 22 Sep 2022 07:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Qi/Jq9vAe/ynL99P1jKgO//PJIcQTC65awVNXqG6oLE=; b=fFf1HjTjwykz34p2ihmdaWqY7zrjkCANDfbW5f5LeK8hJYt0MHnjr3jyltJhZbbKNg RwRe0TiOhfWzlLEcADCqtEoWqVVzfH4PqacZ9Fa+rGun2k8+vYk6IQJon9BS/vFw1Ri9 wgIFS4kaAGzCzKt+CW2Xi5LBfwJ/vR7E4rfaFKiXQZ2MrYsUuaEseObnmdDTw/zI8nHk DjRLv3BS+eIgHYLnqzwga7cPGC8oNv1iA0XScHDpXyqpx8KCOpqoWp4/PE07g7SV3O3O kDpTkw9zVRFbaY9VJ6WlAXY2rLBbCswgQPbFaO+zZ2iP5z/YS135iyOGlifw9YtBxuXH hctw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Qi/Jq9vAe/ynL99P1jKgO//PJIcQTC65awVNXqG6oLE=; b=Ub988IZlWhwiobUKDj82Lr2Wm1+bq1Kxvz2pO5E3Veh0ML6vQbyp3uIBBdr/ykZQyK I8tXis/aoj/ffYePEGqmA9rYZDodo2KHLkSIFN4e80U+g05NOF+TIRxSeyuNqr3gP+FL /Y9ngUmO8GEVtqyAK00Pekhu/Jw/gZB00lyuAPLbIcy3Gan7QWYJeuLMVXIBGwLFKOn1 hNlmuhHFsDYk9nDnoRxfb2vcRdc9cWOYVgcD5OzJnw0XaJviga+u6ydAkqMO/6a+zdTT SrWYpOd85/oi08pUkmMO+dM6peAI//1tIdWaMyD7YlRkU550P74MVZ/LkOD8Xnu4VkKg 6+Jw== X-Gm-Message-State: ACrzQf1asLoQebr9CN+Q2SNhVOYxOwElE/XDHv3LBoXSbeZB7MfiH0Jg bd57yelffDHw8ygQGffalVpP+Q== X-Received: by 2002:a05:6000:144c:b0:22b:dda:eeb0 with SMTP id v12-20020a056000144c00b0022b0ddaeeb0mr2430147wrx.335.1663858714797; Thu, 22 Sep 2022 07:58:34 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id z6-20020a05600c220600b003b492753826sm6019245wml.43.2022.09.22.07.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 07:58:32 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6A70A1FFB8; Thu, 22 Sep 2022 15:58:32 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini Subject: [PATCH v1 1/9] hw: encode accessing CPU index in MemTxAttrs Date: Thu, 22 Sep 2022 15:58:24 +0100 Message-Id: <20220922145832.1934429-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922145832.1934429-1-alex.bennee@linaro.org> References: <20220922145832.1934429-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We currently have hacks across the hw/ to reference current_cpu to work out what the current accessing CPU is. This breaks in some cases including using gdbstub to access HW state. As we have MemTxAttrs to describe details about the access lets extend it to mention if this is a CPU access and which one it is. There are a number of places we need to fix up including: CPU helpers directly calling address_space_*() fns models in hw/ fishing the data out of current_cpu I'll start addressing some of these in following patches. Signed-off-by: Alex Bennée --- v2 - use separate field cpu_index - bool for requester_is_cpu --- include/exec/memattrs.h | 4 ++++ accel/tcg/cputlb.c | 22 ++++++++++++++++------ hw/core/cpu-sysemu.c | 17 +++++++++++++---- 3 files changed, 33 insertions(+), 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..e83a993c21 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -43,6 +43,10 @@ typedef struct MemTxAttrs { * (see MEMTX_ACCESS_ERROR). */ unsigned int memory:1; + /* Requester is CPU (or as CPU, e.g. debug) */ + bool requester_is_cpu:1; + /* cpu_index (if requester_is_cpu) */ + unsigned int cpu_index:16; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; /* Invert endianness for this page */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8fad2d9b83..5d88569eb5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1340,8 +1340,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, uint64_t val; bool locked = false; MemTxResult r; + MemTxAttrs attrs = iotlbentry->attrs; - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + /* encode the accessing CPU */ + attrs.requester_is_cpu = 1; + attrs.cpu_index = cpu->cpu_index; + + section = iotlb_to_section(cpu, iotlbentry->addr, attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; @@ -1353,14 +1358,14 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, qemu_mutex_lock_iothread(); locked = true; } - r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs); + r = memory_region_dispatch_read(mr, mr_offset, &val, op, attrs); if (r != MEMTX_OK) { hwaddr physaddr = mr_offset + section->offset_within_address_space - section->offset_within_region; cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type, - mmu_idx, iotlbentry->attrs, r, retaddr); + mmu_idx, attrs, r, retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1395,8 +1400,13 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, MemoryRegion *mr; bool locked = false; MemTxResult r; + MemTxAttrs attrs = iotlbentry->attrs; + + /* encode the accessing CPU */ + attrs.requester_is_cpu = true; + attrs.cpu_index = cpu->cpu_index; - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section = iotlb_to_section(cpu, iotlbentry->addr, attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; if (!cpu->can_do_io) { @@ -1414,14 +1424,14 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, qemu_mutex_lock_iothread(); locked = true; } - r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs); + r = memory_region_dispatch_write(mr, mr_offset, val, op, attrs); if (r != MEMTX_OK) { hwaddr physaddr = mr_offset + section->offset_within_address_space - section->offset_within_region; cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), - MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r, + MMU_DATA_STORE, mmu_idx, attrs, r, retaddr); } if (locked) { diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 00253f8929..cdabc577d2 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -51,13 +51,22 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs) { CPUClass *cc = CPU_GET_CLASS(cpu); + MemTxAttrs local = { }; + hwaddr res; if (cc->sysemu_ops->get_phys_page_attrs_debug) { - return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); + res = cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, &local); + } else { + /* Fallback for CPUs which don't implement the _attrs_ hook */ + local = MEMTXATTRS_UNSPECIFIED; + res = cc->sysemu_ops->get_phys_page_debug(cpu, addr); } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs = MEMTXATTRS_UNSPECIFIED; - return cc->sysemu_ops->get_phys_page_debug(cpu, addr); + + /* debug access is treated as though it came from the CPU */ + local.requester_is_cpu = 1; + local.cpu_index = cpu->cpu_index; + *attrs = local; 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However because it's not a real system we have places in the code which especially handle check qtest_enabled() before referencing current_cpu. Now we can encode these details in the MemTxAttrs lets do that so we can start removing them. Signed-off-by: Alex Bennée --- v2 - use a common macro instead of specific MEMTXATTRS_QTEST --- include/exec/memattrs.h | 4 ++++ softmmu/qtest.c | 26 +++++++++++++------------- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index e83a993c21..021b68dd06 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -70,6 +70,10 @@ typedef struct MemTxAttrs { */ #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) +/* Helper for setting a basic CPU id */ +#define MEMTXATTRS_CPU(id) ((MemTxAttrs) \ + {.requester_is_cpu = true, .cpu_index = id}) + /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure * of some kind. The memory subsystem will bitwise-OR together results diff --git a/softmmu/qtest.c b/softmmu/qtest.c index f8acef2628..3aa2218b95 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][5] == 'b') { uint8_t data = value; - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 1); } else if (words[0][5] == 'w') { uint16_t data = value; tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 2); } else if (words[0][5] == 'l') { uint32_t data = value; tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 4); } else if (words[0][5] == 'q') { uint64_t data = value; tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 8); } qtest_send_prefix(chr); @@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][4] == 'b') { uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 1); value = data; } else if (words[0][4] == 'w') { uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 2); value = tswap16(data); } else if (words[0][4] == 'l') { uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 4); value = tswap32(data); } else if (words[0][4] == 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &value, 8); tswap64s(&value); } @@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(len); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); enc = g_malloc(2 * len + 1); @@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(ret == 0); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); b64_data = g_base64_encode(data, len); qtest_send_prefix(chr); @@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) data[i] = 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); g_free(data); @@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (len) { data = g_malloc(len); memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); g_free(data); } @@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) out_len = MIN(out_len, len); } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); qtest_send_prefix(chr); From patchwork Thu Sep 22 14:58:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 608218 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp402479pvb; Thu, 22 Sep 2022 08:21:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4RPYX5lEGYvXxTH9h+ozIptCZROjpvv56Vpoyah9m+oEM6+w3aL8m5VJRBniznGGqQR0+t X-Received: by 2002:a05:620a:1720:b0:6ce:7d38:c307 with SMTP id az32-20020a05620a172000b006ce7d38c307mr2563436qkb.149.1663860112464; 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[209.51.188.17]) by mx.google.com with ESMTPS id f30-20020ac840de000000b0035cbf70f63fsi3029343qtm.767.2022.09.22.08.21.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 22 Sep 2022 08:21:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sh1B0sy7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obO1P-0006zb-Tr for patch@linaro.org; Thu, 22 Sep 2022 11:21:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obNez-0001JF-AT for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:41 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:45766) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obNew-0000ve-Fi for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:41 -0400 Received: by mail-wr1-x42f.google.com with SMTP id n10so15930491wrw.12 for ; Thu, 22 Sep 2022 07:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=F+zZe6vtaknwERE4uZ/2QI8HgWfBE9fG1am+Ti0J6hQ=; b=sh1B0sy7A5nR4rWv8wHAsP0I4YkNF2xLXwPDofRoKp5jR1ujiAbhUDkLrcL76HbQJ+ zifdt052qvvY+aJrC9LZ4yVfLK0Utwf+ET1dQGuWpfHb5O2kGaStuF9HV9H/T6Re1ihw S8YKSgCPdka3RoflZ+84VzaDTla/oIwjHCChBDKn8VWQVbSU84hyFpyfYIlRMMHHR+0x pBXeCt1y9eZR435BlY4nuhYgbIWZHLTKBpW4+b3rPrzl7bkLYeEm6WKWNhPpO/wQpdfo r53J+NLl4J4q/SwPRu8Crh/oZdwm+jztt0IRQjG6T6zKVSCiWlYMklfHVAWbP82vpkgJ iOCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=F+zZe6vtaknwERE4uZ/2QI8HgWfBE9fG1am+Ti0J6hQ=; b=U9G8SCTtTkSeG1EX4cYYbILoxqp8XpgheM4GzaBePVAGZbITRGQFNQJj5fo2oiGGMb 2tzc7hveVTeq54Xz6DtbI3wUFUBRQlrfdBLhWDTpxtZr+XYG3sdqg64urPvwp/XuSJ2R 47YXwc2xFwQPwpNJ5v6SqqBsq0xkFn1jDtXJpUVHkKiz9xYfntnaB/JQECC6A1NIFbnC Xy7uKOw0jLPpvplri3soEaHmSszKz9l0OyV2HP88wEgqhvrn2LhlwOTtnsIQXSvr6YRK u6SMY9f0Z+KTsheRWqHoZWqENAFrWnYtrGoL3lrQecB0Z9CUBUCs5YUr3EzgwtE7nHID 2jzg== X-Gm-Message-State: ACrzQf2VM8eKhBFrytFgloMgWvke61gV0B+JTzgFcihHQFssIRJWQajt lRSfdaujM83Cp0Oib+Od6mwlGg== X-Received: by 2002:adf:fa88:0:b0:228:6237:d46c with SMTP id h8-20020adffa88000000b002286237d46cmr2382382wrr.571.1663858716904; Thu, 22 Sep 2022 07:58:36 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id r14-20020a0560001b8e00b0022afcc11f65sm5203305wru.47.2022.09.22.07.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 07:58:35 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9CF8C1FFBB; Thu, 22 Sep 2022 15:58:32 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM cores) Subject: [PATCH v1 3/9] hw/intc/gic: use MxTxAttrs to divine accessing CPU Date: Thu, 22 Sep 2022 15:58:26 +0100 Message-Id: <20220922145832.1934429-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922145832.1934429-1-alex.bennee@linaro.org> References: <20220922145832.1934429-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. Signed-off-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 Reviewed-by: Richard Henderson --- v2 - update for new field - bool asserts --- hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab..b58d3c4a95 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -static inline int gic_get_current_cpu(GICState *s) +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; - } - return 0; + /* + * Something other than a CPU accessing the GIC would be a bug as + * would a CPU index higher than the GICState expects to be + * handling + */ + g_assert(attrs.requester_is_cpu); + g_assert(attrs.cpu_index < s->num_cpu); + + return attrs.requester_id; } -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } /* Return true if this GIC config has interrupt groups, which is @@ -951,7 +956,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) int cm; int mask; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); cm = 1 << cpu; if (offset < 0x100) { if (offset == 0) { /* GICD_CTLR */ @@ -1182,7 +1187,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, int i; int cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); if (offset < 0x100) { if (offset == 0) { if (s->security_extn && !attrs.secure) { @@ -1476,7 +1481,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, int mask; int target_cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); irq = value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1780,7 +1785,7 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1788,7 +1793,7 @@ static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1818,7 +1823,7 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1827,7 +1832,7 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, attrs); } static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1860,7 +1865,7 @@ static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) { - int vcpu = gic_get_current_vcpu(s); + int vcpu = gic_get_current_vcpu(s, attrs); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1995,7 +2000,7 @@ static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *dat { GICState *s = (GICState *)opaque; - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, @@ -2004,7 +2009,7 @@ static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, From patchwork Thu Sep 22 14:58:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 608219 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp404341pvb; Thu, 22 Sep 2022 08:25:19 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6L12jI2rF118+Pv+1IzbVSySyXu631QvOm87/VfCtBcneCWLmT480EATjm9cGsmNEaaPyW X-Received: by 2002:a37:e115:0:b0:6cf:55d:6ac6 with SMTP id c21-20020a37e115000000b006cf055d6ac6mr2538551qkm.251.1663860319030; Thu, 22 Sep 2022 08:25:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663860319; cv=none; d=google.com; s=arc-20160816; b=dOGcBOGhzoMvgT7/pYonYiK0K4objR5Z0lQM54vnvEmliBKudRuzf7NmwrFrlLbD5u jUUg+stcc8zy8KWNGfk0zeCm7DDSCQEmUI0uYIXPJ5B9+hFEFpX7ttIbfR9Q5Vn7wfqv ACj7QcUnySxFDnzDsrBIHwR5pVi9xdf4r7VLCx57xi7rip+RvI917U+D5eUFKp0illZi lZg0S+BHVhUjoqAfQn31JLOepD7WKP/C+DKUiZ4ukYy9mjpxGxS3LSnMzpuPzB1idqi9 UUVXIxrD1Si5JktLhWqfOxEwmaM3G/mNbDIIPYUcKObHObanaO4+T4bIVdeBja1v/a2O 5bKg== ARC-Message-Signature: i=1; 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Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - update for new fields - bool asserts --- hw/timer/arm_mptimer.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cdfca3000b..b48536f6a3 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -41,9 +41,10 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ -static inline int get_current_cpu(ARMMPTimerState *s) +static inline int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs) { - int cpu_id = current_cpu ? current_cpu->cpu_index : 0; + int cpu_id = attrs.cpu_index; + g_assert(attrs.requester_is_cpu); if (cpu_id >= s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", @@ -178,25 +179,27 @@ static void timerblock_write(void *opaque, hwaddr addr, /* Wrapper functions to implement the "read timer/watchdog for * the current CPU" memory regions. */ -static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, - unsigned size) +static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); - return timerblock_read(&s->timerblock[id], addr, size); + int id = get_current_cpu(s, attrs); + *data = timerblock_read(&s->timerblock[id], addr, size); + return MEMTX_OK; } -static void arm_thistimer_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); + int id = get_current_cpu(s, attrs); timerblock_write(&s->timerblock[id], addr, value, size); + return MEMTX_OK; } static const MemoryRegionOps arm_thistimer_ops = { - .read = arm_thistimer_read, - .write = arm_thistimer_write, + .read_with_attrs = arm_thistimer_read, + .write_with_attrs = arm_thistimer_write, .valid = { .min_access_size = 4, .max_access_size = 4, From patchwork Thu Sep 22 14:58:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 608217 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp399682pvb; Thu, 22 Sep 2022 08:17:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6r5r2Pmg/TESheFWlnILrAKJHYsRbKiKAaDAgoy315+MC0nllQnL6UW+qFeXoqaRv/BRa4 X-Received: by 2002:ac8:5a47:0:b0:35c:c82e:3c37 with SMTP id o7-20020ac85a47000000b0035cc82e3c37mr3278248qta.451.1663859824757; Thu, 22 Sep 2022 08:17:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663859824; cv=none; d=google.com; s=arc-20160816; b=hakYaL5Gx77cPSLM+VVOR1WjiBYLVIjtHYPE8tjIWOArW3aF4kFMWa3ODNwvj9YT8R nguWy+WuHjxIFTofUhtqvSWMsXBVR4RLGxpJrMMIMFqNeZLUGH3orzZwkJzREpqQlRhk JR2YxIEl1ARhRE99WhxvUDSzc6jrshcpWI4rixptU/q3e+r028JRQLdRwIvF1PQUBGN7 AI5B1ZCaLAIBnRgN3aQnpoJo+EI+i3AbP+3poCoOMGRzzLr2/DvsEWaqYROTmUQkpqyx 34AAAqnJpNFupa64SC8uxI8FuorSe+kTlKLCsSei9EmpPv0PMOITlwD/4IWWVzH/1m6X pjbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8sQLXny03pJvTAoQ1h1P+6dtK6yjUsxRfofzOnIWm9M=; b=MO3eMBZH4q8R82xPNsfdmFHBCdiIkMX7SXyLKS7vaXTKlcNnFslTj9nIFdBQQkHC4L pNiD0yaC1rVWbRoJC2SSKHZePHF1n9htWHCXH+3zaivHfVj6rFK9QrG+s3VsFfQy0lef u72vPWGbcX5MgpyAoL26yxt2uoGMxNdFi7WGligs1F8n+9aUmGoD/DwkpHBy6wphlRFe iZtVP+eQNdwYC9A5Io/y0e27Q9bZBJtXDeviVwGWv5QGQdjmHXNbHMWZkcRw4mFcKYJN Q3jex0Rp6Y+QPanCJ42PmO6tBN9WTcaF+aoOQ2GnljqyBhyVmks2khudBLZSmFo/8+Jg MG8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uau8ZezT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fixes: 544f4a2578 (tests/tcg: isolate from QEMU's config-host.mak) Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- configure | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configure b/configure index 0bbf9d28af..fce677bd4a 100755 --- a/configure +++ b/configure @@ -2481,6 +2481,8 @@ if test -n "$gdb_bin"; then gdb_version=$($gdb_bin --version | head -n 1) if version_ge ${gdb_version##* } 9.1; then echo "HAVE_GDB_BIN=$gdb_bin" >> $config_host_mak + else + gdb_bin="" fi fi @@ -2565,6 +2567,11 @@ echo "# Automatically generated by configure - do not modify" > $config_host_mak echo "SRC_PATH=$source_path" >> $config_host_mak echo "HOST_CC=$host_cc" >> $config_host_mak +# versioned checked in the main config_host.mak above +if test -n "$gdb_bin"; then + echo "HAVE_GDB_BIN=$gdb_bin" >> $config_host_mak +fi + tcg_tests_targets= for target in $target_list; do arch=${target%%-*} From patchwork Thu Sep 22 14:58:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 608220 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp437079pvb; Thu, 22 Sep 2022 09:20:49 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4jFXfXiofi94i06WZjL5y2JkfeFfus39/g7vkU1sqKBUhr7Kg+EeDqVmSIme39TVriUX0M X-Received: by 2002:a05:622a:246:b0:35c:f707:27bb with SMTP id c6-20020a05622a024600b0035cf70727bbmr3427517qtx.225.1663863648857; Thu, 22 Sep 2022 09:20:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663863648; cv=none; d=google.com; s=arc-20160816; b=si7Xyo04DHYlCazR3OHFwXedBsNzw5Wfk4Y2P1Zt5OH7Ao9aEu2LjVpAf5nxqnOku3 yYRs8oZ3tEvA6TJ8XqRcQ8g4kkyPyfh8f96hE+cGESmfIUfNa1k1Dehb2i+KdtGCR2Dv cggaa7KnBmPyZgaMSXBcBrKNtb24pnpUTSWv6gqy9f4yRNwTscB4ErPkwmlAn7qlx9qV m8Wp/ahgv8rOz3YR++jSnMHQy1ZWmCEVgDDZg3mbvfoRXXe7B7hAG5TEjPVHNiEE77Kk FNYh4QqIBCGnx8PYOKi5wlzv8yN6gMPfedAipXu54B5ifhO61MkUIvdsJv7VbOSbwI1R YvEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z9o2xyA00hgdatFEtcmjPjjMM0wNvRNVxGVmWKD34T8=; b=kNkbQ7/hatm5hebQ44Y8dwXEMOOgBbrKqMLHKGp+A6LoENqKS1cMDuQk8X6vGyU5pW 9R3tooSVLamQ5SfW/eH0SscNXxWJePUbC8SyxK3hqiKx6mbswnk2TQSZeRNFdzT24NfB 3L9fxkf7gS1xuGda033qTbOixkkrj82HMeyvO1Cx+FxC6q+2Fe1kcj1pwJV2KTc3lxXg jLXMhED05Kk+Qqoo9t2ZIdHW6JH3U4PDlELXG6a83l4W7ITnM15mucjlwPYghfrojIYa eTmHNkIyC9VOfW3VeQODh3BBweVHPBCCv3eIS06cdoFmKxHgmD8I8hgOOYChnuJty8nD d+FQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tYIpNMvE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Aside from the minor tweaks to meson and trace.h this is pure code motion. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- meson.build | 4 +++- gdbstub/trace.h | 1 + gdbstub.c => gdbstub/gdbstub.c | 2 +- MAINTAINERS | 2 +- gdbstub/meson.build | 1 + gdbstub/trace-events | 29 +++++++++++++++++++++++++++++ trace-events | 28 ---------------------------- 7 files changed, 36 insertions(+), 31 deletions(-) create mode 100644 gdbstub/trace.h rename gdbstub.c => gdbstub/gdbstub.c (99%) create mode 100644 gdbstub/meson.build create mode 100644 gdbstub/trace-events diff --git a/meson.build b/meson.build index 3885fc1076..2c9209c2b8 100644 --- a/meson.build +++ b/meson.build @@ -2914,6 +2914,7 @@ trace_events_subdirs = [ 'qom', 'monitor', 'util', + 'gdbstub', ] if have_linux_user trace_events_subdirs += [ 'linux-user' ] @@ -3037,6 +3038,7 @@ subdir('authz') subdir('crypto') subdir('ui') subdir('hw') +subdir('gdbstub') if enable_modules @@ -3114,7 +3116,7 @@ common_ss.add(files('cpus-common.c')) subdir('softmmu') common_ss.add(capstone) -specific_ss.add(files('cpu.c', 'disas.c', 'gdbstub.c'), capstone) +specific_ss.add(files('cpu.c', 'disas.c'), capstone) # Work around a gcc bug/misfeature wherein constant propagation looks # through an alias: diff --git a/gdbstub/trace.h b/gdbstub/trace.h new file mode 100644 index 0000000000..dee87b1238 --- /dev/null +++ b/gdbstub/trace.h @@ -0,0 +1 @@ +#include "trace/trace-gdbstub.h" diff --git a/gdbstub.c b/gdbstub/gdbstub.c similarity index 99% rename from gdbstub.c rename to gdbstub/gdbstub.c index cf869b10e3..7d8fe475b3 100644 --- a/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -29,7 +29,7 @@ #include "qemu/ctype.h" #include "qemu/cutils.h" #include "qemu/module.h" -#include "trace/trace-root.h" +#include "trace.h" #include "exec/gdbstub.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" diff --git a/MAINTAINERS b/MAINTAINERS index 738c4eb647..82575b2486 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2670,7 +2670,7 @@ GDB stub M: Alex Bennée R: Philippe Mathieu-Daudé S: Maintained -F: gdbstub* +F: gdbstub/* F: include/exec/gdbstub.h F: gdb-xml/ F: tests/tcg/multiarch/gdbstub/ diff --git a/gdbstub/meson.build b/gdbstub/meson.build new file mode 100644 index 0000000000..6d4ae2d03c --- /dev/null +++ b/gdbstub/meson.build @@ -0,0 +1 @@ +specific_ss.add(files('gdbstub.c')) diff --git a/gdbstub/trace-events b/gdbstub/trace-events new file mode 100644 index 0000000000..03f0c303bf --- /dev/null +++ b/gdbstub/trace-events @@ -0,0 +1,29 @@ +# See docs/devel/tracing.rst for syntax documentation. + +# gdbstub.c +gdbstub_op_start(const char *device) "Starting gdbstub using device %s" +gdbstub_op_exiting(uint8_t code) "notifying exit with code=0x%02x" +gdbstub_op_continue(void) "Continuing all CPUs" +gdbstub_op_continue_cpu(int cpu_index) "Continuing CPU %d" +gdbstub_op_stepping(int cpu_index) "Stepping CPU %d" +gdbstub_op_extra_info(const char *info) "Thread extra info: %s" +gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" +gdbstub_hit_internal_error(void) "RUN_STATE_INTERNAL_ERROR" +gdbstub_hit_break(void) "RUN_STATE_DEBUG" +gdbstub_hit_paused(void) "RUN_STATE_PAUSED" +gdbstub_hit_shutdown(void) "RUN_STATE_SHUTDOWN" +gdbstub_hit_io_error(void) "RUN_STATE_IO_ERROR" +gdbstub_hit_watchdog(void) "RUN_STATE_WATCHDOG" +gdbstub_hit_unknown(int state) "Unknown run state=0x%x" +gdbstub_io_reply(const char *message) "Sent: %s" +gdbstub_io_binaryreply(size_t ofs, const char *line) "0x%04zx: %s" +gdbstub_io_command(const char *command) "Received: %s" +gdbstub_io_got_ack(void) "Got ACK" +gdbstub_io_got_unexpected(uint8_t ch) "Got 0x%02x when expecting ACK/NACK" +gdbstub_err_got_nack(void) "Got NACK, retransmitting" +gdbstub_err_garbage(uint8_t ch) "received garbage between packets: 0x%02x" +gdbstub_err_overrun(void) "command buffer overrun, dropping command" +gdbstub_err_invalid_repeat(uint8_t ch) "got invalid RLE count: 0x%02x" +gdbstub_err_invalid_rle(void) "got invalid RLE sequence" +gdbstub_err_checksum_invalid(uint8_t ch) "got invalid command checksum digit: 0x%02x" +gdbstub_err_checksum_incorrect(uint8_t expected, uint8_t got) "got command packet with incorrect checksum, expected=0x%02x, received=0x%02x" diff --git a/trace-events b/trace-events index bc71006675..035f3d570d 100644 --- a/trace-events +++ b/trace-events @@ -46,34 +46,6 @@ ram_block_discard_range(const char *rbname, void *hva, size_t length, bool need_ memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size) "0x%" PRIx64 " ram_addr 0x%" PRIx64 " size %u" memory_notdirty_set_dirty(uint64_t vaddr) "0x%" PRIx64 -# gdbstub.c -gdbstub_op_start(const char *device) "Starting gdbstub using device %s" -gdbstub_op_exiting(uint8_t code) "notifying exit with code=0x%02x" -gdbstub_op_continue(void) "Continuing all CPUs" -gdbstub_op_continue_cpu(int cpu_index) "Continuing CPU %d" -gdbstub_op_stepping(int cpu_index) "Stepping CPU %d" -gdbstub_op_extra_info(const char *info) "Thread extra info: %s" -gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" -gdbstub_hit_internal_error(void) "RUN_STATE_INTERNAL_ERROR" -gdbstub_hit_break(void) "RUN_STATE_DEBUG" -gdbstub_hit_paused(void) "RUN_STATE_PAUSED" -gdbstub_hit_shutdown(void) "RUN_STATE_SHUTDOWN" -gdbstub_hit_io_error(void) "RUN_STATE_IO_ERROR" -gdbstub_hit_watchdog(void) "RUN_STATE_WATCHDOG" -gdbstub_hit_unknown(int state) "Unknown run state=0x%x" -gdbstub_io_reply(const char *message) "Sent: %s" -gdbstub_io_binaryreply(size_t ofs, const char *line) "0x%04zx: %s" -gdbstub_io_command(const char *command) "Received: %s" -gdbstub_io_got_ack(void) "Got ACK" -gdbstub_io_got_unexpected(uint8_t ch) "Got 0x%02x when expecting ACK/NACK" -gdbstub_err_got_nack(void) "Got NACK, retransmitting" -gdbstub_err_garbage(uint8_t ch) "received garbage between packets: 0x%02x" -gdbstub_err_overrun(void) "command buffer overrun, dropping command" -gdbstub_err_invalid_repeat(uint8_t ch) "got invalid RLE count: 0x%02x" -gdbstub_err_invalid_rle(void) "got invalid RLE sequence" -gdbstub_err_checksum_invalid(uint8_t ch) "got invalid command checksum digit: 0x%02x" -gdbstub_err_checksum_incorrect(uint8_t expected, uint8_t got) "got command packet with incorrect checksum, expected=0x%02x, received=0x%02x" - # job.c job_state_transition(void *job, int ret, const char *legal, const char *s0, const char *s1) "job %p (ret: %d) attempting %s transition (%s-->%s)" job_apply_verb(void *job, const char *state, const char *verb, const char *legal) "job %p in state %s; applying verb %s (%s)" From patchwork Thu Sep 22 14:58:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 608221 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp440260pvb; Thu, 22 Sep 2022 09:26:54 -0700 (PDT) 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[209.51.188.17]) by mx.google.com with ESMTPS id iw9-20020a0562140f2900b004ad0df810cesi3428276qvb.545.2022.09.22.09.26.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 22 Sep 2022 09:26:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIPAjkGf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obP2L-0005j5-D5 for patch@linaro.org; Thu, 22 Sep 2022 12:26:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obNf5-0001Qt-Hk for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:47 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:35716) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obNf3-0000wj-G9 for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:47 -0400 Received: by mail-wm1-x336.google.com with SMTP id r133-20020a1c448b000000b003b494ffc00bso1549776wma.0 for ; Thu, 22 Sep 2022 07:58:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=vf2JT23xeGsCRGs8MEIgnpxzuvmtp2MAFHcV2vIxUmo=; b=OIPAjkGfv+BSxLpUX5VVw4Yj1sQ6Ou+Dtm/aHfbQYheY8ASV/F3bu+dgCfR/PnPdmh QGX4g3yQ2uJa565xwksKo+fCuAY7qWPFW96lg7wqlYqcumd/kCw9qjJqzNKnQ/W+WhQQ v9iE6xMD7iGpLtFOD2BAgTJfpSSLY5Ifa0sE/5HjIODKVVUVIvObkcuLPXtIuFLLeYGA Cpw0lNPElHWK0zolMSIuNme8IvhenELF+/Ja+9ppvgYIR7qtIlwLW5GtTWX8Zajrnd4s LRESLX5cFeN1ynIQBIEam4HhK/PUdIz1stxFibJ+VCU/c9+OW/UAYmojxSI9RvVdH86G Qt+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=vf2JT23xeGsCRGs8MEIgnpxzuvmtp2MAFHcV2vIxUmo=; b=tluYMhQIOqoD9vosSy4l/O1vwlMpU7uAyOwVTi0OCBnmO/IodcY9wd95+erAutYb4H 8ZFqsOkFF3iNu8vYXt/BRcBad74Q5OCkp9UPwvSOzNiTlGLweVwkmnHQ8BKzwSHUAc0h dU2X8vqpNP50yWeTlG+Mw5FgkHbtfvOQlOzs4v87HlyqY3Rc6otARfKj8/mkcGoSdb3i clC+v1gV+kkVn33BRTgIK5qMHn8aCiqWXQN0PxrFj8WsuE/7fsyKhqLvMhlh+1VFsvGq jzevOpJhOR6J8mfakaqsM6dXBTMHxQ8Qslxp8fDy/IzMhjywAyixYxl5ig1UN4n6EkER S/nQ== X-Gm-Message-State: ACrzQf3ibYIrLNwxtiPcwyNoRvap6TzztpBaSJ6VFk22heF2aTXayqbn bznOa/q7i1M/63oSDum6cg+dxciMCXd6PA== X-Received: by 2002:a05:600c:898:b0:3b4:8110:7fab with SMTP id l24-20020a05600c089800b003b481107fabmr9388934wmp.19.1663858719786; Thu, 22 Sep 2022 07:58:39 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id bj4-20020a0560001e0400b0022a403954c3sm5604531wrb.42.2022.09.22.07.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 07:58:36 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1C3ED1FFBF; Thu, 22 Sep 2022 15:58:33 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v1 7/9] gdbstub: move sstep flags probing into AccelClass Date: Thu, 22 Sep 2022 15:58:30 +0100 Message-Id: <20220922145832.1934429-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922145832.1934429-1-alex.bennee@linaro.org> References: <20220922145832.1934429-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The support of single-stepping is very much dependent on support from the accelerator we are using. To avoid special casing in gdbstub move the probing out to an AccelClass function so future accelerators can put their code there. Signed-off-by: Alex Bennée Cc: Mads Ynddal Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qemu/accel.h | 12 ++++++++++++ include/sysemu/kvm.h | 8 -------- accel/accel-common.c | 10 ++++++++++ accel/kvm/kvm-all.c | 14 +++++++++++++- accel/tcg/tcg-all.c | 17 +++++++++++++++++ gdbstub/gdbstub.c | 22 ++++------------------ 6 files changed, 56 insertions(+), 27 deletions(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index be56da1b99..ce4747634a 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -43,6 +43,10 @@ typedef struct AccelClass { bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); #endif + + /* gdbstub related hooks */ + int (*gdbstub_supported_sstep_flags)(void); + bool *allowed; /* * Array of global properties that would be applied when specific @@ -92,4 +96,12 @@ void accel_cpu_instance_init(CPUState *cpu); */ bool accel_cpu_realizefn(CPUState *cpu, Error **errp); +/** + * accel_supported_gdbstub_sstep_flags: + * + * Returns the supported single step modes for the configured + * accelerator. + */ +int accel_supported_gdbstub_sstep_flags(void); + #endif /* QEMU_ACCEL_H */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index efd6dee818..a20ad51aad 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -47,7 +47,6 @@ extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; extern bool kvm_has_guest_debug; -extern int kvm_sstep_flags; #define kvm_enabled() (kvm_allowed) /** @@ -174,12 +173,6 @@ extern int kvm_sstep_flags; */ #define kvm_supports_guest_debug() (kvm_has_guest_debug) -/* - * kvm_supported_sstep_flags - * Returns: SSTEP_* flags that KVM supports for guest debug - */ -#define kvm_get_supported_sstep_flags() (kvm_sstep_flags) - #else #define kvm_enabled() (0) @@ -198,7 +191,6 @@ extern int kvm_sstep_flags; #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) #define kvm_supports_guest_debug() (false) -#define kvm_get_supported_sstep_flags() (0) #endif /* CONFIG_KVM_IS_POSSIBLE */ diff --git a/accel/accel-common.c b/accel/accel-common.c index 50035bda55..df72cc989a 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -129,6 +129,16 @@ bool accel_cpu_realizefn(CPUState *cpu, Error **errp) return true; } +int accel_supported_gdbstub_sstep_flags(void) +{ + AccelState *accel = current_accel(); + AccelClass *acc = ACCEL_GET_CLASS(accel); + if (acc->gdbstub_supported_sstep_flags) { + return acc->gdbstub_supported_sstep_flags(); + } + return 0; +} + static const TypeInfo accel_cpu_type = { .name = TYPE_ACCEL_CPU, .parent = TYPE_OBJECT, diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 5acab1767f..c55938453a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -175,7 +175,7 @@ bool kvm_direct_msi_allowed; bool kvm_ioeventfd_any_length_allowed; bool kvm_msi_use_devid; bool kvm_has_guest_debug; -int kvm_sstep_flags; +static int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size = ~0; @@ -3712,6 +3712,17 @@ static void kvm_accel_instance_init(Object *obj) s->kvm_dirty_ring_size = 0; } +/** + * kvm_gdbstub_sstep_flags(): + * + * Returns: SSTEP_* flags that KVM supports for guest debug. The + * support is probed during kvm_init() + */ +static int kvm_gdbstub_sstep_flags(void) +{ + return kvm_sstep_flags; +} + static void kvm_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); @@ -3719,6 +3730,7 @@ static void kvm_accel_class_init(ObjectClass *oc, void *data) ac->init_machine = kvm_init; ac->has_memory = kvm_accel_has_memory; ac->allowed = &kvm_allowed; + ac->gdbstub_supported_sstep_flags = kvm_gdbstub_sstep_flags; object_class_property_add(oc, "kernel-irqchip", "on|off|split", NULL, kvm_set_kernel_irqchip, diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 47952eecd7..30b503fb22 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "sysemu/tcg.h" +#include "sysemu/replay.h" #include "sysemu/cpu-timers.h" #include "tcg/tcg.h" #include "qapi/error.h" @@ -207,12 +208,28 @@ static void tcg_set_splitwx(Object *obj, bool value, Error **errp) s->splitwx_enabled = value; } +static int tcg_gdbstub_supported_sstep_flags(void) +{ + /* + * In replay mode all events will come from the log and can't be + * suppressed otherwise we would break determinism. However as those + * events are tied to the number of executed instructions we won't see + * them occurring every time we single step. + */ + if (replay_mode != REPLAY_MODE_NONE) { + return SSTEP_ENABLE; + } else { + return SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; + } +} + static void tcg_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); ac->name = "tcg"; ac->init_machine = tcg_init_machine; ac->allowed = &tcg_allowed; + ac->gdbstub_supported_sstep_flags = tcg_gdbstub_supported_sstep_flags; object_class_property_add_str(oc, "thread", tcg_get_thread, diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 7d8fe475b3..a0755e6505 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -383,27 +383,13 @@ static void init_gdbserver_state(void) gdbserver_state.last_packet = g_byte_array_sized_new(MAX_PACKET_LENGTH + 4); /* - * In replay mode all events will come from the log and can't be - * suppressed otherwise we would break determinism. However as those - * events are tied to the number of executed instructions we won't see - * them occurring every time we single step. - */ - if (replay_mode != REPLAY_MODE_NONE) { - gdbserver_state.supported_sstep_flags = SSTEP_ENABLE; - } else if (kvm_enabled()) { - gdbserver_state.supported_sstep_flags = kvm_get_supported_sstep_flags(); - } else { - gdbserver_state.supported_sstep_flags = - SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; - } - - /* - * By default use no IRQs and no timers while single stepping so as to - * make single stepping like an ICE HW step. + * What single-step modes are supported is accelerator dependent. + * By default try to use no IRQs and no timers while single + * stepping so as to make single stepping like a typical ICE HW step. */ + gdbserver_state.supported_sstep_flags = accel_supported_gdbstub_sstep_flags(); gdbserver_state.sstep_flags = SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; gdbserver_state.sstep_flags &= gdbserver_state.supported_sstep_flags; - } #ifndef CONFIG_USER_ONLY From patchwork Thu Sep 22 14:58:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 608222 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp442654pvb; Thu, 22 Sep 2022 09:31:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4y9lH9XvIBOGlu9WFbFqhojq6cqKxlB+ur1ndTbuhESbEFN5UrPZA9Lps2f7zY3VG5Tbtp X-Received: by 2002:ad4:5aaf:0:b0:4a8:a817:e00d with SMTP id u15-20020ad45aaf000000b004a8a817e00dmr3387017qvg.18.1663864290982; Thu, 22 Sep 2022 09:31:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663864290; cv=none; d=google.com; s=arc-20160816; b=KyVV4dtbYx+3BBI1ltnoi0ttmEybGd7McwAXnjkKzu74+n66XLNKQoVQI4k4uUP5eu WnkmdchQ0/8+E97cWX0QIdDvFwTJ/EQVT17cSj8Et3MF7eDjSUPXAKYqNPop5onK23C7 4OQjG84Iv8A1AHTcSO5PYlxujd+pxFQkoR0lZinjaPn06129tREGzG5LIIyunNUXVBcd GeyClZThZTSS2xgbC35DgLTWq5jqqww+GmflViobBYOPuW/N65Ni61ODUntfBhJiX/Ro qhd2Molfrp1IWRQ/5Fs/KABNKZ1eG4AjBDoVJu5TGDClfZP4Cx5D+I4TWlBxz0d5Lotn hSJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PUsqmIg3cIcSF+Cp7vaRpt/1dPSTTn7gEPcc2Xary6E=; b=nz94Hd5pJaVhWePIbYXytrhGbKAE/LwUmfw4/aYCr8gBela33M9+pHiP6q3d2RmSVB Q9dmp98KMQq0QwjzJ7NCVDezKu6GaCdoUC1qb/q/eJM0gyDoxA1b3+rMC/0QOGfUqOcc D43kOKDbmfp9Te/ZTh5JBE0vl6DrOY17qrWYPfaVi7wevEzyE7bcJ+Mbtym2+NEwmbN5 rajNJycTo5UeiI8KKw4jhOoptf5JhEp7iFqQmT9Bll3ZDZmTfbTBFvydxpiFN5qFGWMG dpcZRM+XE71r6Z3L5wRp7WbZlBDDQ+uwoLl6wjuCpRekJVae6+aXvZkCk3f+HP7ozyhO W1ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=padMy8k0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m13-20020ac866cd000000b00338f4b80e6asi3035585qtp.27.2022.09.22.09.31.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 22 Sep 2022 09:31:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=padMy8k0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obP6o-0004AS-FJ for patch@linaro.org; Thu, 22 Sep 2022 12:31:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45072) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obNf6-0001RY-20 for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:48 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:51931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obNf3-0000wX-6f for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:47 -0400 Received: by mail-wm1-x32b.google.com with SMTP id o5so6979058wms.1 for ; Thu, 22 Sep 2022 07:58:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PUsqmIg3cIcSF+Cp7vaRpt/1dPSTTn7gEPcc2Xary6E=; b=padMy8k014wFPOsIMOv0cR8v0FD3UGKFeHIMyYPKwa3Qo5SytvC9UgtnDQ9zSOMGnZ zzM5hOC1x4a21ARMH7LCQTIPgp8g4Q9qO8V9l1C2kk3oIHA4xzjDojJjJTwXiNM0c6oQ pSCoKp1RBm0A0iNh+bhgtFI7y8E/aWhYgNZ3R3Jb13G2WXj95bBqCU3yAs0h6Gy60WoZ +sKm6kOCoup3ACYWkD0xYhPxkCeYomS122uy6vxy3pDhnERneb3gkx5xHhQYzREx3SyY OAxaJ8MUUr5GmgtEt8WIADxtWBprziLsw0Dryips7RqL6od23BMrOQZi+6pdAPbeQqdW UM5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PUsqmIg3cIcSF+Cp7vaRpt/1dPSTTn7gEPcc2Xary6E=; b=4MyviEb4TMBEPWO1ww/YfTieUUrVMll2Ipl/VJ6SI6jSpH2bsf6PegHcq1PIhq4Hhv bAfGp/KNsafqirMuICDmu66aENZfztJ2gGH+zuWUGbCHxZURXka7JAzctiaC6kae7fIz i+6ENojdYgzRQKxUjV3RdYVCHgiNQjw/7faGRp1927/vni2X+ppiCr/xO2KLACWc35kR FVB22bU3DJvvVfkvrMCNqys0M/iYvA6IVVsEq1HHu6puYi9FrVLM7K38FYTeuTJ7HV5/ AXZaPwwbt1WNJYkthBoN7yTh6KOyZ8bowuHRvT/h0zz8Z/OH923RZF061Iara6jmV8Fr ojsw== X-Gm-Message-State: ACrzQf0cb5L0Q2/G2+YJ/Yc/hVwXbZ5CPq6bws3Y6FJoNM+QDwDFJhtJ +D9S2+6X13E5rii/7J/z6U2hGQ== X-Received: by 2002:a05:600c:1910:b0:3b4:bb80:c951 with SMTP id j16-20020a05600c191000b003b4bb80c951mr10039175wmq.81.1663858719300; Thu, 22 Sep 2022 07:58:39 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id u10-20020a05600c210a00b003b50428cf66sm1894688wml.33.2022.09.22.07.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 07:58:36 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 53D961FFC0; Thu, 22 Sep 2022 15:58:33 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, =?utf-8?q?Alex_Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v1 8/9] gdbstub: move breakpoint logic to accel ops Date: Thu, 22 Sep 2022 15:58:31 +0100 Message-Id: <20220922145832.1934429-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922145832.1934429-1-alex.bennee@linaro.org> References: <20220922145832.1934429-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As HW virtualization requires specific support to handle breakpoints lets push out special casing out of the core gdbstub code and into AccelOpsClass. This will make it easier to add other accelerator support and reduces some of the stub shenanigans. Signed-off-by: Alex Bennée Cc: Mads Ynddal Reviewed-by: Richard Henderson --- accel/kvm/kvm-cpus.h | 3 + gdbstub/internals.h | 16 +++++ include/sysemu/accel-ops.h | 6 ++ include/sysemu/cpus.h | 3 + include/sysemu/kvm.h | 5 -- accel/kvm/kvm-accel-ops.c | 8 +++ accel/kvm/kvm-all.c | 24 +------ accel/stubs/kvm-stub.c | 16 ----- accel/tcg/tcg-accel-ops.c | 92 +++++++++++++++++++++++++++ gdbstub/gdbstub.c | 127 +++---------------------------------- gdbstub/softmmu.c | 42 ++++++++++++ gdbstub/user.c | 62 ++++++++++++++++++ softmmu/cpus.c | 7 ++ gdbstub/meson.build | 8 +++ 14 files changed, 259 insertions(+), 160 deletions(-) create mode 100644 gdbstub/internals.h create mode 100644 gdbstub/softmmu.c create mode 100644 gdbstub/user.c diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index bf0bd1bee4..33e435d62b 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -18,5 +18,8 @@ void kvm_destroy_vcpu(CPUState *cpu); void kvm_cpu_synchronize_post_reset(CPUState *cpu); void kvm_cpu_synchronize_post_init(CPUState *cpu); void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu); +int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); +int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); +void kvm_remove_all_breakpoints(CPUState *cpu); #endif /* KVM_CPUS_H */ diff --git a/gdbstub/internals.h b/gdbstub/internals.h new file mode 100644 index 0000000000..41e2e72dbf --- /dev/null +++ b/gdbstub/internals.h @@ -0,0 +1,16 @@ +/* + * gdbstub internals + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _INTERNALS_H_ +#define _INTERNALS_H_ + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); +void gdb_breakpoint_remove_all(CPUState *cs); + +#endif /* _INTERNALS_H_ */ diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index a0572ea87a..86794ac273 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -10,6 +10,7 @@ #ifndef ACCEL_OPS_H #define ACCEL_OPS_H +#include "exec/hwaddr.h" #include "qom/object.h" #define ACCEL_OPS_SUFFIX "-ops" @@ -44,6 +45,11 @@ struct AccelOpsClass { int64_t (*get_virtual_clock)(void); int64_t (*get_elapsed_ticks)(void); + + /* gdbstub hooks */ + int (*insert_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); + int (*remove_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); + void (*remove_all_breakpoints)(CPUState *cpu); }; #endif /* ACCEL_OPS_H */ diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index b5c87d48b3..1bace3379b 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -7,6 +7,9 @@ /* register accel-specific operations */ void cpus_register_accel(const AccelOpsClass *i); +/* return registers ops */ +const AccelOpsClass *cpus_get_accel(void); + /* accel/dummy-cpus.c */ /* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index a20ad51aad..21d3f1d01e 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -254,11 +254,6 @@ int kvm_on_sigbus(int code, void *addr); void kvm_flush_coalesced_mmio_buffer(void); -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type); -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type); -void kvm_remove_all_breakpoints(CPUState *cpu); int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap); /* internal API */ diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index c4244a23c6..5c0e37514c 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -16,12 +16,14 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" #include "sysemu/cpus.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include #include "kvm-cpus.h" static void *kvm_vcpu_thread_fn(void *arg) @@ -95,6 +97,12 @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = kvm_cpu_synchronize_post_init; ops->synchronize_state = kvm_cpu_synchronize_state; ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; + +#ifdef KVM_CAP_SET_GUEST_DEBUG + ops->insert_breakpoint = kvm_insert_breakpoint; + ops->remove_breakpoint = kvm_remove_breakpoint; + ops->remove_all_breakpoints = kvm_remove_all_breakpoints; +#endif } static const TypeInfo kvm_accel_ops_type = { diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index c55938453a..b8c734fe3a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3287,8 +3287,7 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return data.err; } -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) +int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; int err; @@ -3326,8 +3325,7 @@ int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, return 0; } -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) +int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; int err; @@ -3393,26 +3391,10 @@ void kvm_remove_all_breakpoints(CPUState *cpu) #else /* !KVM_CAP_SET_GUEST_DEBUG */ -int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) +static int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) { return -EINVAL; } - -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -void kvm_remove_all_breakpoints(CPUState *cpu) -{ -} #endif /* !KVM_CAP_SET_GUEST_DEBUG */ static int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset) diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 2ac5f9c036..2d79333143 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -51,22 +51,6 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return -ENOSYS; } -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -void kvm_remove_all_breakpoints(CPUState *cpu) -{ -} - int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) { return 1; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 786d90c08f..965c2ad581 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -32,6 +32,8 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" +#include "exec/hwaddr.h" +#include "exec/gdbstub.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" @@ -91,6 +93,92 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) } } +/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ +static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) +{ + static const int xlat[] = { + [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, + [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, + [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, + }; + + CPUClass *cc = CPU_GET_CLASS(cpu); + int cputype = xlat[gdbtype]; + + if (cc->gdb_stop_before_watchpoint) { + cputype |= BP_STOP_BEFORE_ACCESS; + } + return cputype; +} + +static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { + break; + } + } + return err; + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_ACCESS: + CPU_FOREACH(cpu) { + err = cpu_watchpoint_insert(cpu, addr, len, + xlat_gdb_type(cpu, type), NULL); + if (err) { + break; + } + } + return err; + default: + return -ENOSYS; + } +} + +static int tcg_remove_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { + break; + } + } + return err; + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_ACCESS: + CPU_FOREACH(cpu) { + err = cpu_watchpoint_remove(cpu, addr, len, + xlat_gdb_type(cpu, type)); + if (err) { + break; + } + } + return err; + default: + return -ENOSYS; + } +} + +static inline void tcg_remove_all_breakpoints(CPUState *cpu) +{ + cpu_breakpoint_remove_all(cpu, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); +} + static void tcg_accel_ops_init(AccelOpsClass *ops) { if (qemu_tcg_mttcg_enabled()) { @@ -109,6 +197,10 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) ops->handle_interrupt = tcg_handle_interrupt; } } + + ops->insert_breakpoint = tcg_insert_breakpoint; + ops->remove_breakpoint = tcg_remove_breakpoint; + ops->remove_all_breakpoints = tcg_remove_all_breakpoints; } static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index a0755e6505..ff9f3f9586 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -49,8 +49,11 @@ #include "sysemu/runstate.h" #include "semihosting/semihost.h" #include "exec/exec-all.h" +#include "exec/hwaddr.h" #include "sysemu/replay.h" +#include "internals.h" + #ifdef CONFIG_USER_ONLY #define GDB_ATTACHED "0" #else @@ -1012,130 +1015,16 @@ void gdb_register_coprocessor(CPUState *cpu, } } -#ifndef CONFIG_USER_ONLY -/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ -static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) -{ - static const int xlat[] = { - [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, - [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, - [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, - }; - - CPUClass *cc = CPU_GET_CLASS(cpu); - int cputype = xlat[gdbtype]; - - if (cc->gdb_stop_before_watchpoint) { - cputype |= BP_STOP_BEFORE_ACCESS; - } - return cputype; -} -#endif - -static int gdb_breakpoint_insert(int type, target_ulong addr, target_ulong len) -{ - CPUState *cpu; - int err = 0; - - if (kvm_enabled()) { - return kvm_insert_breakpoint(gdbserver_state.c_cpu, addr, len, type); - } - - switch (type) { - case GDB_BREAKPOINT_SW: - case GDB_BREAKPOINT_HW: - CPU_FOREACH(cpu) { - err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); - if (err) { - break; - } - } - return err; -#ifndef CONFIG_USER_ONLY - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_ACCESS: - CPU_FOREACH(cpu) { - err = cpu_watchpoint_insert(cpu, addr, len, - xlat_gdb_type(cpu, type), NULL); - if (err) { - break; - } - } - return err; -#endif - default: - return -ENOSYS; - } -} - -static int gdb_breakpoint_remove(int type, target_ulong addr, target_ulong len) -{ - CPUState *cpu; - int err = 0; - - if (kvm_enabled()) { - return kvm_remove_breakpoint(gdbserver_state.c_cpu, addr, len, type); - } - - switch (type) { - case GDB_BREAKPOINT_SW: - case GDB_BREAKPOINT_HW: - CPU_FOREACH(cpu) { - err = cpu_breakpoint_remove(cpu, addr, BP_GDB); - if (err) { - break; - } - } - return err; -#ifndef CONFIG_USER_ONLY - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_ACCESS: - CPU_FOREACH(cpu) { - err = cpu_watchpoint_remove(cpu, addr, len, - xlat_gdb_type(cpu, type)); - if (err) - break; - } - return err; -#endif - default: - return -ENOSYS; - } -} - -static inline void gdb_cpu_breakpoint_remove_all(CPUState *cpu) -{ - cpu_breakpoint_remove_all(cpu, BP_GDB); -#ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(cpu, BP_GDB); -#endif -} - static void gdb_process_breakpoint_remove_all(GDBProcess *p) { CPUState *cpu = get_first_cpu_in_process(p); while (cpu) { - gdb_cpu_breakpoint_remove_all(cpu); + gdb_breakpoint_remove_all(cpu); cpu = gdb_next_cpu_in_process(cpu); } } -static void gdb_breakpoint_remove_all(void) -{ - CPUState *cpu; - - if (kvm_enabled()) { - kvm_remove_all_breakpoints(gdbserver_state.c_cpu); - return; - } - - CPU_FOREACH(cpu) { - gdb_cpu_breakpoint_remove_all(cpu); - } -} static void gdb_set_cpu_pc(target_ulong pc) { @@ -1667,7 +1556,8 @@ static void handle_insert_bp(GArray *params, void *user_ctx) return; } - res = gdb_breakpoint_insert(get_param(params, 0)->val_ul, + res = gdb_breakpoint_insert(gdbserver_state.c_cpu, + get_param(params, 0)->val_ul, get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { @@ -1690,7 +1580,8 @@ static void handle_remove_bp(GArray *params, void *user_ctx) return; } - res = gdb_breakpoint_remove(get_param(params, 0)->val_ul, + res = gdb_breakpoint_remove(gdbserver_state.c_cpu, + get_param(params, 0)->val_ul, get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { @@ -2541,7 +2432,7 @@ static void handle_target_halt(GArray *params, void *user_ctx) * because gdb is doing an initial connect and the state * should be cleaned up. */ - gdb_breakpoint_remove_all(); + gdb_breakpoint_remove_all(gdbserver_state.c_cpu); } static int gdb_handle_packet(const char *line_buf) diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c new file mode 100644 index 0000000000..4e73890379 --- /dev/null +++ b/gdbstub/softmmu.c @@ -0,0 +1,42 @@ +/* + * gdb server stub - softmmu specific bits + * + * Debug integration depends on support from the individual + * accelerators so most of this involves calling the ops helpers. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/gdbstub.h" +#include "exec/hwaddr.h" +#include "sysemu/cpus.h" +#include "internals.h" + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->insert_breakpoint) { + return ops->insert_breakpoint(cs, type, addr, len); + } + return -ENOSYS; +} + +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->remove_breakpoint) { + return ops->remove_breakpoint(cs, type, addr, len); + } + return -ENOSYS; +} + +void gdb_breakpoint_remove_all(CPUState *cs) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->remove_all_breakpoints) { + ops->remove_all_breakpoints(cs); + } +} diff --git a/gdbstub/user.c b/gdbstub/user.c new file mode 100644 index 0000000000..42652b28a7 --- /dev/null +++ b/gdbstub/user.c @@ -0,0 +1,62 @@ +/* + * gdbstub user-mode helper routines. + * + * We know for user-mode we are using TCG so we can call stuff directly. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "exec/gdbstub.h" +#include "hw/core/cpu.h" +#include "internals.h" + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { + break; + } + } + return err; + default: + /* user-mode doesn't support watchpoints */ + return -ENOSYS; + } +} + +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { + break; + } + } + return err; + default: + /* user-mode doesn't support watchpoints */ + return -ENOSYS; + } +} + +void gdb_breakpoint_remove_all(CPUState *cs) +{ + cpu_breakpoint_remove_all(cs, BP_GDB); +} diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 23b30484b2..61b27ff59d 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -617,6 +617,13 @@ void cpus_register_accel(const AccelOpsClass *ops) cpus_accel = ops; } +const AccelOpsClass *cpus_get_accel(void) +{ + /* broken if we call this early */ + assert(cpus_accel); + return cpus_accel; +} + void qemu_init_vcpu(CPUState *cpu) { MachineState *ms = MACHINE(qdev_get_machine()); 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[209.51.188.17]) by mx.google.com with ESMTPS id kk19-20020a056214509300b0049bf8e12e5bsi3229157qvb.315.2022.09.22.09.38.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 22 Sep 2022 09:38:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tb25KTfM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1obPDt-0001Nm-FK for patch@linaro.org; Thu, 22 Sep 2022 12:38:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1obNf7-0001Su-7R for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:50 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:44596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1obNf3-0000ww-Hy for qemu-devel@nongnu.org; Thu, 22 Sep 2022 10:58:48 -0400 Received: by mail-wr1-x435.google.com with SMTP id c11so15940608wrp.11 for ; Thu, 22 Sep 2022 07:58:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=navtm+gH6yNeb7knk5E3m8UXvhR7UYY2qxKvdX6qN2Q=; b=Tb25KTfMeh3bfFfHp3LUZUNMKprBS5sCZIyYoGnd8YAikMNf4imAlWxzVNRNuk/dq1 1mZrHpZkYPqsiaYWLtbSsIfnxJsTIj2W9g6Q1U58Ku5v9J+zSWBXcpt82qYHHEmpi4Vy ttyGNzzZh0KaKv26BME5b36VJRqK6kflEHtDzbaRcvJz7B/qRjZN3YRH8weL3yOx7lRm rb4d+CYSEsREdU0f+Y4GTUBURQ3fpJcnEdAlg2muLMuXoK55CV61l+LdIZyMiAJ1c03G 6DgZIwGpIub3mJN6INs9aNaXNkqMr7b4ICA4eLLm2GayemgF3ChCjf/1/ovdM0JD1aTx o4IQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=navtm+gH6yNeb7knk5E3m8UXvhR7UYY2qxKvdX6qN2Q=; b=FCyh8+VewMYoxHeY85a6Lkqoz62+dh7t/0KRS3C0UQHg0H+Ud48ibdwMqT2D7iG7zv wIcEYqjz9xyYoZL6rT7vcBfZSL52N7rU9wX1YlHicaTp7BVBIXh+ZC2hlrscDJ2Ub0Dn /tTQFFkgfcqQqjyi/MPFhasMxQMdz7usQuBn9gk31OrOOGHJ6mGHohPZJb5Cz4F6H4Lg tNPIAFjwQwtouHhsF8GHJTp4pF9cHRJKUj1zaZFHBYaRPwt/Xjgpt2StmITywHUq1HwO MsI8z4o3wTs6LptmOdnb2N2U1iLu5tu9NuLc+Hndx27xZOeySIBQ+JCEzQKflSJccPmP o6jQ== X-Gm-Message-State: ACrzQf357r5R5DbUqSBnDurcEIcVqEurZ+4eAgIA8bKqkb9C1g0Lso7r /JKIencFBMNwgGDSTzP+Dj6BYw== X-Received: by 2002:adf:f18d:0:b0:228:9f0a:f291 with SMTP id h13-20020adff18d000000b002289f0af291mr2482447wro.252.1663858720770; Thu, 22 Sep 2022 07:58:40 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id r7-20020a5d52c7000000b0022acb7195aesm5424565wrv.33.2022.09.22.07.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 07:58:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 838C41FFB7; Thu, 22 Sep 2022 15:58:33 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, =?utf-8?q?Alex_Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v1 9/9] gdbstub: move guest debug support check to ops Date: Thu, 22 Sep 2022 15:58:32 +0100 Message-Id: <20220922145832.1934429-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922145832.1934429-1-alex.bennee@linaro.org> References: <20220922145832.1934429-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes the final hard coding of kvm_enabled() in gdbstub and moves the check to an AccelOps. Signed-off-by: Alex Bennée Cc: Mads Ynddal Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/kvm/kvm-cpus.h | 1 + gdbstub/internals.h | 1 + include/sysemu/accel-ops.h | 1 + include/sysemu/kvm.h | 7 ------- accel/kvm/kvm-accel-ops.c | 1 + accel/kvm/kvm-all.c | 6 ++++++ accel/tcg/tcg-accel-ops.c | 6 ++++++ gdbstub/gdbstub.c | 5 ++--- gdbstub/softmmu.c | 9 +++++++++ gdbstub/user.c | 6 ++++++ 10 files changed, 33 insertions(+), 10 deletions(-) diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index 33e435d62b..fd63fe6a59 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -18,6 +18,7 @@ void kvm_destroy_vcpu(CPUState *cpu); void kvm_cpu_synchronize_post_reset(CPUState *cpu); void kvm_cpu_synchronize_post_init(CPUState *cpu); void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu); +bool kvm_supports_guest_debug(void); int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); void kvm_remove_all_breakpoints(CPUState *cpu); diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 41e2e72dbf..eabb0341d1 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -9,6 +9,7 @@ #ifndef _INTERNALS_H_ #define _INTERNALS_H_ +bool gdb_supports_guest_debug(void); int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); void gdb_breakpoint_remove_all(CPUState *cs); diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 86794ac273..8cc7996def 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -47,6 +47,7 @@ struct AccelOpsClass { int64_t (*get_elapsed_ticks)(void); /* gdbstub hooks */ + bool (*supports_guest_debug)(void); int (*insert_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); int (*remove_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); void (*remove_all_breakpoints)(CPUState *cpu); diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 21d3f1d01e..6e1bd01725 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -46,7 +46,6 @@ extern bool kvm_readonly_mem_allowed; extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; -extern bool kvm_has_guest_debug; #define kvm_enabled() (kvm_allowed) /** @@ -168,11 +167,6 @@ extern bool kvm_has_guest_debug; */ #define kvm_msi_devid_required() (kvm_msi_use_devid) -/* - * Does KVM support guest debugging - */ -#define kvm_supports_guest_debug() (kvm_has_guest_debug) - #else #define kvm_enabled() (0) @@ -190,7 +184,6 @@ extern bool kvm_has_guest_debug; #define kvm_direct_msi_enabled() (false) #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) -#define kvm_supports_guest_debug() (false) #endif /* CONFIG_KVM_IS_POSSIBLE */ diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 5c0e37514c..fbf4fe3497 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -99,6 +99,7 @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; #ifdef KVM_CAP_SET_GUEST_DEBUG + ops->supports_guest_debug = kvm_supports_guest_debug; ops->insert_breakpoint = kvm_insert_breakpoint; ops->remove_breakpoint = kvm_remove_breakpoint; ops->remove_all_breakpoints = kvm_remove_all_breakpoints; diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index b8c734fe3a..6ebff6e5a6 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3287,6 +3287,12 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return data.err; } +bool kvm_supports_guest_debug(void) +{ + /* probed during kvm_init() */ + return kvm_has_guest_debug; +} + int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 965c2ad581..19cbf1db3a 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -93,6 +93,11 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) } } +static bool tcg_supports_guest_debug(void) +{ + return true; +} + /* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) { @@ -198,6 +203,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) } } + ops->supports_guest_debug = tcg_supports_guest_debug; ops->insert_breakpoint = tcg_insert_breakpoint; ops->remove_breakpoint = tcg_remove_breakpoint; ops->remove_all_breakpoints = tcg_remove_all_breakpoints; diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index ff9f3f9586..be88ca0d71 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -45,7 +45,6 @@ #include "qemu/sockets.h" #include "sysemu/hw_accel.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "semihosting/semihost.h" #include "exec/exec-all.h" @@ -3447,8 +3446,8 @@ int gdbserver_start(const char *device) return -1; } - if (kvm_enabled() && !kvm_supports_guest_debug()) { - error_report("gdbstub: KVM doesn't support guest debugging"); + if (!gdb_supports_guest_debug()) { + error_report("gdbstub: current accelerator doesn't support guest debugging"); return -1; } diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 4e73890379..f208c6cf15 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -15,6 +15,15 @@ #include "sysemu/cpus.h" #include "internals.h" +bool gdb_supports_guest_debug(void) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->supports_guest_debug) { + return ops->supports_guest_debug(); + } + return false; +} + int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) { const AccelOpsClass *ops = cpus_get_accel(); diff --git a/gdbstub/user.c b/gdbstub/user.c index 42652b28a7..033e5fdd71 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -14,6 +14,12 @@ #include "hw/core/cpu.h" #include "internals.h" +bool gdb_supports_guest_debug(void) +{ + /* user-mode == TCG == supported */ + return true; +} + int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) { CPUState *cpu;