From patchwork Thu Sep 22 22:20:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 608294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DB7FC6FA8B for ; Thu, 22 Sep 2022 22:21:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229833AbiIVWVK (ORCPT ); Thu, 22 Sep 2022 18:21:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229512AbiIVWVJ (ORCPT ); Thu, 22 Sep 2022 18:21:09 -0400 Received: from mail-io1-xd34.google.com (mail-io1-xd34.google.com [IPv6:2607:f8b0:4864:20::d34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9673510D0F0 for ; Thu, 22 Sep 2022 15:21:05 -0700 (PDT) Received: by mail-io1-xd34.google.com with SMTP id e205so8983447iof.1 for ; Thu, 22 Sep 2022 15:21:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=lSdeMmKOatLt1HIEIx6J8l8o81Ep3DSqpQTV4HSGmjQ=; b=BLrB/OURumYJfvjcJAgrrvjpSokfJ/yHuaEheiKd201cRLgLBU2mKAmzUVxzCkuHXS U66diQmI5s64GPFTfjtx30gWBdboZzOkHsyPB/l5jJlJ5WNI1+CuUVZVnJeiO+qpMBwD 1GgbSkLM5Ft6jXzYf1GpK43+7UoX/PkiuRJJ8KISJDq643R26c1TeYxi39YLfVXzptCH 4gNHWI2M9x+3spV3K3i/WnWKtgzSij7A9YUg2QFoei2nuFp9ZuzS+B35VjGT3F8pijwF WLatGGtE/dO5dpY1uOdQqE/1CrurIdCxgCtdj2YYWr+7z+F1Efao4dqHTbTEy2ulsMOs 098Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=lSdeMmKOatLt1HIEIx6J8l8o81Ep3DSqpQTV4HSGmjQ=; b=zYyWrF3d2WqQwtwYxJmWdWnGVvMzDngYL69ZPBVhHrje3HDmFNTONln/JnbcxFAegJ L8GslM0crKCQ0kdD0jb9vADDRTblJXeD3uCyr2OJsW4QhTlWXyKVlY+GiuxDH55frRHx AE5Ou8484yxUlKhNV1OsflSJQg8WRIHdKpIa2Co6tsLK/9Om9tb3cHaPXoO8j8z2kMlz 6XUPlDC6TFLY7JWTwTLzWB0B/VWJQ7zJ1YqcCFcwfOG7lOqJZLdJcWMB0BB4ryRI4+x6 F49QxN+vGFoPGMQUFc/tnHcV93HeAa0TW9fDQGIViWpMdQbIthKYUzKh5oddReGA6C2m x/dg== X-Gm-Message-State: ACrzQf1ohSSq7t9e/3yyDuJ0NyUFeAlRsEzP00ST4Tw1lpo+bxI0G9Y1 FupCSPR9A417+3E0mXXMGJimhA== X-Google-Smtp-Source: AMsMyM49ojpZ4NtZ85F+TDgqbi78KCnusmOwNYbyav9onsrplQqsvWMs9fDUxMB0WWpzSU7jT/Hz2A== X-Received: by 2002:a05:6638:3286:b0:349:fd14:7af6 with SMTP id f6-20020a056638328600b00349fd147af6mr3165876jav.48.1663885265001; Thu, 22 Sep 2022 15:21:05 -0700 (PDT) Received: from localhost.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id g12-20020a92d7cc000000b002f592936fbfsm2483332ilq.41.2022.09.22.15.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 15:21:04 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/8] net: ipa: don't use u32p_replace_bits() Date: Thu, 22 Sep 2022 17:20:53 -0500 Message-Id: <20220922222100.2543621-2-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922222100.2543621-1-elder@linaro.org> References: <20220922222100.2543621-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In two spots we use u32_replace_bits() to replace a set of bits in a register while preserving the rest. Both of those cases just zero the bits being replaced, and this can be done more simply without using that function. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_table.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ipa/ipa_table.c b/drivers/net/ipa/ipa_table.c index 69efe672ca528..037cec2fd5942 100644 --- a/drivers/net/ipa/ipa_table.c +++ b/drivers/net/ipa/ipa_table.c @@ -524,7 +524,7 @@ static void ipa_filter_tuple_zero(struct ipa_endpoint *endpoint) val = ioread32(endpoint->ipa->reg_virt + offset); /* Zero all filter-related fields, preserving the rest */ - u32p_replace_bits(&val, 0, IPA_REG_ENDP_FILTER_HASH_MSK_ALL); + val &= ~IPA_REG_ENDP_FILTER_HASH_MSK_ALL; iowrite32(val, endpoint->ipa->reg_virt + offset); } @@ -571,7 +571,7 @@ static void ipa_route_tuple_zero(struct ipa *ipa, u32 route_id) val = ioread32(ipa->reg_virt + offset); /* Zero all route-related fields, preserving the rest */ - u32p_replace_bits(&val, 0, IPA_REG_ENDP_ROUTER_HASH_MSK_ALL); + val &= ~IPA_REG_ENDP_ROUTER_HASH_MSK_ALL; iowrite32(val, ipa->reg_virt + offset); } From patchwork Thu Sep 22 22:20:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 608293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CC13C6FA91 for ; Thu, 22 Sep 2022 22:21:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229913AbiIVWVN (ORCPT ); Thu, 22 Sep 2022 18:21:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231220AbiIVWVJ (ORCPT ); Thu, 22 Sep 2022 18:21:09 -0400 Received: from mail-io1-xd29.google.com (mail-io1-xd29.google.com [IPv6:2607:f8b0:4864:20::d29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A45110D67E for ; Thu, 22 Sep 2022 15:21:08 -0700 (PDT) Received: by mail-io1-xd29.google.com with SMTP id c4so8977666iof.3 for ; Thu, 22 Sep 2022 15:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=xmsMzMwZV5ZOovBFH/X4I+q5eM58vu3t0RCGdrrJ4lo=; b=lwk5GNqrV4OxPP8qp73gshHXz55xffiQpviZS/ZOTCHHSNl65LvN3ggIYjmO5dCpLr Fs1n4D/MTlA9unQWakS2OsQZLJmgrDzJlQuYZwJ1a0+EFAVmYQ7HYjS6FbCFrUArfl8X CMqugiEzrmfX607XfSUB+NyuToRFg6KRA9OZ/ccE6GfqynlnZVkyhZA8Q0dsmDRaZ5kf m6GsxFiPKivasjIfTp65t4GxlIIZFMawNtLhYaV53HxpcCIBdCrSuVKmkeyedfxLqJ8j rl1kTPr6Ju25tooQeuv9p+vESpBHaWcPAsbikY3DWOzNUVMV7IiKd/wShKcDGbI5pKro psuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=xmsMzMwZV5ZOovBFH/X4I+q5eM58vu3t0RCGdrrJ4lo=; b=cmG/YoPuDXdVwNt9fI6rW6s5I4IBQ+OYzSnxiPavjzLZDtgRpxP13ZOAS3lBwrYdCu MWnJXz2JXCUS2SPmIrl53QKaG9bf7ecB+AkuekWQW9k+S8Kes8sowhrFAWqP6Fh/m4t9 SA7/TV0TzTXWiRgip7i1/jRBcAJrCBYh1u2SSaZXPLgjKd+nNmJgev+o54E9TZkrzcN9 OcyMRSXqIaL497pf3acuHQIV8HxRiz0dxy3RvOucCr2f5R6335K5AWZlgdo1G2d+xE1D p5BXAvvdrq0zG4iKm/6Upiah9G9R6EvWSqF1RIlEo1oZ3ilJZFUu1zw3ji8mDt77rEwG 8mRg== X-Gm-Message-State: ACrzQf1o4VJnFvsjVtkT8WWS3348EMvezrY6lYxmOtwRg+NsIEuFassv Q9TSNWQRgMU64RNz5HZf6+AyqQ== X-Google-Smtp-Source: AMsMyM7C9xX0hkqYnTdMkfO0HNRWwamhjwDGRl38P9k/ct9i5H95W9s0SYARVEP+o9wrJgr8JAKAuA== X-Received: by 2002:a6b:b28b:0:b0:6a1:eb9e:bf62 with SMTP id b133-20020a6bb28b000000b006a1eb9ebf62mr2577093iof.87.1663885267395; Thu, 22 Sep 2022 15:21:07 -0700 (PDT) Received: from localhost.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id g12-20020a92d7cc000000b002f592936fbfsm2483332ilq.41.2022.09.22.15.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 15:21:06 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/8] net: ipa: rearrange functions for similarity Date: Thu, 22 Sep 2022 17:20:55 -0500 Message-Id: <20220922222100.2543621-4-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922222100.2543621-1-elder@linaro.org> References: <20220922222100.2543621-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Both aggr_time_limit_encode() and hol_block_timer_encode() figure out how to encode a millisecond time value so it can be programmed into a register. Rearranging them a bit can make their similarity more obvious, with both taking essentially the same form. To do this: - Return 0 immediately in aggr_time_limit_encode() if the microseconds value supplied is zero. - Reverse the test at top of aggr_time_limit_encode(), so we compute and return the Qtime value in the "true" block, and compute the result the old way otherwise. - Open-code (and eliminate) hol_block_timer_qtime_encode() at the top of hol_block_timer_encode() in the case we use Qtimer. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 86 ++++++++++++++++------------------ 1 file changed, 41 insertions(+), 45 deletions(-) diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 7d91b423a1be7..6db62b6fb6632 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -752,34 +752,38 @@ static int ipa_qtime_val(u32 microseconds, u32 max) /* Encode the aggregation timer limit (microseconds) based on IPA version */ static u32 aggr_time_limit_encode(enum ipa_version version, u32 microseconds) { - u32 gran_sel; u32 fmask; u32 val; - int ret; - if (version < IPA_VERSION_4_5) { - /* We set aggregation granularity in ipa_hardware_config() */ - fmask = aggr_time_limit_fmask(true); - val = DIV_ROUND_CLOSEST(microseconds, IPA_AGGR_GRANULARITY); - WARN(val > field_max(fmask), - "aggr_time_limit too large (%u > %u usec)\n", - val, field_max(fmask) * IPA_AGGR_GRANULARITY); + if (!microseconds) + return 0; /* Nothing to compute if time limit is 0 */ - return u32_encode_bits(val, fmask); - } + if (version >= IPA_VERSION_4_5) { + u32 gran_sel; + int ret; + + /* Compute the Qtime limit value to use */ + fmask = aggr_time_limit_fmask(false); + ret = ipa_qtime_val(microseconds, field_max(fmask)); + if (ret < 0) { + val = -ret; + gran_sel = AGGR_GRAN_SEL_FMASK; + } else { + val = ret; + gran_sel = 0; + } - /* Compute the Qtime limit value to use */ - fmask = aggr_time_limit_fmask(false); - ret = ipa_qtime_val(microseconds, field_max(fmask)); - if (ret < 0) { - val = -ret; - gran_sel = AGGR_GRAN_SEL_FMASK; - } else { - val = ret; - gran_sel = 0; + return gran_sel | u32_encode_bits(val, fmask); } - return gran_sel | u32_encode_bits(val, fmask); + /* We set aggregation granularity in ipa_hardware_config() */ + fmask = aggr_time_limit_fmask(true); + val = DIV_ROUND_CLOSEST(microseconds, IPA_AGGR_GRANULARITY); + WARN(val > field_max(fmask), + "aggr_time_limit too large (%u > %u usec)\n", + val, field_max(fmask) * IPA_AGGR_GRANULARITY); + + return u32_encode_bits(val, fmask); } static u32 aggr_sw_eof_active_encoded(enum ipa_version version, bool enabled) @@ -837,28 +841,6 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) iowrite32(val, endpoint->ipa->reg_virt + offset); } -/* Return the Qtime-based head-of-line blocking timer value that - * represents the given number of microseconds. The result - * includes both the timer value and the selected timer granularity. - */ -static u32 hol_block_timer_qtime_encode(struct ipa *ipa, u32 microseconds) -{ - u32 gran_sel; - u32 val; - int ret; - - ret = ipa_qtime_val(microseconds, field_max(TIME_LIMIT_FMASK)); - if (ret < 0) { - val = -ret; - gran_sel = GRAN_SEL_FMASK; - } else { - val = ret; - gran_sel = 0; - } - - return gran_sel | u32_encode_bits(val, TIME_LIMIT_FMASK); -} - /* The head-of-line blocking timer is defined as a tick count. For * IPA version 4.5 the tick count is based on the Qtimer, which is * derived from the 19.2 MHz SoC XO clock. For older IPA versions @@ -879,8 +861,22 @@ static u32 hol_block_timer_encode(struct ipa *ipa, u32 microseconds) if (!microseconds) return 0; /* Nothing to compute if timer period is 0 */ - if (ipa->version >= IPA_VERSION_4_5) - return hol_block_timer_qtime_encode(ipa, microseconds); + if (ipa->version >= IPA_VERSION_4_5) { + u32 gran_sel; + int ret; + + /* Compute the Qtime limit value to use */ + ret = ipa_qtime_val(microseconds, field_max(TIME_LIMIT_FMASK)); + if (ret < 0) { + val = -ret; + gran_sel = GRAN_SEL_FMASK; + } else { + val = ret; + gran_sel = 0; + } + + return gran_sel | u32_encode_bits(val, TIME_LIMIT_FMASK); + } /* Use 64 bit arithmetic to avoid overflow... */ rate = ipa_core_clock_rate(ipa); From patchwork Thu Sep 22 22:20:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 608292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BA2FECAAD8 for ; Thu, 22 Sep 2022 22:21:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231419AbiIVWVP (ORCPT ); Thu, 22 Sep 2022 18:21:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231387AbiIVWVK (ORCPT ); Thu, 22 Sep 2022 18:21:10 -0400 Received: from mail-il1-x132.google.com (mail-il1-x132.google.com [IPv6:2607:f8b0:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35CE110CA42 for ; Thu, 22 Sep 2022 15:21:08 -0700 (PDT) Received: by mail-il1-x132.google.com with SMTP id a4so3420931ilj.8 for ; Thu, 22 Sep 2022 15:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=DxN4skl57Ip6n+jQkYaK3Z/OC9a58fagmXeHv9SstKE=; b=f0OWnnq6haiADOzRDBqpglUAw/QpO4xOSvS3uO0z1+eiKD+5DAD3rZnm/JJk59CXRm X6xN/ft/h8HudpguVdNk2QVteTUI6i8v8JMR+QtxwczYFdjLtq5gZhsDmPrTa9G765/t Ml7/fJl1fRpeJX5ZLKbtnVuUrNlhy6VZTn4t1yyc0MwK6CEGy44OmNCazBi3amkgrvBt FKstrxkA9mPmpUmc2k++YqQXqcbaY7G6QbalvnPQAWG3/aME/dKu20T+rnSUtHGL3K5I WLH3k6YKaayPZbhryrz7ZFuUrcQcuR+kgo/oDe3aQt1mlUS2QjX7vTHICmpmOIgtIcF/ 7Q9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=DxN4skl57Ip6n+jQkYaK3Z/OC9a58fagmXeHv9SstKE=; b=PZ4l8BsHVcOTPFXJA164OpfvZJBCoAir5ycDvklEiqhNPy1E6PBJjSDyurwyrVI+Tp frjH55WCUW2/0gQCMfCJyJcxzKFoY0VYO98WKefRm1gnm539tKZaI2/Hub9m0m9O2fMB YDhwrlXZi0HXXwWfLwciQduFoy4Ct4a2gXLqM78kNEM90yqgC3USJ/ftqcBqmg8ZlV9S fYdHBjN9Eov7rykXOHhZgq1PqH9mvjFuvYwbjr0qs86rCg8wY/LHjyv/1h/aMTr+72kv L5Sn2cbwuH4XWy7L3gaJYgBw2Ovyd5pIIasnVdThwS9KuABfG6Q1j8yqr8RCfEGSZQSC z7Mw== X-Gm-Message-State: ACrzQf0vdaAyG51QJ7VGHJYGgQDCxu6pIwhPtagADMInznWypYeDOPAT zDDGqjtTV+lZd7GjAPQglB01vKyOKOMvivC0 X-Google-Smtp-Source: AMsMyM55tKcBQjxn0AOH07fVF51W4vb3otwirDCFcdPawDCpeJ6Vc4rJGLjSXT1CSbwHYRmVRlqQrw== X-Received: by 2002:a05:6e02:1c24:b0:2f6:2fae:a4b with SMTP id m4-20020a056e021c2400b002f62fae0a4bmr2929727ilh.131.1663885268500; Thu, 22 Sep 2022 15:21:08 -0700 (PDT) Received: from localhost.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id g12-20020a92d7cc000000b002f592936fbfsm2483332ilq.41.2022.09.22.15.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Sep 2022 15:21:08 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/8] net: ipa: define BCR values using an enum Date: Thu, 22 Sep 2022 17:20:56 -0500 Message-Id: <20220922222100.2543621-5-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922222100.2543621-1-elder@linaro.org> References: <20220922222100.2543621-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The backward compatibility register (BCR) has a set of bit flags that indicate ways in which the IPA hardware should operate in a backward compatible way. The register is not supported starting with IPA v4.5, and where it is supported, defined bits all have the same numeric value. Redefine these flags using an enumerated type, with each member's value representing the bit position that encodes it in the BCR. This replaces all of the single-bit field masks previously defined. Signed-off-by: Alex Elder --- drivers/net/ipa/data/ipa_data-v3.1.c | 2 +- drivers/net/ipa/data/ipa_data-v3.5.1.c | 10 +++++----- drivers/net/ipa/ipa_reg.h | 26 ++++++++++++-------------- 3 files changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/net/ipa/data/ipa_data-v3.1.c b/drivers/net/ipa/data/ipa_data-v3.1.c index 1c1895aea8118..e0d71f6092729 100644 --- a/drivers/net/ipa/data/ipa_data-v3.1.c +++ b/drivers/net/ipa/data/ipa_data-v3.1.c @@ -526,7 +526,7 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v3.1 */ const struct ipa_data ipa_data_v3_1 = { .version = IPA_VERSION_3_1, - .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK, + .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY), .qsb_count = ARRAY_SIZE(ipa_qsb_data), .qsb_data = ipa_qsb_data, .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), diff --git a/drivers/net/ipa/data/ipa_data-v3.5.1.c b/drivers/net/ipa/data/ipa_data-v3.5.1.c index 58b708d2fc75d..383ef18900654 100644 --- a/drivers/net/ipa/data/ipa_data-v3.5.1.c +++ b/drivers/net/ipa/data/ipa_data-v3.5.1.c @@ -407,11 +407,11 @@ static const struct ipa_power_data ipa_power_data = { /* Configuration data for an SoC having IPA v3.5.1 */ const struct ipa_data ipa_data_v3_5_1 = { .version = IPA_VERSION_3_5_1, - .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | - BCR_TX_NOT_USING_BRESP_FMASK | - BCR_SUSPEND_L2_IRQ_FMASK | - BCR_HOLB_DROP_L2_IRQ_FMASK | - BCR_DUAL_TX_FMASK, + .backward_compat = BIT(BCR_CMDQ_L_LACK_ONE_ENTRY) | + BIT(BCR_TX_NOT_USING_BRESP) | + BIT(BCR_SUSPEND_L2_IRQ) | + BIT(BCR_HOLB_DROP_L2_IRQ) | + BIT(BCR_DUAL_TX), .qsb_count = ARRAY_SIZE(ipa_qsb_data), .qsb_data = ipa_qsb_data, .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 3e24bddc682ef..2aa1d1dd0adf5 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -220,20 +220,18 @@ static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) /* The next register is not present for IPA v4.5+ */ #define IPA_REG_BCR_OFFSET 0x000001d0 -/* The next two fields are not present for IPA v4.2+ */ -#define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) -#define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) -/* The next field is invalid for IPA v4.0+ */ -#define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) -/* The next two fields are not present for IPA v4.2+ */ -#define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) -#define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) -/* The next five fields are present for IPA v3.5+ */ -#define BCR_DUAL_TX_FMASK GENMASK(5, 5) -#define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) -#define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) -#define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) -#define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) +enum ipa_bcr_compat { + BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ + BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ + BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ + BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ + BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ + BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ + BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ + BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ + BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ + BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ +}; /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 From patchwork Thu Sep 22 22:20:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 608291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0D1FC54EE9 for ; Thu, 22 Sep 2022 22:21:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229813AbiIVWVc (ORCPT ); Thu, 22 Sep 2022 18:21:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbiIVWVW (ORCPT ); Thu, 22 Sep 2022 18:21:22 -0400 Received: from mail-il1-x133.google.com (mail-il1-x133.google.com [IPv6:2607:f8b0:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD7FE10F718 for ; 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Create another small function to represent configuring hardware timing regardless of version. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_main.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index cca270d2d9a68..8bb4b036df2b4 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -306,6 +306,27 @@ static void ipa_qtime_config(struct ipa *ipa) iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); } +/* Before IPA v4.5 timing is controlled by a counter register */ +static void ipa_hardware_config_counter(struct ipa *ipa) +{ + u32 granularity; + u32 val; + + granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); + + val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK); + + iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET); +} + +static void ipa_hardware_config_timing(struct ipa *ipa) +{ + if (ipa->version < IPA_VERSION_4_5) + ipa_hardware_config_counter(ipa); + else + ipa_qtime_config(ipa); +} + static void ipa_hardware_config_hashing(struct ipa *ipa) { u32 offset; @@ -362,7 +383,6 @@ static void ipa_hardware_dcd_deconfig(struct ipa *ipa) static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) { enum ipa_version version = ipa->version; - u32 granularity; u32 val; /* IPA v4.5+ has no backward compatibility register */ @@ -389,19 +409,8 @@ static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); ipa_hardware_config_comp(ipa); - - /* Configure system bus limits */ ipa_hardware_config_qsb(ipa, data); - - if (version < IPA_VERSION_4_5) { - /* Configure aggregation timer granularity */ - granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); - val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK); - iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET); - } else { - ipa_qtime_config(ipa); - } - + ipa_hardware_config_timing(ipa); ipa_hardware_config_hashing(ipa); ipa_hardware_dcd_config(ipa); }