From patchwork Thu Sep 22 22:03:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 609011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22466ECAAD8 for ; Thu, 22 Sep 2022 22:03:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229772AbiIVWDT (ORCPT ); Thu, 22 Sep 2022 18:03:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229519AbiIVWDS (ORCPT ); Thu, 22 Sep 2022 18:03:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67163F1624; Thu, 22 Sep 2022 15:03:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 046B362373; Thu, 22 Sep 2022 22:03:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88875C433D7; Thu, 22 Sep 2022 22:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663884196; bh=y+77KBXZol4WBiZ164SK0oly/RSyy8n+02CZZWHAZXY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bDc+79A02Ji2hLuNgXu4bjqixhtEOIRNk2WBjICG+v3bPDMTHYBUegz4jBl9NluV+ 750UjKD787VVGPN0SpdrN6SYgQYrpxqfdUdYkqrSCU1NwCZWmsKlpA3NAn87EpuxDX LPj9CewSqk2gHUNKm3xzmTPR1n+YtBwv5Og5ASIyzAP0gIqMZOvAOK37n99zqz/FCb qk6CyDnyOJl/SNeFAYgdtbq7V5xZ72FudPh6naRDSoFZYa2qAlnWSwc40LnODKFHBf +isAhO/IpKoOprjnoo54oGM7NJtzmL+3v19gZZ39RmEyBN+Ioqj3YZNmmGWK7l7QXh AnP42YNomu34w== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCHv2 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Date: Thu, 22 Sep 2022 17:03:06 -0500 Message-Id: <20220922220308.609422-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922220308.609422-1-dinguyen@kernel.org> References: <20220922220308.609422-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen --- v2: added --- .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..aece6a337262 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -38,6 +38,18 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + description: + Contains the phandle to System Manager block that contains + the SDMMC clock-phase control register. The first value is the pointer + to the sysmgr and the 2nd value is the register offset for the SDMMC + clock phase register. + required: - compatible - reg From patchwork Thu Sep 22 22:03:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 609010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14A4FC54EE9 for ; Thu, 22 Sep 2022 22:03:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230164AbiIVWDX (ORCPT ); Thu, 22 Sep 2022 18:03:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229725AbiIVWDW (ORCPT ); Thu, 22 Sep 2022 18:03:22 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C69DD109741; Thu, 22 Sep 2022 15:03:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0BD43B836A8; Thu, 22 Sep 2022 22:03:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B7C79C4347C; Thu, 22 Sep 2022 22:03:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663884197; bh=fYm6Cvv+PSjM2Gv/1imDNQrnZqXuBwzd5QvBMYqyNgY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hF28X7ZwzuSWNycdWLamPNPZI6RPFW7hNfcUffJ3/vAgMeB5Io/crrH/Ky6osBCpm xoSshc//XadLgdDkJSFp6NT+tMXPcao1DmFJG/FUr3bDPw4TuG1QccPE8YuYBjjpGN dyYAM/Ue+hjpWmY/Uf+5HWH4N7Wjk2k881jggeWq/j4y1jUUmCc8McnlGc934Sef7L HtzuO5YsBn8kBMP/I4TsCSj32/fiWqdfPVjseb9hlWSua+g3CPYgmQ2ZBVYF5WwwYD 4jDJgUQQFx6CbXYOlN+gUNB2fzsj6f2+7MWDVxNVC7AUVkKUzuWRNSEGyNqyjweb3Q 5sGHpxHguVnCw== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCHv2 2/3] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Thu, 22 Sep 2022 17:03:07 -0500 Message-Id: <20220922220308.609422-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922220308.609422-1-dinguyen@kernel.org> References: <20220922220308.609422-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v2: no changes --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 14c220d87807..a5d08920ac81 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -309,6 +309,7 @@ mmc: mmc@ff808000 { <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 48424e459f12..19e7284b4cd5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -105,6 +105,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..6353f6a361f4 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -313,6 +313,7 @@ mmc: mmc@ff808000 { <&clkmgr AGILEX_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 26cd3c121757..07c3f8876613 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -83,6 +83,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { From patchwork Thu Sep 22 22:03:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 608328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB7E8C6FA86 for ; Thu, 22 Sep 2022 22:03:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230131AbiIVWDZ (ORCPT ); Thu, 22 Sep 2022 18:03:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230196AbiIVWDY (ORCPT ); Thu, 22 Sep 2022 18:03:24 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 275DC10AB03; Thu, 22 Sep 2022 15:03:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 3EF45B837FA; Thu, 22 Sep 2022 22:03:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 186CCC433B5; Thu, 22 Sep 2022 22:03:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663884198; bh=U7AngiUw9pi/okWYNcJU5584IsfUO2S3/dFVGK48Q4w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e2iHofqL+W7ktB6MheLW/p3dPrdZRVb8UkiARt0rIvt4u2fJevcl1NaiW3sJNrz8+ BzKh6L/5QishNoYOfxY+2uYysB3NyViz/b16ClGLH0dcVK0FL1O92IqpDesgS1VIWU jbBj3Vj/Myq/+RNwvs3AFCIIo73v9ItXLafUA1lmEfkNuZ1vIjsJVnXEX9GhATTacr j2UgKyEJN5hi1UTvBkI41PIG9Aiy0IJu7/pqjlgeXVe6EZIjZZ1LW9wmEOy/bmu3+4 q23J1yqY4yZ+TT/vsJC5C1siYAM/DucDQtDNgL9HKXKqipGzcrPBvCgsfzOjknQVnS 0RhBbif3DPlkA== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCHv2 3/3] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Date: Thu, 22 Sep 2022 17:03:08 -0500 Message-Id: <20220922220308.609422-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922220308.609422-1-dinguyen@kernel.org> References: <20220922220308.609422-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock-phase settings for the SDMMC controller in the SoCFPGA Strarix10/Agilex/N5X platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen --- v2: simplify clk-phase calculations --- drivers/mmc/host/dw_mmc-pltfm.c | 41 ++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 9901208be797..5d64984d382f 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -17,10 +17,16 @@ #include #include #include +#include +#include #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0)) + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -62,9 +68,42 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { }; EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct device_node *np = host->dev->of_node; + struct regmap *sys_mgr_base_addr; + u32 clk_phase[2] = {0}, reg_offset; + int i, rc, hs_timing; + + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); + if (rc) { + sys_mgr_base_addr = + altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); + if (IS_ERR(sys_mgr_base_addr)) { + pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); + return 1; + } + } else + return 1; + + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); + + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); + + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, +}; + static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "altr,socfpga-dw-mshc", .data =&socfpga_drv_data, }, { .compatible = "img,pistachio-dw-mshc", }, {}, };