From patchwork Mon Sep 26 13:38:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609324 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1884193pvb; Mon, 26 Sep 2022 07:14:57 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Cttzyvc4MHoi/mleYCM29uviRH2OFtjG2Txenb15m9r/En312HNlgJPvbgUdYWeYYn6Vm X-Received: by 2002:a05:622a:34d:b0:35d:4338:463e with SMTP id r13-20020a05622a034d00b0035d4338463emr2667612qtw.559.1664201697611; Mon, 26 Sep 2022 07:14:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664201697; cv=none; d=google.com; s=arc-20160816; b=WU7khX6HRPB0/pw+gs8fzxwHknP8YZ0aM1YWUw18K12mak4lF4lcgWlva8Ud9djSbN FFfA5jvqG7ffRtYyRljkVZhJZ69wu7nhntC7SUj0gN0+tfjvuIAjdxpcU9REw3vtVoAY BCEbdP3JtSCKvbH//8W+5W1tyxKRrChmVQXMWBSjs9Si11Shq4XhKj2YTc6yvV3BrDQw rfR9YwYAS3v8s6rYCeJ3SXOWGLdgRp7nRZ8m9HNey7ST/8+9SCP/ublXl2y60aXo8eEk 2tzg3luDS/pk1eNwevXA+0eaBWJpGGM/BXvnCE/zxenQ/pWso42NjKZWXkjQwVVz+bd9 qanA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OSHuYNoeAhBgevG45a7IfEUr6E+OClE/MaFvqiZpjFY=; b=Buf5fLH4dyqOtUHgicHoQEID5+/bibuT/y7noXnrZwcNZEwMAhFKcwMEqe8lB2s/j6 YddPBWUu9LvVXBCkriqxdoXH90eEZJX/0C8EU3DQUBISiEouf7NzU9X2QESgddXXJMu7 mjKnWeNGDILiKsZsyxbzHO5TAo44eYGo0elwI3ROGOo5fp5WSUviKlr0uPSCxY9NRydM laTD7svAe7332UOH7OJHFod2YJv5yalaaprGzVUtZBwRxkxjPVhJCAmXhE/95ZBQXkqF N07hS26/jgzmlgtatD8GSfb5j8W+WKN3JNTpaVEHtDd1Y3YZFwAnL9B5rYFD3kzjrrqB jVeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hB8QKccF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c19-20020ac81e93000000b0035cceb34440si8075230qtm.491.2022.09.26.07.14.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 07:14:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hB8QKccF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocosr-0007iH-4o for patch@linaro.org; Mon, 26 Sep 2022 10:14:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKH-00021R-Fr for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:14 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36526) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKD-0005e4-3Y for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:12 -0400 Received: by mail-wr1-x436.google.com with SMTP id y5so10293546wrh.3 for ; Mon, 26 Sep 2022 06:39:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=OSHuYNoeAhBgevG45a7IfEUr6E+OClE/MaFvqiZpjFY=; b=hB8QKccFUs+W/rKK6Q9jpjwcCxw+IyK3ZF+NUg9Rf6v8tdHgjuKJ35F0ehmBOdb3bx 0It0KSv1mP4RgvXQ6ueAEyeVnJVP1Ck9E8dDvikFJiiILAuWvkCEBSjFVLFIhU59AtMf yQ/FBwFSK6a0bxLsuagHLQx0unb9mtj6ghoctxw4uAAQp1cU1tvIWRu7esZ6/SFeQP4V 9jqLmnU/N/bSzOrOQQI3qb48hT/Xs/EZzYCO9nAFQIsnX9k9SUi1Gn8yvnRH2Z65Q2uc hN9pcQrGlGJJXonqfyMy7RTdpmoRV4aMsYyRCQauSBerXEIw9/5r8urU1eM8jOrTi0lg Wnig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=OSHuYNoeAhBgevG45a7IfEUr6E+OClE/MaFvqiZpjFY=; b=EM/xWKVFkM2lZyWVS988akIEZcYvS383KjemlB/Zfg9s9EhnnrfEFqV8Y8NtDZ8oq8 5y77l9u2IIKr2TXM9JXvqhPrZY0oPT5ebCx+ViHTAquZUQEF0pIMrg2DUQ/X5cCXsY/4 5EX0XroLBgzQZchoigKD+U3UxkdKd3TX+I8qmMFtkTATTs3zA2mX78AAYRzTHNN5c63G ji2jbD7DVTqzb3sAOkcSiKc2GHtgnHdvqYwFb2AMXhQBjTkpFCZLTwqWfTGZDEV5Bj+3 xvb3FXB4svUJU7z2cIb0hBiz+NvBZWLwl+oXLWyaH/u2OfKVLwH673hXOGhSO21c/Y14 Nh8Q== X-Gm-Message-State: ACrzQf23RKYuehM6BN0DaCgL38XolOc2gt2IkE1rTCnAyTSWiPJeYd28 lzamGV34ziVg2UMvhbiCmjbEFg== X-Received: by 2002:a05:6000:124f:b0:228:8713:ced9 with SMTP id j15-20020a056000124f00b002288713ced9mr13755413wrx.198.1664199546384; Mon, 26 Sep 2022 06:39:06 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id z10-20020adfec8a000000b0022afe4fb459sm14283990wrn.51.2022.09.26.06.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:05 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C3A0A1FFB8; Mon, 26 Sep 2022 14:39:04 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= Subject: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs Date: Mon, 26 Sep 2022 14:38:54 +0100 Message-Id: <20220926133904.3297263-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We currently have hacks across the hw/ to reference current_cpu to work out what the current accessing CPU is. This breaks in some cases including using gdbstub to access HW state. As we have MemTxAttrs to describe details about the access lets extend it to mention if this is a CPU access and which one it is. There are a number of places we need to fix up including: CPU helpers directly calling address_space_*() fns models in hw/ fishing the data out of current_cpu hypervisors offloading device emulation to QEMU I'll start addressing some of these in following patches. Signed-off-by: Alex Bennée --- v2 - use separate field cpu_index - bool for requester_is_cpu v3 - switch to enum MemTxRequesterType - move helper #define to patch - revert to overloading requester_id - mention hypervisors in commit message - drop cputlb tweaks, they will move to target specific code --- include/exec/memattrs.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..0fb5f29d25 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -14,6 +14,15 @@ #ifndef MEMATTRS_H #define MEMATTRS_H +/* + * Where the memory transaction comes from + */ +typedef enum MemTxRequesterType { + MEMTXATTRS_CPU, + MEMTXATTRS_MSI, +} MemTxRequesterType; + + /* Every memory transaction has associated with it a set of * attributes. Some of these are generic (such as the ID of * the bus master); some are specific to a particular kind of @@ -43,7 +52,9 @@ typedef struct MemTxAttrs { * (see MEMTX_ACCESS_ERROR). */ unsigned int memory:1; - /* Requester ID (for MSI for example) */ + /* Requester type (e.g. CPU or PCI MSI) */ + MemTxRequesterType requester_type:2; + /* Requester ID */ unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; @@ -66,6 +77,10 @@ typedef struct MemTxAttrs { */ #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) +/* Helper for setting a basic CPU sourced transaction */ +#define MEMTXATTRS_CPU(id) ((MemTxAttrs) \ + {.requester_type = MEMTXATTRS_CPU, .requester_id = id}) + /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure * of some kind. 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[209.51.188.17]) by mx.google.com with ESMTPS id iw9-20020a0562140f2900b004acb01cd58fsi7127013qvb.486.2022.09.26.07.24.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 07:24:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=plSly8c5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocp2G-00020G-Uo for patch@linaro.org; Mon, 26 Sep 2022 10:24:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKH-00021K-FE for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:14 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:44882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKD-0005eM-3b for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:12 -0400 Received: by mail-wr1-x430.google.com with SMTP id c11so10239473wrp.11 for ; Mon, 26 Sep 2022 06:39:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=V4i8lyUq3ft9QoTbl1zxUdvI+GWdEaQO+D0hzFqAlY0=; b=plSly8c5E/WG+nx6kAibnGo8ff7ST9cz2GuSc/wrfacIvaN2g1OKDcYHRZZB5OFtd2 FX6jLnBJ9hlRzvWbXwJn9Db6En14ei6b+NRTIBDzX4wtMn0XXhG0fZaWLBVbn3aV9K3O kJGo0lmwdU6ytTglIaxczE0TofqpfGIFflgaDgckjGnuqgmb54GonbEhnSDMcKbKG702 46H4Hs/HejcWCUy9bq82fA4JTBBe3rDV31GD/Usah70j8UHewBtVN08im1mhT50oS+LX ZkoOz8qjqNthFYmylQJlKI4KfJ/cs/yH6QDSggSOBa1ADM/HesTtfiwBR3eTkmrDCUBi 1ieg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=V4i8lyUq3ft9QoTbl1zxUdvI+GWdEaQO+D0hzFqAlY0=; b=bfe6u8ejnEr1Oub6zSxSpuSODHc35B6xGJoNqDqVMgLS95YBzzHxOvQCLfQt7Y9PxR 5ykbfRy9/e7ACARNYe44KlQa+pAQ/mjN7f0LtC8vSExjOc7d1iSNF6RM35kD94fdkTVX EPqMAQE4vvuGcRznSdahKl3lqzvYvcbplOalNb60No5N5QhDMDwvlidy1Q/+V+D5Ro0K voExa5jY5rlkHCwEkRicgIGT1D7jb+fkfLho9uNRas/rprHIqIwnuigKvTd3Axsj370J HWkuSTsiE1El6WEhyk6W2JWA2gzCvw0cFobvC7q4liOqrahgpiJyy4v3eKdU6RQukBLC yKKg== X-Gm-Message-State: ACrzQf3bEEKmQ/VQh3rC2wN+VxKJpruHcx5Wne7nZOSqCvtz/dx5fFrs 7Y5YDawO2CIziWtR/RsTOaLbcA== X-Received: by 2002:a5d:6808:0:b0:22a:c437:5b36 with SMTP id w8-20020a5d6808000000b0022ac4375b36mr13550393wru.459.1664199547707; Mon, 26 Sep 2022 06:39:07 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id t12-20020a5d534c000000b0022c906ffedasm6660951wrv.70.2022.09.26.06.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:05 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DA00B1FFBA; Mon, 26 Sep 2022 14:39:04 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Peter Maydell Subject: [PATCH v2 02/11] target/arm: enable tracking of CPU index in MemTxAttrs Date: Mon, 26 Sep 2022 14:38:55 +0100 Message-Id: <20220926133904.3297263-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both arm_cpu_tlb_fill (for normal IO) and arm_cpu_get_phys_page_attrs_debug (for debug access) come through get_phys_addr which is setting the other memory attributes for the transaction. As these are all by definition CPU accesses we can also set the requested_type/index as appropriate. Signed-off-by: Alex Bennée --- target/arm/ptw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3261039d93..644d450662 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2315,6 +2315,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, { ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); + attrs->requester_type = MEMTXATTRS_CPU; + attrs->requester_id = env_cpu(env)->cpu_index; + if (mmu_idx != s1_mmu_idx) { /* * Call ourselves recursively to do the stage 1 and then stage 2 From patchwork Mon Sep 26 13:38:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609325 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1887497pvb; Mon, 26 Sep 2022 07:20:40 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6zLPomcYVG/BLaDoodzOJL+L5m/G5txxSro2LzofLYv9pqaUuIn9kbxJ2msLrHeJ1MRH3H X-Received: by 2002:a05:620a:4c:b0:6ce:b5f:1320 with SMTP id t12-20020a05620a004c00b006ce0b5f1320mr14507040qkt.569.1664202040093; Mon, 26 Sep 2022 07:20:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664202040; cv=none; d=google.com; s=arc-20160816; b=J3D01uDkTKzBV9OtVZSCF/aeND03XOwER2JDiqkX/NNalCsW7oLTDo0LJJPqWUeH0z O5mro5FRkgVlKAQ6ZwFTHQAsaLVtPeF7/sghJCtlwfpWyMNOUcjQ5kvly8eN7LRpPgkd O/x4T+A3GLNrPXrAwoBGRDPG8Nm1HZPOsaPvcgJHb8H8wvrNB1pbmLJIL3QymCzELaPv dh9IQEO9lapHPn521+nv9Le0pJzQRgt+PgeF0pVMkMWb4GEIMFCMkXt4fZ9OACvriZAf JEW+hH7PMQVPD/ux6B58ttsOGYQGwONV400P/+p7CcqX1U9yr7Zrog7fTH7w/l8PwYlm M8Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8kZr1rxByNkxMPVyKr7Y5lFL0hfWuti5PLDqMUepXx8=; b=KHqINXky0ZxOl1YgoomozNkeXLqzXZX9rOX1E/9TPBRKL2g4gzNE64sa2YNHJy2tmV VQadIQxQ9xi6VYFvKhnIWpQCmb6LBeCAPy1RgJMoUkxCgxkecuHcLzZiBMVes+vv34PE GjQoreSfoBsm6PAm7+MBQBAE3GyyIMMYbLUT5bN9GsRrixI0citGnsUDBOKOGxW26pOQ z3977eQe/iQb3BHlnC7+tuwLyt5Ac4vv+m4BZRViHZD/Zu5UwcdXH+XxLMg0on4gwchw gybMXiXKjFacmQcKX9eURrT8vzqLRbMPAmR4ftgUK5eUl2dWHLtF4Md+Cfr0TVmfVqQK yogw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ndwy5+eZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gw10-20020a0562140f0a00b004ad6fe3b784si9176749qvb.69.2022.09.26.07.20.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 07:20:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ndwy5+eZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocoyN-00057h-3T for patch@linaro.org; Mon, 26 Sep 2022 10:20:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48182) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKH-00021V-Ht for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:14 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:50833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKD-0005eR-Kx for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:13 -0400 Received: by mail-wm1-x32f.google.com with SMTP id ay36so4546363wmb.0 for ; Mon, 26 Sep 2022 06:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=8kZr1rxByNkxMPVyKr7Y5lFL0hfWuti5PLDqMUepXx8=; b=ndwy5+eZkVYESsES7LBxBD3/B8G371rAOcNuqnAtAQ9nxRsUWFxCrTizlD0qkJKV3Q a51WtnaAehNkkWxwddzKW06t24i0AFDJSspiXJn3Y9pH1KB/OtLzdntSC+QKPeccGRAo vKpuh5zotD58D2Qr0t0AS1Nh5iXGql8mBF2/7ZjPZf2+7z/i4f/WcmXlqVkoQFqkZt9j AprIBjCtmAc/LxlXFD4tX58lYFU7zZxzKgFpNWdL6ehav4fcfCzgYCF8KdIOPeKO4K1q HFZvtTb0i7+tEkLianYZuy8x0+x9A/FMAdZ/Vi9eqLti5aToR6huOu0shV0jXGm787TH PCXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=8kZr1rxByNkxMPVyKr7Y5lFL0hfWuti5PLDqMUepXx8=; b=vajlz7lOWUyDiEtOJ+a4y9YG//Hx+njwJa2fc3/29VJ7o3tW9XqGpXgkp3AR123G5R obA/+eyj71YY69dtvdfUGMthcab8bHyucsqwB/KGOvSAxn8K7ouPKsbLwfQypEgJTDnz yiMQRHC3azYgsagiD8Yz4XgsMsfPicJF/8v9PGdcNibuE50pNubgv/0xVNmP4PzedtzZ pLkyn56d2WvuqIgUuoFmHXZnHgvshhkrUBNiWLoDi5esevwG2YBA7OfFqTyytkNw7HYx aEVh98udeZcn3mmOZm9YhDf/SCtq6GehhYrIYXGZpRfDQPSZ8k5GkzIma4eqezf7VLct oSMA== X-Gm-Message-State: ACrzQf00E/QQFVkDC5pBLO09gPezNKjbaRrE40WYQb/tr0H7HnljxpY8 yX3KpIKd6HBiGtdpvVsI7N0egA== X-Received: by 2002:a05:600c:a07:b0:3ab:945:77c4 with SMTP id z7-20020a05600c0a0700b003ab094577c4mr22167987wmp.97.1664199548086; Mon, 26 Sep 2022 06:39:08 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id i6-20020a05600c354600b003b47b80cec3sm11918658wmq.42.2022.09.26.06.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:05 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id F34651FFBB; Mon, 26 Sep 2022 14:39:04 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Alexander Graf , Peter Maydell Subject: [PATCH v2 03/11] target/arm: ensure HVF traps set appropriate MemTxAttrs Date: Mon, 26 Sep 2022 14:38:56 +0100 Message-Id: <20220926133904.3297263-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As most HVF devices are done purely in software we need to make sure we properly encode the source CPU in MemTxAttrs. This will allow the device emulations to use those attributes rather than relying on current_cpu (although current_cpu will still be correct in this case). Signed-off-by: Alex Bennée Cc: Mads Ynddal Cc: Alexander Graf Acked-by: Alexander Graf --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 060aa0ccf4..13b7971560 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1233,11 +1233,11 @@ int hvf_vcpu_exec(CPUState *cpu) val = hvf_get_reg(cpu, srt); address_space_write(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu->cpu_index), &val, len); } else { address_space_read(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu->cpu_index), &val, len); hvf_set_reg(cpu, srt, val); } From patchwork Mon Sep 26 13:38:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609327 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1891997pvb; Mon, 26 Sep 2022 07:28:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4hCNKoCyXboIII03rwjpa0M1fi5OchMW7tbI05UTCgLkFbdv0odxngXBXE4l94UXXGMvuN X-Received: by 2002:a0c:d987:0:b0:4a5:192c:faff with SMTP id y7-20020a0cd987000000b004a5192cfaffmr17606271qvj.106.1664202528419; Mon, 26 Sep 2022 07:28:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664202528; cv=none; d=google.com; s=arc-20160816; b=Qx2SAx9oZ5S9l6+Ky/e3IWX5IwAG+l5aek1bpRgZG9UwjqhypItXnRn6d0ycptOTFM nTo/vdMnNJeMQxY1gZa1h+78FRDeCgq2xKAxWt+072AfDQc3xWjbkLWe7KiMCs6h8oFT f4sLH7yDJ4ZzRYfNMlDgMJVGQDWRNteNbfVIU5Ana9D8sb6GZa09tQjbpSZGcYysmSfa Zne+x6AwNUqWygFtU9Sz5ejlao4CPDh/inUM6nJrAQDY8teC60E2MaKGUvQmPxZAPiLu MMC+1YJ7KLe41pEZxHQlHAR0CiAnqcDZiVF9vns+DQnUcob1mDHnE4+zuk0+Nc/QHD+K uM5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Wq3HlctCe78yvKE2dJl/lmSv5/GtdmA9RfU6fehuz/0=; b=l6pu/QfkeCfxpzd3UXUlv7bzYoBuJRUOTqk0Sa+lHAUx7v18JBCPHduLlZMNdSF9PH lOc+t7np1sr4h4qqg6tiUyNpR/pGd/N9FuMQnD3/LaJtmK9DkT72fVwL2g9NYikfYuDJ PY0ojlVP5hZcGAl4sxSz70gNv/f9JRKDZQL2EkaarH4Mzmke6YTvbrZkWMq/ehffuvxa eWQmTCwJzuvSlaAaYxyrYvoVmGFWhJwmTTI995wFDkmtnFAJ0ODQqs8KTtJzLlAvRwgA 5qovZbrAWMHeW3K68FuA3d4ZGipfur3gIzAdCmf0Cvsu+zKsMARVAYnb+nu2onozreq2 Pc2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nbf0JDLC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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However because it's not a real system we have places in the code which especially handle check qtest_enabled() before referencing current_cpu. Now we can encode these details in the MemTxAttrs lets do that so we can start removing them. Signed-off-by: Alex Bennée Acked-by: Thomas Huth --- v2 - use a common macro instead of specific MEMTXATTRS_QTEST v3 - macro moved to earlier --- softmmu/qtest.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index f8acef2628..3aa2218b95 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][5] == 'b') { uint8_t data = value; - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 1); } else if (words[0][5] == 'w') { uint16_t data = value; tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 2); } else if (words[0][5] == 'l') { uint32_t data = value; tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 4); } else if (words[0][5] == 'q') { uint64_t data = value; tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 8); } qtest_send_prefix(chr); @@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][4] == 'b') { uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 1); value = data; } else if (words[0][4] == 'w') { uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 2); value = tswap16(data); } else if (words[0][4] == 'l') { uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &data, 4); value = tswap32(data); } else if (words[0][4] == 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), &value, 8); tswap64s(&value); } @@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(len); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); enc = g_malloc(2 * len + 1); @@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(ret == 0); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); b64_data = g_base64_encode(data, len); qtest_send_prefix(chr); @@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) data[i] = 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); g_free(data); @@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (len) { data = g_malloc(len); memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); g_free(data); } @@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) out_len = MIN(out_len, len); } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu->cpu_index), data, len); qtest_send_prefix(chr); From patchwork Mon Sep 26 13:38:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609314 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1867944pvb; Mon, 26 Sep 2022 06:50:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4shL5JFwZ8Rhh7bpJIudn681wwsedn7dcaKLPaUpsU/5YQsM8gXFFYOVlhar3X0daxuL+s X-Received: by 2002:a05:622a:5cc:b0:35d:10c4:c0c5 with SMTP id d12-20020a05622a05cc00b0035d10c4c0c5mr18291998qtb.79.1664200210474; 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[209.51.188.17]) by mx.google.com with ESMTPS id c5-20020a05620a268500b006ce5ba64da7si9172301qkp.555.2022.09.26.06.50.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 06:50:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y9kyFXT2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocoUr-0006tL-Vl for patch@linaro.org; Mon, 26 Sep 2022 09:50:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKK-00023d-OS for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:17 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:44581) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKH-0005f6-5u for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:16 -0400 Received: by mail-wm1-x32e.google.com with SMTP id k3-20020a05600c1c8300b003b4fa1a85f8so3735682wms.3 for ; Mon, 26 Sep 2022 06:39:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=aG890OAM4la1STKlhUzUAHk//B/vPqbxIBEMPlxySJs=; b=Y9kyFXT2Uq22TnF+aX55a7s+xxPR+k8s0XRTkOgZVwXXHE4Jsqmf3VbGd/M6Cwpmdo imDE17hiMZhPscidbf8SbXi+yXzkklCT8eEGD4Y6nMEuNQZp89ZEdaRglpzj/m8Llv2Z VYHWuovZlFIog9fPK8RElB42zIYHvsywEUJluGItpm8qVcawDGSAoK1tG9jfRBT4m+Hl UvcgQMCIN3UzUBJB79yl7kLPIeqvUl3fXRQJWcMnIikckKHj0gZ44saiZMw1h5uURbVi mIb6Gqfgx+Ynyw34kyUPi7oKddZUilcfGAcxlJa4nUJHUau8UWrxhyR0gGGbIty55Beh UjSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=aG890OAM4la1STKlhUzUAHk//B/vPqbxIBEMPlxySJs=; b=5XYJ/680WBd/o+x6j/pQz8B/0i7MtJb8TdfPfAIASgwEh1Unpo4jbip6eO/pfiNYXR wPU3Otydsz0350t7Zc4dlnEKHBSkDEmYJg9ZyVDkDQBI4ro+wr2vk3DQ+h4tHWdlW4aY Xnf2bIEW7ex4/r/lSG8Y2l5gHk/KHco8xqx0xODAkhoIr0yPai4IWHsvHhcS8oGRCfMq yoM7tB7E8Rvryg+Szf+eFxC4ysQga0RKxraixUc+DSt39fwwELmhgy/DQGzrmqt5/oz1 /ie0TfPqsyjy0ELEdF7jOO3mg9EpCEwLufBPxFrhOu66/mIa75AhCdF6D2lIhs5sMXK6 6NcA== X-Gm-Message-State: ACrzQf19JhZvMDcMFydlsekUK1vGQmoQ8BYda5OU7NTVhzii+KN0VrLp U+pQIsBgKQL3oLNFPke+t6AitQ== X-Received: by 2002:a05:600c:a49:b0:3a6:673a:2a9b with SMTP id c9-20020a05600c0a4900b003a6673a2a9bmr21643143wmq.3.1664199550606; Mon, 26 Sep 2022 06:39:10 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id p8-20020a05600c1d8800b003a342933727sm11844696wms.3.2022.09.26.06.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:08 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2E1041FFBD; Mon, 26 Sep 2022 14:39:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson , Peter Maydell Subject: [PATCH v2 05/11] hw/intc/gic: use MxTxAttrs to divine accessing CPU Date: Mon, 26 Sep 2022 14:38:58 +0100 Message-Id: <20220926133904.3297263-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 --- v2 - update for new field - bool asserts --- hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab..d907df3884 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -static inline int gic_get_current_cpu(GICState *s) +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; - } - return 0; + /* + * Something other than a CPU accessing the GIC would be a bug as + * would a CPU index higher than the GICState expects to be + * handling + */ + g_assert(attrs.requester_type == MEMTXATTRS_CPU); + g_assert(attrs.requester_id < s->num_cpu); + + return attrs.requester_id; } -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } /* Return true if this GIC config has interrupt groups, which is @@ -951,7 +956,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) int cm; int mask; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); cm = 1 << cpu; if (offset < 0x100) { if (offset == 0) { /* GICD_CTLR */ @@ -1182,7 +1187,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, int i; int cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); if (offset < 0x100) { if (offset == 0) { if (s->security_extn && !attrs.secure) { @@ -1476,7 +1481,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, int mask; int target_cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); irq = value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1780,7 +1785,7 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1788,7 +1793,7 @@ static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1818,7 +1823,7 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1827,7 +1832,7 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, attrs); } static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1860,7 +1865,7 @@ static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) { - int vcpu = gic_get_current_vcpu(s); + int vcpu = gic_get_current_vcpu(s, attrs); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1995,7 +2000,7 @@ static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *dat { GICState *s = (GICState *)opaque; - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, @@ -2004,7 +2009,7 @@ static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, From patchwork Mon Sep 26 13:38:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609313 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1867782pvb; Mon, 26 Sep 2022 06:49:50 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Mmj5pJbf1KpA1eu2ivSg/UMjkh3vUT9KFISvotA1aEzEdhFxp/y85INg4pS2GGTUGXJZg X-Received: by 2002:a05:622a:198c:b0:35c:c630:dfd8 with SMTP id u12-20020a05622a198c00b0035cc630dfd8mr18460787qtc.76.1664200190407; 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[209.51.188.17]) by mx.google.com with ESMTPS id k17-20020ae9f111000000b006cf56f3432esi4252936qkg.603.2022.09.26.06.49.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 06:49:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hbNZb0Hi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocoUX-0005uc-So for patch@linaro.org; Mon, 26 Sep 2022 09:49:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKJ-00022K-Cn for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:17 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:43773) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKH-0005es-0Z for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:14 -0400 Received: by mail-wr1-x432.google.com with SMTP id t7so10241126wrm.10 for ; Mon, 26 Sep 2022 06:39:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=IRUW2pm7zwTwXKyvk91nrv12NDMnIiyMSqxZ62fe2xY=; b=hbNZb0HiWW46FdJzuX55kN0jAW/OLv8ouYLybLOZ39gZzE3KyDakHvV+iZdv9V5HTZ 2uJ8uf3tNLs1mKnHvFW/zkp9HZpKWJE0apKrrFYivkN1Jh3XH8zJ2GA3wxOeZgizwe0T Y9uV8GmxVUuieo2ByTsA9cve7eGf0he/yTZ5OKGs81+ckS69ZrqKNViVydSvQfWDCZDH zNgNy9gn009UfkyoziRnoiFY6FbvRfvm675kbKYQBSiq2K4on4ml0jRpwfCgNAvpi8i6 VrtWh3esXaeT0D6M4k9V6Sy0ewq331ipf8qZoMdpriRWrSXhyTDP1t+nXMyS/IRKmbau jcYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=IRUW2pm7zwTwXKyvk91nrv12NDMnIiyMSqxZ62fe2xY=; b=eaMEOOTxWheHHsA4TLFhoLIEbsnbxGovjrfy/AR8CTfe9fsUGVUJd0luvPZg5BhpyQ QYDICFO4bw/MZ0BXcyNhFyrkAz3hXIPTNsM5n8VcjnocpfzRmsHEaP7WhfhHFnFMAml7 CgZhpHzCc/2zaPkmSZXu9qLgpkz8dVi4SQGegG5hZmhrIZsEaxBuRnPiGFgVGjE7TBXD 8RxJFp6ypT+uxtmcC92u4pQFK5yDebriSLknLHi8Gva9DmKLP0UqbSwoSNPXjCbzU/j4 42xfo85MedYPJ8A8lHhTFtZvyl62oAsN9OaC1mcbPeYZt7dGlSizN1hfYPTz+vYqo5uz N4BQ== X-Gm-Message-State: ACrzQf0cv6hoclgRqLyqWcIKzLXxAfbAIW68pm5UYKPJDOGbJMjo7x9O cGTxhhNlSdAsJRgR3ZtKPaOUPg== X-Received: by 2002:a5d:6987:0:b0:228:623e:2dc5 with SMTP id g7-20020a5d6987000000b00228623e2dc5mr13924955wru.574.1664199550137; Mon, 26 Sep 2022 06:39:10 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id fc17-20020a05600c525100b003b435c41103sm12046538wmb.0.2022.09.26.06.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:08 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 46AC61FFBE; Mon, 26 Sep 2022 14:39:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson , Peter Maydell Subject: [PATCH v2 06/11] hw/timer: convert mptimer access to attrs to derive cpu index Date: Mon, 26 Sep 2022 14:38:59 +0100 Message-Id: <20220926133904.3297263-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes the hacks to deal with empty current_cpu. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- v2 - update for new fields - bool asserts --- hw/timer/arm_mptimer.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cdfca3000b..813ba3b7e8 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -41,9 +41,10 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ -static inline int get_current_cpu(ARMMPTimerState *s) +static inline int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs) { - int cpu_id = current_cpu ? current_cpu->cpu_index : 0; + int cpu_id = attrs.requester_id; + g_assert(attrs.requester_type == MEMTXATTRS_CPU); if (cpu_id >= s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", @@ -178,25 +179,27 @@ static void timerblock_write(void *opaque, hwaddr addr, /* Wrapper functions to implement the "read timer/watchdog for * the current CPU" memory regions. */ -static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, - unsigned size) +static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); - return timerblock_read(&s->timerblock[id], addr, size); + int id = get_current_cpu(s, attrs); + *data = timerblock_read(&s->timerblock[id], addr, size); + return MEMTX_OK; } -static void arm_thistimer_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); + int id = get_current_cpu(s, attrs); timerblock_write(&s->timerblock[id], addr, value, size); + return MEMTX_OK; } static const MemoryRegionOps arm_thistimer_ops = { - .read = arm_thistimer_read, - .write = arm_thistimer_write, + .read_with_attrs = arm_thistimer_read, + .write_with_attrs = arm_thistimer_write, .valid = { .min_access_size = 4, .max_access_size = 4, From patchwork Mon Sep 26 13:39:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609328 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1895265pvb; Mon, 26 Sep 2022 07:34:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7IMI9KvnUbNviSKA+7cT6kU3GmjfqIHqamz7Gq0sDl3Emw+q+Be6ZBl0oPcLJXFYc4Lle+ X-Received: by 2002:ac8:7a8e:0:b0:35b:b23f:d03 with SMTP id x14-20020ac87a8e000000b0035bb23f0d03mr18309925qtr.665.1664202867513; Mon, 26 Sep 2022 07:34:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664202867; cv=none; d=google.com; s=arc-20160816; b=H9s07g+pbNAr7mo+yWJvwvDnj/X9YfiD4AX0+a+kG6QRQywLXsRrTGPnl6PR+h/ejh XdzSAdJzGepXQjgl9r5bz11EqQGQngYAKvqOQKnoOk6yaXdH9Eop5IEPtoCqcFIhfmpe cfHtZ7h8CRS7VZg7dMI7Xf5MVn+VRwtvSRorect6q1RBn6MHAGnoQEWg3fhy1vMN854Y Ufv24biwOMT41WcgdFNzIJL6h15iH/wt3do/SV3QHQoayiVaZKYbOczPn3wNSTWiblGE 7ekI1cEHcP9uXUgoXcLDWyuJuBi2l0q98ltdkRY5HTIlbutGG58fDiTzR0kXVnI+FHid UzbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PI0lzKVBNSGjEUI0jEXjRiLwo5dV6hN1IML/GBrLC6Y=; b=FFK/VOmeKqq1NY+UCLkJuvZaCsdv/5LO3dPDaanr/QjjgWGt18ehOupyWHZmS0PHzX YfvLuH6f3XQThFFBkACqLtAB0xeP0XLBTFMEWgMHb4BGVa6J4x+CfU/UWBj41ZicUekA Jf0v/h00PF6EKoB+GSPGEwlCweYt1mpimqLPcvYLS7/VgdqecM59eUgJGWYrng8TQ/g/ nqs6KCLZ+o9G6K9LOK7fAeK6LgWszQkTQfZMCqj2M+ZrD2lwfLq3RPCm//ePWT+IqinC TzPQpCQ7+mKw7PPGPW3JlR5YpILddv9SAZtP6GMbL9YeQAWPWhGQYwGOT4kyNcd1ijGQ LsGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=loBEqcBt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j17-20020a05620a289100b006bb41a6959fsi9165108qkp.579.2022.09.26.07.34.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 07:34:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=loBEqcBt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocpBi-0005TV-Uv for patch@linaro.org; Mon, 26 Sep 2022 10:34:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKJ-00022A-D7 for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:17 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:50838) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKH-0005fO-5b for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:14 -0400 Received: by mail-wm1-x334.google.com with SMTP id ay36so4546464wmb.0 for ; Mon, 26 Sep 2022 06:39:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PI0lzKVBNSGjEUI0jEXjRiLwo5dV6hN1IML/GBrLC6Y=; b=loBEqcBt2PNYeExZwPhAsE0NmiOkGgD5hTe4yKNpUZtD6IYaWU+8CtjQexetZrE5/i VHJMROOpBMYFL89CnyEvHOBEju6q4H0iPGKpZa3PyCUv5FZHLTmcekCDfV557FO+2Nmv scbsZc2psCZsu9QWOTU84uDZZHohmFTfbRwqCVeNo7oT4mks8ARcP1VpjfyfdWh8PDam Nb09uhNcbggyCR0d6+wjFGSCB43MizvL8yxg8F011FyoaR0f/asMHfzXWzwYqvacy6e4 PshRAOVmwUVEEyjH2TP1XzAKkH0qiOVc+NUS1/HU8yMQ8UAY1HTClVX9MhPndsJqeUi+ 0qaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PI0lzKVBNSGjEUI0jEXjRiLwo5dV6hN1IML/GBrLC6Y=; b=ZGMPAIQTW6DO37iqBZGG71VzJOyN+5fWaVRBPCko/NVVwV8etKVjrK7z0jYOcuHFrt kyEItHPM4D8ane5UMV4E8wUXRLoOJCBfMBA5PscVn7toHC33wVWyo3xPCV4VDzT+Iv3P 5PVnASVkAlq9v07YOswWX7H+cDtKD2GX1WsCq/ZZjaKfsi7loq9GD57VmwGpL1iTvTOS IA9DOg0HF+SqPPm23SpPZ8WLDND7VTRypfGY3ZLwd23WNAEYObySbVhVOzX5N4FKVfiI bMXf/y8NeVlHCyhPliFXtpioCcHw1pidt2lsGiMJC/wKYE6PdwS6Zr/TIDUjyfeQZzFA bCSA== X-Gm-Message-State: ACrzQf2oyqURja+XP3gYcT4+d2l4edWeOWxLsCx86eFKBcAYrLNmfMWW AHWEInj+OjDpIT81v4KeczLXxw== X-Received: by 2002:a7b:c056:0:b0:3b4:e007:2050 with SMTP id u22-20020a7bc056000000b003b4e0072050mr22266153wmc.38.1664199551517; Mon, 26 Sep 2022 06:39:11 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id ay16-20020a5d6f10000000b0022af70874a1sm18448548wrb.36.2022.09.26.06.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:08 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5C73D1FFBF; Mon, 26 Sep 2022 14:39:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson Subject: [PATCH v2 07/11] configure: move detected gdb to TCG's config-host.mak Date: Mon, 26 Sep 2022 14:39:00 +0100 Message-Id: <20220926133904.3297263-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When tests/tcg gained it's own config-host.mak we forgot to move the GDB detection. Fixes: 544f4a2578 (tests/tcg: isolate from QEMU's config-host.mak) Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- configure | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configure b/configure index 0bbf9d28af..fce677bd4a 100755 --- a/configure +++ b/configure @@ -2481,6 +2481,8 @@ if test -n "$gdb_bin"; then gdb_version=$($gdb_bin --version | head -n 1) if version_ge ${gdb_version##* } 9.1; then echo "HAVE_GDB_BIN=$gdb_bin" >> $config_host_mak + else + gdb_bin="" fi fi @@ -2565,6 +2567,11 @@ echo "# Automatically generated by configure - do not modify" > $config_host_mak echo "SRC_PATH=$source_path" >> $config_host_mak echo "HOST_CC=$host_cc" >> $config_host_mak +# versioned checked in the main config_host.mak above +if test -n "$gdb_bin"; then + echo "HAVE_GDB_BIN=$gdb_bin" >> $config_host_mak +fi + tcg_tests_targets= for target in $target_list; do arch=${target%%-*} From patchwork Mon Sep 26 13:39:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609316 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1870690pvb; Mon, 26 Sep 2022 06:55:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7fmDCwZ6ZH8OkRLH9KfK0EOeZXE6ryz9MW8tOJ07OKLJ2cH+zYsfB2Gq7cJmeY5H2h+Mys X-Received: by 2002:a37:9785:0:b0:6cf:55d:e554 with SMTP id z127-20020a379785000000b006cf055de554mr14334662qkd.459.1664200501205; Mon, 26 Sep 2022 06:55:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664200501; cv=none; d=google.com; s=arc-20160816; b=WpeHnV5QWgd2NIRoq2Mx/TF5HxF9TJwDAw4T2e7nAllX1FGOdBjPtkR6nzrlI3rQ6b PPljS15IlD/bQlJsaXvAvFpa6jSHIOsX5ag3NvUaIkPNg6fk3fQI1++yyzAAojSp1LBm gZdlURESgxe3wYrjk3V9nFgVeY013C+ukltcyf3WnNZdnnnzC5HO109DT9BJIoqMVIfV Np4xktEtwS2Jx4yCAA7yj4hYfaGCr8bIePIoGAO1GDr+tLfvzmg6N2QqmrBA5w9Vp+d3 srUoagq9+QyR4ABLAWHqjNvzaYRzJoYd2XHQ9yew05rIONu5xfbhKu4HU3dBrnvVRLiV roVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XZUpjPpadlAUHW/RreWII3CPwNzHzHCurB5FcarW70s=; b=cmp6rtVuAJ4qMgmbl5qGxvMuC1ymwxJoLOKtqZARMpHGg89tg06E0tGhgybwPzijAF iXw/uAdUzxgO6Zwgl9oBOA2MHyPvZYRGwY0Sx9OQS5motFvUWYr0xIUrHUDAdw+TC9xS PDPeydXca4KOjqK4+WDIVRvkWxP4viHy+tvOtdVUvzSDKWiUJc1MHAiHiKtlUveuiUaS xxLbRo6xsCvPDLA2dYXfYDydvdYTn47mD0zevqkGdQwNBo2rJMSFKbqSk3e7OeE4UNEI 3qrnMgD7wc/HOhU+8YLzT2KJbGFw+lQ0XxZfJwKUfZhbCzVYXnhABbfZ4Ar/nWtB66zK /rpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CxXecedO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n17-20020a05620a223100b006bae7e78f96si7523540qkh.676.2022.09.26.06.55.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 06:55:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CxXecedO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocoZY-0004Gd-NR for patch@linaro.org; Mon, 26 Sep 2022 09:55:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKL-00024q-C4 for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:18 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:41608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKH-0005fZ-9V for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:16 -0400 Received: by mail-wr1-x430.google.com with SMTP id t14so10262246wrx.8 for ; Mon, 26 Sep 2022 06:39:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=XZUpjPpadlAUHW/RreWII3CPwNzHzHCurB5FcarW70s=; b=CxXecedO5PLRrsWsYKTJ9rYCGejuvgvccFXWXmiRKML6su5AHkaMhHeg684YI6lDxe tD8BdU2i845ePYzkuF1avk1zL1T0R3N/Tp+0+E8kSo6f9Z9OszY1hdasxlIeILrhiUfO 6mxJbhphzdw1L2Wr4sEHED/7AhjI11NKrqtIKPJAMdmNWsNKPF+TpOGwhV69UQXsH4rP 8RLIbaaofGxVgNTifAsThxJaMNY/hBQsP/mn0N3nfR96myvickmM3iDmqaPX2oYCxegW /UTwcxFRwwI46+G3Q+6IvpiV0apCdq18hTGA2PGxOy6+X4goD68JfLwP4xkoGpWWavDt rMAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=XZUpjPpadlAUHW/RreWII3CPwNzHzHCurB5FcarW70s=; b=EJZFcXJZd+53vlncZwpgrm9A+Cd3JXspD+O6wsrywsE6dXRQ4Pttc4oyQEbrYrC4xc eiXmWCOa7E8MeJ4v4zw2Tc70rvUqBaTcN42PHoxBG8O0bXPqiCbhCXctFb/BgWsldVEY cvP0gt0hwUukpqjy4SueZjn5SjSBLLCk6o0fpzlz9OQqAfyaQMvNTxqqBvARsWVziy8a t/Op16WvrAkQ7LOQr/vJlEulal/toYUPqlmscRAcFrXhfexayhIgXjjuC2uMyCQG1FDo frr5o2UE7rzAad6ckjwiBBCCc5sMzXQWEMx8yZxxEzJktuMcHJ29P6K68qltKmaXRtEo 0AwA== X-Gm-Message-State: ACrzQf2InvykMfSq4iT8N0rk3XKoYrrxYBep+UfcMT3vDAVzbH3R09TZ f25M0wz/ZkwPYhk0mShMidZVTA== X-Received: by 2002:adf:ebcf:0:b0:22c:9eb4:d6f6 with SMTP id v15-20020adfebcf000000b0022c9eb4d6f6mr4581820wrn.251.1664199551927; Mon, 26 Sep 2022 06:39:11 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b4fdbb6319sm13149120wmq.21.2022.09.26.06.39.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:08 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 82FC01FFC0; Mon, 26 Sep 2022 14:39:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson , Stefan Hajnoczi Subject: [PATCH v2 08/11] gdbstub: move into its own sub directory Date: Mon, 26 Sep 2022 14:39:01 +0100 Message-Id: <20220926133904.3297263-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is in preparation of future refactoring as well as cleaning up the source tree. Aside from the minor tweaks to meson and trace.h this is pure code motion. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- meson.build | 4 +++- gdbstub/trace.h | 1 + gdbstub.c => gdbstub/gdbstub.c | 2 +- MAINTAINERS | 2 +- gdbstub/meson.build | 1 + gdbstub/trace-events | 29 +++++++++++++++++++++++++++++ trace-events | 28 ---------------------------- 7 files changed, 36 insertions(+), 31 deletions(-) create mode 100644 gdbstub/trace.h rename gdbstub.c => gdbstub/gdbstub.c (99%) create mode 100644 gdbstub/meson.build create mode 100644 gdbstub/trace-events diff --git a/meson.build b/meson.build index 3885fc1076..2c9209c2b8 100644 --- a/meson.build +++ b/meson.build @@ -2914,6 +2914,7 @@ trace_events_subdirs = [ 'qom', 'monitor', 'util', + 'gdbstub', ] if have_linux_user trace_events_subdirs += [ 'linux-user' ] @@ -3037,6 +3038,7 @@ subdir('authz') subdir('crypto') subdir('ui') subdir('hw') +subdir('gdbstub') if enable_modules @@ -3114,7 +3116,7 @@ common_ss.add(files('cpus-common.c')) subdir('softmmu') common_ss.add(capstone) -specific_ss.add(files('cpu.c', 'disas.c', 'gdbstub.c'), capstone) +specific_ss.add(files('cpu.c', 'disas.c'), capstone) # Work around a gcc bug/misfeature wherein constant propagation looks # through an alias: diff --git a/gdbstub/trace.h b/gdbstub/trace.h new file mode 100644 index 0000000000..dee87b1238 --- /dev/null +++ b/gdbstub/trace.h @@ -0,0 +1 @@ +#include "trace/trace-gdbstub.h" diff --git a/gdbstub.c b/gdbstub/gdbstub.c similarity index 99% rename from gdbstub.c rename to gdbstub/gdbstub.c index cf869b10e3..7d8fe475b3 100644 --- a/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -29,7 +29,7 @@ #include "qemu/ctype.h" #include "qemu/cutils.h" #include "qemu/module.h" -#include "trace/trace-root.h" +#include "trace.h" #include "exec/gdbstub.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" diff --git a/MAINTAINERS b/MAINTAINERS index 738c4eb647..82575b2486 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2670,7 +2670,7 @@ GDB stub M: Alex Bennée R: Philippe Mathieu-Daudé S: Maintained -F: gdbstub* +F: gdbstub/* F: include/exec/gdbstub.h F: gdb-xml/ F: tests/tcg/multiarch/gdbstub/ diff --git a/gdbstub/meson.build b/gdbstub/meson.build new file mode 100644 index 0000000000..6d4ae2d03c --- /dev/null +++ b/gdbstub/meson.build @@ -0,0 +1 @@ +specific_ss.add(files('gdbstub.c')) diff --git a/gdbstub/trace-events b/gdbstub/trace-events new file mode 100644 index 0000000000..03f0c303bf --- /dev/null +++ b/gdbstub/trace-events @@ -0,0 +1,29 @@ +# See docs/devel/tracing.rst for syntax documentation. + +# gdbstub.c +gdbstub_op_start(const char *device) "Starting gdbstub using device %s" +gdbstub_op_exiting(uint8_t code) "notifying exit with code=0x%02x" +gdbstub_op_continue(void) "Continuing all CPUs" +gdbstub_op_continue_cpu(int cpu_index) "Continuing CPU %d" +gdbstub_op_stepping(int cpu_index) "Stepping CPU %d" +gdbstub_op_extra_info(const char *info) "Thread extra info: %s" +gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" +gdbstub_hit_internal_error(void) "RUN_STATE_INTERNAL_ERROR" +gdbstub_hit_break(void) "RUN_STATE_DEBUG" +gdbstub_hit_paused(void) "RUN_STATE_PAUSED" +gdbstub_hit_shutdown(void) "RUN_STATE_SHUTDOWN" +gdbstub_hit_io_error(void) "RUN_STATE_IO_ERROR" +gdbstub_hit_watchdog(void) "RUN_STATE_WATCHDOG" +gdbstub_hit_unknown(int state) "Unknown run state=0x%x" +gdbstub_io_reply(const char *message) "Sent: %s" +gdbstub_io_binaryreply(size_t ofs, const char *line) "0x%04zx: %s" +gdbstub_io_command(const char *command) "Received: %s" +gdbstub_io_got_ack(void) "Got ACK" +gdbstub_io_got_unexpected(uint8_t ch) "Got 0x%02x when expecting ACK/NACK" +gdbstub_err_got_nack(void) "Got NACK, retransmitting" +gdbstub_err_garbage(uint8_t ch) "received garbage between packets: 0x%02x" +gdbstub_err_overrun(void) "command buffer overrun, dropping command" +gdbstub_err_invalid_repeat(uint8_t ch) "got invalid RLE count: 0x%02x" +gdbstub_err_invalid_rle(void) "got invalid RLE sequence" +gdbstub_err_checksum_invalid(uint8_t ch) "got invalid command checksum digit: 0x%02x" +gdbstub_err_checksum_incorrect(uint8_t expected, uint8_t got) "got command packet with incorrect checksum, expected=0x%02x, received=0x%02x" diff --git a/trace-events b/trace-events index bc71006675..035f3d570d 100644 --- a/trace-events +++ b/trace-events @@ -46,34 +46,6 @@ ram_block_discard_range(const char *rbname, void *hva, size_t length, bool need_ memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size) "0x%" PRIx64 " ram_addr 0x%" PRIx64 " size %u" memory_notdirty_set_dirty(uint64_t vaddr) "0x%" PRIx64 -# gdbstub.c -gdbstub_op_start(const char *device) "Starting gdbstub using device %s" -gdbstub_op_exiting(uint8_t code) "notifying exit with code=0x%02x" -gdbstub_op_continue(void) "Continuing all CPUs" -gdbstub_op_continue_cpu(int cpu_index) "Continuing CPU %d" -gdbstub_op_stepping(int cpu_index) "Stepping CPU %d" -gdbstub_op_extra_info(const char *info) "Thread extra info: %s" -gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" -gdbstub_hit_internal_error(void) "RUN_STATE_INTERNAL_ERROR" -gdbstub_hit_break(void) "RUN_STATE_DEBUG" -gdbstub_hit_paused(void) "RUN_STATE_PAUSED" -gdbstub_hit_shutdown(void) "RUN_STATE_SHUTDOWN" -gdbstub_hit_io_error(void) "RUN_STATE_IO_ERROR" -gdbstub_hit_watchdog(void) "RUN_STATE_WATCHDOG" -gdbstub_hit_unknown(int state) "Unknown run state=0x%x" -gdbstub_io_reply(const char *message) "Sent: %s" -gdbstub_io_binaryreply(size_t ofs, const char *line) "0x%04zx: %s" -gdbstub_io_command(const char *command) "Received: %s" -gdbstub_io_got_ack(void) "Got ACK" -gdbstub_io_got_unexpected(uint8_t ch) "Got 0x%02x when expecting ACK/NACK" -gdbstub_err_got_nack(void) "Got NACK, retransmitting" -gdbstub_err_garbage(uint8_t ch) "received garbage between packets: 0x%02x" -gdbstub_err_overrun(void) "command buffer overrun, dropping command" -gdbstub_err_invalid_repeat(uint8_t ch) "got invalid RLE count: 0x%02x" -gdbstub_err_invalid_rle(void) "got invalid RLE sequence" -gdbstub_err_checksum_invalid(uint8_t ch) "got invalid command checksum digit: 0x%02x" -gdbstub_err_checksum_incorrect(uint8_t expected, uint8_t got) "got command packet with incorrect checksum, expected=0x%02x, received=0x%02x" - # job.c job_state_transition(void *job, int ret, const char *legal, const char *s0, const char *s1) "job %p (ret: %d) attempting %s transition (%s-->%s)" job_apply_verb(void *job, const char *state, const char *verb, const char *legal) "job %p in state %s; applying verb %s (%s)" From patchwork Mon Sep 26 13:39:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609329 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1898017pvb; Mon, 26 Sep 2022 07:39:12 -0700 (PDT) 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[209.51.188.17]) by mx.google.com with ESMTPS id kj25-20020a056214529900b004aaa7dcf307si8471987qvb.376.2022.09.26.07.39.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 07:39:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hIQ/3ftc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocpGJ-0003m8-Gd for patch@linaro.org; Mon, 26 Sep 2022 10:39:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKM-00024t-5u for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:18 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKJ-0005gV-D7 for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:17 -0400 Received: by mail-wr1-x42d.google.com with SMTP id x18so10266871wrm.7 for ; Mon, 26 Sep 2022 06:39:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=uPWI1zT5RA3MTBLfOSsbd8UM7dwx7REeUZ6YlYd0oe4=; b=hIQ/3ftczCI0GBfvYERTE3hSvszZAAz68CjitXhOoHUWZKjSoGByygyoLPAoUzQT8J BtbsyjFrHXoZgK8S32cYB2k42YogtinGj9fNy+kIYt+Qc3FCcCd/OB2OvNXw0/DPMIVz HM6O9bjwyLmoGmdfBgoefwxb1quxbiRr8OGiEmwStkD2EQ3ReJzI4o8gwDEWbgV+tKEI EWHCD4GMoF5ghzmTWBqZpSr9TyZmV1Ad0QrnyLZH1gf9DUTTbTnGVuFK6C+FB3W3+vNd oXbYXRqT/bIaICFcvoNj3b80iT/PTjEvE51mcqHTXoG+L87V3+jaupR15zJPLHkHCA/o kmTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=uPWI1zT5RA3MTBLfOSsbd8UM7dwx7REeUZ6YlYd0oe4=; b=mrt3Tb93G+ZQIfCmUOC1qvz4zeNnFXd0MT/g3ft/fIQGzLsfbCghhDXplwbOib+wxb BN3FIXFy8JjZXB/iuLqA+Q3DN18bgOPs+/dG/R9B0EbQ+W7m9dOlnRWBwVatVy5BXyoE u1j7ou0OhO6gV1YF+u6+CmF/q4wWZ7iVSdkpR4DzOQOnSVd/Np/dOPZNp2F5D+xnTeWW wSB7KGH0Vah83asZt/vkQFTf7zeP8OSOnLHwa7e5bz6ikkYCQIMd9KO0v/jKyQkA9IL2 1JQioRBYGm+rhIjmWfBmHIhiFC6QQHiHKtmCBIZ7z17NDoy1ytIkIsQfojx44PlDoU4v onug== X-Gm-Message-State: ACrzQf2uGEDHDEymyfmqrF4WXwav5jT745oeKrpW8/4LNzJu1jMhEmYG kjifrI6EaKHuvrNP6iRJLtH/VSPUklRQbg== X-Received: by 2002:adf:e186:0:b0:22a:3329:540f with SMTP id az6-20020adfe186000000b0022a3329540fmr13417102wrb.278.1664199553616; Mon, 26 Sep 2022 06:39:13 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id t16-20020a05600c199000b003a1980d55c4sm12080553wmq.47.2022.09.26.06.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:09 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A6E8C1FFC1; Mon, 26 Sep 2022 14:39:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson , Paolo Bonzini , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v2 09/11] gdbstub: move sstep flags probing into AccelClass Date: Mon, 26 Sep 2022 14:39:02 +0100 Message-Id: <20220926133904.3297263-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The support of single-stepping is very much dependent on support from the accelerator we are using. To avoid special casing in gdbstub move the probing out to an AccelClass function so future accelerators can put their code there. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Cc: Mads Ynddal --- include/qemu/accel.h | 12 ++++++++++++ include/sysemu/kvm.h | 8 -------- accel/accel-common.c | 10 ++++++++++ accel/kvm/kvm-all.c | 14 +++++++++++++- accel/tcg/tcg-all.c | 17 +++++++++++++++++ gdbstub/gdbstub.c | 22 ++++------------------ 6 files changed, 56 insertions(+), 27 deletions(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index be56da1b99..ce4747634a 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -43,6 +43,10 @@ typedef struct AccelClass { bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); #endif + + /* gdbstub related hooks */ + int (*gdbstub_supported_sstep_flags)(void); + bool *allowed; /* * Array of global properties that would be applied when specific @@ -92,4 +96,12 @@ void accel_cpu_instance_init(CPUState *cpu); */ bool accel_cpu_realizefn(CPUState *cpu, Error **errp); +/** + * accel_supported_gdbstub_sstep_flags: + * + * Returns the supported single step modes for the configured + * accelerator. + */ +int accel_supported_gdbstub_sstep_flags(void); + #endif /* QEMU_ACCEL_H */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index efd6dee818..a20ad51aad 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -47,7 +47,6 @@ extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; extern bool kvm_has_guest_debug; -extern int kvm_sstep_flags; #define kvm_enabled() (kvm_allowed) /** @@ -174,12 +173,6 @@ extern int kvm_sstep_flags; */ #define kvm_supports_guest_debug() (kvm_has_guest_debug) -/* - * kvm_supported_sstep_flags - * Returns: SSTEP_* flags that KVM supports for guest debug - */ -#define kvm_get_supported_sstep_flags() (kvm_sstep_flags) - #else #define kvm_enabled() (0) @@ -198,7 +191,6 @@ extern int kvm_sstep_flags; #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) #define kvm_supports_guest_debug() (false) -#define kvm_get_supported_sstep_flags() (0) #endif /* CONFIG_KVM_IS_POSSIBLE */ diff --git a/accel/accel-common.c b/accel/accel-common.c index 50035bda55..df72cc989a 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -129,6 +129,16 @@ bool accel_cpu_realizefn(CPUState *cpu, Error **errp) return true; } +int accel_supported_gdbstub_sstep_flags(void) +{ + AccelState *accel = current_accel(); + AccelClass *acc = ACCEL_GET_CLASS(accel); + if (acc->gdbstub_supported_sstep_flags) { + return acc->gdbstub_supported_sstep_flags(); + } + return 0; +} + static const TypeInfo accel_cpu_type = { .name = TYPE_ACCEL_CPU, .parent = TYPE_OBJECT, diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 5acab1767f..c55938453a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -175,7 +175,7 @@ bool kvm_direct_msi_allowed; bool kvm_ioeventfd_any_length_allowed; bool kvm_msi_use_devid; bool kvm_has_guest_debug; -int kvm_sstep_flags; +static int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size = ~0; @@ -3712,6 +3712,17 @@ static void kvm_accel_instance_init(Object *obj) s->kvm_dirty_ring_size = 0; } +/** + * kvm_gdbstub_sstep_flags(): + * + * Returns: SSTEP_* flags that KVM supports for guest debug. The + * support is probed during kvm_init() + */ +static int kvm_gdbstub_sstep_flags(void) +{ + return kvm_sstep_flags; +} + static void kvm_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); @@ -3719,6 +3730,7 @@ static void kvm_accel_class_init(ObjectClass *oc, void *data) ac->init_machine = kvm_init; ac->has_memory = kvm_accel_has_memory; ac->allowed = &kvm_allowed; + ac->gdbstub_supported_sstep_flags = kvm_gdbstub_sstep_flags; object_class_property_add(oc, "kernel-irqchip", "on|off|split", NULL, kvm_set_kernel_irqchip, diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 47952eecd7..30b503fb22 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "sysemu/tcg.h" +#include "sysemu/replay.h" #include "sysemu/cpu-timers.h" #include "tcg/tcg.h" #include "qapi/error.h" @@ -207,12 +208,28 @@ static void tcg_set_splitwx(Object *obj, bool value, Error **errp) s->splitwx_enabled = value; } +static int tcg_gdbstub_supported_sstep_flags(void) +{ + /* + * In replay mode all events will come from the log and can't be + * suppressed otherwise we would break determinism. However as those + * events are tied to the number of executed instructions we won't see + * them occurring every time we single step. + */ + if (replay_mode != REPLAY_MODE_NONE) { + return SSTEP_ENABLE; + } else { + return SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; + } +} + static void tcg_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); ac->name = "tcg"; ac->init_machine = tcg_init_machine; ac->allowed = &tcg_allowed; + ac->gdbstub_supported_sstep_flags = tcg_gdbstub_supported_sstep_flags; object_class_property_add_str(oc, "thread", tcg_get_thread, diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 7d8fe475b3..a0755e6505 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -383,27 +383,13 @@ static void init_gdbserver_state(void) gdbserver_state.last_packet = g_byte_array_sized_new(MAX_PACKET_LENGTH + 4); /* - * In replay mode all events will come from the log and can't be - * suppressed otherwise we would break determinism. However as those - * events are tied to the number of executed instructions we won't see - * them occurring every time we single step. - */ - if (replay_mode != REPLAY_MODE_NONE) { - gdbserver_state.supported_sstep_flags = SSTEP_ENABLE; - } else if (kvm_enabled()) { - gdbserver_state.supported_sstep_flags = kvm_get_supported_sstep_flags(); - } else { - gdbserver_state.supported_sstep_flags = - SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; - } - - /* - * By default use no IRQs and no timers while single stepping so as to - * make single stepping like an ICE HW step. + * What single-step modes are supported is accelerator dependent. + * By default try to use no IRQs and no timers while single + * stepping so as to make single stepping like a typical ICE HW step. */ + gdbserver_state.supported_sstep_flags = accel_supported_gdbstub_sstep_flags(); gdbserver_state.sstep_flags = SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; gdbserver_state.sstep_flags &= gdbserver_state.supported_sstep_flags; - } #ifndef CONFIG_USER_ONLY From patchwork Mon Sep 26 13:39:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609319 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1873708pvb; Mon, 26 Sep 2022 07:00:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM59CI1544+CxfiaR9K6y4sarS3QoJ4g3c+9bfuZMIEqxxyRGLPcjth6gfs0M91zHzsRJlyQ X-Received: by 2002:a37:a97:0:b0:6cf:849:fb10 with SMTP id 145-20020a370a97000000b006cf0849fb10mr13966618qkk.546.1664200829775; Mon, 26 Sep 2022 07:00:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664200829; cv=none; d=google.com; s=arc-20160816; b=pdDVNLtGSbXQ6gCKTf5In2ByClJSfwcooSsGDCWR4u6CgZ9QK/L8yC6f7vH90aDbHS 6HtQ78AmUTyenhZYtWexz2Lc0CLSyK0CU7ud0UeQK3tR6P6ga+HoP2C2NRaV2zyEOusl 57N96CYAWnkew8Rs4076GffcKCmC8ADmCi4qxJnNJpnBK4wAzIWGf9kqoBmE/VVJv8BZ wybMnk3TkpnTtdGCzW4hrL2rKzp/uEfhOeKFQwbm12teXoYwi0qUvRVXZe+xSHYdFrSQ weuYuQmV/15cprEcqiv4xO1q//S3PfNSR0ES9nzLD35hvQF90U9JSg4IXLhrlKTDayvL U21A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fTabJPCIPlhP85UMkzUVWmjvUxpiXA1PS7vvmHzeVyk=; b=mPeLJtjhXDGF72ct/P29hNirhF7V3aA4sknPBZfJ/po1WMX/8Pv6DDOb3ZKgdlFUoL m4I3yg8dFVyBIedOE3FwoWaAUPCPe3eFW4XBeDl3srHQEDieqpPy5FVxNAsXG7xuu/jR Zoi/bwCZcNxHQbQ00NQKZS7VmjXwHCfODmzVYNdTM/ABYaVqgd23NJoCW3dnlN4DOI7U UNhlrFd0ldQRMvTdlfokPVK8rFnyY+7iWUnfHScG55hCvm0P21juRpn2Adi8FKXfcVUY aoqnocgoO9V9l7h6xXPweyyMwbi9kqVHElvYQsGta7KyNus/fI3M7T7B8Gh5w8iRFJkj sO5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dk2MNVCJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f1-20020ac87f01000000b0035bbb364c4asi10919929qtk.288.2022.09.26.07.00.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 07:00:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dk2MNVCJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocoer-0002N9-9n for patch@linaro.org; Mon, 26 Sep 2022 10:00:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKN-00027Y-OW for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:20 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:41474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKK-0005gd-EM for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:19 -0400 Received: by mail-wm1-x329.google.com with SMTP id fn7-20020a05600c688700b003b4fb113b86so3770694wmb.0 for ; Mon, 26 Sep 2022 06:39:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=fTabJPCIPlhP85UMkzUVWmjvUxpiXA1PS7vvmHzeVyk=; b=dk2MNVCJbHMDxbHQH4Hxb6qCchcSU2AedQFrMyqAme1APNCSfRkRioa5WpZwVjPEEa AQBWPgSSyeeAM/tMPfVhH4eHkSeoGqNM5sEoDmllsMm/rdAgbBlsKqXAXkm4WSd2bGp2 RIrFCNyth4d5DLzxu/1QqlV+IY8kJCBmwq20Jgf+yjSkbfI9NagNFUzw7MAh7HwhITJ7 O432reIpM7Y/+/57sb2+87/ZCcxmZDh29fMWp1lWLKW7V5sCHU/BOlg+lz2d9tLCOw3p cyGqjdTQG4eS1ZeKG2D1NUx0Auk7CxcjxbqAdRM0TEbmiqeufj3DF5CWJiJ18jt/Sxpd BHag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=fTabJPCIPlhP85UMkzUVWmjvUxpiXA1PS7vvmHzeVyk=; b=XCkj448SDapDI5JeIwDBbvSBllQpVA34NG3U12KYCr6aRetO/jJaXeY7zojKV90zMb 0dJ3czTKtHChJxoPqveywvbbxnZGd6Fn3Q6feMye9Pm2hwtl3r+Wd2PekulqqIe5mxen b1matJ2JZl/V0W99crf7oObLZY1ci5bd0eulS3kKIeRuyDtKhh7SN5cfCAIfeB8x8UV3 qppNLKxbJvoBMgTk8GAuc5YzTH0oFP9dwDiA3EJXx7QuRdJmKwNOdmA/4lENI9fRh5HG 2tBx6Yu22QLvQdGcDsYZnaAwWjVyJy8La7Ey5oQluFOH4ZRPsVX9w9XeZ0i175MbWx1G Cpsg== X-Gm-Message-State: ACrzQf0VpxEi4k7y6iPVjLZtDtLz8L2afiOgnkwIKQQWCK5/4Ijab9wX 3w6UJi/MsqBbJhw/64Es08BLBQ== X-Received: by 2002:a05:600c:3781:b0:3b4:63c8:554b with SMTP id o1-20020a05600c378100b003b463c8554bmr22111257wmr.25.1664199553996; Mon, 26 Sep 2022 06:39:13 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id w10-20020a05600c474a00b003b4ac05a8a4sm13874247wmo.27.2022.09.26.06.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:09 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E542E1FFC2; Mon, 26 Sep 2022 14:39:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson , Paolo Bonzini , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v2 10/11] gdbstub: move breakpoint logic to accel ops Date: Mon, 26 Sep 2022 14:39:03 +0100 Message-Id: <20220926133904.3297263-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As HW virtualization requires specific support to handle breakpoints lets push out special casing out of the core gdbstub code and into AccelOpsClass. This will make it easier to add other accelerator support and reduces some of the stub shenanigans. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Cc: Mads Ynddal --- accel/kvm/kvm-cpus.h | 3 + gdbstub/internals.h | 16 +++++ include/sysemu/accel-ops.h | 6 ++ include/sysemu/cpus.h | 3 + include/sysemu/kvm.h | 5 -- accel/kvm/kvm-accel-ops.c | 8 +++ accel/kvm/kvm-all.c | 24 +------ accel/stubs/kvm-stub.c | 16 ----- accel/tcg/tcg-accel-ops.c | 92 +++++++++++++++++++++++++++ gdbstub/gdbstub.c | 127 +++---------------------------------- gdbstub/softmmu.c | 42 ++++++++++++ gdbstub/user.c | 62 ++++++++++++++++++ softmmu/cpus.c | 7 ++ gdbstub/meson.build | 8 +++ 14 files changed, 259 insertions(+), 160 deletions(-) create mode 100644 gdbstub/internals.h create mode 100644 gdbstub/softmmu.c create mode 100644 gdbstub/user.c diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index bf0bd1bee4..33e435d62b 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -18,5 +18,8 @@ void kvm_destroy_vcpu(CPUState *cpu); void kvm_cpu_synchronize_post_reset(CPUState *cpu); void kvm_cpu_synchronize_post_init(CPUState *cpu); void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu); +int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); +int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); +void kvm_remove_all_breakpoints(CPUState *cpu); #endif /* KVM_CPUS_H */ diff --git a/gdbstub/internals.h b/gdbstub/internals.h new file mode 100644 index 0000000000..41e2e72dbf --- /dev/null +++ b/gdbstub/internals.h @@ -0,0 +1,16 @@ +/* + * gdbstub internals + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _INTERNALS_H_ +#define _INTERNALS_H_ + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); +void gdb_breakpoint_remove_all(CPUState *cs); + +#endif /* _INTERNALS_H_ */ diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index a0572ea87a..86794ac273 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -10,6 +10,7 @@ #ifndef ACCEL_OPS_H #define ACCEL_OPS_H +#include "exec/hwaddr.h" #include "qom/object.h" #define ACCEL_OPS_SUFFIX "-ops" @@ -44,6 +45,11 @@ struct AccelOpsClass { int64_t (*get_virtual_clock)(void); int64_t (*get_elapsed_ticks)(void); + + /* gdbstub hooks */ + int (*insert_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); + int (*remove_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); + void (*remove_all_breakpoints)(CPUState *cpu); }; #endif /* ACCEL_OPS_H */ diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index b5c87d48b3..1bace3379b 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -7,6 +7,9 @@ /* register accel-specific operations */ void cpus_register_accel(const AccelOpsClass *i); +/* return registers ops */ +const AccelOpsClass *cpus_get_accel(void); + /* accel/dummy-cpus.c */ /* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index a20ad51aad..21d3f1d01e 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -254,11 +254,6 @@ int kvm_on_sigbus(int code, void *addr); void kvm_flush_coalesced_mmio_buffer(void); -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type); -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type); -void kvm_remove_all_breakpoints(CPUState *cpu); int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap); /* internal API */ diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index c4244a23c6..5c0e37514c 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -16,12 +16,14 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" #include "sysemu/cpus.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include #include "kvm-cpus.h" static void *kvm_vcpu_thread_fn(void *arg) @@ -95,6 +97,12 @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = kvm_cpu_synchronize_post_init; ops->synchronize_state = kvm_cpu_synchronize_state; ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; + +#ifdef KVM_CAP_SET_GUEST_DEBUG + ops->insert_breakpoint = kvm_insert_breakpoint; + ops->remove_breakpoint = kvm_remove_breakpoint; + ops->remove_all_breakpoints = kvm_remove_all_breakpoints; +#endif } static const TypeInfo kvm_accel_ops_type = { diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index c55938453a..b8c734fe3a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3287,8 +3287,7 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return data.err; } -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) +int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; int err; @@ -3326,8 +3325,7 @@ int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, return 0; } -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) +int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; int err; @@ -3393,26 +3391,10 @@ void kvm_remove_all_breakpoints(CPUState *cpu) #else /* !KVM_CAP_SET_GUEST_DEBUG */ -int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) +static int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) { return -EINVAL; } - -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -void kvm_remove_all_breakpoints(CPUState *cpu) -{ -} #endif /* !KVM_CAP_SET_GUEST_DEBUG */ static int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset) diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 2ac5f9c036..2d79333143 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -51,22 +51,6 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return -ENOSYS; } -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -void kvm_remove_all_breakpoints(CPUState *cpu) -{ -} - int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) { return 1; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 786d90c08f..965c2ad581 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -32,6 +32,8 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" +#include "exec/hwaddr.h" +#include "exec/gdbstub.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" @@ -91,6 +93,92 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) } } +/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ +static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) +{ + static const int xlat[] = { + [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, + [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, + [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, + }; + + CPUClass *cc = CPU_GET_CLASS(cpu); + int cputype = xlat[gdbtype]; + + if (cc->gdb_stop_before_watchpoint) { + cputype |= BP_STOP_BEFORE_ACCESS; + } + return cputype; +} + +static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { + break; + } + } + return err; + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_ACCESS: + CPU_FOREACH(cpu) { + err = cpu_watchpoint_insert(cpu, addr, len, + xlat_gdb_type(cpu, type), NULL); + if (err) { + break; + } + } + return err; + default: + return -ENOSYS; + } +} + +static int tcg_remove_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { + break; + } + } + return err; + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_ACCESS: + CPU_FOREACH(cpu) { + err = cpu_watchpoint_remove(cpu, addr, len, + xlat_gdb_type(cpu, type)); + if (err) { + break; + } + } + return err; + default: + return -ENOSYS; + } +} + +static inline void tcg_remove_all_breakpoints(CPUState *cpu) +{ + cpu_breakpoint_remove_all(cpu, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); +} + static void tcg_accel_ops_init(AccelOpsClass *ops) { if (qemu_tcg_mttcg_enabled()) { @@ -109,6 +197,10 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) ops->handle_interrupt = tcg_handle_interrupt; } } + + ops->insert_breakpoint = tcg_insert_breakpoint; + ops->remove_breakpoint = tcg_remove_breakpoint; + ops->remove_all_breakpoints = tcg_remove_all_breakpoints; } static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index a0755e6505..ff9f3f9586 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -49,8 +49,11 @@ #include "sysemu/runstate.h" #include "semihosting/semihost.h" #include "exec/exec-all.h" +#include "exec/hwaddr.h" #include "sysemu/replay.h" +#include "internals.h" + #ifdef CONFIG_USER_ONLY #define GDB_ATTACHED "0" #else @@ -1012,130 +1015,16 @@ void gdb_register_coprocessor(CPUState *cpu, } } -#ifndef CONFIG_USER_ONLY -/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ -static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) -{ - static const int xlat[] = { - [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, - [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, - [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, - }; - - CPUClass *cc = CPU_GET_CLASS(cpu); - int cputype = xlat[gdbtype]; - - if (cc->gdb_stop_before_watchpoint) { - cputype |= BP_STOP_BEFORE_ACCESS; - } - return cputype; -} -#endif - -static int gdb_breakpoint_insert(int type, target_ulong addr, target_ulong len) -{ - CPUState *cpu; - int err = 0; - - if (kvm_enabled()) { - return kvm_insert_breakpoint(gdbserver_state.c_cpu, addr, len, type); - } - - switch (type) { - case GDB_BREAKPOINT_SW: - case GDB_BREAKPOINT_HW: - CPU_FOREACH(cpu) { - err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); - if (err) { - break; - } - } - return err; -#ifndef CONFIG_USER_ONLY - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_ACCESS: - CPU_FOREACH(cpu) { - err = cpu_watchpoint_insert(cpu, addr, len, - xlat_gdb_type(cpu, type), NULL); - if (err) { - break; - } - } - return err; -#endif - default: - return -ENOSYS; - } -} - -static int gdb_breakpoint_remove(int type, target_ulong addr, target_ulong len) -{ - CPUState *cpu; - int err = 0; - - if (kvm_enabled()) { - return kvm_remove_breakpoint(gdbserver_state.c_cpu, addr, len, type); - } - - switch (type) { - case GDB_BREAKPOINT_SW: - case GDB_BREAKPOINT_HW: - CPU_FOREACH(cpu) { - err = cpu_breakpoint_remove(cpu, addr, BP_GDB); - if (err) { - break; - } - } - return err; -#ifndef CONFIG_USER_ONLY - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_ACCESS: - CPU_FOREACH(cpu) { - err = cpu_watchpoint_remove(cpu, addr, len, - xlat_gdb_type(cpu, type)); - if (err) - break; - } - return err; -#endif - default: - return -ENOSYS; - } -} - -static inline void gdb_cpu_breakpoint_remove_all(CPUState *cpu) -{ - cpu_breakpoint_remove_all(cpu, BP_GDB); -#ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(cpu, BP_GDB); -#endif -} - static void gdb_process_breakpoint_remove_all(GDBProcess *p) { CPUState *cpu = get_first_cpu_in_process(p); while (cpu) { - gdb_cpu_breakpoint_remove_all(cpu); + gdb_breakpoint_remove_all(cpu); cpu = gdb_next_cpu_in_process(cpu); } } -static void gdb_breakpoint_remove_all(void) -{ - CPUState *cpu; - - if (kvm_enabled()) { - kvm_remove_all_breakpoints(gdbserver_state.c_cpu); - return; - } - - CPU_FOREACH(cpu) { - gdb_cpu_breakpoint_remove_all(cpu); - } -} static void gdb_set_cpu_pc(target_ulong pc) { @@ -1667,7 +1556,8 @@ static void handle_insert_bp(GArray *params, void *user_ctx) return; } - res = gdb_breakpoint_insert(get_param(params, 0)->val_ul, + res = gdb_breakpoint_insert(gdbserver_state.c_cpu, + get_param(params, 0)->val_ul, get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { @@ -1690,7 +1580,8 @@ static void handle_remove_bp(GArray *params, void *user_ctx) return; } - res = gdb_breakpoint_remove(get_param(params, 0)->val_ul, + res = gdb_breakpoint_remove(gdbserver_state.c_cpu, + get_param(params, 0)->val_ul, get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { @@ -2541,7 +2432,7 @@ static void handle_target_halt(GArray *params, void *user_ctx) * because gdb is doing an initial connect and the state * should be cleaned up. */ - gdb_breakpoint_remove_all(); + gdb_breakpoint_remove_all(gdbserver_state.c_cpu); } static int gdb_handle_packet(const char *line_buf) diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c new file mode 100644 index 0000000000..4e73890379 --- /dev/null +++ b/gdbstub/softmmu.c @@ -0,0 +1,42 @@ +/* + * gdb server stub - softmmu specific bits + * + * Debug integration depends on support from the individual + * accelerators so most of this involves calling the ops helpers. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/gdbstub.h" +#include "exec/hwaddr.h" +#include "sysemu/cpus.h" +#include "internals.h" + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->insert_breakpoint) { + return ops->insert_breakpoint(cs, type, addr, len); + } + return -ENOSYS; +} + +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->remove_breakpoint) { + return ops->remove_breakpoint(cs, type, addr, len); + } + return -ENOSYS; +} + +void gdb_breakpoint_remove_all(CPUState *cs) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->remove_all_breakpoints) { + ops->remove_all_breakpoints(cs); + } +} diff --git a/gdbstub/user.c b/gdbstub/user.c new file mode 100644 index 0000000000..42652b28a7 --- /dev/null +++ b/gdbstub/user.c @@ -0,0 +1,62 @@ +/* + * gdbstub user-mode helper routines. + * + * We know for user-mode we are using TCG so we can call stuff directly. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "exec/gdbstub.h" +#include "hw/core/cpu.h" +#include "internals.h" + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { + break; + } + } + return err; + default: + /* user-mode doesn't support watchpoints */ + return -ENOSYS; + } +} + +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { + break; + } + } + return err; + default: + /* user-mode doesn't support watchpoints */ + return -ENOSYS; + } +} + +void gdb_breakpoint_remove_all(CPUState *cs) +{ + cpu_breakpoint_remove_all(cs, BP_GDB); +} diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 23b30484b2..61b27ff59d 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -617,6 +617,13 @@ void cpus_register_accel(const AccelOpsClass *ops) cpus_accel = ops; } +const AccelOpsClass *cpus_get_accel(void) +{ + /* broken if we call this early */ + assert(cpus_accel); + return cpus_accel; +} + void qemu_init_vcpu(CPUState *cpu) { MachineState *ms = MACHINE(qdev_get_machine()); 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[209.51.188.17]) by mx.google.com with ESMTPS id z18-20020ac86b92000000b0035caacf0060si7984235qts.31.2022.09.26.07.11.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 07:11:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wexBxmB/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocopm-0001Lc-TP for patch@linaro.org; Mon, 26 Sep 2022 10:11:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKb-0002UO-CM for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:33 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:42952) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKL-0005eN-3p for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:33 -0400 Received: by mail-wr1-x436.google.com with SMTP id n12so10259886wrx.9 for ; Mon, 26 Sep 2022 06:39:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=vjojPbAZCZTm66THKz2INVh3tZm0jABrqXmO5V1a0wU=; b=wexBxmB/+F7WpA4XCpQWiP1Rrs6Z3ERduhyLAQUDh/dWQohA03uXYxPG6Sirmf1gsA mRuRwsEZ3/oGSgnN4R+qSi2nFzQnxNxhc4S7TeiFDRSMgjbnELMfNp5T77vQ2RRB3sZ+ 3717+FXb3fFCqUJrBTk30MyGg5QD1aZmFE3yXxBYGMk8pXtqt0n9X+DZ3vFAJO1Gy87G y2We++AuLr472gg0N5hdAD2+xGirI3IKqFHhJI1SM7tyfdppqbcbZoBLOJTTRz2fns76 gjqOmDZckZupk5gkcMTWZ7LAeo0/+TSut/6buzQd9iZCWeqb7tcvYUc0VGUQzXlImroy 7ZLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=vjojPbAZCZTm66THKz2INVh3tZm0jABrqXmO5V1a0wU=; b=gl7OjMjqdhAhJALR8QDMMEruoJfwOiM6mH4Io8NK12aKOrUsncTL/frV9OdUGwSDoe bXA9eqNIsunSSwd9TJ4UMQOd7OweLx5oaUIkdrqgxhJZ13sQJ8eyOW77NBU/cCrrEgRd 1i4oPqMEMfOHPQnoAy9IFuByAgvNsDlyWUDFwK/FyqP6rYODG5MtRe/BA05qZPC5S1J5 yL4SvRv2f7iSrtaTlV2Ulo6wAK+SvCKa4nj2YYVt6Q5J2/L07dqSz7vk+ErDwpileY1e kqO+twsl6nt2DQIHj1eCxoMQCBr94xn5PJ45ZHVPm44XnHValNoHPi76ulGt2VfrE8B4 WY7g== X-Gm-Message-State: ACrzQf3pT7Xk9HBwDU7O/gsZauNLGXf/mDICBOTKcZHRt5JO736abuF9 6nxo9v9yXYubLWHCwakCj4HmZQ== X-Received: by 2002:a5d:5259:0:b0:22c:8c3b:31f2 with SMTP id k25-20020a5d5259000000b0022c8c3b31f2mr9207067wrc.150.1664199555021; Mon, 26 Sep 2022 06:39:15 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id m10-20020a05600c3b0a00b003b47b913901sm25520688wms.1.2022.09.26.06.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:12 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1E5BE1FFC3; Mon, 26 Sep 2022 14:39:06 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Paolo Bonzini , Richard Henderson , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v2 11/11] gdbstub: move guest debug support check to ops Date: Mon, 26 Sep 2022 14:39:04 +0100 Message-Id: <20220926133904.3297263-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes the final hard coding of kvm_enabled() in gdbstub and moves the check to an AccelOps. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Cc: Mads Ynddal --- accel/kvm/kvm-cpus.h | 1 + gdbstub/internals.h | 1 + include/sysemu/accel-ops.h | 1 + include/sysemu/kvm.h | 7 ------- accel/kvm/kvm-accel-ops.c | 1 + accel/kvm/kvm-all.c | 6 ++++++ accel/tcg/tcg-accel-ops.c | 6 ++++++ gdbstub/gdbstub.c | 5 ++--- gdbstub/softmmu.c | 9 +++++++++ gdbstub/user.c | 6 ++++++ 10 files changed, 33 insertions(+), 10 deletions(-) diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index 33e435d62b..fd63fe6a59 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -18,6 +18,7 @@ void kvm_destroy_vcpu(CPUState *cpu); void kvm_cpu_synchronize_post_reset(CPUState *cpu); void kvm_cpu_synchronize_post_init(CPUState *cpu); void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu); +bool kvm_supports_guest_debug(void); int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); void kvm_remove_all_breakpoints(CPUState *cpu); diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 41e2e72dbf..eabb0341d1 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -9,6 +9,7 @@ #ifndef _INTERNALS_H_ #define _INTERNALS_H_ +bool gdb_supports_guest_debug(void); int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); void gdb_breakpoint_remove_all(CPUState *cs); diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 86794ac273..8cc7996def 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -47,6 +47,7 @@ struct AccelOpsClass { int64_t (*get_elapsed_ticks)(void); /* gdbstub hooks */ + bool (*supports_guest_debug)(void); int (*insert_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); int (*remove_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); void (*remove_all_breakpoints)(CPUState *cpu); diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 21d3f1d01e..6e1bd01725 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -46,7 +46,6 @@ extern bool kvm_readonly_mem_allowed; extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; -extern bool kvm_has_guest_debug; #define kvm_enabled() (kvm_allowed) /** @@ -168,11 +167,6 @@ extern bool kvm_has_guest_debug; */ #define kvm_msi_devid_required() (kvm_msi_use_devid) -/* - * Does KVM support guest debugging - */ -#define kvm_supports_guest_debug() (kvm_has_guest_debug) - #else #define kvm_enabled() (0) @@ -190,7 +184,6 @@ extern bool kvm_has_guest_debug; #define kvm_direct_msi_enabled() (false) #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) -#define kvm_supports_guest_debug() (false) #endif /* CONFIG_KVM_IS_POSSIBLE */ diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 5c0e37514c..fbf4fe3497 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -99,6 +99,7 @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; #ifdef KVM_CAP_SET_GUEST_DEBUG + ops->supports_guest_debug = kvm_supports_guest_debug; ops->insert_breakpoint = kvm_insert_breakpoint; ops->remove_breakpoint = kvm_remove_breakpoint; ops->remove_all_breakpoints = kvm_remove_all_breakpoints; diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index b8c734fe3a..6ebff6e5a6 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3287,6 +3287,12 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return data.err; } +bool kvm_supports_guest_debug(void) +{ + /* probed during kvm_init() */ + return kvm_has_guest_debug; +} + int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 965c2ad581..19cbf1db3a 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -93,6 +93,11 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) } } +static bool tcg_supports_guest_debug(void) +{ + return true; +} + /* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) { @@ -198,6 +203,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) } } + ops->supports_guest_debug = tcg_supports_guest_debug; ops->insert_breakpoint = tcg_insert_breakpoint; ops->remove_breakpoint = tcg_remove_breakpoint; ops->remove_all_breakpoints = tcg_remove_all_breakpoints; diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index ff9f3f9586..be88ca0d71 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -45,7 +45,6 @@ #include "qemu/sockets.h" #include "sysemu/hw_accel.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "semihosting/semihost.h" #include "exec/exec-all.h" @@ -3447,8 +3446,8 @@ int gdbserver_start(const char *device) return -1; } - if (kvm_enabled() && !kvm_supports_guest_debug()) { - error_report("gdbstub: KVM doesn't support guest debugging"); + if (!gdb_supports_guest_debug()) { + error_report("gdbstub: current accelerator doesn't support guest debugging"); return -1; } diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 4e73890379..f208c6cf15 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -15,6 +15,15 @@ #include "sysemu/cpus.h" #include "internals.h" +bool gdb_supports_guest_debug(void) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->supports_guest_debug) { + return ops->supports_guest_debug(); + } + return false; +} + int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) { const AccelOpsClass *ops = cpus_get_accel(); diff --git a/gdbstub/user.c b/gdbstub/user.c index 42652b28a7..033e5fdd71 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -14,6 +14,12 @@ #include "hw/core/cpu.h" #include "internals.h" +bool gdb_supports_guest_debug(void) +{ + /* user-mode == TCG == supported */ + return true; +} + int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) { CPUState *cpu;