From patchwork Tue Sep 27 14:14:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609608 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp425704pvb; Tue, 27 Sep 2022 08:46:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7DgWNg1/xHVMtMVMImG9qyyf7pgz+USsOnDNbyl/ZQE3b98361LDmkUHL0pD+BxOLGRbQA X-Received: by 2002:ac8:5f0b:0:b0:35c:e719:c507 with SMTP id x11-20020ac85f0b000000b0035ce719c507mr22415599qta.611.1664293570336; Tue, 27 Sep 2022 08:46:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293570; cv=none; d=google.com; s=arc-20160816; b=OfrKPHIRHCZnmcSGtX6dxBolP+5aYby8iLHNP4RnYTgBuLEEmbMX7RXMPYLv8Ps2rL GWfOQH3zv0iVGcSzlcuKitJOn8KXqqyh1xhAWEJQ7/oaH6lyZrFS/RYy3g9NtdZE6J+1 nHH5jEFVEWVOSgOG7n7gh7/AhPtfWoN2CwGQSAgyO8S9HnBURV1LtyvBDxjlvQOYnhsh Nw1/nAqJVw4Y72NAr9AIWMDi02c13Z1NpFEfAF2367z7YDQuufKBmg7/5F5JQv8K45H1 mxaRL+HaezK9FKVzZC73zw5pBqoiQD7t1/w5yJ3z9G3vPr8+wteMzLJr9NdKBE8XBT1N s22w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gjSZ32211XyjP4AalLHKuJrm0n7lepu/2c5c9y26d4M=; b=sEqrJvSeBkyw10bSVllHWg19bwuYBxqZzG6npomvLXySibbYPm8w0/wDrsNXL07Tb4 FC1cEsNXOqHuZaOCNHrxg3iAmjahxgYGfgH4CM3tninNHctCJjAA+iLMrpJ+XMDerBx6 CoxmjcEhI1h6BZTcIyHEcGDgK7OcLOuS3jsvX9w04Z3rZtX6QnmRz/HBqVoZoZ03osPO T69VpMnSYwONts7lDvuiaSyfWcB7y/KFvHXZCrR6B/yY9/VlJtYg7ixijCW/1lpzzcr1 ttpZedzRLc0RMOiA+jizlrEjU40dmkkselj7t+/VhkrRYgwG7QRUndI4F/XuXyxTrKuR PTDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AXJ03JnS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i14-20020a05620a248e00b006ce191f4441si1457951qkn.476.2022.09.27.08.46.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:46:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AXJ03JnS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCmf-00014Y-R8 for patch@linaro.org; Tue, 27 Sep 2022 11:46:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMj-00055h-W8 for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:19 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:34458) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMb-0005yA-50 for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:13 -0400 Received: by mail-wm1-x331.google.com with SMTP id n35-20020a05600c502300b003b4924c6868so895535wmr.1 for ; Tue, 27 Sep 2022 07:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=gjSZ32211XyjP4AalLHKuJrm0n7lepu/2c5c9y26d4M=; b=AXJ03JnSBVPdEv+bEq+TA5noChnaJ/wsrqKMP/E2M6ldjjqS1sOn8lchpS9yReDe5E RrjQyKIlFB1tkwL31vpwkZA3n5U0dept2PhnWtnAecb/6vlHg4JardXV6/lmMgc5wUsi WABnwDA2J7W7tDEEnhvFI5PrUjMgNFPlsHTOJZEIecI+Bu0TwUhmjcCBb26JINxgDbOK atn77v0EMoyQ848olTFVO/Z5KJeuR1ZWS5HrSYak/gxMiVG0HfyDBEV+K9+QFaz8vq5x T9cJ4EjdZXNXKKu0wSdZeVi/wxozWXTCixGqOwXCPWLjXMjSo4wcjeVhydCJG0X6Ijto 8VBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=gjSZ32211XyjP4AalLHKuJrm0n7lepu/2c5c9y26d4M=; b=hg7Hr0h7inyTRbKHlEizw+SvsDMdcQ5lT/nZKg+P0J+xsSbTy3InlJ+zPl68w9fPL8 799s5ZpMRuy+5iqn/TgDNbBNDH1uAn76lnbiWsc7eEGuOh6S94D1Uize3TZ/jdsYwiWf or7MW2kptmqEW2WYeYN48Rbn62yAySoliFVXHYrmK+kjIDZJ+sT5ulbzufQ394AHMiQR /MCKv/2gIVU2EKHhjiJ0nIZiss4+5wr0FSkjbYwfUEnXF0GdKhE8yQdijxj6FLwbyISr qF8R6ZCgJ0pUmI+cllEFnedSSUy+n4Qaz0TKD3p8QQWJTlTiWlFnTJcrqlYGJeRLbe5Z t+YA== X-Gm-Message-State: ACrzQf2vj79drVsfji0OMuqRgiZsZMX+RlkRzdBi5yog5eW14r5lAIHX Ov1Jucur2f1w6HEgOu1zdBhcrA== X-Received: by 2002:a05:600c:1547:b0:3b4:c56b:a3a6 with SMTP id f7-20020a05600c154700b003b4c56ba3a6mr2957201wmg.29.1664288106941; Tue, 27 Sep 2022 07:15:06 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id g6-20020a5d5546000000b00228aea99efcsm1929458wrw.14.2022.09.27.07.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:05 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4445E1FFB8; Tue, 27 Sep 2022 15:15:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Peter Xu , Jason Wang , Peter Maydell Subject: [PATCH v3 01/15] hw: encode accessing CPU index in MemTxAttrs Date: Tue, 27 Sep 2022 15:14:50 +0100 Message-Id: <20220927141504.3886314-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We currently have hacks across the hw/ to reference current_cpu to work out what the current accessing CPU is. This breaks in some cases including using gdbstub to access HW state. As we have MemTxAttrs to describe details about the access lets extend it so CPU accesses can be explicitly marked. To achieve this we create a new requester_type which indicates to consumers how requester_id it to be consumed. We absorb the existing unspecified:1 bitfield into this type and also document a potential machine specific encoding which will be useful to (currently) out-of-tree extensions. There are a number of places we need to fix up including: CPU helpers directly calling address_space_*() fns models in hw/ fishing the data out of current_cpu hypervisors offloading device emulation to QEMU I'll start addressing some of these in following patches. Signed-off-by: Alex Bennée --- v2 - use separate field cpu_index - bool for requester_is_cpu v3 - switch to enum MemTxRequesterType - move helper #define to patch - revert to overloading requester_id - mention hypervisors in commit message - drop cputlb tweaks, they will move to target specific code v4 - merge unspecified:1 into MTRT_UNSPECIFIED - document a MTRT_MACHINE for more complex encoding - ensure existing users of requester_id set MTRT_PCI - ensure existing consumers of requester_id check type is MTRT_PCI - have MEMTXATTRS_CPU take CPUState * directly --- include/exec/memattrs.h | 39 +++++++++++++++++++++++++++++++-------- hw/i386/amd_iommu.c | 3 ++- hw/i386/intel_iommu.c | 2 +- hw/misc/tz-mpc.c | 2 +- hw/misc/tz-msc.c | 8 ++++---- hw/pci/pci.c | 7 ++++--- 6 files changed, 43 insertions(+), 18 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..67625c6344 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -14,6 +14,24 @@ #ifndef MEMATTRS_H #define MEMATTRS_H +/* + * Every memory transaction comes from a specific place which defines + * how requester_id should be handled. For CPU's the requester_id is + * the global cpu_index which needs further processing if you need to + * work out which socket or complex it comes from. UNSPECIFIED is the + * default for otherwise undefined MemTxAttrs. PCI indicates the + * requester_id is a PCI id. MACHINE indicates a machine specific + * encoding which needs further processing to decode into its + * constituent parts. + */ +typedef enum MemTxRequesterType { + MTRT_CPU = 0, + MTRT_UNSPECIFIED, + MTRT_PCI, + MTRT_MACHINE +} MemTxRequesterType; + + /* Every memory transaction has associated with it a set of * attributes. Some of these are generic (such as the ID of * the bus master); some are specific to a particular kind of @@ -23,12 +41,6 @@ * different semantics. */ typedef struct MemTxAttrs { - /* Bus masters which don't specify any attributes will get this - * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can - * distinguish "all attributes deliberately clear" from - * "didn't specify" if necessary. - */ - unsigned int unspecified:1; /* ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ @@ -43,7 +55,9 @@ typedef struct MemTxAttrs { * (see MEMTX_ACCESS_ERROR). */ unsigned int memory:1; - /* Requester ID (for MSI for example) */ + /* Requester type (e.g. CPU or PCI MSI) */ + MemTxRequesterType requester_type:2; + /* Requester ID */ unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; @@ -64,7 +78,16 @@ typedef struct MemTxAttrs { * (so that we can distinguish "all attributes deliberately clear" * from "didn't specify" if necessary). */ -#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) +#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) \ + { .requester_type = MTRT_UNSPECIFIED }) + +/* + * Helper for setting a basic CPU sourced transaction, it expects a + * CPUState * + */ +#define MEMTXATTRS_CPU(cs) ((MemTxAttrs) \ + {.requester_type = MTRT_CPU, \ + .requester_id = cs->cpu_index}) /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 725f69095b..8db2b6b692 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -154,6 +154,7 @@ static void amdvi_generate_msi_interrupt(AMDVIState *s) { MSIMessage msg = {}; MemTxAttrs attrs = { + .requester_type = MTRT_PCI, .requester_id = pci_requester_id(&s->pci.dev) }; @@ -1356,7 +1357,7 @@ static MemTxResult amdvi_mem_ir_write(void *opaque, hwaddr addr, trace_amdvi_mem_ir_write_req(addr, value, size); - if (!attrs.unspecified) { + if (attrs.requester_type == MTRT_PCI) { /* We have explicit Source ID */ sid = attrs.requester_id; } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 05d53a1aa9..89b9b9a3e6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3394,7 +3394,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr, from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; from.data = (uint32_t) value; - if (!attrs.unspecified) { + if (attrs.requester_type == MTRT_PCI) { /* We have explicit Source ID */ sid = attrs.requester_id; } diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index 30481e1c90..4beb5daa1a 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -461,7 +461,7 @@ static int tz_mpc_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs) * All the real during-emulation transactions from the CPU will * specify attributes. */ - return (attrs.unspecified || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_NS; + return ((attrs.requester_type == MTRT_UNSPECIFIED) || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_NS; } static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu) diff --git a/hw/misc/tz-msc.c b/hw/misc/tz-msc.c index acbe94400b..0b47972a46 100644 --- a/hw/misc/tz-msc.c +++ b/hw/misc/tz-msc.c @@ -137,11 +137,11 @@ static MemTxResult tz_msc_read(void *opaque, hwaddr addr, uint64_t *pdata, return MEMTX_OK; case MSCAllowSecure: attrs.secure = 1; - attrs.unspecified = 0; + attrs.requester_type = MTRT_CPU; break; case MSCAllowNonSecure: attrs.secure = 0; - attrs.unspecified = 0; + attrs.requester_type = MTRT_CPU; break; } @@ -179,11 +179,11 @@ static MemTxResult tz_msc_write(void *opaque, hwaddr addr, uint64_t val, return MEMTX_OK; case MSCAllowSecure: attrs.secure = 1; - attrs.unspecified = 0; + attrs.requester_type = MTRT_CPU; break; case MSCAllowNonSecure: attrs.secure = 0; - attrs.unspecified = 0; + attrs.requester_type = MTRT_CPU; break; } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..ccdd71e4ba 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -319,9 +319,10 @@ void pci_device_deassert_intx(PCIDevice *dev) static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg) { - MemTxAttrs attrs = {}; - - attrs.requester_id = pci_requester_id(dev); + MemTxAttrs attrs = { + .requester_type = MTRT_PCI, + .requester_id = pci_requester_id(dev) + }; address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, attrs, NULL); } From patchwork Tue Sep 27 14:14:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609603 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp419152pvb; Tue, 27 Sep 2022 08:34:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7RaJYVwtaOFxjUcMGckMbQ87G0A+cZPKTe9G5L0Wy17mUq2XzJKRTAGD7TLb3KSbV3JRLk X-Received: by 2002:ab0:70c8:0:b0:39f:7528:6289 with SMTP id r8-20020ab070c8000000b0039f75286289mr11473875ual.36.1664292857890; Tue, 27 Sep 2022 08:34:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664292857; cv=none; d=google.com; s=arc-20160816; b=0B+RkZAl9znOMAe8Tt6V8gp2BPNU43E+//54EiNIpfV5nKwnOcHxBxIJpquytAw0ej G7yTnX1zJoOAOAUdObXeC21YO77OLwmtI/krQN1GQBxiz8ndKDmqTSCKyHcpsE6r2Kbp wa4I+2UgSs3iPlyRekC0e4MFmeJe3L/Gr2q67ZPoXvMLJEGdMzBj9Rlzh2ms/fAzR1WE xZeUuaVBX+U4ZxL8MZeX+UJYiS8JXsyfSDf5yilw5ig92/Ws2Xvgu4fSJjLbX6iB4CYx 2uSonhg6B0hM4ne8UI2X1F6G1z9O2WTD+r6If99LQXGI0hzFSscwOLSxWbD+4bxQj4XO Rm0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kwIb/itvs3rKbwTJEqXho8uP1946GYiAG+/duWCVn30=; b=rYciftjiWyW64bAkG1AKyNuQLhrJzJnFOmxn9oWqfMLlsF9LmNyjLldgDWu5onHVXo 0CbgvOLlYSI39EvH/641CI4qcvIA/C5RSnbULmPJGfpQ8Q1+GmaYWMpP7sbtfrNiT2df 2Cv4JWBEH1F0HJ9J7WB13KxXRS9FL/m26YSwZDd5C/747FFllj9xYCw0qmI52t6EDYtR keSHgczr2lbV1OpOiJ5QVYoanxYZlFsRT9WKxLf+DHs7GntyJAppcAi/SF6x3qZfCjnL BnPYz9WyHVq7IW9cVeijdGR7C8VQIXjt/GIhrihtI4a7HHleLjINb7J4ZLjogvbMu9AT kizg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="W9SC7/+T"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s142-20020a1f9094000000b003a38e9e978bsi395251vkd.190.2022.09.27.08.34.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:34:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="W9SC7/+T"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCbB-0002I3-Ao for patch@linaro.org; Tue, 27 Sep 2022 11:34:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMe-00053z-OS for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:13 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:52114) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMc-0005zB-44 for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:12 -0400 Received: by mail-wm1-x335.google.com with SMTP id o5so6648626wms.1 for ; Tue, 27 Sep 2022 07:15:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=kwIb/itvs3rKbwTJEqXho8uP1946GYiAG+/duWCVn30=; b=W9SC7/+Tf5OCooTlzhP4Sis/4s2IihlstIcDh0P59xQeUidh5CSTHMWMDbH8stIAw1 yeHHLR5Ha4Mi1aBjzZRFlA0vV+MkztOchTrhVfvL+NjG2muHVbno3etCyyvETewjIRet c2+IQOl/hGHtn7aXE/dfxOjM2WvDBwW+Khmp24YNup5gwrstuW4Hbw08IPS1pBxEWEHW FxkvJxgzPemAcIV0szrbH7+JSsKcpaIzNY0p5y8/DiTg95sN9zW0IIJibb/xsHvbmB19 DWy3EQB3tMOE74BcDzebTxkG1wnV1vqCZhoqjs/KdLRpXmQT+ngtqWoCo5Iq6oxE24Gh 4ECQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=kwIb/itvs3rKbwTJEqXho8uP1946GYiAG+/duWCVn30=; b=VkQqegUoGlp7U0JBQwJ+fImRXSW8yPXl8Dxch4r0OWXFNqYvRl44xfqngZw4hMUKiW dZ84AQRlYuhAACvVkJvBAu1D5rWzXBMy/SfmtHYPcNl2c6YDA3UIJqVGh2YAyhJ4uaBo UYnn1wx2BbUOQvoGCZQ8XzsWUYCLPyCLPPD44oldPZ22bLljTNztfYBiUvwXxv5b/Q/m rlVp2POIpdvTAMkUz7bJ3Ie9JzZzBQIcADpWjBuWgcDRveBQ/hsYHsnqzwsZ2QPTzNoc Hl83JtJrDduii+Lq5RQHFPqVKbJ/NSbBRvcsbJoBD+jOGYxXP58SwftR0MWoqX3or4oe UIjw== X-Gm-Message-State: ACrzQf3IXSWnQShWQPhQyJDW//wAIhmPJTP7tmx7ooUY4eOTROwFx2Yk y8u352VkRm15sYR7aGo83QXDXmX9VMSBTw== X-Received: by 2002:a05:600c:1ca0:b0:3a8:41cf:a31f with SMTP id k32-20020a05600c1ca000b003a841cfa31fmr2960353wms.161.1664288108496; Tue, 27 Sep 2022 07:15:08 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id d16-20020adff850000000b0022ae59d472esm1853489wrq.112.2022.09.27.07.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:06 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 775281FFBA; Tue, 27 Sep 2022 15:15:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Subject: [PATCH v3 02/15] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Date: Tue, 27 Sep 2022 15:14:51 +0100 Message-Id: <20220927141504.3886314-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both arm_cpu_tlb_fill (for normal IO) and arm_cpu_get_phys_page_attrs_debug (for debug access) come through get_phys_addr which is setting the other memory attributes for the transaction. As these are all by definition CPU accesses we can also set the requested_type/index as appropriate. Signed-off-by: Alex Bennée --- v3 - reword commit summary --- target/arm/ptw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2ddfc028ab..4b0dc9bd14 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2289,6 +2289,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); bool is_secure = regime_is_secure(env, mmu_idx); + attrs->requester_type = MEMTXATTRS_CPU; + attrs->requester_id = env_cpu(env)->cpu_index; + if (mmu_idx != s1_mmu_idx) { /* * Call ourselves recursively to do the stage 1 and then stage 2 From patchwork Tue Sep 27 14:14:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609604 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp421376pvb; Tue, 27 Sep 2022 08:38:00 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5lxuBRY0bQ0nfaKzH0uiDuE3REe20WSQxJvRtEp2BLo2D9wws/DVBkdD+fddBiVpNZRdSu X-Received: by 2002:a05:6214:29c2:b0:4ad:68be:8c57 with SMTP id gh2-20020a05621429c200b004ad68be8c57mr22143398qvb.3.1664293080783; Tue, 27 Sep 2022 08:38:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293080; cv=none; d=google.com; s=arc-20160816; b=xxEsDfhg4qubAIH9KuQOC3N7fIHCOPCE4811tfK6vC4+YGY93DjxAfyG2iE5PDA50+ 0YyoObivSTSwnj1SDijDE+z1C+hOrhhRbNR4aiBrx82q0zQLS5OVEAxLoOx6FN298MCF XIc35CFVMgrD00ajDeDh7ZuROw+9jP4a+QpLtMbK8U2KCJCW36HNEEg/GskuovTyzMV3 YqsiNLZHtW544kfnhw7gcZgvMNYe1b9/TjfNOwrN8KaA8c/EtfOXb4St/9ZfcVSaN/sO +8ClGJAXObUroQDffgE7WsGwg0EwbhdbQv9YYsXdZikXihEOS3IADnbrBsez0zh6PsJ9 nC1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tuxNv9/88S7ezaeS7QVX6RVgPFquMHRDAzKT6wAF58Q=; b=hjZwsWAbuHXK37koiCRU65nLHtT4gAwy2MJCkg1/88Df4pQ8mkuC37EmCuvH92Ytk+ HBEb4p5wO1QAn3kOU/OUpvuSJORxJF1MNaZsUEapmPPrYeTUqyBpdaHoBX+cqDFlbjd8 SOQ/LyNN/dQXYL4NcbRCCV9qm2hfo/zULMZDrkHFmNR5EUYDLas4XjBkMuT5ggk5wsQ6 bCltGIolx+xyROOzHPiIWwLN2/1Cwl9tVsYPvNVKBjKPwfvsNh9ag+N/J7JYlgygGdq4 6f/2b4AjNFyDapkLBTVUXlfb8LnPdbndR3q2NbneojqeDeZyTNRoJHYOSwfiUUk/HPmQ vipw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="TU/IHbgs"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c9-20020ac80549000000b0035bb73fa23esi1051953qth.363.2022.09.27.08.38.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:38:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="TU/IHbgs"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40052 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCem-0007Ey-7M for patch@linaro.org; Tue, 27 Sep 2022 11:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMe-00053y-OH for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:13 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMb-0005yp-N5 for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:12 -0400 Received: by mail-wr1-x42d.google.com with SMTP id x18so15215703wrm.7 for ; Tue, 27 Sep 2022 07:15:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=tuxNv9/88S7ezaeS7QVX6RVgPFquMHRDAzKT6wAF58Q=; b=TU/IHbgsBWvhI/LiwObqBNrJ635QK32n5ZKe0vWT486YUFn3wClp0UI68x8IpSuq3A T1SYm6oLvS2GKcYVQ1Ubm1MGn27HOlxfz4xxGUO72N76tuKBv3oL9ycNs+gG3OTO2PC6 2J94kplvKI6gjfqci5btZav6f3CooHxcd5QSu+1ar3y9G6JGQIzLPn2jWAju6/Bp1dPh bP8S7j36zl5Ksh61EEExHEG2NezJNosmr/cXF8+wircmAM9DVV7h5OOH7iL3Gsb/IP1V IHiGUDMgWAU/W5HX2IAybtTe0hAniuPHR7LfJ7/X9OVC7lVz2KB0BZ6hz4QeqJq4eiHf /xzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=tuxNv9/88S7ezaeS7QVX6RVgPFquMHRDAzKT6wAF58Q=; b=caCX2UuNFNJAhGn/t1xFHrHDBdETSjMFb1Lg4PyE00nFSAmZLMRu5bexgXyBqq4Zhk EPN1Iet6Aq5TG6FOEfFMiYegKTwSvSIFElbK+kqpID8po57wWGePhKmZnQQ2jUj2dD/c +J8SgYl1J3BkpLdk1GCF1Bq1VTgwEzjzCkBOML12KJC8uONe9HcZhkK1GwG0U+AkNe4b M4p5ioqhON2tAcJyzDoBhb5fa2ervQy9GZ1Ee3GzcEbRPWNXcbshc6ldxAoGWZfa/mLw l1FI/gdPs4hSHWkyjRVB49yz8LhH/WVVhpVdbuedg6WaYE2bX/D773mgTnoPYbyrExEO ymPQ== X-Gm-Message-State: ACrzQf12k26/FQxC68XKk3dVARqPQb1cGFTP3GG2FFdcyGUqYur2aFQU JFhgaPWE11xASxfRRcgY0Blv8A== X-Received: by 2002:adf:f18d:0:b0:228:9f0a:f291 with SMTP id h13-20020adff18d000000b002289f0af291mr18117532wro.252.1664288107948; Tue, 27 Sep 2022 07:15:07 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id p2-20020adfce02000000b00226dba960b4sm1983711wrn.3.2022.09.27.07.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:06 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9F8E71FFBB; Tue, 27 Sep 2022 15:15:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Alexander Graf , Mads Ynddal , Peter Maydell Subject: [PATCH v3 03/15] target/arm: ensure HVF traps set appropriate MemTxAttrs Date: Tue, 27 Sep 2022 15:14:52 +0100 Message-Id: <20220927141504.3886314-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As most HVF devices are done purely in software we need to make sure we properly encode the source CPU in MemTxAttrs. This will allow the device emulations to use those attributes rather than relying on current_cpu (although current_cpu will still be correct in this case). Acked-by: Alexander Graf Signed-off-by: Alex Bennée Cc: Mads Ynddal Reviewed-by: Richard Henderson Reviewed-by: Mads Ynddal --- v2 - update MEMTXATTRS macro --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 060aa0ccf4..d81fbbb2df 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1233,11 +1233,11 @@ int hvf_vcpu_exec(CPUState *cpu) val = hvf_get_reg(cpu, srt); address_space_write(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu), &val, len); } else { address_space_read(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu), &val, len); hvf_set_reg(cpu, srt, val); } From patchwork Tue Sep 27 14:14:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609605 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp421893pvb; Tue, 27 Sep 2022 08:39:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6QrJUF0tZvLs5gVhJxpv4RuP0/KBhjaW1eqom4AaffFCl/Xqll6yj8EWn0OG6vgBZ8Q9IF X-Received: by 2002:a05:6214:2345:b0:473:a82c:34eb with SMTP id hu5-20020a056214234500b00473a82c34ebmr22172300qvb.9.1664293144625; Tue, 27 Sep 2022 08:39:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293144; cv=none; d=google.com; s=arc-20160816; b=qZGmVlOrCUUYLV5rIN1a5bigcMj7Ka0Iue20KSTVl2YOC8zMHPU+EId7k4fGGZoKfL vlAw9W2ydzRYnECQ5hVGkTmaPoTO4SqYC2ct2hhKcPJjo8W4OOVtL1W0QL+l/tC/f47p D5uSI6JOpONpCzf+OeVZOYhOJ3/PM4YaiTCs14ej04lwNxwhEeCoIHGhsBZKs5KByB30 oncJX7MAtAzoMF3ICljtbAhrGQRgnPqJWSRNk7+q2Sb3pDU89F0WbPJOWMLtwgl6Tgxw cTVvLcZkXp86+jxwNBwEEE+V5owCGD/LU+2GYqJbEIIcnJw8E97rfhrSPj4ovYZ2tu4Z qRfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jinC1E8FBpCtwExy5oEB2wbtRevFZPQmAbFk5PB8kRY=; b=F4sbJKWZe0i8eaVOD51WEW0QYkHbdZCLSNqI1O0Xf3DZPfx8v5mJbPAqCcvPeWxKAe jIxEmcFcmgaOdCVRapMKYySO7FL06Ukv7ikmPL7z/VlqSx0KQqdQdKZZeZfiRzZ2E+kb 3brGw+fkCzY1auK+AMi86BegMl3NgDVhvnoru3iYTAMBfRV5eCInON3eTnrgkFjVwCau xoCdh0HWEbrZe9HyJRToWbvNuroJbxd4mwIlKb455nIZ3lYPW7S5jtdSch595HoAO3Rd yzQG9YTV7m+KAs9oxUqcDazy59HaDwY4vFeB9ic72XzN1Qf7xrt5KYA+Wz3bbstmLlZA +Igw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gLTcB6Cz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id fw8-20020a056214238800b0049ab8c6d74csi1149771qvb.296.2022.09.27.08.39.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:39:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gLTcB6Cz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCfo-0000mb-5O for patch@linaro.org; Tue, 27 Sep 2022 11:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMj-00055e-VS for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:19 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:43895) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMc-0005zh-IS for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:13 -0400 Received: by mail-wm1-x329.google.com with SMTP id r3-20020a05600c35c300b003b4b5f6c6bdso5526688wmq.2 for ; Tue, 27 Sep 2022 07:15:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=jinC1E8FBpCtwExy5oEB2wbtRevFZPQmAbFk5PB8kRY=; b=gLTcB6Czzx3VJdWGNqcAsFy6R1+SJ8DAs8+LrUAwxlvZ0DQRJYm4UzukgAUx3G804/ It5yr7e/JoxhrUch8KFQtTMV7w2oU5fyLZFtVelUWvw2gYJzt9nQRyho2BZ/2saA746y MQqesr8JPIRTmb2pB5lF0RJTrWI9suoghsWm6lxBCCznI+NUS5jwQTXbfP77UV/yTRsI +whj2hNU//YRUfHnwev5F6s1+KdDn3hJ2clhvk0bagJOq5mjG30gXxZl0THdon8WmTnu rnDm4iB/ayxzF8RJfIVFbgDakhp1KgGVaSylSdQMHTJ06wcxYjQlGtg+eMwX/w1mowAU ak7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=jinC1E8FBpCtwExy5oEB2wbtRevFZPQmAbFk5PB8kRY=; b=hWtU0Gf/2TQw9pO88QiRYZQjwoe3p0TdF+iCYp6f2pFGTzSbkFuYQKWNwOa+7ZwhC8 NrbC0xPuyd4ezdVVz1NFkDmAQWFhrC9+xDkZWPKxrsOKVekjABhzpCA5BpVkLDoZDVbK 4VcOovf4g02VqkBlaR7nAAB9a+Jz/taDu5MidHjXDzvfVCNEbaDWmqGH37xfVdko+6eo CYC6lt4KBMy9oLVOzn4ocdQpc9mtmMG1/4DAifDJNR2ErC+MF4ReixR/DYmEi1bPcwAN YGnoL7zdLevdZPglbXQcKQEhRI/xNDCiVgWVKHgyyH6xSh1r+r1SLvugZD8K9+VGi+c2 8sqw== X-Gm-Message-State: ACrzQf0NzypCGyTM99Q0C/ljLwqm+sqzaJOlCmmx4KeIEHk56dYi4nMA rWePRoUE4GIrEciRC+2nTP+3Hg== X-Received: by 2002:a05:600c:34d2:b0:3b4:a617:f3b9 with SMTP id d18-20020a05600c34d200b003b4a617f3b9mr2846431wmq.204.1664288109247; Tue, 27 Sep 2022 07:15:09 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id az19-20020a05600c601300b003a83ca67f73sm2107341wmb.3.2022.09.27.07.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:07 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DAF1D1FFBC; Tue, 27 Sep 2022 15:15:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v3 04/15] target/arm: ensure KVM traps set appropriate MemTxAttrs Date: Tue, 27 Sep 2022 15:14:53 +0100 Message-Id: <20220927141504.3886314-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Although most KVM users will use the in-kernel GIC emulation it is perfectly possible not to. In this case we need to ensure the MemTxAttrs are correctly populated so the GIC can divine the source CPU of the operation. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- v3 - new for v3 --- target/arm/kvm.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e5c1bd50d2..05056562f4 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -801,13 +801,14 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) { ARMCPU *cpu; uint32_t switched_level; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); if (kvm_irqchip_in_kernel()) { /* * We only need to sync timer states with user-space interrupt * controllers, so return early and save cycles if we don't. */ - return MEMTXATTRS_UNSPECIFIED; + return attrs; } cpu = ARM_CPU(cs); @@ -848,7 +849,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) qemu_mutex_unlock_iothread(); } - return MEMTXATTRS_UNSPECIFIED; + return attrs; } void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) @@ -1003,6 +1004,10 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, hwaddr xlat, len, doorbell_gpa; MemoryRegionSection mrs; MemoryRegion *mr; + MemTxAttrs attrs = { + .requester_type = MTRT_PCI, + .requester_id = pci_requester_id(dev) + }; if (as == &address_space_memory) { return 0; @@ -1012,8 +1017,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, RCU_READ_LOCK_GUARD(); - mr = address_space_translate(as, address, &xlat, &len, true, - MEMTXATTRS_UNSPECIFIED); + mr = address_space_translate(as, address, &xlat, &len, true, attrs); if (!mr) { return 1; From patchwork Tue Sep 27 14:14:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609611 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp429360pvb; Tue, 27 Sep 2022 08:53:07 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5c293Dsa7xyEE+85fIK5hqylSOmSESCAe3+QC2P2C/8oCGT4ldzu13csxAP+pH3Ox1JyPN X-Received: by 2002:a0c:dd14:0:b0:4ac:9789:825b with SMTP id u20-20020a0cdd14000000b004ac9789825bmr22321824qvk.122.1664293987273; Tue, 27 Sep 2022 08:53:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293987; cv=none; d=google.com; s=arc-20160816; b=DC3oNid2evbULAicEVJ73/PvXFAw9D5VvwKkpfJ/0xhHYCIxvyXvXVLmCobEVpN0rm fJv3IMkc+gOwPNjYL6ggeRvr4hlA7csZp2pRTzZOkHwOVcplWAozIK0pZ2dalnZCCjg4 cZnBmenRVOi9/Rc37SLmR4U86dr2by0a8K0WpQI49i2k0C69/wqNyfLlTDSEcj4HvhOF Cl2HtcwjVcX1VcCpd5/bcbrYIUbQyl0bYilzWcRY1ubHrircEjBzWogkVdDrSMejwnkS UtzCzioefdNblP9HdAaaDzpzxhgigyOnNmYigWHsXHMtkEiOADdDV6j0LQdpljp+vvCM SYDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cGbCxNKhFGQVcMMapIUG9BPWHYHoG4uT47TtDyR3AMU=; b=V2qYSJ+7+uMI62pBa5qlypvpYYFUlnVqjvXFFjGNFtzl9vcTCDRyXT0PcMmXV34fjP BV71LoWnXw3KbOLPd7oCVdUtZXbDNF1MzEvaTKNFYoMBUEA2c65MgvZ7OSePADgDvX2T 7V4CwJAKNQhPSP1adkCMbhHPkA2ikoSK1KmyJKkJCU00ppclNv1GaHFDR/c0WyvIYI4i dxGWMia+uMaqHD6Yr5qu1zg3kAI9WutwL+2udOZdVJtKPlVU4zaqVkhnpzGdNPI3NllU eLzuZv9R3TIe4kjqqIcvgSlrjkkiZyWQ3QSC4x3vpW0RGJn2kCks8yPKgY6L31uTQo2T a++A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lsws4lrn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id kk3-20020a056214508300b004ac81b27beesi1145793qvb.316.2022.09.27.08.53.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:53:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lsws4lrn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48176 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCtO-0007kL-Qk for patch@linaro.org; Tue, 27 Sep 2022 11:53:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMj-00055f-VW for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:19 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:42766) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMe-00060a-DV for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:15 -0400 Received: by mail-wm1-x330.google.com with SMTP id o20-20020a05600c4fd400b003b4a516c479so5530209wmq.1 for ; Tue, 27 Sep 2022 07:15:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=cGbCxNKhFGQVcMMapIUG9BPWHYHoG4uT47TtDyR3AMU=; b=Lsws4lrnM+tr6CCFMECW5Fw8QApKP6w4FaUF0O/elr7wEd9ipxsmhJTvf2Em2VLjaa 0SV1SBYW5pIoMWVUmS1n9vPUtD0lMhEwJDn5PCQVztSjkPq2EEHzwVy0mb4636ZXRJYD kVffjTsP4fLvOPXgAnkVFqZfoB/FgbMgWoFoBWuOII1RrIm0yfZOAI+RuOB7tIDCilL7 bX95Nm47Jhv3YYOz+10BkaTfKrkbbLfM1bQiQ2VaAc0iqJkvZP/Rgosr51uyT0hhVurK 2RoSpadlHRJtxt26nfUR6YbJhFddOUEIPuP5Cx+K/Ki7MUhUmPVw2auXTNycZJtXjxtT qeXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=cGbCxNKhFGQVcMMapIUG9BPWHYHoG4uT47TtDyR3AMU=; b=c7bVa/RbLej//BuNznJYzJexg4pl9qy3EkVvYsP1Qe0RtJVaBRRSGmSu/i7mmt+xlK 9TO+3EDVLdVPuXyYnlvAOT7sWwt04jIhbBjuH3bNtdB5AFUXwe8pVsOFHwXdCctsEl1K D4kVxhKhe8wc4P2vBDEPVHLRHtEfwMv+jJjiJKqZCtBEB+ceZsQQqLc+5M4hX/imLnhl tJ4eDH51burRUIC0dbnGctQnelAUFdzRvvL/e7QyLbvzEcGphcgdyICCJIKxtiTQpD6R JxbTNX8lNB+VgEZQkpcygvEEat8SCdvdLOeh1bi76JSPyxNO544H0fnjxQpkXtoYebx4 cu5A== X-Gm-Message-State: ACrzQf0vsKYQi6NLy+GpH1suINcbEVHLVtUnfF9im0Y5mgLrNF8WAqBh oZwfGVbrnGJD7j0t52SKDfO30Q== X-Received: by 2002:a05:600c:3585:b0:3b4:a308:1581 with SMTP id p5-20020a05600c358500b003b4a3081581mr2968645wmq.77.1664288111021; Tue, 27 Sep 2022 07:15:11 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id bj7-20020a0560001e0700b00228d183f9c2sm1824946wrb.89.2022.09.27.07.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:09 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 11D511FFBD; Tue, 27 Sep 2022 15:15:06 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Subject: [PATCH v3 05/15] target/arm: ensure ptw accesses set appropriate MemTxAttrs Date: Tue, 27 Sep 2022 15:14:54 +0100 Message-Id: <20220927141504.3886314-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While mapping your page table base to the GICs address space would be an "interesting" design choice the resultant loads would still be CPU initiated so should be tagged as such. Signed-off-by: Alex Bennée --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4b0dc9bd14..62d32d660a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -252,7 +252,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); MemTxResult result = MEMTX_OK; AddressSpace *as; uint32_t data; @@ -280,7 +280,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); MemTxResult result = MEMTX_OK; AddressSpace *as; uint64_t data; @@ -2289,8 +2289,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); bool is_secure = regime_is_secure(env, mmu_idx); - attrs->requester_type = MEMTXATTRS_CPU; - attrs->requester_id = env_cpu(env)->cpu_index; + result->attrs.requester_type = MTRT_CPU; + result->attrs.requester_id = env_cpu(env)->cpu_index; if (mmu_idx != s1_mmu_idx) { /* From patchwork Tue Sep 27 14:14:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609607 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp424017pvb; Tue, 27 Sep 2022 08:43:19 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7D7M/r9Z4HD/PYHBVbVK9ZzyO3HADWG8HIn4zCSDg3u+YRq77LJi/TaXIyWlsN/Mk5WvUZ X-Received: by 2002:a05:620a:400e:b0:6ce:bec8:473d with SMTP id h14-20020a05620a400e00b006cebec8473dmr18181278qko.745.1664293398918; Tue, 27 Sep 2022 08:43:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293398; cv=none; d=google.com; s=arc-20160816; b=owpTyhKiv+g/3sArJQsiGHSNKGRHpwTGVDluxM6ZcPJVXWq7+hvQme9tork/d9Zgx1 Lh0MAnKvIkE+PDf3UZychTssFTet2rH6ILXQXEO9csZNI4CdBkhBXSwdRX4LPph2IcPH GtkKdAQRpa3KYT4jLgreZmnR7zAiNlAuWTBlHqBxxaHQ86Z3J+0IzOSYc34X3mMxgXZs nUuDtTwgFA8eszGjg290uFFHZqAnB3JuZ9J6OHgdOsO6L+K2pG1Z8VBSnK+uiT57c6nt kTJlBIiLxGurMn77HaQ/ZrM8AfMQESiq87VF3d2JI98i1FJutTy/zbV1r5pkyaGnlSdy A3Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ypkcIc7MqpzsX3cZua0u7P07Gz67TZaVkdDsCvohyYQ=; b=y3ws5kMeVEURNnPxdbQdGGFmMMECp9L1Nwg6MwuLC1WtlrWVDYx0nA+QdmmRJxTy0u LT9Wz9KqklNflNcd0wnYfcYEHPOJiqCKlZINO/R0tOIAa+zu7msCIM/iuoNmH/UkvdSh hmepifRjZ9TdrjOPVoLOikJwrA/kIHQp80CsMp7eWt2fWsgYHnAkMonklbmSm5+2inko LXBtGwHthAvN9BmnHbFTFjz4IaSlF7p++/XhbNZURcdt5lRJsLhoozU1SGAxw69EOXeb PZRsOw9buKxUJB7Q6lBG3ew7EGB+cRLZMqvK6sS+AMHXt6os/cPQ0x69cCI4NDlpe3TK 5sGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PukeLICF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x4-20020ae9e904000000b006c9cefca940si936142qkf.346.2022.09.27.08.43.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:43:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PukeLICF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCju-0006fn-Bj for patch@linaro.org; Tue, 27 Sep 2022 11:43:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMm-00057A-Bq for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:20 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:44841) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMf-00060k-G8 for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:19 -0400 Received: by mail-wr1-x432.google.com with SMTP id c11so15184183wrp.11 for ; Tue, 27 Sep 2022 07:15:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ypkcIc7MqpzsX3cZua0u7P07Gz67TZaVkdDsCvohyYQ=; b=PukeLICFUkolcbzy8hAIXWne70lu2acOfjrhiqJjX6VDtlXlxhK1P9n8v353nnMryg cFQKinkFEcFTHfSGV82ClTtFUJIIIbejRofk9Su99O2SuQv8Y+J6NjIbCplZK5ouVtGY I0gLwt1CNYtsXQ6pliSskk8lsXIFIcoHXgdI6GFRYHAa4Jb5xN8t6Ne/kbC1pmC4lOnV tUo5RijT4Uef0eGuUom/+OVBgxGQM5t47mhmcT2qa6Px/XNQyf8QmVdd4+uAy0jmVTZB cN57f5xmOYiGkXt86/xHbNjFIgZscjEtQKDgO4kOHUSrMk02X8DOlEgWj3YeFQQz0UVD h/Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ypkcIc7MqpzsX3cZua0u7P07Gz67TZaVkdDsCvohyYQ=; b=izlseDwPlsrqLFPlS1e/16oWRUsL6khRZwOpCWbbYVJlcv1R9fiqaG4SFEOmS5UNpu bZp9Bz0UqpJXtKNHe2SczOxDxYzwYxr0pflzreTuuK2RAEvmEr8KPhJYTd27kRiya4sg qKdAb0zb/BCYOxiwvVMSbVwuLzIgE5QPrfe+NW30/15uBBz3tQ+v52Bf5k5tXptwULko QtZAPQyUDtnjVSpEWZAnn4yviwYF7x1Y7nPz8A6ZUiEf4MbxDoSgYStU4fGhuG/eL96l 7+UdjGMHSTqMio936EQKOwnX+lvcR6jyD3pewyITqRbW7TvIYY+rO3nPHqrSgXhqZtBS bJmQ== X-Gm-Message-State: ACrzQf3skzPBvI3Zeto6KiqRv5qcRVGX7PcmRxHdu0gnYDYDmgFCxHWu 7wZ36PRIaHVHK3+UDbNjy9SBMg== X-Received: by 2002:a05:6000:1689:b0:22a:a66d:1f37 with SMTP id y9-20020a056000168900b0022aa66d1f37mr17118191wrd.197.1664288111487; Tue, 27 Sep 2022 07:15:11 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id j7-20020a5d4527000000b0022af5e36981sm2311832wra.9.2022.09.27.07.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:09 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3D4211FFBE; Tue, 27 Sep 2022 15:15:06 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Subject: [PATCH v3 06/15] target/arm: ensure m-profile helpers set appropriate MemTxAttrs Date: Tue, 27 Sep 2022 15:14:55 +0100 Message-Id: <20220927141504.3886314-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are a number of helpers for M-profile that deal with CPU initiated access to the vector and stack areas. While it is unlikely these coincided with memory mapped IO devices it is not inconceivable. Embedded targets tend to attract all sorts of interesting code and for completeness we should tag the transaction appropriately. Signed-off-by: Alex Bennée --- target/arm/m_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 5ee4ee15b3..d244e9c1c5 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -184,7 +184,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult txres; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; bool secure = mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -272,7 +272,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult txres; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; bool secure = mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -665,7 +665,7 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, MemTxResult result; uint32_t addr = env->v7m.vecbase[targets_secure] + exc * 4; uint32_t vector_entry; - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); ARMMMUIdx mmu_idx; bool exc_secure; @@ -1999,7 +1999,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; V8M_SAttributes sattrs = {}; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; MemTxResult txres; @@ -2048,7 +2048,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult txres; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; uint32_t value; @@ -2806,7 +2806,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) != 0 || alt) { - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .attrs = MEMTXATTRS_CPU(env_cpu(env)) }; ARMMMUFaultInfo fi = {}; /* We can ignore the return value as prot is always set */ From patchwork Tue Sep 27 14:14:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609606 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp423307pvb; Tue, 27 Sep 2022 08:41:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5u92FV/Lqnu/DvHvmJBrp1NZWXY/nS4fQtST1w47Eb33g8GiCkXr/bFgk++EJrZNEVSh+g X-Received: by 2002:ad4:4ea2:0:b0:4ad:3423:cab with SMTP id ed2-20020ad44ea2000000b004ad34230cabmr22253765qvb.32.1664293311565; Tue, 27 Sep 2022 08:41:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293311; cv=none; d=google.com; s=arc-20160816; b=R10+Hw7uZfUjWpt1T7X7ohjFUb7D+VFE8T9pKpvFw4soAHt6tmbxp4lnsV0qslYGMz kvs1sCYypHgM9hLMIdhXPlRRGzw7p9org1khnhj3OBmtNCt+ZCHHLiNyQe3MuWB8LLjt dEAAQmkEcfRZZLsO/e2lY1phu2B5J8slXhYtBwvUaRvWpKN/UrlrtCv5A+5oEpKZbYJW jy3He1/Pi/8ay9Np3vAq3KhB5E2ayzdyZoUu5ZtHnZW9vnQmpgYPJaXiZI7WGfX9OS8N IID6Cl6y2tvEtyDxJydKligL+thrLVZyz8l/EPBibDZoshAahtlGU8W2sr37hS91SGtj tQOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zdiXkimx6yrJ4O6i51JAC+sskNh3W/xe5mevtbdNW+o=; b=FqPWQKE45MU7uXlE5mLPRI1gmVqxSdmXlH5vQJAwcAEMJQ5X4R9+uItN0S/yfKrHbZ C0Oe37C2GB9N/mcinfqstVuvUXIAjoIZHdMvIY+5kByZu/EhQyYO9oTKSd7bupJdw77v UaC5zafGeBr4eHW5WBPwXyCM5J6NrfNXgovHPJwggwR80Xs4FBoJzf1MkY9NyUY5Y5UF iDSWsxf14LzSQs9vDGDNn/TOfQobnSsVQARQp03e/n2HemxkSDZt+C7kRG7ESiWAvJKh FKNkUpM4/vSXANjTRDxGNbQgdKWgm5agUQ3iQu6tyaVfPZ+7MBPiH4hmUiffAw3EPhOZ Q/8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LePijOWU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s16-20020a05622a1a9000b0035badeedde0si1406376qtc.524.2022.09.27.08.41.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:41:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LePijOWU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCiU-0005AG-T1 for patch@linaro.org; Tue, 27 Sep 2022 11:41:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMl-00055t-MX for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:19 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:53051) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMf-0005y0-En for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:18 -0400 Received: by mail-wm1-x332.google.com with SMTP id l8so6632993wmi.2 for ; Tue, 27 Sep 2022 07:15:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=zdiXkimx6yrJ4O6i51JAC+sskNh3W/xe5mevtbdNW+o=; b=LePijOWUPexf3+OU1xXnquCjeWfd63FHeBihImHGiYuB4AMAjmBGhT8W08qy4PHLel d4JKYK93UY7jJfeAXiGF82Uq3MeIZ//zrXXhdPHJKFnNork1QDDzrikzeJdtUk+zteeq IS+ZspLabI7ogNU0enuXdeb5rqBdLHPvZIm4TYdHAKzwqUrox8zPHzAboZPw+0DlOXQS 1KpxObQXCLyst+3FEwHGjqQrtNvUWHLaaIzyCFta5QlqFwUqFLjfPLqDUVU+H4mps9rX IaqvM+pRrLxy3Hkq7POu7XtPDHcTQgQPTkSw1LyHelsNscANXGVYmL18CpGrK/beB9q6 K7QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=zdiXkimx6yrJ4O6i51JAC+sskNh3W/xe5mevtbdNW+o=; b=pVZNH05DAj68WKQG6LJnu2p3RBGAyWjh0tHFAEgoSkMboIKS88QfiKEzneCddKz3Ca r6MIxNLylwz4RPkA6EZ+O+tSYLuwmPlRb1Zc+LPcMar6u0bliSbcHO2MRXKEmNX3tzPM w2DBqGmwVirdgH6vx+h9KFqlgJC32Mwd6o7FdmCQU1RZvia6BuRJxYgV20J+A0pyml3d fqKAK1fjaUCuLNDc3KCwJr7cvVdrtWqPEyABK+eGImLbgcaO9CgDMecIPP5btA0yKqNe 85PUON/J7OX0vYMj5i5ZCWhsdKF5aJuWPYmnuLDjwv+duoPN/Bkh7vBUkEtPpqTZsxOP REXQ== X-Gm-Message-State: ACrzQf2GviKo4ueYB5SXNqnaC5TSP64iFR3rcNk7qqCZiIBM1OXUFe7H fODmDymCZKkHXMRbRUrm0GalWA== X-Received: by 2002:a05:600c:3511:b0:3b4:bb85:f1dd with SMTP id h17-20020a05600c351100b003b4bb85f1ddmr2991289wmq.42.1664288112703; Tue, 27 Sep 2022 07:15:12 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id d6-20020a05600c34c600b003b49ab8ff53sm1978578wmq.8.2022.09.27.07.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:09 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6508B1FFBF; Tue, 27 Sep 2022 15:15:06 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PATCH v3 07/15] qtest: make read/write operation appear to be from CPU Date: Tue, 27 Sep 2022 15:14:56 +0100 Message-Id: <20220927141504.3886314-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The point of qtest is to simulate how running code might interact with the system. However because it's not a real system we have places in the code which especially handle check qtest_enabled() before referencing current_cpu. Now we can encode these details in the MemTxAttrs lets do that so we can start removing them. Acked-by: Thomas Huth Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - use a common macro instead of specific MEMTXATTRS_QTEST v3 - macro moved to earlier patch --- softmmu/qtest.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index f8acef2628..7d29d54a4c 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][5] == 'b') { uint8_t data = value; - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 1); } else if (words[0][5] == 'w') { uint16_t data = value; tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 2); } else if (words[0][5] == 'l') { uint32_t data = value; tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 4); } else if (words[0][5] == 'q') { uint64_t data = value; tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 8); } qtest_send_prefix(chr); @@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][4] == 'b') { uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 1); value = data; } else if (words[0][4] == 'w') { uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 2); value = tswap16(data); } else if (words[0][4] == 'l') { uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 4); value = tswap32(data); } else if (words[0][4] == 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &value, 8); tswap64s(&value); } @@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(len); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); enc = g_malloc(2 * len + 1); @@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(ret == 0); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); b64_data = g_base64_encode(data, len); qtest_send_prefix(chr); @@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) data[i] = 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); g_free(data); @@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (len) { data = g_malloc(len); memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); g_free(data); } @@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) out_len = MIN(out_len, len); } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); qtest_send_prefix(chr); From patchwork Tue Sep 27 14:14:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609614 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp430971pvb; Tue, 27 Sep 2022 08:56:25 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6SLXmQvWC13eqyuu6/0WbB8S2mE5V/4MlDk8c/okEha3dj2OgQQ/mmwhLmf3Hty2wTPEsi X-Received: by 2002:a05:622a:4204:b0:35c:ddac:9896 with SMTP id cp4-20020a05622a420400b0035cddac9896mr23601166qtb.478.1664294185765; Tue, 27 Sep 2022 08:56:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664294185; cv=none; d=google.com; s=arc-20160816; b=BhW5RVn7MGbdQ0GkLNu9pdDBKe6elSUsfzEAEdge0YcSEUYKAE0VLMxWncXMo6P8VQ HyYFbg5q5vUHHTtQNKDXvfaiBMfoS9bCULG4rRdFFOF/CGt3UifhekrFrxOExokGh4Mh S8idbR2/aS4mkUmFsWvjuj9Gv5SjcuqWVVKngsBwhzTC0MdBAny+4t2ZhHvVqXF2mu5L CUtaMikY9a5vq/zw8sXk7eghCY94ydxP1ZolwBOav0TExwFeSzmp906p3BWewS/iwBOy RjbhN9bRen5yheI67/bYeqtkVdDC9HZKTZjEuIkg9NjZ7Y4YlSNsmoARZqYBv4/0VcRV sP7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=r0tBXvF/ifeoq8b5qrcFwHoN4i2ZgT7ReFA291oacHo=; b=Q3MYWUt6hpQIBxmaKNlyLCkqP8LVGEWQfdgpyEkdIj3PV/vKyC+zb+k79uOAXE9i/U 9MSTbA0PYdV5FTplAjqddL+QzvUwrxg54iPMSHqxqbZxSnA53Xd7JVCSlwxQ31QZSGvl PZD4U9k2NzNqTMVzSkzQyoDUcOTtMg8vn/kIVdrKqTHNstlv23IPnOyLaWw/AQ7OH0bi /XrVN0L/DE1+xoGTr6m4DGz+sV0r9YqeLSivrgkWYdJdVDH9HT2uoUJtk4i1+vEqt46M tf2lmrcTwYD/DKBe1+zirIlwguczIh9MAs+X03pXCNxpVV8GhdEfgVB/axE7Q4dAzhtX BFkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kv34vR1c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ge10-20020a05621427ca00b004738ba79f81si1292347qvb.300.2022.09.27.08.56.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:56:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kv34vR1c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCwb-0005Mb-98 for patch@linaro.org; Tue, 27 Sep 2022 11:56:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMm-000595-PO for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:20 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:54962) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMf-0005y9-Hj for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:20 -0400 Received: by mail-wm1-x329.google.com with SMTP id iv17so6621186wmb.4 for ; Tue, 27 Sep 2022 07:15:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=r0tBXvF/ifeoq8b5qrcFwHoN4i2ZgT7ReFA291oacHo=; b=kv34vR1csQQ4KdNOsTQCVTPCw8psYKECHCtNqbWdHe88h7QWnJa+mJkY6MD3Os8Hdt noEzWWrPgogIgyiFH3K45ZB6j8AaVhutapgVo6W9d+gLMJ8YB5uAbiSyXh5JVU9BaMya QyGpFuko1Y00wrIgiuwnN59CXdichDHgOqAepebzHyg5i3Wi6PES/Jr5u3+w+jMjUiut Z7TffNI4CEr1vrKtJGSDgy0jussRyo++ztmXn9UkAZ3oc/jT6l18xuTdATFhsC+9omze foKrCKIt957JFIxKr2g4TkEliLQb1oPY+I3qOEylzbkGmmDlbOvN06HFD5o1jOz7kL1K Rl6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=r0tBXvF/ifeoq8b5qrcFwHoN4i2ZgT7ReFA291oacHo=; b=7kgE3NAhMZdyvMY9kPrali0KBfbHO+fLCi3bjMyEjRX6DoPEFPr0VN9e752TFcUirc 2uOL7wP5vKP0EOH4bUEH5jByCFU/4eoyT2eKC2i/nFh7UarOMZOYkxvABYeDhSNRQco6 ONpJTEY1QQGvHzaMV4bzHKxHy3DBbkBkL1NslNaSZPUean0oiM9BmwTMUDNPTFhvxIR7 36Vv2NbsT6NOSjgRODqZfigZscb3lHhEbKNC4P3YtCeUXX122NtZsiCvgFbF/TeyDkda SSfag0SARSzBUSSzAWIe5Nn+X7oq/QN2dMlhbuyIxwNDSwGhhb+ptlop2PRRTX1fji98 PLng== X-Gm-Message-State: ACrzQf0iInaze9M/K3KRDGEhCom5Y0z+AbXBK/7BWouXMlsZgKViXnvq Y5wm3BxCbk1NhmcGY/cyW7qzNg== X-Received: by 2002:a05:600c:4f13:b0:3b4:9a07:efdb with SMTP id l19-20020a05600c4f1300b003b49a07efdbmr2879933wmq.94.1664288112156; Tue, 27 Sep 2022 07:15:12 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id j27-20020a05600c1c1b00b003b332a7bf15sm15107398wms.7.2022.09.27.07.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:09 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id ACAF41FFB7; Tue, 27 Sep 2022 15:15:06 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Peter Maydell Subject: [PATCH v3 08/15] hw/intc/gic: use MxTxAttrs to divine accessing CPU Date: Tue, 27 Sep 2022 15:14:57 +0100 Message-Id: <20220927141504.3886314-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. As we should only be processing accesses from CPU cores we can push the CPU extraction logic out to the main access functions. If the access does not come from a CPU we log it and fail the transaction with MEMTX_ACCESS_ERROR. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 --- v2 - update for new field - bool asserts v3 - fail non-CPU transactions --- hw/intc/arm_gic.c | 174 +++++++++++++++++++++++++++++++--------------- 1 file changed, 118 insertions(+), 56 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab..7b4f3fb81a 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,42 @@ static const uint8_t gic_id_gicv2[] = { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -static inline int gic_get_current_cpu(GICState *s) + +/* + * The GIC should only be accessed by the CPU so if it is not we + * should fail the transaction (it would either be a bug in how we've + * wired stuff up, a limitation of the translator or the guest doing + * something weird like programming a DMA master to write to the MMIO + * region). + * + * Note the cpu_index is global and we currently don't have any models + * with multiple SoC's with different CPUs. However if we did we would + * need to transform the cpu_index into the socket core. + */ +typedef struct { + bool valid; + int cpu_index; +} GicCPU; + +static inline GicCPU gic_get_current_cpu(GICState *s, MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; + if (attrs.requester_type != MTRT_CPU) { + qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR, + "%s: saw non-CPU transaction", __func__); + return (GicCPU) { .valid = false }; } - return 0; + g_assert(attrs.requester_id < s->num_cpu); + + return (GicCPU) { .valid = true, .cpu_index = attrs.requester_id }; } -static inline int gic_get_current_vcpu(GICState *s) +static inline GicCPU gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + GicCPU cpu = gic_get_current_cpu(s, attrs); + if (cpu.valid) { + cpu.cpu_index += GIC_NCPU; + } + return cpu; } /* Return true if this GIC config has interrupt groups, which is @@ -941,17 +966,14 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) gic_update(s); } -static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) +static uint32_t gic_dist_readb(GICState *s, int cpu, hwaddr offset, MemTxAttrs attrs) { - GICState *s = (GICState *)opaque; uint32_t res; int irq; int i; - int cpu; int cm; int mask; - cpu = gic_get_current_cpu(s); cm = 1 << cpu; if (offset < 0x100) { if (offset == 0) { /* GICD_CTLR */ @@ -1152,19 +1174,26 @@ bad_reg: static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, unsigned size, MemTxAttrs attrs) { + GICState *s = (GICState *)opaque; + GicCPU cpu = gic_get_current_cpu(s, attrs); + + if (!cpu.valid) { + return MEMTX_ACCESS_ERROR; + } + switch (size) { case 1: - *data = gic_dist_readb(opaque, offset, attrs); + *data = gic_dist_readb(s, cpu.cpu_index, offset, attrs); break; case 2: - *data = gic_dist_readb(opaque, offset, attrs); - *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; + *data = gic_dist_readb(s, cpu.cpu_index, offset, attrs); + *data |= gic_dist_readb(s, cpu.cpu_index, offset + 1, attrs) << 8; break; case 4: - *data = gic_dist_readb(opaque, offset, attrs); - *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; - *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; - *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; + *data = gic_dist_readb(s, cpu.cpu_index, offset, attrs); + *data |= gic_dist_readb(s, cpu.cpu_index, offset + 1, attrs) << 8; + *data |= gic_dist_readb(s, cpu.cpu_index, offset + 2, attrs) << 16; + *data |= gic_dist_readb(s, cpu.cpu_index, offset + 3, attrs) << 24; break; default: return MEMTX_ERROR; @@ -1174,15 +1203,12 @@ static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, return MEMTX_OK; } -static void gic_dist_writeb(void *opaque, hwaddr offset, +static void gic_dist_writeb(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - GICState *s = (GICState *)opaque; int irq; int i; - int cpu; - cpu = gic_get_current_cpu(s); if (offset < 0x100) { if (offset == 0) { if (s->security_extn && !attrs.secure) { @@ -1459,24 +1485,21 @@ bad_reg: "gic_dist_writeb: Bad offset %x\n", (int)offset); } -static void gic_dist_writew(void *opaque, hwaddr offset, +static void gic_dist_writew(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - gic_dist_writeb(opaque, offset, value & 0xff, attrs); - gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); + gic_dist_writeb(s, cpu, offset, value & 0xff, attrs); + gic_dist_writeb(s, cpu, offset + 1, value >> 8, attrs); } -static void gic_dist_writel(void *opaque, hwaddr offset, +static void gic_dist_writel(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - GICState *s = (GICState *)opaque; if (offset == 0xf00) { - int cpu; int irq; int mask; int target_cpu; - cpu = gic_get_current_cpu(s); irq = value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1503,24 +1526,31 @@ static void gic_dist_writel(void *opaque, hwaddr offset, gic_update(s); return; } - gic_dist_writew(opaque, offset, value & 0xffff, attrs); - gic_dist_writew(opaque, offset + 2, value >> 16, attrs); + gic_dist_writew(s, cpu, offset, value & 0xffff, attrs); + gic_dist_writew(s, cpu, offset + 2, value >> 16, attrs); } static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs) { + GICState *s = (GICState *)opaque; + GicCPU cpu = gic_get_current_cpu(s, attrs); + + if (!cpu.valid) { + return MEMTX_ACCESS_ERROR; + } + trace_gic_dist_write(offset, size, data); switch (size) { case 1: - gic_dist_writeb(opaque, offset, data, attrs); + gic_dist_writeb(s, cpu.cpu_index, offset, data, attrs); return MEMTX_OK; case 2: - gic_dist_writew(opaque, offset, data, attrs); + gic_dist_writew(s, cpu.cpu_index, offset, data, attrs); return MEMTX_OK; case 4: - gic_dist_writel(opaque, offset, data, attrs); + gic_dist_writel(s, cpu.cpu_index, offset, data, attrs); return MEMTX_OK; default: return MEMTX_ERROR; @@ -1780,7 +1810,12 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + GicCPU cpu = gic_get_current_cpu(s, attrs); + if (cpu.valid) { + return gic_cpu_read(s, cpu.cpu_index, addr, data, attrs); + } else { + return MEMTX_ACCESS_ERROR; + } } static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1788,7 +1823,12 @@ static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + GicCPU cpu = gic_get_current_cpu(s, attrs); + if (cpu.valid) { + return gic_cpu_write(s, cpu.cpu_index, addr, value, attrs); + } else { + return MEMTX_ACCESS_ERROR; + } } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1817,8 +1857,12 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + GicCPU cpu = gic_get_current_vcpu(s, attrs); + if (cpu.valid) { + return gic_cpu_read(s, cpu.cpu_index, addr, data, attrs); + } else { + return MEMTX_ACCESS_ERROR; + } } static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1826,8 +1870,12 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + GicCPU cpu = gic_get_current_vcpu(s, attrs); + if (cpu.valid) { + return gic_cpu_write(s, cpu.cpu_index, addr, value, attrs); + } else { + return MEMTX_ACCESS_ERROR; + } } static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1858,9 +1906,8 @@ static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) return ret; } -static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) +static void gic_vmcr_write(GICState *s, int vcpu, uint32_t value, MemTxAttrs attrs) { - int vcpu = gic_get_current_vcpu(s); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1881,7 +1928,10 @@ static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, uint64_t *data, MemTxAttrs attrs) { GICState *s = ARM_GIC(opaque); - int vcpu = cpu + GIC_NCPU; + GicCPU vcpu = gic_get_current_vcpu(s, attrs); + if (!vcpu.valid) { + return MEMTX_ACCESS_ERROR; + } switch (addr) { case A_GICH_HCR: /* Hypervisor Control */ @@ -1898,11 +1948,11 @@ static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, case A_GICH_VMCR: /* Virtual Machine Control */ *data = FIELD_DP32(0, GICH_VMCR, VMCCtlr, - extract32(s->cpu_ctlr[vcpu], 0, 10)); - *data = FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]); - *data = FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]); + extract32(s->cpu_ctlr[vcpu.cpu_index], 0, 10)); + *data = FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu.cpu_index]); + *data = FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu.cpu_index]); *data = FIELD_DP32(*data, GICH_VMCR, VMPriMask, - extract32(s->priority_mask[vcpu], 3, 5)); + extract32(s->priority_mask[vcpu.cpu_index], 3, 5)); break; case A_GICH_MISR: /* Maintenance Interrupt Status */ @@ -1949,7 +1999,10 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, uint64_t value, MemTxAttrs attrs) { GICState *s = ARM_GIC(opaque); - int vcpu = cpu + GIC_NCPU; + GicCPU vcpu = gic_get_current_vcpu(s, attrs); + if (!vcpu.valid) { + return MEMTX_ACCESS_ERROR; + } trace_gic_hyp_write(addr, value); @@ -1959,12 +2012,13 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, break; case A_GICH_VMCR: /* Virtual Machine Control */ - gic_vmcr_write(s, value, attrs); + gic_vmcr_write(s, vcpu.cpu_index, value, attrs); break; case A_GICH_APR: /* Active Priorities */ s->h_apr[cpu] = value; - s->running_priority[vcpu] = gic_get_prio_from_apr_bits(s, vcpu); + s->running_priority[vcpu.cpu_index] = + gic_get_prio_from_apr_bits(s, vcpu.cpu_index); break; case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ @@ -1991,20 +2045,28 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, } static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *data, - unsigned size, MemTxAttrs attrs) + unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + GicCPU cpu = gic_get_current_cpu(s, attrs); + if (cpu.valid) { + return gic_hyp_read(s, cpu.cpu_index, addr, data, attrs); + } else { + return MEMTX_ACCESS_ERROR; + } } static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) + uint64_t value, unsigned size, + MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + GicCPU cpu = gic_get_current_cpu(s, attrs); + if (cpu.valid) { + return gic_hyp_write(s, cpu.cpu_index, addr, value, attrs); + } else { + return MEMTX_ACCESS_ERROR; + } } static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, From patchwork Tue Sep 27 14:14:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609610 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp428236pvb; Tue, 27 Sep 2022 08:50:40 -0700 (PDT) X-Google-Smtp-Source: AMsMyM41i6v9SUdSs5EpMuuPW3EYVKnJxiObjBDAFQ1Y+1tUKVPRJgpZi5ZZtjyRW9d5/zDMy6Sa X-Received: by 2002:a05:620a:12f0:b0:6ce:4076:a80e with SMTP id f16-20020a05620a12f000b006ce4076a80emr18521550qkl.541.1664293840257; Tue, 27 Sep 2022 08:50:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293840; cv=none; d=google.com; s=arc-20160816; b=pGOoRYmBW+uljplI/3u3vW6uFPXiWUb9Jz8Kuy69AXsoSMSQMTbRiq/770cHtRXbLr JHSFbSuDDxAzrl59RoAr69aFWiK6R1My4w76J0QH4kRUYBQce9HetFKc5romLkCMNJ0W oA95Bg9+U0/pGdQHwhPUWRTy4uHQf4wOiSQhi6F60t6uNAjc4zDpajvzmopy5Kc1GuPR 9282dONnLjdeXiPLmMDRuUqC0bc3yo7kwN94adX8Uiy9DuK3ri3bflDjZK07PNHpvKpl cL0Co1qBrahgxFPHlviWA0Q5RBMCXHgPxIETfmlkwMcoxvGsLhoHOt9+rv2w0GGM/c6u TDtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9V9LEBkVMIt0gNfbFS+tXVi8Jwwq7HDOfuY//HgX7ok=; b=JSqwIyOzWVaoDAymVSY8zP0DrKI8k3Op4eoLS8C7Zm6bh115YmNGEeU+O/JkuLhIZi vN2o2xqxDXvXQ4NkPXD5auwVRToxtGSVmKwuRlvFz04ahzJmidMqpyQ4z3oG+q9bIosH mnVpOcKbokNyujw6ZBU07Z4eIYECo6xGTRdZLHiGG0twLlSrV8CicckOXSs+Dg7GZdUK 676/b1F/Tkghfivp9BbXNT0zfH8AcEM/60G1BZ4BPm2qwqZqc44e44KaHq40BRXy1vCn LIzhr4xD9NJgRAotNUVzUd23/5e7L0/8pNwkwgJkEE8Xkjj0W72jK2ctYxscSLgermYu QDIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=POsf1l2Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m9-20020a05620a24c900b006b920f7b5a2si1366404qkn.702.2022.09.27.08.50.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:50:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=POsf1l2Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCr1-0004Bt-Qf for patch@linaro.org; Tue, 27 Sep 2022 11:50:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMn-0005A4-3r for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:21 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:46940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMj-00061f-Ox for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:20 -0400 Received: by mail-wr1-x42b.google.com with SMTP id bk15so7472677wrb.13 for ; Tue, 27 Sep 2022 07:15:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9V9LEBkVMIt0gNfbFS+tXVi8Jwwq7HDOfuY//HgX7ok=; b=POsf1l2YOZ4HYa8opijLwGMGJqQhh9MPr1yNJf9NX9Bnao5LC70yNnQtyhrjQ1MAOv WSq6saiyH8qF7SU4PbGQMmpFfWlb00zwiQctj7JukLqe+7KwOLVF3kXNeDo3oKGjR9pp u6KimzDFcGdWJ7EHN/edh0nfPmrclKcmPE1qI6O+MVVy3UJiX3JK7bm5hngQy4eMyiXy mKydhvMlCerMq0bDqmn7knkK7Skzp4uPrCkAcbWkMZHMWlIy0WzxbZ63Ko2Fk2RU8/RU gUw7mpbUt0XrvbioTquu+U22TQ8hh9ykkTHAWSFS/VllPky6aDkj3RWilkFo2rt0HwFf meig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9V9LEBkVMIt0gNfbFS+tXVi8Jwwq7HDOfuY//HgX7ok=; b=zpF9s8oAjj5C1Zk79vffezEJ9JpeSjrFhM2+EulUaow92D9jt2ltTkWE9V/T0StZA1 HD3IY2s8tUY4p6/FiXEQSU83feJwinrQekIQGYvAv+OEiMaYAn2Cblb20ywUYGZ0WxpK FJrsgk0V1rz6AVNC6F6GBaAgryIA7FAMBk11vYGUhJnDNhkX/T50lSZmcUWykKRcKIxf DHEPkQmeCeHp4+fbPVWlT0p6yEFKTAmgI5OSFe60HQgiEDRThR7bxjhniZ5bIIx7DeXS e7Nocs9+ikXHat5wyxOZiIk186mmh5h1XBnsCwJ1KVTNCpBCDLnMJg84mD2Vgmwlp7ZX opnQ== X-Gm-Message-State: ACrzQf3G8z+1LyaUMnSj16GGYmYN6mA4tNB0N4kvvKLCq/JXninjWeGa swqBM6nIC/V1qdmSk7yccXye8w== X-Received: by 2002:a5d:588f:0:b0:22b:623:ad04 with SMTP id n15-20020a5d588f000000b0022b0623ad04mr16915896wrf.607.1664288113769; Tue, 27 Sep 2022 07:15:13 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id p14-20020adfce0e000000b0022af6c93340sm1957085wrn.17.2022.09.27.07.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:10 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DCC711FFC0; Tue, 27 Sep 2022 15:15:06 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Peter Maydell Subject: [PATCH v3 09/15] hw/timer: convert mptimer access to attrs to derive cpu index Date: Tue, 27 Sep 2022 15:14:58 +0100 Message-Id: <20220927141504.3886314-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes the hacks to deal with empty current_cpu. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- v2 - update for new fields - bool asserts --- hw/timer/arm_mptimer.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cdfca3000b..34693a2534 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -41,9 +41,10 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ -static inline int get_current_cpu(ARMMPTimerState *s) +static inline int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs) { - int cpu_id = current_cpu ? current_cpu->cpu_index : 0; + int cpu_id = attrs.requester_id; + g_assert(attrs.requester_type == MTRT_CPU); if (cpu_id >= s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", @@ -178,25 +179,27 @@ static void timerblock_write(void *opaque, hwaddr addr, /* Wrapper functions to implement the "read timer/watchdog for * the current CPU" memory regions. */ -static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, - unsigned size) +static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); - return timerblock_read(&s->timerblock[id], addr, size); + int id = get_current_cpu(s, attrs); + *data = timerblock_read(&s->timerblock[id], addr, size); + return MEMTX_OK; } -static void arm_thistimer_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); + int id = get_current_cpu(s, attrs); timerblock_write(&s->timerblock[id], addr, value, size); + return MEMTX_OK; } static const MemoryRegionOps arm_thistimer_ops = { - .read = arm_thistimer_read, - .write = arm_thistimer_write, + .read_with_attrs = arm_thistimer_read, + .write_with_attrs = arm_thistimer_write, .valid = { .min_access_size = 4, .max_access_size = 4, From patchwork Tue Sep 27 14:14:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609609 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp428168pvb; Tue, 27 Sep 2022 08:50:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5E6pKEJASRywBrecHrvQlEVYyP4MWHsPmq6WgeTOoddea9tjPpqBSGolM4Gl/x7xxos+mj X-Received: by 2002:ac8:7d96:0:b0:35b:ae40:2210 with SMTP id c22-20020ac87d96000000b0035bae402210mr22702954qtd.649.1664293829066; Tue, 27 Sep 2022 08:50:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664293829; cv=none; d=google.com; s=arc-20160816; b=T+l/x6Ak77PU7VooyAtdTH/ZpUQoalv3qvGv7nzKchIvo7tygAti3EFo+eoRhaHvGk xPPwu4qnroZjiHtN83g+K751a54EQ9Fy/B6WpaI/XhcH8bYNXmZ47q+xt9PsYS1BEzPe x8yKqahc24bm0IuFIC5NfWF9SK43v941GgQ2JByXmFsXpRIfTT3iOKzqVGdCoX6Q8XaR WRLnAak0SPulAO+P/Rj8r6W0f7FclAzwuOqbZZLH8Mwp0E725nGq5u/bX2rQo1bxuLrB DDHAYoW5i6R6EOLjD9MYrdoFXuMpPsZlNcMpF4ohJzn6MhlGPIjvJPq6KUm1kwBjTEUP NEWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=97ac4mk+qRn8Kl2p6oRtCylE7z7H+goRcyRaHwAJvpk=; b=I5b23EKWUpCZqTrVrwFWzJWCfo0RSNjDsOXcYjqns5Py95GR59F9RRNWCsQ4X9TbnS cR5FVkQszw+Xpktthy+dyMrHGolRO2/nn+V3Fzj6PylzAWl8s5VdsMP8gMziPZFpWubU 62Mz1FrLY/GtsKKQfRWDftWgeDwdJPN/RN4YP0XopZMq3ZelbFALYl8Hr5LmYmR7FBE+ YshnfjsnYDRpkFbefcnVSbgVJWekFxr+n3qqCfT1tXOBNtp1xYvo2R+uaYp369FnF4q9 FS13pvmU1kZot+UmWXBt/BvdPe1oO14/88h1L9Lsx9ghJeRvqJSIUYqRV4h3Hq5YULf+ Lbdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=czRlF50R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x11-20020a05620a448b00b006cebca69defsi1374851qkp.755.2022.09.27.08.50.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:50:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=czRlF50R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCqq-0003kB-K5 for patch@linaro.org; Tue, 27 Sep 2022 11:50:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMo-0005D7-Er for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:22 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:40765) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMl-00061X-Ti for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:22 -0400 Received: by mail-wm1-x330.google.com with SMTP id u16-20020a05600c211000b003b5152ebf09so6974561wml.5 for ; Tue, 27 Sep 2022 07:15:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=97ac4mk+qRn8Kl2p6oRtCylE7z7H+goRcyRaHwAJvpk=; b=czRlF50RH3LoDellwxcGp7CG1W7b47/roQ7W+JMF3aQe1l4jPeiRZyqTFG5pZ+y728 wcGSRwupm5hUbYa453c/X9UQSbI7bNGQXtTllkbX+K8jhlv2BomOXANWYEjfph2ck6bM JCR5F3ycFYqEAylzMyDZj48yzGqYDy/tGSRsQ/oXkKdBKUDMj/ht9zcHCdkK+pjziS0G uzdKZdtX6lizLAz46285OpQ7nDN1MgvbSjMeOwOND2pt+8sVLPQflR7SyXEO9P2Ave7l 4OO9dh/amt3Hd/AmXp/TQZC/HHgcKSyTHy+cLCrI7JqCWil5LnHuyIEkMh75poz2bFJb Jsvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=97ac4mk+qRn8Kl2p6oRtCylE7z7H+goRcyRaHwAJvpk=; b=J0VamacMjmOMVC0jc4almvvYvlc1mnD+DC4PIp7LveZNjkAmd0qJlIMS48H+z5Zdh3 QxMM8eWeq4k3Rffc+6b2LZGdbyc0mMqbom5xEGG/2UXiou1ew03OJjGCrUKKqTGGvISj vL+cu6BfCVuZzkZtZSAmAVefbkWwAvLSCxZbYwWtq7s8Y5xLrgXW6SgvoB7YJICTvWO+ zglUPxY54fOdzs8CSTHV6bD2nOvSKojAS2PUVcMWFl3ZJ59A/+1Z2oG7EZ4N8kk3yY/H 2j+L/l1GNA9L7oGD2/k+Mqrn8kRDG76e6BaDUSDwbmpnT5ENW2SuTM3/1I1GAhB/GAGp bxCg== X-Gm-Message-State: ACrzQf2n4RMGwL5blRew2sNHamUjdb1fwNNdTTqkuypXQw3lMeQHeD2F 9WedqmMR0xfk1Ftvg5O5NsAAtkZ5S+SPPw== X-Received: by 2002:a05:600c:4fcb:b0:3b4:a4dd:6154 with SMTP id o11-20020a05600c4fcb00b003b4a4dd6154mr2826700wmq.60.1664288113211; Tue, 27 Sep 2022 07:15:13 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id k22-20020a05600c1c9600b003b340f00f10sm14701857wms.31.2022.09.27.07.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:10 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 12BC31FFB8; Tue, 27 Sep 2022 15:15:07 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v3 10/15] configure: move detected gdb to TCG's config-host.mak Date: Tue, 27 Sep 2022 15:14:59 +0100 Message-Id: <20220927141504.3886314-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When tests/tcg gained it's own config-host.mak we forgot to move the GDB detection. Fixes: 544f4a2578 (tests/tcg: isolate from QEMU's config-host.mak) Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- configure | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configure b/configure index cc4ecd6008..f6a36a5361 100755 --- a/configure +++ b/configure @@ -2475,6 +2475,8 @@ if test -n "$gdb_bin"; then gdb_version=$($gdb_bin --version | head -n 1) if version_ge ${gdb_version##* } 9.1; then echo "HAVE_GDB_BIN=$gdb_bin" >> $config_host_mak + else + gdb_bin="" fi fi @@ -2559,6 +2561,11 @@ echo "# Automatically generated by configure - do not modify" > $config_host_mak echo "SRC_PATH=$source_path" >> $config_host_mak echo "HOST_CC=$host_cc" >> $config_host_mak +# versioned checked in the main config_host.mak above +if test -n "$gdb_bin"; then + echo "HAVE_GDB_BIN=$gdb_bin" >> $config_host_mak +fi + tcg_tests_targets= for target in $target_list; do arch=${target%%-*} From patchwork Tue Sep 27 14:15:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609612 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp429819pvb; Tue, 27 Sep 2022 08:54:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5JqHp7tsthVIXzdFRnqi5J4g/a0c/OZxHMfG0xXVKC1SzB9J+gphjrbu4z12rfhOd3CTLH X-Received: by 2002:a05:622a:286:b0:35d:4ce4:f643 with SMTP id z6-20020a05622a028600b0035d4ce4f643mr2716438qtw.110.1664294048747; Tue, 27 Sep 2022 08:54:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664294048; cv=none; d=google.com; s=arc-20160816; b=AOwAX/cilku+slLe7axRUtiQ+eP11PQu8fBWkiftBreHI2sqDqVu45NNXVX+WQC98j dS31qhUxJ/YmnJo6/5YNa7czSaPguDUqFQc0H3+IPxqyZh2ZKaAJch3SgWfgxY8hYQm7 bUfXrNm6T6qu39VlkY5R1jf/q4NDvyxAb7GKf345c7ftw/oHsrGjS9seDpg/4rmUmYas 3G/qc6JiXOhbK04a+y8nQ7yO0cUnZATV2IYq7+ff4wA3AiJ1Q2GyzIZ2NJ2jfEqLB7iJ sphZZyltEmJ1pdmsXHBr8NP7ytB+isrCRWRsJSEv7XDH/BM563TZXDWn8rS/uGLOPSqJ 7+8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XZUpjPpadlAUHW/RreWII3CPwNzHzHCurB5FcarW70s=; b=vYd4AvV0y+SINDOk1Lf2/PWmUOVlIlUSpx5aA4Jdy6gEkUAVUL1bCyMgdLb7RtvNAm IkZErVNfDt+wgmwS7sdTcorsqPqgqnO1hzNEhEr6M2vZLpN6XLc2+Hd4Fcw1nkfcIS0a 8WY8zVykotRQ3KpPR2vgwm7gSEOpveQaBl+V5IUeh8SfHTMkyalWoxdS/2DtL/BYmWYP bohY1UWxqdq694JjNQMePDMzR0hdItf9PDqjBcWIF+iGaLaKVbwFmfxJn24Q6LnN/rKz I44DaWczaIR7L3v+NXzjApdaSdeRWRX26Wsr357UosIbWp7QMdHGaQ52K26rmx5KUS1x sXBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H0UhZ3v1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p15-20020ad45f4f000000b004aaa2c92f48si1314237qvg.482.2022.09.27.08.54.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:54:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H0UhZ3v1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCuO-0001Xw-9G for patch@linaro.org; Tue, 27 Sep 2022 11:54:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMo-0005CN-05 for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:22 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:39667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMl-000621-Ek for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:21 -0400 Received: by mail-wr1-x431.google.com with SMTP id cc5so15228446wrb.6 for ; Tue, 27 Sep 2022 07:15:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=XZUpjPpadlAUHW/RreWII3CPwNzHzHCurB5FcarW70s=; b=H0UhZ3v1/NELxdrMprGbtIBN9ALoQgajIWFuuKgORwBvKYHa0wfoMMlWTIl7ZDhPn8 DoH7fGM3wxEFV+OX3wvnwR1ufZjXFonXe65gHMOjjl0Q5V5mBsAJ4pdDQaqbvodlu2d+ 2ZM35EieJY6fjPF4IWHwG+cECtZm8sh2OC888RZEam2p2UJmbJNF5vFAN/nECoKNgw75 6vfVSbm3mhFNNVzFKY5t3w/sS1LDeMEo2TLzYgQPtV83M2GGyve15Q6ZujbV3d4EXROJ Mh82EyaOTDTarizUQkhKVYr4tI/7KGEDj64zBYJ9BI4D31TkEjs1nv44U6Hqp61Nfx2W yqWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=XZUpjPpadlAUHW/RreWII3CPwNzHzHCurB5FcarW70s=; b=lDb4fSpgySfo6MSfqtoG0mBNFgHzb6txz4rFPW/zlxI6+8gMU2lN2WnLO34ZBm28f0 FdAG3QpnO7P3EbgQeomr5lXshsMa+a/ElYXVvcQCidddbEO+5wabkClzSSB+tmkuGEaQ 9b1ltC4fY3k+uBZRSdG1UqUpm45RSE2k1sOzLfKxq9pQ7VH88YlBMyyqGT4Kg9uM7FyI 1GdECyxYZdp7x9eLErtK4z4Wr1bCf7GB9jceIjTrNFa9T43pqtrWqPhWllzlae/jaMh7 adu2PZFR3iog3IhNg5vXk2Ah9UbVqJx4M5hks1//hTBrjvoCFlzbgF4fjN2ee0Jzitxq 1WGw== X-Gm-Message-State: ACrzQf0+DrE5YcYkPlJoeBZ+FOhjbADQiCOBt/kZGc0eVRpztJeBzuSN wDzyxa6czGkwP90vt2CJzFm6zA== X-Received: by 2002:a05:6000:144f:b0:22a:7098:6472 with SMTP id v15-20020a056000144f00b0022a70986472mr17397460wrx.685.1664288115117; Tue, 27 Sep 2022 07:15:15 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id x14-20020adfec0e000000b0022a297950cesm1973733wrn.23.2022.09.27.07.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:10 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7A2C81FFC1; Tue, 27 Sep 2022 15:15:07 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Stefan Hajnoczi Subject: [PATCH v3 11/15] gdbstub: move into its own sub directory Date: Tue, 27 Sep 2022 15:15:00 +0100 Message-Id: <20220927141504.3886314-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is in preparation of future refactoring as well as cleaning up the source tree. Aside from the minor tweaks to meson and trace.h this is pure code motion. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- meson.build | 4 +++- gdbstub/trace.h | 1 + gdbstub.c => gdbstub/gdbstub.c | 2 +- MAINTAINERS | 2 +- gdbstub/meson.build | 1 + gdbstub/trace-events | 29 +++++++++++++++++++++++++++++ trace-events | 28 ---------------------------- 7 files changed, 36 insertions(+), 31 deletions(-) create mode 100644 gdbstub/trace.h rename gdbstub.c => gdbstub/gdbstub.c (99%) create mode 100644 gdbstub/meson.build create mode 100644 gdbstub/trace-events diff --git a/meson.build b/meson.build index 3885fc1076..2c9209c2b8 100644 --- a/meson.build +++ b/meson.build @@ -2914,6 +2914,7 @@ trace_events_subdirs = [ 'qom', 'monitor', 'util', + 'gdbstub', ] if have_linux_user trace_events_subdirs += [ 'linux-user' ] @@ -3037,6 +3038,7 @@ subdir('authz') subdir('crypto') subdir('ui') subdir('hw') +subdir('gdbstub') if enable_modules @@ -3114,7 +3116,7 @@ common_ss.add(files('cpus-common.c')) subdir('softmmu') common_ss.add(capstone) -specific_ss.add(files('cpu.c', 'disas.c', 'gdbstub.c'), capstone) +specific_ss.add(files('cpu.c', 'disas.c'), capstone) # Work around a gcc bug/misfeature wherein constant propagation looks # through an alias: diff --git a/gdbstub/trace.h b/gdbstub/trace.h new file mode 100644 index 0000000000..dee87b1238 --- /dev/null +++ b/gdbstub/trace.h @@ -0,0 +1 @@ +#include "trace/trace-gdbstub.h" diff --git a/gdbstub.c b/gdbstub/gdbstub.c similarity index 99% rename from gdbstub.c rename to gdbstub/gdbstub.c index cf869b10e3..7d8fe475b3 100644 --- a/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -29,7 +29,7 @@ #include "qemu/ctype.h" #include "qemu/cutils.h" #include "qemu/module.h" -#include "trace/trace-root.h" +#include "trace.h" #include "exec/gdbstub.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" diff --git a/MAINTAINERS b/MAINTAINERS index 738c4eb647..82575b2486 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2670,7 +2670,7 @@ GDB stub M: Alex Bennée R: Philippe Mathieu-Daudé S: Maintained -F: gdbstub* +F: gdbstub/* F: include/exec/gdbstub.h F: gdb-xml/ F: tests/tcg/multiarch/gdbstub/ diff --git a/gdbstub/meson.build b/gdbstub/meson.build new file mode 100644 index 0000000000..6d4ae2d03c --- /dev/null +++ b/gdbstub/meson.build @@ -0,0 +1 @@ +specific_ss.add(files('gdbstub.c')) diff --git a/gdbstub/trace-events b/gdbstub/trace-events new file mode 100644 index 0000000000..03f0c303bf --- /dev/null +++ b/gdbstub/trace-events @@ -0,0 +1,29 @@ +# See docs/devel/tracing.rst for syntax documentation. + +# gdbstub.c +gdbstub_op_start(const char *device) "Starting gdbstub using device %s" +gdbstub_op_exiting(uint8_t code) "notifying exit with code=0x%02x" +gdbstub_op_continue(void) "Continuing all CPUs" +gdbstub_op_continue_cpu(int cpu_index) "Continuing CPU %d" +gdbstub_op_stepping(int cpu_index) "Stepping CPU %d" +gdbstub_op_extra_info(const char *info) "Thread extra info: %s" +gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" +gdbstub_hit_internal_error(void) "RUN_STATE_INTERNAL_ERROR" +gdbstub_hit_break(void) "RUN_STATE_DEBUG" +gdbstub_hit_paused(void) "RUN_STATE_PAUSED" +gdbstub_hit_shutdown(void) "RUN_STATE_SHUTDOWN" +gdbstub_hit_io_error(void) "RUN_STATE_IO_ERROR" +gdbstub_hit_watchdog(void) "RUN_STATE_WATCHDOG" +gdbstub_hit_unknown(int state) "Unknown run state=0x%x" +gdbstub_io_reply(const char *message) "Sent: %s" +gdbstub_io_binaryreply(size_t ofs, const char *line) "0x%04zx: %s" +gdbstub_io_command(const char *command) "Received: %s" +gdbstub_io_got_ack(void) "Got ACK" +gdbstub_io_got_unexpected(uint8_t ch) "Got 0x%02x when expecting ACK/NACK" +gdbstub_err_got_nack(void) "Got NACK, retransmitting" +gdbstub_err_garbage(uint8_t ch) "received garbage between packets: 0x%02x" +gdbstub_err_overrun(void) "command buffer overrun, dropping command" +gdbstub_err_invalid_repeat(uint8_t ch) "got invalid RLE count: 0x%02x" +gdbstub_err_invalid_rle(void) "got invalid RLE sequence" +gdbstub_err_checksum_invalid(uint8_t ch) "got invalid command checksum digit: 0x%02x" +gdbstub_err_checksum_incorrect(uint8_t expected, uint8_t got) "got command packet with incorrect checksum, expected=0x%02x, received=0x%02x" diff --git a/trace-events b/trace-events index bc71006675..035f3d570d 100644 --- a/trace-events +++ b/trace-events @@ -46,34 +46,6 @@ ram_block_discard_range(const char *rbname, void *hva, size_t length, bool need_ memory_notdirty_write_access(uint64_t vaddr, uint64_t ram_addr, unsigned size) "0x%" PRIx64 " ram_addr 0x%" PRIx64 " size %u" memory_notdirty_set_dirty(uint64_t vaddr) "0x%" PRIx64 -# gdbstub.c -gdbstub_op_start(const char *device) "Starting gdbstub using device %s" -gdbstub_op_exiting(uint8_t code) "notifying exit with code=0x%02x" -gdbstub_op_continue(void) "Continuing all CPUs" -gdbstub_op_continue_cpu(int cpu_index) "Continuing CPU %d" -gdbstub_op_stepping(int cpu_index) "Stepping CPU %d" -gdbstub_op_extra_info(const char *info) "Thread extra info: %s" -gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" -gdbstub_hit_internal_error(void) "RUN_STATE_INTERNAL_ERROR" -gdbstub_hit_break(void) "RUN_STATE_DEBUG" -gdbstub_hit_paused(void) "RUN_STATE_PAUSED" -gdbstub_hit_shutdown(void) "RUN_STATE_SHUTDOWN" -gdbstub_hit_io_error(void) "RUN_STATE_IO_ERROR" -gdbstub_hit_watchdog(void) "RUN_STATE_WATCHDOG" -gdbstub_hit_unknown(int state) "Unknown run state=0x%x" -gdbstub_io_reply(const char *message) "Sent: %s" -gdbstub_io_binaryreply(size_t ofs, const char *line) "0x%04zx: %s" -gdbstub_io_command(const char *command) "Received: %s" -gdbstub_io_got_ack(void) "Got ACK" -gdbstub_io_got_unexpected(uint8_t ch) "Got 0x%02x when expecting ACK/NACK" -gdbstub_err_got_nack(void) "Got NACK, retransmitting" -gdbstub_err_garbage(uint8_t ch) "received garbage between packets: 0x%02x" -gdbstub_err_overrun(void) "command buffer overrun, dropping command" -gdbstub_err_invalid_repeat(uint8_t ch) "got invalid RLE count: 0x%02x" -gdbstub_err_invalid_rle(void) "got invalid RLE sequence" -gdbstub_err_checksum_invalid(uint8_t ch) "got invalid command checksum digit: 0x%02x" -gdbstub_err_checksum_incorrect(uint8_t expected, uint8_t got) "got command packet with incorrect checksum, expected=0x%02x, received=0x%02x" - # job.c job_state_transition(void *job, int ret, const char *legal, const char *s0, const char *s1) "job %p (ret: %d) attempting %s transition (%s-->%s)" job_apply_verb(void *job, const char *state, const char *verb, const char *legal) "job %p in state %s; applying verb %s (%s)" From patchwork Tue Sep 27 14:15:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609617 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp440831pvb; Tue, 27 Sep 2022 09:10:21 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7id4Mkb62CaBtFZ7awq0QBnNEflwhzziLkFkx5psBJ0BkU1wNLJlX+Do/3ksoJv7/sHAKM X-Received: by 2002:a05:622a:1790:b0:35c:8450:d9e4 with SMTP id s16-20020a05622a179000b0035c8450d9e4mr22953640qtk.130.1664295021816; Tue, 27 Sep 2022 09:10:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664295021; cv=none; d=google.com; s=arc-20160816; b=oXNdqaFa6VhpSQMfy7qk5RR5k6tKamPpf/nrtK+HG3WH/WsLrwok8VT6DgZDXZEFnf dvEB3dYqHcOMU4pLztr7rOXiouMAHSXY7EML4IJ+GT/Sg6yjnXFKiMO9pLDX8HjI9mjy ueLJ2Ng6sg0Iakr+wdsW95CRsz1KrMpvQyoDrAZcci0wxArF1HnKX/nNI2LkkOfIg78Z SZGDfz4nkGfhhc90RdVdP5AvCCdR4Mxt67vdaOiWwTLOxfHH+bsNufyIp94lcge7MHJb Z6MQro7mppSJkHg9ugXW75200jGH4v8LYo0zbyyCsDHRUwP1kqss4ZAUztI5AOeXgdYm ctDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uPWI1zT5RA3MTBLfOSsbd8UM7dwx7REeUZ6YlYd0oe4=; b=jvt9EUzCjstJLd6NQDeyx1Hi75WNFtiw11AC+t4gjDLfms9e+i9PyiMks6hc6jKesj kEevd6WVbtgvImuxPFnFU37dlwpppwxTKknWmK619X6AFH9g1Ysm8WT73kUQ0lXiOZ1k ymz15v2RxnfXoATYCcEdr7GbQejF2Nhf4q4Tp4vB/4jSV71f4KFb2qDpv5kGMNeWt6Bc ACJfU8x8sQ6JW7j/rx67lKT/kQ5ZhUyKZlYlxb26OVZd3bm8r3eDntbgi3qpdnDlTear 9tfgIH+jSS3GbfqBBHRvBkNLihDa2fNUbVibJsAZEMiwT81qqerDLEMCEmLKNFT4ny+E c3WQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ku/FJr2y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r2-20020ad45762000000b00498f6c644easi1369195qvx.374.2022.09.27.09.10.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 09:10:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ku/FJr2y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odDA5-0003ml-CH for patch@linaro.org; Tue, 27 Sep 2022 12:10:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52414) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBWH-0005UP-Uq for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:25:33 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:41590) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBW2-0007RQ-O4 for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:24:56 -0400 Received: by mail-wm1-x329.google.com with SMTP id fn7-20020a05600c688700b003b4fb113b86so5570512wmb.0 for ; Tue, 27 Sep 2022 07:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=uPWI1zT5RA3MTBLfOSsbd8UM7dwx7REeUZ6YlYd0oe4=; b=ku/FJr2y7hvg9lXsgzMSw75QzXdl7A8OeyfLtni1dK+UZsEFM8qyBjOX+NZe6Aslnx Vdyk3zIk6xYTz7LX0uoyHAfgZ6mFB6R1SYlajsC2oFrZSQnKq95hWLV/evKlWeghixiy KlTpqaEZSoTuzll3iWKXhVGUYly3CPR+Cez1n9Hyc2WF37xMFZ3u50Co33OaG2hD2DMI fz6pYTeK9GmKFznVS1RoHLaD6vDBPa5xVMbgOJ6VM4M4W7UQKaRISZvlJRGhz12jBRDZ z+H0oQoM0E0vyyK6+zKQerfvXSZlGCq2gaLOhUUXlfqc8YC592rFV7T4djNOIrSOzr4B 06Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=uPWI1zT5RA3MTBLfOSsbd8UM7dwx7REeUZ6YlYd0oe4=; b=GJ0vjm6jkEgB2TIaUC1WQnsKuBbzaBOQhstVZJZEMaDQZ2RcdkFWbHA6PSe1uv4SdT wN07/R5sJPo+D5+wGyOPemBYNWsvJY/KvxGDeqn3WZ9R6EF8ygcw1OF5J71O17by5P5v u6QDMKYayKbhxi/bb1i4xkq4eCRLCjiWM3IHD8fukrzyo9nL4BJzAcxa1PZUjyKapN1c KZm4xvhQOXIBeC54xVs0HzRuw6zRWvgC47JkFff9XmopfxsaBqGq5PI6OgxLV9bmVqoU mYzAzmjs8A5Ro/1+k3hKEoTW5Pwu5h1h9dbBAfU6dXu1awI48WHJVPYOdlvi8Uttds7S K7XA== X-Gm-Message-State: ACrzQf1p4J33be6pJrXMsaYVdM0WalzWDYdjHdjwCSA8cfLamX21Vb3w B1eMKtyxED3SjTVUNGCdVazGHA== X-Received: by 2002:a05:600c:1e24:b0:3b4:6c1e:8bb7 with SMTP id ay36-20020a05600c1e2400b003b46c1e8bb7mr3072568wmb.1.1664288692398; Tue, 27 Sep 2022 07:24:52 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id x17-20020adff651000000b00228fa832b7asm1948368wrp.52.2022.09.27.07.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:24:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D4AC71FFC2; Tue, 27 Sep 2022 15:15:07 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Mads Ynddal , Paolo Bonzini , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v3 12/15] gdbstub: move sstep flags probing into AccelClass Date: Tue, 27 Sep 2022 15:15:01 +0100 Message-Id: <20220927141504.3886314-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The support of single-stepping is very much dependent on support from the accelerator we are using. To avoid special casing in gdbstub move the probing out to an AccelClass function so future accelerators can put their code there. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Cc: Mads Ynddal Reviewed-by: Mads Ynddal --- include/qemu/accel.h | 12 ++++++++++++ include/sysemu/kvm.h | 8 -------- accel/accel-common.c | 10 ++++++++++ accel/kvm/kvm-all.c | 14 +++++++++++++- accel/tcg/tcg-all.c | 17 +++++++++++++++++ gdbstub/gdbstub.c | 22 ++++------------------ 6 files changed, 56 insertions(+), 27 deletions(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index be56da1b99..ce4747634a 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -43,6 +43,10 @@ typedef struct AccelClass { bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); #endif + + /* gdbstub related hooks */ + int (*gdbstub_supported_sstep_flags)(void); + bool *allowed; /* * Array of global properties that would be applied when specific @@ -92,4 +96,12 @@ void accel_cpu_instance_init(CPUState *cpu); */ bool accel_cpu_realizefn(CPUState *cpu, Error **errp); +/** + * accel_supported_gdbstub_sstep_flags: + * + * Returns the supported single step modes for the configured + * accelerator. + */ +int accel_supported_gdbstub_sstep_flags(void); + #endif /* QEMU_ACCEL_H */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index efd6dee818..a20ad51aad 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -47,7 +47,6 @@ extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; extern bool kvm_has_guest_debug; -extern int kvm_sstep_flags; #define kvm_enabled() (kvm_allowed) /** @@ -174,12 +173,6 @@ extern int kvm_sstep_flags; */ #define kvm_supports_guest_debug() (kvm_has_guest_debug) -/* - * kvm_supported_sstep_flags - * Returns: SSTEP_* flags that KVM supports for guest debug - */ -#define kvm_get_supported_sstep_flags() (kvm_sstep_flags) - #else #define kvm_enabled() (0) @@ -198,7 +191,6 @@ extern int kvm_sstep_flags; #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) #define kvm_supports_guest_debug() (false) -#define kvm_get_supported_sstep_flags() (0) #endif /* CONFIG_KVM_IS_POSSIBLE */ diff --git a/accel/accel-common.c b/accel/accel-common.c index 50035bda55..df72cc989a 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -129,6 +129,16 @@ bool accel_cpu_realizefn(CPUState *cpu, Error **errp) return true; } +int accel_supported_gdbstub_sstep_flags(void) +{ + AccelState *accel = current_accel(); + AccelClass *acc = ACCEL_GET_CLASS(accel); + if (acc->gdbstub_supported_sstep_flags) { + return acc->gdbstub_supported_sstep_flags(); + } + return 0; +} + static const TypeInfo accel_cpu_type = { .name = TYPE_ACCEL_CPU, .parent = TYPE_OBJECT, diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 5acab1767f..c55938453a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -175,7 +175,7 @@ bool kvm_direct_msi_allowed; bool kvm_ioeventfd_any_length_allowed; bool kvm_msi_use_devid; bool kvm_has_guest_debug; -int kvm_sstep_flags; +static int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size = ~0; @@ -3712,6 +3712,17 @@ static void kvm_accel_instance_init(Object *obj) s->kvm_dirty_ring_size = 0; } +/** + * kvm_gdbstub_sstep_flags(): + * + * Returns: SSTEP_* flags that KVM supports for guest debug. The + * support is probed during kvm_init() + */ +static int kvm_gdbstub_sstep_flags(void) +{ + return kvm_sstep_flags; +} + static void kvm_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); @@ -3719,6 +3730,7 @@ static void kvm_accel_class_init(ObjectClass *oc, void *data) ac->init_machine = kvm_init; ac->has_memory = kvm_accel_has_memory; ac->allowed = &kvm_allowed; + ac->gdbstub_supported_sstep_flags = kvm_gdbstub_sstep_flags; object_class_property_add(oc, "kernel-irqchip", "on|off|split", NULL, kvm_set_kernel_irqchip, diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 47952eecd7..30b503fb22 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "sysemu/tcg.h" +#include "sysemu/replay.h" #include "sysemu/cpu-timers.h" #include "tcg/tcg.h" #include "qapi/error.h" @@ -207,12 +208,28 @@ static void tcg_set_splitwx(Object *obj, bool value, Error **errp) s->splitwx_enabled = value; } +static int tcg_gdbstub_supported_sstep_flags(void) +{ + /* + * In replay mode all events will come from the log and can't be + * suppressed otherwise we would break determinism. However as those + * events are tied to the number of executed instructions we won't see + * them occurring every time we single step. + */ + if (replay_mode != REPLAY_MODE_NONE) { + return SSTEP_ENABLE; + } else { + return SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; + } +} + static void tcg_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); ac->name = "tcg"; ac->init_machine = tcg_init_machine; ac->allowed = &tcg_allowed; + ac->gdbstub_supported_sstep_flags = tcg_gdbstub_supported_sstep_flags; object_class_property_add_str(oc, "thread", tcg_get_thread, diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 7d8fe475b3..a0755e6505 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -383,27 +383,13 @@ static void init_gdbserver_state(void) gdbserver_state.last_packet = g_byte_array_sized_new(MAX_PACKET_LENGTH + 4); /* - * In replay mode all events will come from the log and can't be - * suppressed otherwise we would break determinism. However as those - * events are tied to the number of executed instructions we won't see - * them occurring every time we single step. - */ - if (replay_mode != REPLAY_MODE_NONE) { - gdbserver_state.supported_sstep_flags = SSTEP_ENABLE; - } else if (kvm_enabled()) { - gdbserver_state.supported_sstep_flags = kvm_get_supported_sstep_flags(); - } else { - gdbserver_state.supported_sstep_flags = - SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; - } - - /* - * By default use no IRQs and no timers while single stepping so as to - * make single stepping like an ICE HW step. + * What single-step modes are supported is accelerator dependent. + * By default try to use no IRQs and no timers while single + * stepping so as to make single stepping like a typical ICE HW step. */ + gdbserver_state.supported_sstep_flags = accel_supported_gdbstub_sstep_flags(); gdbserver_state.sstep_flags = SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; gdbserver_state.sstep_flags &= gdbserver_state.supported_sstep_flags; - } #ifndef CONFIG_USER_ONLY From patchwork Tue Sep 27 14:15:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609615 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp431777pvb; Tue, 27 Sep 2022 08:57:55 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6H3ACfVTAxRvNX0/vi7oOMCQ9RedRBJq5PBxNYY0vBByv0qC6M6RkC/gPSBMxKZKdI6Rpb X-Received: by 2002:ad4:5cc1:0:b0:4a7:dbb4:1118 with SMTP id iu1-20020ad45cc1000000b004a7dbb41118mr22295783qvb.84.1664294275009; Tue, 27 Sep 2022 08:57:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664294275; cv=none; d=google.com; s=arc-20160816; b=qNQzHhDfd13LraPmx7Zq7qTtYVWJgDs07HE8/sBD3gVg61pybXMxKAh0hUzHEc3pL0 TqV53xG2+HmpO0eGbl4RPElWPj1LsFQODdAkx2Jv2Fc5+9y+O1AcDlv0xfOXgFBEds5o A9089sShG6cqVM8Po8MwXdDaqLCv67Sgcggcn7W9m8KAHF+D35XKxVIhbaIeIbxJBwwk 8uoeyuJZkvxgqud8ShfNCC5cVETe4z0EUeVIxRAgL1pP0oNUKhqkskNtZ82V+b4Lj2eP 8jpmxSAzRAJdDl918Y9tNohltMurFfA0PN4Nmu9HF7NUQ07MO+yQlfrX6Ruqp7Cnq3/J bT8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fTabJPCIPlhP85UMkzUVWmjvUxpiXA1PS7vvmHzeVyk=; b=ktc6iysGhX+QFvs8LNqdq+usLnokxO2h6sZI3imNxYmwjchuU9kDdFrLXTEF17Ibue laLU5f1rDAz9L0+dPSSEpTim+ioT7SwvYZXNrsXxnQkox57rMbRVYpAvbOdaPtuNivyg 8ELec7215dZUs4kMMqZ4GwI88Ah0qxC1oL8EhRIhK5UAWU3egNzWM/1ucJQBWrZH5T6J ipIZY/y6U9gkCOyOA27Y744YxLTcnAjcKr8NQT/M/+3iLE/WGWlcniifGTrjbfED4siy +rfFRwLWbt0EB0OcFIbyyY0IsXidae9+lj8pWd1X8bebuZP/ttmE/wHYalQYTVGHB9Nr 0Kww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lwckCi7R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8-20020a0562140d0800b004ad1a00d349si1160711qvh.281.2022.09.27.08.57.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:57:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lwckCi7R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCy2-0007wp-Gs for patch@linaro.org; Tue, 27 Sep 2022 11:57:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMq-0005IK-Oh for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:24 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:39529) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMl-000625-TW for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:24 -0400 Received: by mail-wm1-x32d.google.com with SMTP id e10-20020a05600c4e4a00b003b4eff4ab2cso9514679wmq.4 for ; Tue, 27 Sep 2022 07:15:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=fTabJPCIPlhP85UMkzUVWmjvUxpiXA1PS7vvmHzeVyk=; b=lwckCi7R/CY+POaFVOCZaTOc0LImUUDH9/3CXVxQvkpq74L824UkYznKqqsBUSnIcY qKZlkAgu1F6eTHcdkYmUIQ6L5Aet46WqYBo8vbaXNf0CrHU1oSlWUb1XfaVat6daMmI8 KiTwI42aP6sBUJuof6/yGR8qptDYMLjnvCSW+nyN9dDuv0lffe6EpwRlgHgnv0sXYhrN uYJE8dL8fsFJUisyVlIZtoJ0O0HTZmm4y1VO3sOT6p1vC5uz/Jz1sjA9uHgpnshvU9PC 3+tdWLTI6M7+ryqo67BPc6J4unNmu9dbyD2VugPukwkwmdG7/Con65NdwUC48dxXbXKB OvSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=fTabJPCIPlhP85UMkzUVWmjvUxpiXA1PS7vvmHzeVyk=; b=eOwZN6lPBcPmbMrB8tBCGtGdB14CwilF8FqT+yhZhP4SGnS7aTn4NoPcj6tJDKkOtk FjbRZZzgCvawtD7Kfo+eiuE9NtV2BH8yaHBjuKqC30ftC7wa+3DCMFBRex9v0QarrtIj 8ATVcYumcNwG5/WKYo3ZYBXyZzJtZ9u4eS+D6t8iVyBXh/EI7IvMbWQUjnZ0LjG0ERiW 3a1Qke37WPUgtqOGQrvy/mGGj5RO2xjlSkouwBawgLR2zrMDIKa3qN4K7zh6i43E7GXx q08HYcOoYRV2nR7CxDfWlqzXwShAOczrtyLLIR6H8E04ky8ZpiPEhKF2onPl5F2hggO3 vdrQ== X-Gm-Message-State: ACrzQf0qKTAZe5JgDLsWf+C8pE2UqP/HHoZnfHNSryuUSpka0RuWbGDT djR9taUqgsWOvP5UyDpQv325YA== X-Received: by 2002:a7b:c4cc:0:b0:3b4:757b:492f with SMTP id g12-20020a7bc4cc000000b003b4757b492fmr2980454wmk.74.1664288115692; Tue, 27 Sep 2022 07:15:15 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id t11-20020a05600c41cb00b003b31fc77407sm13907811wmh.30.2022.09.27.07.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:11 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 814AD1FFBB; Tue, 27 Sep 2022 15:15:08 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Mads Ynddal , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v3 13/15] gdbstub: move breakpoint logic to accel ops Date: Tue, 27 Sep 2022 15:15:02 +0100 Message-Id: <20220927141504.3886314-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As HW virtualization requires specific support to handle breakpoints lets push out special casing out of the core gdbstub code and into AccelOpsClass. This will make it easier to add other accelerator support and reduces some of the stub shenanigans. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Cc: Mads Ynddal Reviewed-by: Mads Ynddal --- accel/kvm/kvm-cpus.h | 3 + gdbstub/internals.h | 16 +++++ include/sysemu/accel-ops.h | 6 ++ include/sysemu/cpus.h | 3 + include/sysemu/kvm.h | 5 -- accel/kvm/kvm-accel-ops.c | 8 +++ accel/kvm/kvm-all.c | 24 +------ accel/stubs/kvm-stub.c | 16 ----- accel/tcg/tcg-accel-ops.c | 92 +++++++++++++++++++++++++++ gdbstub/gdbstub.c | 127 +++---------------------------------- gdbstub/softmmu.c | 42 ++++++++++++ gdbstub/user.c | 62 ++++++++++++++++++ softmmu/cpus.c | 7 ++ gdbstub/meson.build | 8 +++ 14 files changed, 259 insertions(+), 160 deletions(-) create mode 100644 gdbstub/internals.h create mode 100644 gdbstub/softmmu.c create mode 100644 gdbstub/user.c diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index bf0bd1bee4..33e435d62b 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -18,5 +18,8 @@ void kvm_destroy_vcpu(CPUState *cpu); void kvm_cpu_synchronize_post_reset(CPUState *cpu); void kvm_cpu_synchronize_post_init(CPUState *cpu); void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu); +int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); +int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); +void kvm_remove_all_breakpoints(CPUState *cpu); #endif /* KVM_CPUS_H */ diff --git a/gdbstub/internals.h b/gdbstub/internals.h new file mode 100644 index 0000000000..41e2e72dbf --- /dev/null +++ b/gdbstub/internals.h @@ -0,0 +1,16 @@ +/* + * gdbstub internals + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _INTERNALS_H_ +#define _INTERNALS_H_ + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); +void gdb_breakpoint_remove_all(CPUState *cs); + +#endif /* _INTERNALS_H_ */ diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index a0572ea87a..86794ac273 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -10,6 +10,7 @@ #ifndef ACCEL_OPS_H #define ACCEL_OPS_H +#include "exec/hwaddr.h" #include "qom/object.h" #define ACCEL_OPS_SUFFIX "-ops" @@ -44,6 +45,11 @@ struct AccelOpsClass { int64_t (*get_virtual_clock)(void); int64_t (*get_elapsed_ticks)(void); + + /* gdbstub hooks */ + int (*insert_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); + int (*remove_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); + void (*remove_all_breakpoints)(CPUState *cpu); }; #endif /* ACCEL_OPS_H */ diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index b5c87d48b3..1bace3379b 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -7,6 +7,9 @@ /* register accel-specific operations */ void cpus_register_accel(const AccelOpsClass *i); +/* return registers ops */ +const AccelOpsClass *cpus_get_accel(void); + /* accel/dummy-cpus.c */ /* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index a20ad51aad..21d3f1d01e 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -254,11 +254,6 @@ int kvm_on_sigbus(int code, void *addr); void kvm_flush_coalesced_mmio_buffer(void); -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type); -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type); -void kvm_remove_all_breakpoints(CPUState *cpu); int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap); /* internal API */ diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index c4244a23c6..5c0e37514c 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -16,12 +16,14 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" #include "sysemu/cpus.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include #include "kvm-cpus.h" static void *kvm_vcpu_thread_fn(void *arg) @@ -95,6 +97,12 @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_post_init = kvm_cpu_synchronize_post_init; ops->synchronize_state = kvm_cpu_synchronize_state; ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; + +#ifdef KVM_CAP_SET_GUEST_DEBUG + ops->insert_breakpoint = kvm_insert_breakpoint; + ops->remove_breakpoint = kvm_remove_breakpoint; + ops->remove_all_breakpoints = kvm_remove_all_breakpoints; +#endif } static const TypeInfo kvm_accel_ops_type = { diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index c55938453a..b8c734fe3a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3287,8 +3287,7 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return data.err; } -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) +int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; int err; @@ -3326,8 +3325,7 @@ int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, return 0; } -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) +int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; int err; @@ -3393,26 +3391,10 @@ void kvm_remove_all_breakpoints(CPUState *cpu) #else /* !KVM_CAP_SET_GUEST_DEBUG */ -int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) +static int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) { return -EINVAL; } - -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -void kvm_remove_all_breakpoints(CPUState *cpu) -{ -} #endif /* !KVM_CAP_SET_GUEST_DEBUG */ static int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset) diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 2ac5f9c036..2d79333143 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -51,22 +51,6 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return -ENOSYS; } -int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, - target_ulong len, int type) -{ - return -EINVAL; -} - -void kvm_remove_all_breakpoints(CPUState *cpu) -{ -} - int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) { return 1; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 786d90c08f..965c2ad581 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -32,6 +32,8 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" +#include "exec/hwaddr.h" +#include "exec/gdbstub.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" @@ -91,6 +93,92 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) } } +/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ +static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) +{ + static const int xlat[] = { + [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, + [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, + [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, + }; + + CPUClass *cc = CPU_GET_CLASS(cpu); + int cputype = xlat[gdbtype]; + + if (cc->gdb_stop_before_watchpoint) { + cputype |= BP_STOP_BEFORE_ACCESS; + } + return cputype; +} + +static int tcg_insert_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { + break; + } + } + return err; + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_ACCESS: + CPU_FOREACH(cpu) { + err = cpu_watchpoint_insert(cpu, addr, len, + xlat_gdb_type(cpu, type), NULL); + if (err) { + break; + } + } + return err; + default: + return -ENOSYS; + } +} + +static int tcg_remove_breakpoint(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { + break; + } + } + return err; + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_ACCESS: + CPU_FOREACH(cpu) { + err = cpu_watchpoint_remove(cpu, addr, len, + xlat_gdb_type(cpu, type)); + if (err) { + break; + } + } + return err; + default: + return -ENOSYS; + } +} + +static inline void tcg_remove_all_breakpoints(CPUState *cpu) +{ + cpu_breakpoint_remove_all(cpu, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); +} + static void tcg_accel_ops_init(AccelOpsClass *ops) { if (qemu_tcg_mttcg_enabled()) { @@ -109,6 +197,10 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) ops->handle_interrupt = tcg_handle_interrupt; } } + + ops->insert_breakpoint = tcg_insert_breakpoint; + ops->remove_breakpoint = tcg_remove_breakpoint; + ops->remove_all_breakpoints = tcg_remove_all_breakpoints; } static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index a0755e6505..ff9f3f9586 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -49,8 +49,11 @@ #include "sysemu/runstate.h" #include "semihosting/semihost.h" #include "exec/exec-all.h" +#include "exec/hwaddr.h" #include "sysemu/replay.h" +#include "internals.h" + #ifdef CONFIG_USER_ONLY #define GDB_ATTACHED "0" #else @@ -1012,130 +1015,16 @@ void gdb_register_coprocessor(CPUState *cpu, } } -#ifndef CONFIG_USER_ONLY -/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ -static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) -{ - static const int xlat[] = { - [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, - [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, - [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, - }; - - CPUClass *cc = CPU_GET_CLASS(cpu); - int cputype = xlat[gdbtype]; - - if (cc->gdb_stop_before_watchpoint) { - cputype |= BP_STOP_BEFORE_ACCESS; - } - return cputype; -} -#endif - -static int gdb_breakpoint_insert(int type, target_ulong addr, target_ulong len) -{ - CPUState *cpu; - int err = 0; - - if (kvm_enabled()) { - return kvm_insert_breakpoint(gdbserver_state.c_cpu, addr, len, type); - } - - switch (type) { - case GDB_BREAKPOINT_SW: - case GDB_BREAKPOINT_HW: - CPU_FOREACH(cpu) { - err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); - if (err) { - break; - } - } - return err; -#ifndef CONFIG_USER_ONLY - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_ACCESS: - CPU_FOREACH(cpu) { - err = cpu_watchpoint_insert(cpu, addr, len, - xlat_gdb_type(cpu, type), NULL); - if (err) { - break; - } - } - return err; -#endif - default: - return -ENOSYS; - } -} - -static int gdb_breakpoint_remove(int type, target_ulong addr, target_ulong len) -{ - CPUState *cpu; - int err = 0; - - if (kvm_enabled()) { - return kvm_remove_breakpoint(gdbserver_state.c_cpu, addr, len, type); - } - - switch (type) { - case GDB_BREAKPOINT_SW: - case GDB_BREAKPOINT_HW: - CPU_FOREACH(cpu) { - err = cpu_breakpoint_remove(cpu, addr, BP_GDB); - if (err) { - break; - } - } - return err; -#ifndef CONFIG_USER_ONLY - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_ACCESS: - CPU_FOREACH(cpu) { - err = cpu_watchpoint_remove(cpu, addr, len, - xlat_gdb_type(cpu, type)); - if (err) - break; - } - return err; -#endif - default: - return -ENOSYS; - } -} - -static inline void gdb_cpu_breakpoint_remove_all(CPUState *cpu) -{ - cpu_breakpoint_remove_all(cpu, BP_GDB); -#ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(cpu, BP_GDB); -#endif -} - static void gdb_process_breakpoint_remove_all(GDBProcess *p) { CPUState *cpu = get_first_cpu_in_process(p); while (cpu) { - gdb_cpu_breakpoint_remove_all(cpu); + gdb_breakpoint_remove_all(cpu); cpu = gdb_next_cpu_in_process(cpu); } } -static void gdb_breakpoint_remove_all(void) -{ - CPUState *cpu; - - if (kvm_enabled()) { - kvm_remove_all_breakpoints(gdbserver_state.c_cpu); - return; - } - - CPU_FOREACH(cpu) { - gdb_cpu_breakpoint_remove_all(cpu); - } -} static void gdb_set_cpu_pc(target_ulong pc) { @@ -1667,7 +1556,8 @@ static void handle_insert_bp(GArray *params, void *user_ctx) return; } - res = gdb_breakpoint_insert(get_param(params, 0)->val_ul, + res = gdb_breakpoint_insert(gdbserver_state.c_cpu, + get_param(params, 0)->val_ul, get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { @@ -1690,7 +1580,8 @@ static void handle_remove_bp(GArray *params, void *user_ctx) return; } - res = gdb_breakpoint_remove(get_param(params, 0)->val_ul, + res = gdb_breakpoint_remove(gdbserver_state.c_cpu, + get_param(params, 0)->val_ul, get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { @@ -2541,7 +2432,7 @@ static void handle_target_halt(GArray *params, void *user_ctx) * because gdb is doing an initial connect and the state * should be cleaned up. */ - gdb_breakpoint_remove_all(); + gdb_breakpoint_remove_all(gdbserver_state.c_cpu); } static int gdb_handle_packet(const char *line_buf) diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c new file mode 100644 index 0000000000..4e73890379 --- /dev/null +++ b/gdbstub/softmmu.c @@ -0,0 +1,42 @@ +/* + * gdb server stub - softmmu specific bits + * + * Debug integration depends on support from the individual + * accelerators so most of this involves calling the ops helpers. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/gdbstub.h" +#include "exec/hwaddr.h" +#include "sysemu/cpus.h" +#include "internals.h" + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->insert_breakpoint) { + return ops->insert_breakpoint(cs, type, addr, len); + } + return -ENOSYS; +} + +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->remove_breakpoint) { + return ops->remove_breakpoint(cs, type, addr, len); + } + return -ENOSYS; +} + +void gdb_breakpoint_remove_all(CPUState *cs) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->remove_all_breakpoints) { + ops->remove_all_breakpoints(cs); + } +} diff --git a/gdbstub/user.c b/gdbstub/user.c new file mode 100644 index 0000000000..42652b28a7 --- /dev/null +++ b/gdbstub/user.c @@ -0,0 +1,62 @@ +/* + * gdbstub user-mode helper routines. + * + * We know for user-mode we are using TCG so we can call stuff directly. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "exec/gdbstub.h" +#include "hw/core/cpu.h" +#include "internals.h" + +int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { + break; + } + } + return err; + default: + /* user-mode doesn't support watchpoints */ + return -ENOSYS; + } +} + +int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len) +{ + CPUState *cpu; + int err = 0; + + switch (type) { + case GDB_BREAKPOINT_SW: + case GDB_BREAKPOINT_HW: + CPU_FOREACH(cpu) { + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { + break; + } + } + return err; + default: + /* user-mode doesn't support watchpoints */ + return -ENOSYS; + } +} + +void gdb_breakpoint_remove_all(CPUState *cs) +{ + cpu_breakpoint_remove_all(cs, BP_GDB); +} diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 23b30484b2..61b27ff59d 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -617,6 +617,13 @@ void cpus_register_accel(const AccelOpsClass *ops) cpus_accel = ops; } +const AccelOpsClass *cpus_get_accel(void) +{ + /* broken if we call this early */ + assert(cpus_accel); + return cpus_accel; +} + void qemu_init_vcpu(CPUState *cpu) { MachineState *ms = MACHINE(qdev_get_machine()); diff --git a/gdbstub/meson.build b/gdbstub/meson.build index 6d4ae2d03c..fc895a2c39 100644 --- a/gdbstub/meson.build +++ b/gdbstub/meson.build @@ -1 +1,9 @@ +# +# The main gdbstub still relies on per-build definitions of various +# types. The bits pushed to softmmu/user.c try to use guest agnostic +# types such as hwaddr. +# + specific_ss.add(files('gdbstub.c')) +softmmu_ss.add(files('softmmu.c')) +user_ss.add(files('user.c')) From patchwork Tue Sep 27 14:15:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609613 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp429907pvb; Tue, 27 Sep 2022 08:54:22 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5/J7IQqqdtVkpc4RNt6uEnTxkFrQ90gxtU3mIvN5IvMSN9IDK+pRWOaMovDdLWi727y55J X-Received: by 2002:a05:6214:4017:b0:4ac:6db5:66f0 with SMTP id kd23-20020a056214401700b004ac6db566f0mr22416341qvb.105.1664294061850; Tue, 27 Sep 2022 08:54:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664294061; cv=none; d=google.com; s=arc-20160816; b=ZycIld+dhqjzMGDt7lgJ+9aQl+X2dCGmy4ZWmt8xu1vceI+oJ5FSDoN524iKL0Rt77 vsCMngB2Cd/AcMqsUbvx8BrhUPRuFbCNAeHE9NZIReoTRPgmFYI3taxOAi8b3Jbwnu6j QDr+m9UWEzzUkWSwY+7IVji8wv0RzpX+oQjN5txHcCjG2VKooxBQin9GgoRIBicVd4mK O/EkF2EMQ7+A2eI13z2JnkDP50S+1d8g9UsYZAEUAv6VIHMNL0iM2fqlJFAq2wF1KdjN 3xq4dmvFnDihIMdK+o3exE///pTDij36wDQLRpoRYCt7MBp0VL4n46uD/rniN+4bhB0+ 104Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vjojPbAZCZTm66THKz2INVh3tZm0jABrqXmO5V1a0wU=; b=A+R3xPGzVP8iZgtXxuoe6Zn7RoN/myWtJiEv3f5auZWf3zeH9ZX/orbVCo8AXmEssJ Y0CLdpLXZ5xTPpF0dKHppd1apiSVo4W+lLUbVe15kz/6IgeFp6DtxmTVesAVujjdyj1d MTDSIRiWPN8G1AYYcqArYbpzt4s1ggrassI/W/5rGOQlN+5kDG352LLfnjgO5llIzbNe SejBC2yBKp0Tk9fkCVhwvc8btigsmPJdxYgNO4FaLFiybdoWUCKXHVJcNl5bLOBPTcHF 5TnGxzUbkdI1cLt08oUx/JNFA6KlstuSflWzlI8GY50fFje+JiqwRNqwmtOyShi32wbS SM5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bOncOETT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i2-20020a05620a27c200b006be5a7cd63csi1023448qkp.224.2022.09.27.08.54.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:54:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bOncOETT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36664 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCub-0001z8-Cm for patch@linaro.org; Tue, 27 Sep 2022 11:54:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMp-0005Et-QD for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:23 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:46734) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMl-00062E-Ki for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:22 -0400 Received: by mail-wm1-x336.google.com with SMTP id n40-20020a05600c3ba800b003b49aefc35fso5517191wms.5 for ; Tue, 27 Sep 2022 07:15:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=vjojPbAZCZTm66THKz2INVh3tZm0jABrqXmO5V1a0wU=; b=bOncOETTUL52OFCBTuM6WiteaXsBwHa8z81wgpPagwiAIvVOm4UmMX1d3Gr7Pnz+/S e0qWcNNoSWL3Ac3fbZeK0pTCVRYP38cmKZjSJV3f7dth683kApw0iKYbunASionRqiFi Zw+6NpqJgTW8n7Ea8urXSsQ431pj5nF3hdXI5IKF3ztD/b8eDRYCoAMFEHjACwa4PCBx woURAwnaHiQBJ1eIV5tYz+H+gTkvrBmMsx0BQX7g3uFG0dB3illtXRJ0l/KcXsBkFRoc tzc1kkTLFIXbz4JMFBnb2Vy7DXHaD7W8y0/RWbg57yKnzDP92y/X/wBf7SdSiNKGnIRr DbLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=vjojPbAZCZTm66THKz2INVh3tZm0jABrqXmO5V1a0wU=; b=LpOOLEpPYUE9EZfPsI767t27I8qa/UAiRwUvPLLrt2IVlZYCYljx4bCS7tSrhg+mdn CE0Wlb29WJ3AG9Z3PumRypRhWcTEKRESUjm7T8JmBTNU/pQsiuSRXu90L/pMPQ1vhnKK C0MXmUvRv9qUyff2aPtFBEb4W/bQ03ppz+7A8AlIK/wbV32lgliRE3k5H1vYZm4VTile cynCnYhOHJ0zkmDNJ/pO2GdjH0zSCUVS/LDiY1wcduEC0ZpZSYVWYyPal87zx7FsH7t3 nJbGwg8lcr35OZS7FRFT7XUdBkop7Q3oYfnnRixX+QSTwQySxFjNSDDsKmHUeopgSPw6 mkkg== X-Gm-Message-State: ACrzQf3heezarhT1p32BKWWg0M5VqcJyN3ngzsEDEjASd2o+RPxPycsH dv99SDil3BmI7pj31Dk4CwqsHQ== X-Received: by 2002:a1c:4c18:0:b0:3b4:9b1d:5501 with SMTP id z24-20020a1c4c18000000b003b49b1d5501mr2884277wmf.13.1664288116334; Tue, 27 Sep 2022 07:15:16 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id d4-20020adffd84000000b0022b0064841esm1281877wrr.59.2022.09.27.07.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:11 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0308F1FFBA; Tue, 27 Sep 2022 15:15:09 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= , Mads Ynddal , Paolo Bonzini , Richard Henderson , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v3 14/15] gdbstub: move guest debug support check to ops Date: Tue, 27 Sep 2022 15:15:03 +0100 Message-Id: <20220927141504.3886314-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes the final hard coding of kvm_enabled() in gdbstub and moves the check to an AccelOps. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Cc: Mads Ynddal Reviewed-by: Mads Ynddal --- accel/kvm/kvm-cpus.h | 1 + gdbstub/internals.h | 1 + include/sysemu/accel-ops.h | 1 + include/sysemu/kvm.h | 7 ------- accel/kvm/kvm-accel-ops.c | 1 + accel/kvm/kvm-all.c | 6 ++++++ accel/tcg/tcg-accel-ops.c | 6 ++++++ gdbstub/gdbstub.c | 5 ++--- gdbstub/softmmu.c | 9 +++++++++ gdbstub/user.c | 6 ++++++ 10 files changed, 33 insertions(+), 10 deletions(-) diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index 33e435d62b..fd63fe6a59 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -18,6 +18,7 @@ void kvm_destroy_vcpu(CPUState *cpu); void kvm_cpu_synchronize_post_reset(CPUState *cpu); void kvm_cpu_synchronize_post_init(CPUState *cpu); void kvm_cpu_synchronize_pre_loadvm(CPUState *cpu); +bool kvm_supports_guest_debug(void); int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); int kvm_remove_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len); void kvm_remove_all_breakpoints(CPUState *cpu); diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 41e2e72dbf..eabb0341d1 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -9,6 +9,7 @@ #ifndef _INTERNALS_H_ #define _INTERNALS_H_ +bool gdb_supports_guest_debug(void); int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); void gdb_breakpoint_remove_all(CPUState *cs); diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 86794ac273..8cc7996def 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -47,6 +47,7 @@ struct AccelOpsClass { int64_t (*get_elapsed_ticks)(void); /* gdbstub hooks */ + bool (*supports_guest_debug)(void); int (*insert_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); int (*remove_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); void (*remove_all_breakpoints)(CPUState *cpu); diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 21d3f1d01e..6e1bd01725 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -46,7 +46,6 @@ extern bool kvm_readonly_mem_allowed; extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; -extern bool kvm_has_guest_debug; #define kvm_enabled() (kvm_allowed) /** @@ -168,11 +167,6 @@ extern bool kvm_has_guest_debug; */ #define kvm_msi_devid_required() (kvm_msi_use_devid) -/* - * Does KVM support guest debugging - */ -#define kvm_supports_guest_debug() (kvm_has_guest_debug) - #else #define kvm_enabled() (0) @@ -190,7 +184,6 @@ extern bool kvm_has_guest_debug; #define kvm_direct_msi_enabled() (false) #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) -#define kvm_supports_guest_debug() (false) #endif /* CONFIG_KVM_IS_POSSIBLE */ diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 5c0e37514c..fbf4fe3497 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -99,6 +99,7 @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; #ifdef KVM_CAP_SET_GUEST_DEBUG + ops->supports_guest_debug = kvm_supports_guest_debug; ops->insert_breakpoint = kvm_insert_breakpoint; ops->remove_breakpoint = kvm_remove_breakpoint; ops->remove_all_breakpoints = kvm_remove_all_breakpoints; diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index b8c734fe3a..6ebff6e5a6 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3287,6 +3287,12 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return data.err; } +bool kvm_supports_guest_debug(void) +{ + /* probed during kvm_init() */ + return kvm_has_guest_debug; +} + int kvm_insert_breakpoint(CPUState *cpu, int type, hwaddr addr, hwaddr len) { struct kvm_sw_breakpoint *bp; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 965c2ad581..19cbf1db3a 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -93,6 +93,11 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) } } +static bool tcg_supports_guest_debug(void) +{ + return true; +} + /* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) { @@ -198,6 +203,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) } } + ops->supports_guest_debug = tcg_supports_guest_debug; ops->insert_breakpoint = tcg_insert_breakpoint; ops->remove_breakpoint = tcg_remove_breakpoint; ops->remove_all_breakpoints = tcg_remove_all_breakpoints; diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index ff9f3f9586..be88ca0d71 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -45,7 +45,6 @@ #include "qemu/sockets.h" #include "sysemu/hw_accel.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "semihosting/semihost.h" #include "exec/exec-all.h" @@ -3447,8 +3446,8 @@ int gdbserver_start(const char *device) return -1; } - if (kvm_enabled() && !kvm_supports_guest_debug()) { - error_report("gdbstub: KVM doesn't support guest debugging"); + if (!gdb_supports_guest_debug()) { + error_report("gdbstub: current accelerator doesn't support guest debugging"); return -1; } diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 4e73890379..f208c6cf15 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -15,6 +15,15 @@ #include "sysemu/cpus.h" #include "internals.h" +bool gdb_supports_guest_debug(void) +{ + const AccelOpsClass *ops = cpus_get_accel(); + if (ops->supports_guest_debug) { + return ops->supports_guest_debug(); + } + return false; +} + int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) { const AccelOpsClass *ops = cpus_get_accel(); diff --git a/gdbstub/user.c b/gdbstub/user.c index 42652b28a7..033e5fdd71 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -14,6 +14,12 @@ #include "hw/core/cpu.h" #include "internals.h" +bool gdb_supports_guest_debug(void) +{ + /* user-mode == TCG == supported */ + return true; +} + int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len) { CPUState *cpu; From patchwork Tue Sep 27 14:15:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 609616 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp437308pvb; Tue, 27 Sep 2022 09:05:12 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5PJ5welomWMkbzjScinuK0KxK5vgh4RWFVPk78TZ3PhYclml5/y9sRwmEYecig6dN8RbBY X-Received: by 2002:ac8:7d90:0:b0:35b:afd3:20aa with SMTP id c16-20020ac87d90000000b0035bafd320aamr22576200qtd.252.1664294711962; Tue, 27 Sep 2022 09:05:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664294711; cv=none; d=google.com; s=arc-20160816; b=Qxem3zDTRm8/epjLUiFvm9UDjy+CL5C2qzIKLCgHq9zbMDLBIf6l00W/KokbxgqSA0 N0buinmPloO5RTj2/dk5ppingsQUpbCO3WsnyOWfY5bFqKbwHUMxaQ4OQE6csQuS56Kb Uz1JKXlZ+B5xjvYPow3TxKbxfKca52ixdjRl0QA2vkMrxbFWEOKHA18hrQUR0LKbjLk8 3nFPVxBc1HmdFDjMKYUiKFxUfTsRymHIV8NHIFYisBkIRsENIA/TqP96yAxAaDLawFzy oR4l7CpBsV+GP9zGeBonJ0dkdpC/AYHEiP2rcpSNezsODcFQN7h7z5sISMCB7BaiG6qp 56tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ICOJrCaCj9cyypnb7sgwStZZcWx3y8ZLrngrBB6RAFU=; b=Zi2vECnskir3i4NOMy6f9yoDnljiqztCbmmPeQb59gN6mkUxNL+nquPR8DA6ij5E0k 8Ho5QHGUHui2CTMUdiW4jG5G3LGIWyuVAYc78m3PpT15GyIzJr9NrZ372gDdMk3yh3MD dr00m/TAI99GePhYRCKB8wKREdUhs5rRWegwI1pkfBSIyXgWr1SS0oKZmwjhTwYgkhIB ag6Bmg+KoCVsiCxpS3sbbgRG73XH1o2Nk/l1agTmd201lWdB5HJSk214Rdm180IBGbiP B+d1H/tWIwI9LJsPyyDpB3ykcRmDrhO/3umKupRzG1GV014C8fpZJry4Ml2eu1m1jvxX M4yQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qSrmH2UB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h5-20020ab03345000000b003c6ff9fbe20si418578uap.154.2022.09.27.09.05.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 09:05:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qSrmH2UB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odD55-0006PZ-Fz for patch@linaro.org; Tue, 27 Sep 2022 12:05:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBWH-0005UO-UX for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:25:33 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35525) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBW2-0007RT-Ee for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:24:56 -0400 Received: by mail-wr1-x435.google.com with SMTP id r7so15302968wrm.2 for ; Tue, 27 Sep 2022 07:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ICOJrCaCj9cyypnb7sgwStZZcWx3y8ZLrngrBB6RAFU=; b=qSrmH2UBqPGT3YtEKljR+7n1k28yT2fED4/Whs/vCufLDoNUyGR2oIWHc3iF6kxtwZ Rf9xybgycx5I2GGXrnIfEaM5kJ27o+t8ENJNXuhDR5i1jBff3sM0cjqZapc7l0/NWv6n yiP1gmijwk0D2UXxGGQ5OFCp0+pfAntQ6Ssqmbs+r1Z3MawYwRclGYKgi83oWCQWON9j ynEaFy0Ht2JCUvYTkL5L++MUyul44TYB6/pIVLZHVGkwRh6vZCEwEcqoNtia2ob4tnKJ OSkDYzpL2RfZ7weqMVIjGKxVOdRLPQipPI66BqdYGweZf4Siew6jqpHYfGouzsHl5pZA 3urA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ICOJrCaCj9cyypnb7sgwStZZcWx3y8ZLrngrBB6RAFU=; b=df/Cz+W62YWIlp92XV0OnQHQJ9G8MY5+Uv75B2emVRip0j35NNxNzh/FKX7cP7tFH/ ot4fpid++eYQh/YFuhX2O7RY9Q3yqgujGqg7McEK2BttbfkRKqYVk3ZXZ5AzO6UZZWqj Pz330R5SvJdBFYuy1ajCSB7BYbWZ/+r5vnQc0s1xR3FmJrsHUVS6cvyF00A7oQXHAvd+ 9rFvWI5jt9Yczq0L3fMlqNnEDavsQsZZu6LZkLjURuSYqMZm79oWJ32XDYDgeENxHABz gO3X2xMeT1R77Nk3xACwfaKuKG/vtNcnKA5MVu43SsdcUFfRA76JFOcM7QhZITrT6YoS ekag== X-Gm-Message-State: ACrzQf0ffN/oUdgORY1RBKJxb376pz2vrS765CHa38WcSFWR4fjoMVdK eBfVRzXn6tRQJhVP1aFfV1Pk/g== X-Received: by 2002:a5d:598f:0:b0:22a:f74d:ae24 with SMTP id n15-20020a5d598f000000b0022af74dae24mr17220870wri.544.1664288692690; Tue, 27 Sep 2022 07:24:52 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id n43-20020a05600c502b00b003b486027c8asm14419123wmr.20.2022.09.27.07.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:24:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4DFBC1FFBC; Tue, 27 Sep 2022 15:15:09 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Paolo Bonzini , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v3 15/15] accel/kvm: move kvm_update_guest_debug to inline stub Date: Tue, 27 Sep 2022 15:15:04 +0100 Message-Id: <20220927141504.3886314-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- include/sysemu/kvm.h | 16 ++++++++++++++++ accel/kvm/kvm-all.c | 6 ------ accel/stubs/kvm-stub.c | 5 ----- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 6e1bd01725..790d35ef78 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -247,7 +247,23 @@ int kvm_on_sigbus(int code, void *addr); void kvm_flush_coalesced_mmio_buffer(void); +/** + * kvm_update_guest_debug(): ensure KVM debug structures updated + * @cs: the CPUState for this cpu + * @reinject_trap: KVM trap injection control + * + * There are usually per-arch specifics which will be handled by + * calling down to kvm_arch_update_guest_debug after the generic + * fields have been set. + */ +#ifdef KVM_CAP_SET_GUEST_DEBUG int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap); +#else +static inline int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) +{ + return -EINVAL; +} +#endif /* internal API */ diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 6ebff6e5a6..423fb1936f 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3395,12 +3395,6 @@ void kvm_remove_all_breakpoints(CPUState *cpu) } } -#else /* !KVM_CAP_SET_GUEST_DEBUG */ - -static int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) -{ - return -EINVAL; -} #endif /* !KVM_CAP_SET_GUEST_DEBUG */ static int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset) diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 2d79333143..5d2dd8f351 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -46,11 +46,6 @@ int kvm_has_many_ioeventfds(void) return 0; } -int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) -{ - return -ENOSYS; -} - int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) { return 1;