From patchwork Fri Feb 22 02:41:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158968 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1218919jaa; Thu, 21 Feb 2019 18:51:04 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia8kSUeizpidHIPzgN9Hz6hs8GXB4Q+krazXwN3ZF0r+8FR+/dreWOzRoTszJJzTQlDxWmL X-Received: by 2002:a25:aa8d:: with SMTP id t13mr1605328ybi.143.1550803864673; Thu, 21 Feb 2019 18:51:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550803864; cv=none; d=google.com; s=arc-20160816; b=D9VYFFKFdvMArCtEvZsv66ei3HZsev+vqNMWvzs9/I9bCrRnKlv7L8hwC2rXZ2LFb7 PLX24wH0B8U0FGC6f07Adp0zCNSflf0Y0RYbjOdgiUnZiApZwrxPr615Jg0Ro3+nmhWX SXxv1w531sqKgG7EJYAYLNvzSGg/rdSsC8ELWPN+E3rDJc+UDHR/6WMe6PxzlGdIFojy uzT+65udRoLGgBTAULFiJBE6OIXoKNbhM4VLop5rF2sMyzSiuT4iTXdh69B5wj9+c/dL miTskJEiS85YsK4IPUqhHSRjM600+ghzLNwgsgr/jPDw7j6zeTzrzSV6nH0AX0SxMWYj v9PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CBQ8Xc2iiIXC8ygx5OS3Q6XQ/FWqjNqGCzR2YV4MDI8=; b=t0svi8bbwK30symXjPBK3ZULj/gmk1E1nhEukf2NAEjiWzCwXOAnPnil6PmXJGpdbO fucOT2FYBFsYezlpExET6CKLfdEdcQ9zBZ9ZTKyAPRaooBpLxWjY5JHFOu1FghHD9ux1 w+S+81VZAxLyL1v60I4wfZvA9aHNSBAuCbNPIjOwLeSzPMv9GuZECApBewg+0fEy6kio e4/T0l2SJGf6BA5m/P9iO5S4lMAKNc2wAO3U1dALbPEKbtEiHr0HQo7TchsmPYMYlgl4 e8wAdj1ix+QbS4q+Y614loJKMSvXZJ5WceuK9EriHGDOKOiQWtOuZRBUzK8UhITjPEtT iNdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="b6A/M7LR"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o12si141701ybk.74.2019.02.21.18.51.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 21 Feb 2019 18:51:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="b6A/M7LR"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:43059 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx0vY-0003Pi-3K for patch@linaro.org; Thu, 21 Feb 2019 21:51:04 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx0mf-0005Ap-UG for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gx0mU-0005BG-QY for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:45 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:38207) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gx0mU-0004ZG-3y for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:42 -0500 Received: by mail-pf1-x429.google.com with SMTP id n125so384710pfn.5 for ; Thu, 21 Feb 2019 18:41:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CBQ8Xc2iiIXC8ygx5OS3Q6XQ/FWqjNqGCzR2YV4MDI8=; b=b6A/M7LRo7nTov26SXnejYZzXSS1/K/AO4JIo65sv0MAq10Y5l0YIUuX7KVPnrw0Vs mE6z3teLIp4Duj6/WBJN73lSqn3GeRoEH+PMQ0BNFZ8HjIazHII04RRtEGCN1cquZ9KR RRyoSjM3LlWphP/uV4u5x+iVUt+5szrOK4HERiYEgz13T5hrcBqx5vGHnxbdBIImZyWu 7hqlBoPGnbOZwfie55vx/4vQVjhk6oHzQScVvYU/wLBVGw0Bo1Tdlc+XmCyRpNn/01Oq WojJpDACyh4VAsaX670ZUEZ14mqtQzOYQw9ClDaCta3g7LjE8eJ6fy8ycRc0yKpThHbr GkLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CBQ8Xc2iiIXC8ygx5OS3Q6XQ/FWqjNqGCzR2YV4MDI8=; b=S/RriYo9fPnP6VMiPbVxc/lBr07DpYWuGs1e+PG5UVAIW0MHTv04RdNLudsMtoa9p9 ckCZGodG77m3X0izr1j8Wh500lvfPPNsgUZZdpHeF++ps5pQCGD4W3OBlw67kxLvsrcm 9r/amm+e6dcMnzqOrSNKQrPVnZbJfMzqCC8uhZR0MBcoe1Mxse9TdkU4ZA86ibxNK01w TPZ/N/SnF4naqTj1U1sSsS/jpMaM+IzDFUjfCBuh6Oij2jhAGIU0iKpUgqxVwdl77wXz 6ejHPu02H7yyVw38hVjrwNZEeyS28fM8PUgDLaj2Z4aCsC0EAFuuePfQ4t0M2YzJBfxW T4aw== X-Gm-Message-State: AHQUAuYGognzrOTJYsGz1oHEHbcPYtyjitsQtHKO8uj/ILh4SjEIfXRw DMs6AIA1VLDlXDhBJ0jV97r0s5UTHHs= X-Received: by 2002:a62:e911:: with SMTP id j17mr1324190pfh.107.1550803270024; Thu, 21 Feb 2019 18:41:10 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id v6sm187429pgb.2.2019.02.21.18.41.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 18:41:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 21 Feb 2019 18:41:04 -0800 Message-Id: <20190222024106.9167-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190222024106.9167-1-richard.henderson@linaro.org> References: <20190222024106.9167-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH v3 1/3] target/arm: Split out recompute_hflags et al X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will use these to minimize the computation for every call to cpu_get_tb_cpu_state. For now, the env->hflags variable is not used. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v3: Do not cache VECLEN, VECSTRIDE, VFPEN. Move HANDLER and STACKCHECK to rebuild_hflags_a32. --- target/arm/cpu.h | 28 +++-- target/arm/helper.h | 3 + target/arm/internals.h | 3 + target/arm/helper.c | 254 ++++++++++++++++++++++++----------------- 4 files changed, 175 insertions(+), 113 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 84ae6849c2..30532bf53e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -240,6 +240,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3065,25 +3068,28 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) -FIELD(TBFLAG_A32, VECLEN, 1, 3) -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) -FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime @@ -3105,7 +3111,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) @@ -3190,6 +3196,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.h b/target/arm/helper.h index 923e8e1525..bbc1a48089 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -89,6 +89,9 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, i32) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..8c1b813364 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); +uint32_t rebuild_hflags_a32(CPUARMState *env, int el); +uint32_t rebuild_hflags_a64(CPUARMState *env, int el); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index a018eb23fe..29486a09f6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13886,139 +13886,183 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif +static uint32_t common_hflags(CPUARMState *env, int el, ARMMMUIdx mmu_idx, + int fp_el, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, + arm_to_core_mmu_idx(mmu_idx)); + if (arm_cpu_data_is_big_endian(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + return flags; +} + +uint32_t rebuild_hflags_a32(CPUARMState *env, int el) +{ + uint32_t flags = 0; + ARMMMUIdx mmu_idx; + int fp_el; + + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); + + if (arm_v7m_is_handler_mode(env)) { + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + } + + mmu_idx = arm_mmu_idx(env); + + /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is + * suppressing them because the requested execution priority is less than 0. + */ + if (arm_feature(env, ARM_FEATURE_V8) && + arm_feature(env, ARM_FEATURE_M) && + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + } + + fp_el = fp_exception_el(env, el); + return common_hflags(env, el, mmu_idx, fp_el, flags); +} + +uint32_t rebuild_hflags_a64(CPUARMState *env, int el) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + int fp_el = fp_exception_el(env, el); + uint32_t flags = 0; + uint64_t sctlr; + int tbii, tbid; + + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* Get control bits for tagged addresses. */ + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid = p0.tbi; + tbii = tbid & !p0.tbid; + } + + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, cpu)) { + int sve_el = sve_exception_el(env, el); + uint32_t zcr_len; + + /* If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el != 0 && fp_el == 0) { + zcr_len = 0; + } else { + zcr_len = sve_zcr_len_for_el(env, el); + } + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[el]; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, cpu)) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + } + + return common_hflags(env, el, mmu_idx, fp_el, flags); +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + int el = arm_current_el(env); + env->hflags = (is_a64(env) + ? rebuild_hflags_a64(env, el) + : rebuild_hflags_a32(env, el)); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, uint32_t el) +{ + tcg_debug_assert(!is_a64(env)); + env->hflags = rebuild_hflags_a32(env, el); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, uint32_t el) +{ + tcg_debug_assert(is_a64(env)); + env->hflags = rebuild_hflags_a64(env, el); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); - int fp_el = fp_exception_el(env, current_el); - uint32_t flags = 0; + uint32_t flags; + uint32_t pstate_for_ss; + *cs_base = 0; if (is_a64(env)) { - ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t sctlr; - *pc = env->pc; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } - - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el = sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, current_el); - } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - if (current_el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[current_el]; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } - flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); - } + flags = rebuild_hflags_a64(env, current_el); + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; + flags = rebuild_hflags_a32(env, current_el); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); + flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); - flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); + pstate_for_ss = env->uncached_cpsr; } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } - } - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); - - if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); - } - - /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is - * suppressing them because the requested execution priority is less than 0. - */ - if (arm_feature(env, ARM_FEATURE_V8) && - arm_feature(env, ARM_FEATURE_M) && - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) + && (pstate_for_ss & PSTATE_SS)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } *pflags = flags; - *cs_base = 0; } #ifdef TARGET_AARCH64 From patchwork Fri Feb 22 02:41:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158969 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1224712jaa; Thu, 21 Feb 2019 19:00:11 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia82VcIygVX+g8WaQcXdNAktwj/c7mCw/YvNoX314BkQda6oHpBhXB/hCK1Kfur6c3bwQYy X-Received: by 2002:a81:6385:: with SMTP id x127mr1551045ywb.450.1550804411595; Thu, 21 Feb 2019 19:00:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550804411; cv=none; d=google.com; s=arc-20160816; b=cuot8Bq/iSbFlQ1gXLEEJdWX8CIFo1JHQJjB5uvfhiQGBUwTHVYDbLDxS0RlrGUn7H EppkESWx0ah1S4kVuTZ2/v7CvkrPTdmS+T668xS89qhPHLaiK7+/b1d1qmep5CgjN9lq P0ccNqZ9y7E3HJXW3YtONsuQxSjsEpK06YKkGIZZV6yxk5dvQXcTprK4Eyxh0Fkw8fKI cSPOol3oJ5bxGlYQiuyhOgKtZiTCZQ3NYxkHlUOMunLkT/zhDk89SitJcc8g8wYQWrSN wmDkkld0TFoR6U4ZuhSpEmMnwjTgnFT4cN5B1KBHOtgAgeDFLM83Ywf2ZsMdqyd5ZkKR iutQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=jTRGT1JA87ZJcxIZDZl7HvmmMpohbUTfLdwB8l5Rhhs=; b=TQAjZfAPbFMhMLzACoWZ0Z4IlCNNJxbFuuWdC6fKfDk0ZXsxlQktn1rSq7311VXNRP Hie/FJlcsDnFpCZx7WQkRDQ6ad5ZIaHNKSZXk9s+mHf9YQAu6dYpeqN1bu3EB9EXbwM7 Iw+bpcr4UkbzFqUYoDMXkuAXEH7fteHyKO2OBnuFqabHm5ZP+UjP4uEay4jsfGTp41E0 JiXIcDiS7dCClcYB08uuBNwI3qpHAaqhSurzrHSwZDvHkTg2x9evCxMGUpalTv4OY3TD QcgLRGtHFtT/duGMfsdNzu8nAg8dqZWTETzUZf4VoLISboCmxtPJLosipPxbli9Um74g OiKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VhYaYin3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n19si130021yba.200.2019.02.21.19.00.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 21 Feb 2019 19:00:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VhYaYin3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:43175 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx14N-00022d-4Y for patch@linaro.org; Thu, 21 Feb 2019 22:00:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50573) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx0mU-00052B-MM for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gx0mS-00057S-UU for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:42 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:45521) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gx0mS-0004bR-5E for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:40 -0500 Received: by mail-pg1-x543.google.com with SMTP id y4so365417pgc.12 for ; Thu, 21 Feb 2019 18:41:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jTRGT1JA87ZJcxIZDZl7HvmmMpohbUTfLdwB8l5Rhhs=; b=VhYaYin3X/ymM/dFQvV5bKZcN2JrG6J5TaT4mKq5VhEgSjUhpxXpMhejT6YqgcAdXv ZxokP1rE/S6mK1woqrVo7Ah1lkrTRYdb4iUtjFfiRA3gKDmyS74+a2NN3R7ZYTMkbwf0 7Kk+SgOcon/3KX/+7ky0bM1//HGtf8lD+7NWcjG+O5S6XyQsAYxL8VwWjE/bxfy2SIbd 2qxMPRM15MRDiiAOpyGNsddEzKYjSx07Li517jkm9isCTJLMbu4kKOaARLdsZgr0laNE WorlXHYMc1BYdF9MDz5YEXqP3dR6DTWOcOnudvbPa1vAysqCD412a459VYsOHWuHeOlu e3EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jTRGT1JA87ZJcxIZDZl7HvmmMpohbUTfLdwB8l5Rhhs=; b=YJmWM2s5lzlBA2Q1DS/9dRCejgFIzH+2vAVPIXAbY746oz4OrQBlQgH9OvBomIv3WG FEPjhVTkgq2A1bmWE/FG0Rx7qYRajZHUHRgRUIWU0z20mAZcLp8DZ/O5Vg9dODhRWEk6 MFbaJ8tTHllafCFPp4gd7oLIM13fXiLTpXvAgLPZx4GvcMHbMc3EaysW4uxUfxLtLbMC I1+VdpDNhllGLLL+NWvu6bPOTxvPTlzQT9a9OXHl18nNbcAZHJkBK2C9H3IFIhslhUsj UplcRug244DcOYmDKgAWY3GOO/8wJ4nxIM+DZL/+4lZPSp5Knd8GWRAMC31e930btVvG /cUw== X-Gm-Message-State: AHQUAua+gKe8dohzk0kCCUAXJK5tg4vvGxz+jgemjeS1GDCyI6rYE5Y6 RQGYpJrhFAk0k8gdXlIS9LsEGUNIMbM= X-Received: by 2002:a62:ee03:: with SMTP id e3mr1802379pfi.241.1550803271453; Thu, 21 Feb 2019 18:41:11 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id v6sm187429pgb.2.2019.02.21.18.41.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 18:41:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 21 Feb 2019 18:41:05 -0800 Message-Id: <20190222024106.9167-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190222024106.9167-1-richard.henderson@linaro.org> References: <20190222024106.9167-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 2/3] target/arm: Rebuild hflags at el changes and MSR writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Fixed partial conversion to assignment to env->hflags. --- target/arm/internals.h | 1 + linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + target/arm/translate-a64.c | 6 +++++- target/arm/translate.c | 14 ++++++++++++-- 9 files changed, 27 insertions(+), 3 deletions(-) -- 2.17.2 diff --git a/target/arm/internals.h b/target/arm/internals.h index 8c1b813364..235f4fafec 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -970,5 +970,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, uint32_t rebuild_hflags_a32(CPUARMState *env, int el); uint32_t rebuild_hflags_a64(CPUARMState *env, int el); +void rebuild_hflags_any(CPUARMState *env); #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5bbb72f3d5..123f342bdc 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9691,6 +9691,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); ret = vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..e4da513eb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -390,6 +390,7 @@ static void arm_cpu_reset(CPUState *s) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 70850e564d..17200f1288 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -995,6 +995,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } else { env->regs[15] = new_pc & ~0x3; } + env->hflags = rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1006,10 +1007,12 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc = new_pc; + env->hflags = rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index 29486a09f6..1140739d6b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9201,6 +9201,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; + env->hflags = rebuild_hflags_a32(env, arm_current_el(env)); } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -9546,6 +9547,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; + env->hflags = rebuild_hflags_a64(env, new_el); aarch64_restore_sp(env, new_el); env->pc = addr; diff --git a/target/arm/machine.c b/target/arm/machine.c index 124192bfc2..e944d6b736 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -743,6 +743,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..f82eeae7e4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -571,6 +571,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) */ env->regs[15] &= (env->thumb ? ~1 : ~3); + env->hflags = rebuild_hflags_a32(env, arm_current_el(env)); qemu_mutex_lock_iothread(); arm_call_el_change_hook(arm_env_get_cpu(env)); qemu_mutex_unlock_iothread(); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index af8e4fd4be..a786c7ef5f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1841,11 +1841,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->base.is_jmp = DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); s->base.is_jmp = DISAS_UPDATE; } } diff --git a/target/arm/translate.c b/target/arm/translate.c index dac737f6ca..1cdb575ccd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8563,6 +8563,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -8735,15 +8737,23 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } + need_exit_tb = false; if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + need_exit_tb = true; + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + need_exit_tb = true; + } + if (need_exit_tb) { gen_lookup_tb(s); } From patchwork Fri Feb 22 02:41:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158970 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1225875jaa; Thu, 21 Feb 2019 19:01:27 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ6m1zz5rI7Di5NeVi2uqFtS0bPEGHmcyxyHAQ5tYavGuik0nvtqE4L/QeZmKqCI9jdkp1H X-Received: by 2002:a5b:706:: with SMTP id g6mr1522654ybq.330.1550804487762; Thu, 21 Feb 2019 19:01:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550804487; cv=none; d=google.com; s=arc-20160816; b=iuHZSSi1bd7NKkRqpniCpfej/ifVkp+NbWUE5hbaOmd2qFdOescSaij1yJ2Z3M5GcQ dLnHJdXEduG421dJjhqR4yiroyqirJhngglNPXeLnFNlLnti46tWYAtnuw6gcAytUL+m K2j5LkxNcVMWanFnq2DE22Caqu2t5kvFA6fgtRdhUtVgPnZt9ditXGO+vaPOKbXXYYEd tkvFNeE3Ao2traE5xpgmXl+FTjSrhoSzUgONCASnCnTsvRH4IyC4EH8hw/A5nAOaz4p1 9gWFPG+Srql6Vi5i7La4TUWatHlBn9x0qjQBN2mP2vl/6Sdy4ubA5rBexCqR6rxM1gsB IGZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7za0oe+S+pDjXtPVWoLW1jUXBpKdAwHxIVRqazhFQik=; b=cOaEEsC659EpgpIe3249q4AK0DdPgDOc9nwIABno5CvBUk2ijvNhi3z0VOB94UddXP S0dU+qCFTm/pJKlaMGKykTEV0fMfY9PGZweMsPY/0XJVafFpVPFrww2MI6Plq3+gDBXh ZEDPXpaE9NhpwleJXJ9Z+5GxtZ0JJ0JQEQYkQqk9qeNrv0KD9sBvkzX+0/fdbzkaWRH+ m4SbZ6LHh+BWnvmX9hwwpu+nzaZZEMVgTeojcFU/lOhITH8tzzuFACO3lbRX7zKYgw5D XptWilDIg2Ht0i3HAIigFdigVOfWqriEj0WIcGc0LOZCcCITW2mHzz9XdnlVDTxPXTZz rUzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Bo+ALpEg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t12si145560ybc.91.2019.02.21.19.01.27 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 21 Feb 2019 19:01:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Bo+ALpEg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:43207 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx15b-0002TL-C6 for patch@linaro.org; Thu, 21 Feb 2019 22:01:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gx0mj-0005EY-MW for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gx0mX-0005Fm-0F for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:49 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:35540) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gx0mW-0004dH-EK for qemu-devel@nongnu.org; Thu, 21 Feb 2019 21:41:44 -0500 Received: by mail-pf1-x442.google.com with SMTP id j5so393412pfa.2 for ; Thu, 21 Feb 2019 18:41:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7za0oe+S+pDjXtPVWoLW1jUXBpKdAwHxIVRqazhFQik=; b=Bo+ALpEgvkJjPayK/eZg++ocYuLYY9QI0hTefDosQ0uK5/f3KM0Ot1ylzCG9E1bEiB ygvRgoPCMDeSaS1fgOMvo7ZIE0nG2NBhzm0HohTxYNB2wtEVLfXIyoW8sYqwBhre1Viu 5QPrY6oyi8IOsnMTml6nnOv9wv0XSfx+qBbnY//EpIyfI3Wc6TPfL1dbiy1VNHu8yG1E nfjOCF+7z1NiNVQoWOzpCt0F2bHGCN4kunMVvrTVgxL0xVtKBkfEBgM4LsjU1RujzGBg Eugn9GVwLXkLjjiPSYJ6TyBgE8UiFMRK1xHHFIvUzq5cq61MsJ5GlJcBCrPll8L3BnhF r0WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7za0oe+S+pDjXtPVWoLW1jUXBpKdAwHxIVRqazhFQik=; b=WxsmbNbVahAnEBkrBCn/e0acvgKCbJ2bqtVgfyDylkm9XWjm0DhnRqD6ivVxPogKVv 4dq4rwDkb3Wb+zJclRj43nslwqXZOqDda8TfHFbSmTuWKHt/6M/yb/mgKTp6i0IbLbxZ S7u/rwHzWhsNe/C+1DdQHlCiGiHNPwOKma92tOz3W6PbXKu4rpSI2j2ma4bLzcYVpSwK afj84QRfx1I3yKubwqNb7viv+IcxpUW/S2IiZyszw5xGwNGenCRzgX7fXygJQA67UJsz u/RL2gBA/hW/mkCt0ft7cOvCgT2MLYwBfUgACkzo1vHgqeRBzMzbSrn2qaxjK/tK2T+v b9Mw== X-Gm-Message-State: AHQUAuaspAJ+euA+VhZMTESOIcv+YCWcpk7+PgGH7oK1O5yn3VbT4nYe T71+WqmIlLk4awMjYpIvxdLJ7JnVlig= X-Received: by 2002:aa7:80c8:: with SMTP id a8mr1782344pfn.27.1550803272603; Thu, 21 Feb 2019 18:41:12 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id v6sm187429pgb.2.2019.02.21.18.41.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Feb 2019 18:41:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 21 Feb 2019 18:41:06 -0800 Message-Id: <20190222024106.9167-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190222024106.9167-1-richard.henderson@linaro.org> References: <20190222024106.9167-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 3/3] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the payoff. >From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Assertions are retained for --enable-debug-tcg. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Retain asserts for future debugging. --- target/arm/helper.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 1140739d6b..0d19333be0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14027,19 +14027,29 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, uint32_t el) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - int current_el = arm_current_el(env); - uint32_t flags; + uint32_t flags = env->hflags; uint32_t pstate_for_ss; +#ifdef CONFIG_DEBUG_TCG + { + int el = arm_current_el(env); + uint32_t check_flags; + if (is_a64(env)) { + check_flags = rebuild_hflags_a64(env, el); + } else { + check_flags = rebuild_hflags_a32(env, el); + } + g_assert_cmphex(flags, ==, check_flags); + } +#endif + *cs_base = 0; - if (is_a64(env)) { + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc = env->pc; - flags = rebuild_hflags_a64(env, current_el); flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; - flags = rebuild_hflags_a32(env, current_el); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);