From patchwork Fri Sep 30 22:03:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610973 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1764958pvb; Fri, 30 Sep 2022 15:05:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4UHO3Y5/PmNuxExtwZXgG85KC6sM1MJ6mJ7C4lNCSiLeSoYsd1bUv+DkAG0/CPCz+NGZKa X-Received: by 2002:ac8:5b53:0:b0:35b:a603:6cdf with SMTP id n19-20020ac85b53000000b0035ba6036cdfmr8744312qtw.357.1664575523961; Fri, 30 Sep 2022 15:05:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664575523; cv=none; d=google.com; s=arc-20160816; b=sXAVDuxucHRFKl4x3tjX61UYRl6so9Fvwq6g0Cr6xdSXj5EOf4KSqCgh83gnEndK+I lOnI1vuUeWVer/3Ds/6Q3WMFzNjWO8HYvZzc4VCdu+l1bh8ECJ1yVNPAYLmpzeJlF+vq XB4E1y9eVis4Cnz9xHZ7aICb3AxvRAA8TNkxTkyJysG/BwEoxsy8Y0OtsHI+hvgr9O8N PEM8EWlH8iZOkjAm3+R+0H74eyyuToF6QXcQ/J1jNJoMj3jCDtWC6ATsTxXeSzocA62S nh9Zo1ki37j1Kfv28Ptij6DveMJgUUQNP+H5kpz+BAD/dILWBR356FogHHl7+HsvZ+tx 7Ezw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=apBe+xOEG/yN097g7gF2sx0rQ+06LZSBxstARnEgFm4=; b=fQUP9O+J/+foYGoR5MkNY3U8e09GYaMYaMuDsuZzCns0aIl0W8ciibL1hZpraVP71U pFD/K4ZgOrClfDhWqQ+97PARNLHbKcmadczKmtt60JaOL6UxR/mu8sqQRFJePZKSqHPB yhQ2bwyYVmIX+rGEAdP3BFdi+nHn3H9BRLguROoJrECt3VaSpulFIMJwlQJHEKG2ja3G n6PgbHBjBLupuw9qEDYrwvGSHbOyTg36d3KbZx0a0+ahNohvkEZMfVSKFSpvkEck2lOU ZitmquOsan4EreaP0bc4D18tcmBfkN3awEFlhXXdaDzFwv9P+t7pUwJwGq01gOC6LpQx MKTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PkzGp7ke; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c14-20020ad45aee000000b004ac24871ae8si1671630qvh.575.2022.09.30.15.05.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:05:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PkzGp7ke; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeO8J-0001hY-FC for patch@linaro.org; Fri, 30 Sep 2022 18:05:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6M-0001fD-R6 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:22 -0400 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]:45024) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6K-0002Y3-5C for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:22 -0400 Received: by mail-qt1-x82c.google.com with SMTP id f26so3490268qto.11 for ; Fri, 30 Sep 2022 15:03:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=apBe+xOEG/yN097g7gF2sx0rQ+06LZSBxstARnEgFm4=; b=PkzGp7kePNj8r+lMIpFGsMPF+hyb1SSdTxbLdFYByhPXNQ6QuVSDPrKO5v9qU11Vfy 3y/J5gLqIN5XkIm1x27tvd2dZMiijM+BNaCbcnOHpWw4Lke9D/jOB1BlxgCpr4AbriJt gjl3bn9ybOdrhFJsGIOu/UvMAeMewFhjITFfx4aaKO2ibG/QuOUS+O4laaXUrjGBMXV2 huem5IqxS5w5Q0zNTTrIcZvjsJfMaJruttQU2HFr/3ZKGA3CqwIm/nS0s/nWF0FTXkI/ jQArGPT34AFW2l01EAUIIGjcR0yul/qiswK2h0pkkvENo6E0L9ZIun7fEdE24RqVLF3G mMVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=apBe+xOEG/yN097g7gF2sx0rQ+06LZSBxstARnEgFm4=; b=EM5g99CD1XxQBRZrRZZqiE6Lsh/mLDZkwwOSR64KpdICSMJK/e/fIwNo95ii6L7X0p raKPcfaN773qyllCSbHbzelStn0/Im+T1SaYw10mAnJkjNYk8rXMrGgSrGOP6BE8H6cT P5RDzap3654o0RWH9rEnA3pRGiypDl5ILevUWVBLjdzWnmJbPFBlihE3f63wT57q8/fE /+eJmwJQJnowKC+6+yLMF+KVBI7goWVq2dzezlXVw5qDWZTN+lVejyVU3M/KwOsbdGP1 7OEmxBc3dZqct+wuCrZHvVF0he6w121Lv73wng0W4dEsBZ2XkWEgzTuGgDfRgfd0tbBo YMWw== X-Gm-Message-State: ACrzQf20ng5kwG3ctFypbKPy5wIvJHmkuOzpr/CpZFpftpUQ1HI7vgVI i0EMFxp+azKWVGwrGjgH/JhdhIPkf0v7wQ== X-Received: by 2002:ac8:5990:0:b0:35c:b943:1cde with SMTP id e16-20020ac85990000000b0035cb9431cdemr8811081qte.239.1664575398997; Fri, 30 Sep 2022 15:03:18 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 1/9] target/arm: Introduce curr_insn_len Date: Fri, 30 Sep 2022 15:03:04 -0700 Message-Id: <20220930220312.135327-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A simple helper to retrieve the length of the current insn. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.h | 5 +++++ target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 5 ++--- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index af5d4a7086..90bf7c57fc 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -226,6 +226,11 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) s->insn_start = NULL; } +static inline int curr_insn_len(DisasContext *s) +{ + return s->base.pc_next - s->pc_curr; +} + /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ /* CPU state was modified dynamically; exit to main loop for interrupts. */ diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index bd5ae27d09..94cc1e4b77 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -242,7 +242,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) if (s->sme_trap_nonstreaming) { gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, - s->base.pc_next - s->pc_curr == 2)); + curr_insn_len(s) == 2)); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 5aaccbbf71..42e11102f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6654,7 +6654,7 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) /* ISS not valid if writeback */ if (p && !w) { ret = rd; - if (s->base.pc_next - s->pc_curr == 2) { + if (curr_insn_len(s) == 2) { ret |= ISSIs16Bit; } } else { @@ -9817,8 +9817,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(cpu_env, - tcg_constant_i32(dc->base.pc_next - dc->pc_curr)); + gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc))); /* * The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anyway. From patchwork Fri Sep 30 22:03:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610976 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1766282pvb; Fri, 30 Sep 2022 15:08:40 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4SvhL/juUgRS9lYmqzmcCds/gzbrisLfWYVrNcBk3QLJmTi0PEoJbvcZyOUxpAs7zaIdKa X-Received: by 2002:a05:6214:300b:b0:4ad:a84b:99cd with SMTP id ke11-20020a056214300b00b004ada84b99cdmr8547270qvb.42.1664575720027; Fri, 30 Sep 2022 15:08:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664575720; cv=none; d=google.com; s=arc-20160816; b=L4fkgVO7/8V/Eng6bj1fbklZjNQvNv2OrkauCqWKtcqncBtnFG6OULuC+d3kmSIv46 MJfRuJFNzfhNKWUcICd9IJEk0iduLJtG787s7h+yFM/rOAXBajv1v6Vp1E8Zfv5fGyTK VKwLvKZilkoJac7HVna1ZQP1WkhS4n4OSF3/nfoHuhpLaQVXERrVPTqrsfpBuLv1wTa3 LIY+sn93zYGj2v6iax1QqBPbsbvLRtfxU1MPKj+YgkxDY+4xXmhPCOJi9dkpDQBo6TMS 31KXGyRjxG1souCY1e54Y2XMOXaBeTGEL/9X5sH+UeMy4GTJtsNnNCmn3nhLYEwydDS8 x0Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+B8rOtkjvONjZSA2MWgoQbv6N8UN3QaAqQ4YsJ87nAo=; b=D3n3kpT+q17U61WrbdR6eqvKtWykdrXmF0hmW7s8dbdNPuq0Iej9YyiJiUMlSDx5Nm 3Arw8RpNk8luz+6EGYayZKkgzoRc/xQ9fZJywkElqW5rvASLuZjNvSsGwwa/9nCywITu 99Enk2PFqwLIQQAQ4olw3Mbb5UhWeKTI4Gzg1uzsw/0atesx8G/w3HpWxF+5OtI3Hj8q vLmqoS8sS9AMq8swx5wGcPtqHuHiNDZtSmB79cnVTP3sWK4qiIRLE5kL1AF52ZqIx66G uqf6c6XWp1P+R/oK4PkHj0+P9kX9llAGnn17llmj2ZU3JUVVfT+f4rmFEGEvileLQF8B /djw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DZ018cOh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l7-20020ae9f007000000b006cbc44e8a14si1735907qkg.723.2022.09.30.15.08.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:08:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DZ018cOh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeOBT-0007ai-Iu for patch@linaro.org; Fri, 30 Sep 2022 18:08:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6P-0001fx-8X for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:27 -0400 Received: from mail-qk1-x72b.google.com ([2607:f8b0:4864:20::72b]:33306) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6M-0002YJ-1F for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:23 -0400 Received: by mail-qk1-x72b.google.com with SMTP id h28so3681525qka.0 for ; Fri, 30 Sep 2022 15:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=+B8rOtkjvONjZSA2MWgoQbv6N8UN3QaAqQ4YsJ87nAo=; b=DZ018cOhANM3iGgmBtCGePN2toJxeG6/s7RKRUZOhyFh7d9ADLk6lZVNrVzQPvwaCH 5ClrJ2/QILcOmeyktRuEMLp3q4cvPG0smt6bZbE1Ly8Xip9KDZjHLK/C8NpF5aKiDXKQ ZdL2NsTlsaLBkRwsIz7KaS04FpSlfoz8L+1cQ4tD6Vwt51MUPKFo0QZfKy+kLtkrs7xN 3jmyCRJqjxnF6uz187VzVxR9x+7sZXHyKVTal8LZpLgvI+N4kFbdAtm9J8sAtTwRKOKl 4QOi+DEC8/pZM9YbixPRTb/SI7lV43JNzDVC6hiPxZXd2drRpstXhY5WBizcciX+fDww 8l4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=+B8rOtkjvONjZSA2MWgoQbv6N8UN3QaAqQ4YsJ87nAo=; b=uOiMhSV+zGHw4fb86RkKsdbtldRlWX2XeARnM9r78SKcPjvnpqVmPSft7brBBC9krz Ctqn4dcdlE9QROjjcjYuVS1qpmuiZsiGaqECpRSUka9Av6wCCYBN3QXl/X+Kk6fUIp9/ h/TcCISDAKQtjYLJD9sGeFXIRDtjHy2C776OdQ4PH6G2MEVQfmz+P1RJYVqNq69PC1wU fMSUz6cjEY7co/zt8lRJg5I82hQ/LgJ6xfVQ3+E/0t57ab33asMOGaI/SX+Gf9K+0d7N u/uHDDtjhD0pQs3EqM79Yi8NVxUB82k2B7Ql7h/gxsiAlsZH+hrgWIK3w/keIsYmsCaM wH7g== X-Gm-Message-State: ACrzQf1NNslhgIdDX1kzJisbP5ABD0OpqcCQyL894jhW32JFPIRBuTcq aRweTn6XYuHLPSFVNwv+GgCVeRGyHRYGjg== X-Received: by 2002:a05:620a:151b:b0:6ce:1584:49f2 with SMTP id i27-20020a05620a151b00b006ce158449f2mr7769142qkk.195.1664575400937; Fri, 30 Sep 2022 15:03:20 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 2/9] target/arm: Change gen_goto_tb to work on displacements Date: Fri, 30 Sep 2022 15:03:05 -0700 Message-Id: <20220930220312.135327-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 40 ++++++++++++++++++++------------------ target/arm/translate.c | 10 ++++++---- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 78b2d91ed4..8f5c2675f7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -378,8 +378,10 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest) return translator_use_goto_tb(&s->base, dest); } -static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) +static void gen_goto_tb(DisasContext *s, int n, int64_t diff) { + uint64_t dest = s->pc_curr + diff; + if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); @@ -1362,7 +1364,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { - uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4; + int64_t diff = sextract32(insn, 0, 26) * 4; if (insn & (1U << 31)) { /* BL Branch with link */ @@ -1371,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) /* B Branch / BL Branch with link */ reset_btype(s); - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } /* Compare and branch (immediate) @@ -1383,14 +1385,14 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { unsigned int sf, op, rt; - uint64_t addr; + int64_t diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; sf = extract32(insn, 31, 1); op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt = extract32(insn, 0, 5); - addr = s->pc_curr + sextract32(insn, 5, 19) * 4; + diff = sextract32(insn, 5, 19) * 4; tcg_cmp = read_cpu_reg(s, rt, sf); label_match = gen_new_label(); @@ -1399,9 +1401,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } /* Test and branch (immediate) @@ -1413,13 +1415,13 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) static void disas_test_b_imm(DisasContext *s, uint32_t insn) { unsigned int bit_pos, op, rt; - uint64_t addr; + int64_t diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ - addr = s->pc_curr + sextract32(insn, 5, 14) * 4; + diff = sextract32(insn, 5, 14) * 4; rt = extract32(insn, 0, 5); tcg_cmp = tcg_temp_new_i64(); @@ -1430,9 +1432,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } /* Conditional branch (immediate) @@ -1444,13 +1446,13 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) static void disas_cond_b_imm(DisasContext *s, uint32_t insn) { unsigned int cond; - uint64_t addr; + int64_t diff; if ((insn & (1 << 4)) || (insn & (1 << 24))) { unallocated_encoding(s); return; } - addr = s->pc_curr + sextract32(insn, 5, 19) * 4; + diff = sextract32(insn, 5, 19) * 4; cond = extract32(insn, 0, 4); reset_btype(s); @@ -1458,12 +1460,12 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) /* genuinely conditional branches */ TCGLabel *label_match = gen_new_label(); arm_gen_test_cc(cond, label_match); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } else { /* 0xe and 0xf are both "always" conditions */ - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } } @@ -1637,7 +1639,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * any pending interrupts immediately. */ reset_btype(s); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; case 7: /* SB */ @@ -1649,7 +1651,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * MB and end the TB instead. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; default: @@ -14955,7 +14957,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, 4); break; default: case DISAS_UPDATE_EXIT: diff --git a/target/arm/translate.c b/target/arm/translate.c index 42e11102f7..6855128fb1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2594,8 +2594,10 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + target_ulong dest = s->pc_curr + diff; + if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); @@ -2629,7 +2631,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest); + gen_goto_tb(s, tbno, dest - s->pc_curr); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -9798,7 +9800,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: gen_set_pc_im(dc, dc->base.pc_next); @@ -9850,7 +9852,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_set_pc_im(dc, dc->base.pc_next); gen_singlestep_exception(dc); } else { - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); } } } From patchwork Fri Sep 30 22:03:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610975 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1766120pvb; Fri, 30 Sep 2022 15:08:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6JkG7EMW38St0FNmPDCFrm6wKBAivkMdVADQkHK577jJINxv4+5RakplbmXqVLbatoM/ze X-Received: by 2002:a37:503:0:b0:6ce:8a8e:7625 with SMTP id 3-20020a370503000000b006ce8a8e7625mr7704634qkf.288.1664575694009; Fri, 30 Sep 2022 15:08:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664575694; cv=none; d=google.com; s=arc-20160816; b=Cz3YtswhRFtu6gURFltHrEDwOdtm3NvSrtzaLvjKgPFpMYhOvr+1lcG+Tl9vjki5ee tpHgkP+5YZm9OvMhcipcMCAbcnPFSZ0Wpw0Y/W9xhmJsQk5ahhHfZpZKbz32okaQ7u6M mCTmM5Wmfzz76ssDi+q32nwECe79ZRwilGdQJdz5bUASef8YnlEIn+N+PnQs4HVZ7tfx DEs317J4GPhb4l+UQGiJbW0gPEMlrM2GSoKR5R7uPAuVbeZwhRZKdYkPnVzD/wcc+ZWM ajrwb1kGJWqoFd0Tcg+Esvbgd+nV5oz+D+NWuuMo0imUm5JtCqUC9lsottSi1Me++GBT f5Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f1Po5le8MyIkVpmSBO1IOtHFtuAYm1c/MbSae2bI718=; b=md1qdsZEDY7AhGFExgEwrL1aAeP0RzCcBOhU21Y21qOKbEYujsMJhP7+3Z0N6m07JZ tHdMhuwL8ijSP76RnZ6VsK8F09JZrHvY0bZP95PVX9SeiofpNIHnsoV+D9hzkSmMxHBF +XUWdKNQYE1vmEnRydWN+1WGs4gjOP7w9ASCKQo6GznetZfWu7CFQ+ojPWoSE086Cp84 xc0h5lons/wnH1laVvKF4+d5z02MCJJyf3S/EvvI2fDXxlQ+pmsOnamBiI9Ijr0ejj+B M4EKORultA7OQusQvdQFFxmWO18cRluc2TWtYG43QYthqdtCSgk+koleYHQmFyGHB3De pTWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qqUyelGX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h5-20020a0562140da500b004aaa653517fsi2019147qvh.232.2022.09.30.15.08.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:08:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qqUyelGX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeOB3-00070p-7w for patch@linaro.org; Fri, 30 Sep 2022 18:08:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6T-0001jH-K4 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:29 -0400 Received: from mail-qv1-xf2b.google.com ([2607:f8b0:4864:20::f2b]:37418) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6N-0002Ye-UW for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:29 -0400 Received: by mail-qv1-xf2b.google.com with SMTP id jy22so3094904qvb.4 for ; Fri, 30 Sep 2022 15:03:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=f1Po5le8MyIkVpmSBO1IOtHFtuAYm1c/MbSae2bI718=; b=qqUyelGX8wwVhm0sYj6c3cDsfYXGFP3hQ9cCX7DrSYl5l+1CBcYo4gOZVbjyTgqUNn 8Zv/5d+CpgEcyhw8QvF1JBT5Gqdf9B9e0NoAAs+asRBODnkX/Y1ehdoguqc3eq7cJdvb 6ACpwv1p8EmuLkS4yGXxnH8emiPbitmgtvvp/4wqhbBKyos6smaUoNWueAjad61wbYmO E96FK28LxN0DztAsstWded8atK4N4tUM8zNBkIjevfpi7JcibZ83aXnH/eX29rhuN0w1 aw3g8k0SmDA8PaHZC6HpFhxMnMXL/F/jYs4SjpmXtoBSKh9qj69vQodmn9Ji3VqEXH1V ntNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=f1Po5le8MyIkVpmSBO1IOtHFtuAYm1c/MbSae2bI718=; b=U1rQxiMiDSTM4vAet0YuBLtJIGx0LAHnDHXYF9KNUeFp1bxvTmU5Iz6uUuawlrzTNS V2VuDXeJg3RyYZ//G8L5DaQLtZylS8hwTiENhMWW6C1L9mOQnnzhUN5byj4WdP3iPJHI kWRBBoTXNvD2l8SozLH572ocamhvc8jiDWBHdKzgGn+ooEfxUBqYBkW32GspedMy9wKm VsQiSVUiFYvUnQqeS+Pk/vBRslphPNdrJjjd08eHNbRgvKipUPW2W6/NUaT+khzragBl 42K73mzgtKO9AA9Cn6ehE6QGSWHipgSDNMkHr/MjI4nPGNMEhjtA9Cq7xGGHhCAFH/vG 62Kw== X-Gm-Message-State: ACrzQf3nsvCGdBBempuZEOvM+3uH00gN/g8QIVI48ATpoFvfRLQF4rr3 GuoXoDLw3lBvHEKQMFsuM6p25ja2X3MBJw== X-Received: by 2002:ad4:5d68:0:b0:4af:af07:580b with SMTP id fn8-20020ad45d68000000b004afaf07580bmr7940822qvb.14.1664575402511; Fri, 30 Sep 2022 15:03:22 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 3/9] target/arm: Change gen_*set_pc_im to gen_*update_pc Date: Fri, 30 Sep 2022 15:03:06 -0700 Message-Id: <20220930220312.135327-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2b; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values by passing in pc difference. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/translate-a32.h | 2 +- target/arm/translate.h | 6 ++-- target/arm/translate-a64.c | 32 +++++++++--------- target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 68 ++++++++++++++++++++------------------ 5 files changed, 56 insertions(+), 54 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 78a84c1414..5339c22f1e 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); void gen_set_cpsr(TCGv_i32 var, uint32_t mask); void gen_set_condexec(DisasContext *s); -void gen_set_pc_im(DisasContext *s, target_ulong val); +void gen_update_pc(DisasContext *s, target_long diff); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); diff --git a/target/arm/translate.h b/target/arm/translate.h index 90bf7c57fc..d651044855 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -254,7 +254,7 @@ static inline int curr_insn_len(DisasContext *s) * For instructions which want an immediate exit to the main loop, as opposed * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this * doesn't write the PC on exiting the translation loop so you need to ensure - * something (gen_a64_set_pc_im or runtime helper) has done so before we reach + * something (gen_a64_update_pc or runtime helper) has done so before we reach * return from cpu_tb_exec. */ #define DISAS_EXIT DISAS_TARGET_9 @@ -263,14 +263,14 @@ static inline int curr_insn_len(DisasContext *s) #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_a64_set_pc_im(uint64_t val); +void gen_a64_update_pc(DisasContext *s, target_long diff); extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } -static inline void gen_a64_set_pc_im(uint64_t val) +static inline void gen_a64_update_pc(DisasContext *s, target_long diff) { } #endif diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8f5c2675f7..914c789187 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,9 @@ static void reset_btype(DisasContext *s) } } -void gen_a64_set_pc_im(uint64_t val) +void gen_a64_update_pc(DisasContext *s, target_long diff) { - tcg_gen_movi_i64(cpu_pc, val); + tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); } /* @@ -342,14 +342,14 @@ static void gen_exception_internal(int excp) static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); gen_exception_internal(excp); s->base.is_jmp = DISAS_NORETURN; } static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp = DISAS_NORETURN; } @@ -384,11 +384,11 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff) if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); - gen_a64_set_pc_im(dest); + gen_a64_update_pc(s, diff); tcg_gen_exit_tb(s->base.tb, n); s->base.is_jmp = DISAS_NORETURN; } else { - gen_a64_set_pc_im(dest); + gen_a64_update_pc(s, diff); if (s->ss_active) { gen_step_complete_exception(s); } else { @@ -1960,7 +1960,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, uint32_t syndrome; syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_access_check_cp_reg(cpu_env, tcg_constant_ptr(ri), tcg_constant_i32(syndrome), @@ -1970,7 +1970,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, * The readfn or writefn might raise an exception; * synchronize the CPU state in case it does. */ - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); } /* Handle special cases first */ @@ -2180,7 +2180,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) /* The pre HVC helper handles cases when HVC gets trapped * as an undefined insn by runtime configuration. */ - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, @@ -2191,7 +2191,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) unallocated_encoding(s); break; } - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); gen_ss_advance(s); gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, @@ -14944,7 +14944,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) */ switch (dc->base.is_jmp) { default: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, 4); /* fall through */ case DISAS_EXIT: case DISAS_JUMP: @@ -14961,13 +14961,13 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) break; default: case DISAS_UPDATE_EXIT: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, 4); /* fall through */ case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; case DISAS_UPDATE_NOCHAIN: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, 4); /* fall through */ case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(); @@ -14976,11 +14976,11 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) case DISAS_SWI: break; case DISAS_WFE: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, 4); gen_helper_wfe(cpu_env); break; case DISAS_YIELD: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, 4); gen_helper_yield(cpu_env); break; case DISAS_WFI: @@ -14988,7 +14988,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) * This is a special case because we don't want to just halt * the CPU if trying to debug across a WFI. */ - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, 4); gen_helper_wfi(cpu_env, tcg_constant_i32(4)); /* * The helper doesn't necessarily throw an exception, but we diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 94cc1e4b77..070f465b17 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -856,7 +856,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) case ARM_VFP_FPSID: if (s->current_el == 1) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_check_hcr_el2_trap(cpu_env, tcg_constant_i32(a->rt), tcg_constant_i32(a->reg)); diff --git a/target/arm/translate.c b/target/arm/translate.c index 6855128fb1..01b7536c7e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -772,9 +772,9 @@ void gen_set_condexec(DisasContext *s) } } -void gen_set_pc_im(DisasContext *s, target_ulong val) +void gen_update_pc(DisasContext *s, target_long diff) { - tcg_gen_movi_i32(cpu_R[15], val); + tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff); } /* Set PC and Thumb state from var. var is marked as dead. */ @@ -866,7 +866,7 @@ static inline void gen_bxns(DisasContext *s, int rm) /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory * we need to sync state before calling it, but: - * - we don't need to do gen_set_pc_im() because the bxns helper will + * - we don't need to do gen_update_pc() because the bxns helper will * always set the PC itself * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE * unless it's outside an IT block or the last insn in an IT block, @@ -887,7 +887,7 @@ static inline void gen_blxns(DisasContext *s, int rm) * We do however need to set the PC, because the blxns helper reads it. * The blxns helper may throw an exception. */ - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); gen_helper_v7m_blxns(cpu_env, var); tcg_temp_free_i32(var); s->base.is_jmp = DISAS_EXIT; @@ -1055,7 +1055,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * as an undefined insn by runtime configuration (ie before * the insn really executes). */ - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters @@ -1063,7 +1063,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * for single stepping.) */ s->svc_imm = imm16; - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp = DISAS_HVC; } @@ -1072,16 +1072,16 @@ static inline void gen_smc(DisasContext *s) /* As with HVC, we may take an exception either before or after * the insn executes. */ - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp = DISAS_SMC; } static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); gen_exception_internal(excp); s->base.is_jmp = DISAS_NORETURN; } @@ -1107,10 +1107,10 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); } else { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp = DISAS_NORETURN; @@ -1125,10 +1125,10 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) { if (s->aarch64) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); } else { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); } gen_exception(excp, syn); s->base.is_jmp = DISAS_NORETURN; @@ -1137,7 +1137,7 @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); s->base.is_jmp = DISAS_NORETURN; } @@ -2600,10 +2600,10 @@ static void gen_goto_tb(DisasContext *s, int n, int diff) if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); tcg_gen_exit_tb(s->base.tb, n); } else { - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); gen_goto_ptr(); } s->base.is_jmp = DISAS_NORETURN; @@ -2612,9 +2612,11 @@ static void gen_goto_tb(DisasContext *s, int n, int diff) /* Jump, specifying which TB number to use if we gen_goto_tb() */ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) { + int diff = dest - s->pc_curr; + if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. */ - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); s->base.is_jmp = DISAS_JUMP; return; } @@ -2631,7 +2633,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest - s->pc_curr); + gen_goto_tb(s, tbno, diff); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -2640,7 +2642,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) * Avoid using goto_tb so we really do exit back to the main loop * and don't chain to another TB. */ - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); gen_goto_ptr(); s->base.is_jmp = DISAS_NORETURN; break; @@ -2908,7 +2910,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because msr_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); tcg_reg = load_reg(s, rn); gen_helper_msr_banked(cpu_env, tcg_reg, tcg_constant_i32(tgtmode), @@ -2928,7 +2930,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because mrs_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); tcg_reg = tcg_temp_new_i32(); gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_constant_i32(tgtmode), @@ -4749,7 +4751,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, } gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_access_check_cp_reg(cpu_env, tcg_constant_ptr(ri), tcg_constant_i32(syndrome), @@ -4760,7 +4762,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, * synchronize the CPU state in case it does. */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); } /* Handle special cases first */ @@ -4774,7 +4776,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, unallocated_encoding(s); return; } - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp = DISAS_WFI; return; default: @@ -5161,7 +5163,7 @@ static void gen_srs(DisasContext *s, addr = tcg_temp_new_i32(); /* get_r13_banked() will raise an exception if called from System mode */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); switch (amode) { case 0: /* DA */ @@ -6230,7 +6232,7 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a) * scheduling of other vCPUs. */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp = DISAS_YIELD; } return true; @@ -6246,7 +6248,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a) * implemented so we can't sleep like WFI does. */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp = DISAS_WFE; } return true; @@ -6255,7 +6257,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a) static bool trans_WFI(DisasContext *s, arg_WFI *a) { /* For WFI, halt the vCPU until an IRQ. */ - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp = DISAS_WFI; return true; } @@ -8765,7 +8767,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) (a->imm == semihost_imm)) { gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->svc_imm = a->imm; s->base.is_jmp = DISAS_SWI; } @@ -9779,7 +9781,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) case DISAS_TOO_MANY: case DISAS_UPDATE_EXIT: case DISAS_UPDATE_NOCHAIN: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ @@ -9803,13 +9805,13 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_JUMP: gen_goto_ptr(); break; case DISAS_UPDATE_EXIT: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ default: /* indicate that the hash table must be used to find the next TB */ @@ -9849,7 +9851,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_set_label(dc->condlabel); gen_set_condexec(dc); if (unlikely(dc->ss_active)) { - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); gen_singlestep_exception(dc); } else { gen_goto_tb(dc, 1, curr_insn_len(dc)); From patchwork Fri Sep 30 22:03:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610978 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1767638pvb; Fri, 30 Sep 2022 15:11:44 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6mC5uVsaF72b6K7o8SFDBI7akq4T8atp3NwCZIL7b5m7sXwCmESHW68zqC1SfuAVAwkkiC X-Received: by 2002:a05:620a:4310:b0:6ac:f9df:178d with SMTP id u16-20020a05620a431000b006acf9df178dmr7908820qko.773.1664575904622; Fri, 30 Sep 2022 15:11:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664575904; cv=none; d=google.com; s=arc-20160816; b=y6aq7WfTeMKEMEUi3oLhoRMJHtiLv89s1C053a/WtmEY3NDqAPIkPnRekd9RIJigY2 eDi5mKLFLKYQhfy9VrkIKNwpX7zuJSmsrTOTN6kO+cVojpKCHQB66wjyQm47Dkourjfw /oL9HHiYo/5ZBqrA/a4Du5ADeemZ4/WR9OIX22GKVFAMqxYojoIcS6ADQIPlRJ0tW1xD h6ND9ya1GGqJlTi/8Rb+ZYI7J/kZHuu5WMeHdMf5d37ylVOeHLWdJXo6A/GbkpIm6Y2T j77cw65lSPYW+a/u8WNBUmlGeHlFlZqLKvm8sr9OhrrfqFOJzGf+p6dyt88ziwn/y1zB 574g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hFl8uWsQzDd9Py9/TFuMYAbgSSC7mya+NEHGXFsft2o=; b=JhSnlk/Y+7sJwR4HqCdoGeO8Yo1j6qeNf5Lb/JBfTMGh75Iio+I7dxdc2uLnylSI3h ZzTAIWJoL9cZqSbSJ+yKgLy1YsAb0kBRBR3kx2FiE9zT4kmslGL06Y9ZxIjf2yU91cZE n6X3Jy+nfHlWTykHmR1KQVDB1ClrDcvKnWvsZLS/wiSPR8YGQkprrzowlhiaWc9EVgm3 hNyh0L39ClV3AFvG4n7DJ8tJ8n+IxJEBVLYRdFAns9IJOSI98xSp14LGg8DwVoMNihDi hs+hk+sbzloCaXzhCUB6BiEoxWAuxHG2OOzX4kDRDxd43BDxAeoo9XVuQT6fVHKBGTQu nLtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wWrF3or8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id cm7-20020a05622a250700b0035cef5008bcsi1849940qtb.626.2022.09.30.15.11.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:11:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wWrF3or8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeOES-0004pe-4W for patch@linaro.org; Fri, 30 Sep 2022 18:11:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6S-0001g4-0P for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:28 -0400 Received: from mail-qv1-xf31.google.com ([2607:f8b0:4864:20::f31]:36467) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6P-0002Z4-4g for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:27 -0400 Received: by mail-qv1-xf31.google.com with SMTP id r14so3644633qvn.3 for ; Fri, 30 Sep 2022 15:03:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=hFl8uWsQzDd9Py9/TFuMYAbgSSC7mya+NEHGXFsft2o=; b=wWrF3or8PPssHKYCMR0dv6OCKG9AylMTtJMODKLcMacTkf5UcrBq4twW5kbRLihOM2 F+MCHDLal/AE9hnbuJymN11UjBIj4j5dRV5T1hWaJ7Ktl/DvAdzSVyLbUrXAZUxCzWFn rU4iiNHNJi1buoJd/diMDjlq0k96QGHIe/2UQsTpoVUHkJ7ra+u7KU6Msz+RuIYZG4ip +2m+sxMiKIy0KbM6W/TJGORvt29RzmP4HSNdG6e0WXyXVyPUsxQbnEclcHKhYuWiYfSY Usp0HRsrAxG8bnDhN4eJYvuFkxBb0TXMSOteX0sv2zgETzYzP8G2eLSigGG1SzKKDUOW 49Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=hFl8uWsQzDd9Py9/TFuMYAbgSSC7mya+NEHGXFsft2o=; b=bAqwlgInNqMXZp8ai37OHepQ/JNsNp1ZZWCFi2SS3Is3ctjk71Qk46dWbzo4FYbSIh DY9A+Gu7WGyeOH/GDCErbpy6EDTaJw3PwdofShoDyuisXpAU5hC5eqkhNdjJ7WEHwwn0 I0WJWLPiZ+9KBa0BLeAI6QwT36NpaV6WIVCpmcVwM+1tHz6sl/mJJuCehMkOQkGoAQ4B /AXT4seoOWDboJbwbP+GfOxXWTNuI9YKKljpKTIEVB9EziZcUj3AxjTwwynUeU0FPKkz vbNuKxl5q8mTKAUBuGoUkOnX0wQzt05FT46cvomNAIVO7Ps7ADz1d4oPnIAnEcfISRBh suxA== X-Gm-Message-State: ACrzQf24fE9Gdp5zEZZ/v6ad7iNd8EO4mlhkqQDnAFNQtWZlq4kwjEx+ jHU5oc9lg5rSzA4qLH/U4UeH0ath0s9LAQ== X-Received: by 2002:a0c:b30b:0:b0:4af:8a8d:5687 with SMTP id s11-20020a0cb30b000000b004af8a8d5687mr8631364qve.77.1664575404060; Fri, 30 Sep 2022 15:03:24 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 4/9] target/arm: Change gen_exception_insn* to work on displacements Date: Fri, 30 Sep 2022 15:03:07 -0700 Message-Id: <20220930220312.135327-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f31; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/translate.h | 5 +++-- target/arm/translate-a64.c | 28 ++++++++++------------- target/arm/translate-m-nocp.c | 6 ++--- target/arm/translate-mve.c | 2 +- target/arm/translate-vfp.c | 6 ++--- target/arm/translate.c | 42 +++++++++++++++++------------------ 6 files changed, 43 insertions(+), 46 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index d651044855..4aa239e23c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -281,9 +281,10 @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); -void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, +void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, uint32_t syn, uint32_t target_el); -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn); +void gen_exception_insn(DisasContext *s, target_long pc_diff, + int excp, uint32_t syn); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 914c789187..2621b3b36a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1163,7 +1163,7 @@ static bool fp_access_check_only(DisasContext *s) assert(!s->fp_access_checked); s->fp_access_checked = true; - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false, 0), s->fp_excp_el); return false; @@ -1178,7 +1178,7 @@ static bool fp_access_check(DisasContext *s) return false; } if (s->sme_trap_nonstreaming && s->is_nonstreaming) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, false)); return false; } @@ -1198,7 +1198,7 @@ bool sve_access_check(DisasContext *s) goto fail_exit; } } else if (s->sve_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); goto fail_exit; } @@ -1220,7 +1220,7 @@ bool sve_access_check(DisasContext *s) static bool sme_access_check(DisasContext *s) { if (s->sme_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_AccessTrap, false), s->sme_excp_el); return false; @@ -1250,12 +1250,12 @@ bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req) return false; } if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_NotStreaming, false)); return false; } if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_InactiveZA, false)); return false; } @@ -1915,7 +1915,7 @@ static void gen_sysreg_undef(DisasContext *s, bool isread, } else { syndrome = syn_uncategorized(); } - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome); + gen_exception_insn(s, 0, EXCP_UDEF, syndrome); } /* MRS - move from system register @@ -2169,8 +2169,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC */ gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_SWI, - syn_aa64_svc(imm16)); + gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16)); break; case 2: /* HVC */ if (s->current_el == 0) { @@ -2183,8 +2182,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, - syn_aa64_hvc(imm16), 2); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); break; case 3: /* SMC */ if (s->current_el == 0) { @@ -2194,8 +2192,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, - syn_aa64_smc(imm16), 3); + gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); break; default: unallocated_encoding(s); @@ -14833,7 +14830,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate()); return; } @@ -14864,8 +14861,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) if (s->btype != 0 && s->guarded_page && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype)); + gen_exception_insn(s, 0, EXCP_UDEF, syn_btitrap(s->btype)); return; } } else { diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 4029d7fdd4..694fae7e2e 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -143,7 +143,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); if (s->fp_excp_el != 0) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } @@ -765,12 +765,12 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) } if (a->cp != 10) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_NOCP, syn_uncategorized()); return true; } if (s->fp_excp_el != 0) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 0cf1b5ea4f..db7ea3f603 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -100,7 +100,7 @@ bool mve_eci_check(DisasContext *s) return true; default: /* Reserved value: INVSTATE UsageFault */ - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); return false; } } diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 070f465b17..5c5d58d2c6 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -230,7 +230,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn, s->fp_excp_el); return false; } @@ -240,7 +240,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) * appear to be any insns which touch VFP which are allowed. */ if (s->sme_trap_nonstreaming) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, curr_insn_len(s) == 2)); return false; @@ -272,7 +272,7 @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update) * the encoding space handled by the patterns in m-nocp.decode, * and for them we may need to raise NOCP here. */ - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 01b7536c7e..f9d3128656 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1103,32 +1103,34 @@ static void gen_exception(int excp, uint32_t syndrome) tcg_constant_i32(syndrome)); } -static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, - uint32_t syn, TCGv_i32 tcg_el) +static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff, + int excp, uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); } else { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp = DISAS_NORETURN; } -void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, +void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, uint32_t syn, uint32_t target_el) { - gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); + gen_exception_insn_el_v(s, pc_diff, excp, syn, + tcg_constant_i32(target_el)); } -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) +void gen_exception_insn(DisasContext *s, target_long pc_diff, + int excp, uint32_t syn) { if (s->aarch64) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); } else { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); } gen_exception(excp, syn); s->base.is_jmp = DISAS_NORETURN; @@ -1145,7 +1147,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); } /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -2869,7 +2871,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, tcg_el = tcg_constant_i32(3); } - gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el_v(s, 0, EXCP_UDEF, syn_uncategorized(), tcg_el); tcg_temp_free_i32(tcg_el); return false; @@ -2895,7 +2897,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, undef: /* If we get here then some access check did not pass */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); return false; } @@ -5119,8 +5121,7 @@ static void gen_srs(DisasContext *s, * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_uncategorized(), 3); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_uncategorized(), 3); return; } @@ -8502,7 +8503,7 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * Do the check-and-raise-exception by hand. */ if (s->fp_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } @@ -8605,7 +8606,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tmp = load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); tcg_temp_free_i32(tmp); - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); gen_set_label(skipexc); } @@ -9073,7 +9074,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); return; } @@ -9082,7 +9083,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate()); return; } @@ -9647,7 +9648,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(dc, 0, EXCP_UDEF, syn_illegalstate()); return; } @@ -9720,8 +9721,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) */ tcg_remove_ops_after(dc->insn_eci_rewind); dc->condjmp = 0; - gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, - syn_uncategorized()); + gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized()); } arm_post_translate_insn(dc); From patchwork Fri Sep 30 22:03:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610974 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1764963pvb; Fri, 30 Sep 2022 15:05:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Yq62P2cKTiI78jML2rj/spc9z5/mDKMwJBNw7lphBwWSQJHCzDXF+c3ccj7x9ZpAlX0fB X-Received: by 2002:ad4:5c8b:0:b0:4aa:8a44:8810 with SMTP id o11-20020ad45c8b000000b004aa8a448810mr8826008qvh.4.1664575524182; Fri, 30 Sep 2022 15:05:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664575524; cv=none; d=google.com; s=arc-20160816; b=oGkFjDIwpD+efsBnPFiomE12AL6LhqaVjiBHSzd+6r1R8uJ/1gWwqyrIBLSY3dxCdq Fd7AfMwsZB3GTY9ceSegCzYfbHkcNaY91bpsdP0/R8hDU0gqfAiEexvkrehr6iR+kdox vdNVXXHTYRjAepUug2JdDfxIuejNxhV40xtMj8Fn0GOduKS/cWwz0CiGDXzJABwdQ71D 4EY8eEJDTPp3zUDaKflRXWOuMYTatD1ksVeDBoNV2uuqgutaDSFCRmpKviYLFCYCBQm/ 0hN85kb7/cI11AmT3V06kv8FTNnhEM0rG7x/4FvI3EcPQlQhzyKSthjS4Zc6LKIWSVs7 pF5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6YmhwBNEkuM0BFWCxU5vS57JWawvJkZaQY6laYf14Ok=; b=cnxJBfn04tZ8AnmYWPEF/KT0/UlRWFn62eqDC4ffQA0mC5hzlFnrS0Yyb6G6O44Oo0 pfEIlZci7E+v7j/BPkx73YUo5PaGdnQZhE9ccvWtk7ipVM5rMZvdfSp5uEh0IHVMlsV6 C0TrrCMDtZ0stsqf2U61R3cpZNAkZV0O6+9CvUfSZxxvmkiewrCv+djiCRhAz7zKBzwV alQLWJQKFF2lRzAAc6piWVd8RECWXPvwBC6UNrCBDC4NFSAETWTFvuR8bJA4jRYXkyNf N9OVDpGGaChGgLtiiwbghgcuAqZ1xQ7v6DsyuIaVENq7KIAnGQl6zahph7P/WCN9k/8V wKQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="A68L/Obd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 9-20020a05621420a900b004990f3b13f4si1687726qvd.531.2022.09.30.15.05.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:05:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="A68L/Obd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeO8J-0001jD-Lj for patch@linaro.org; Fri, 30 Sep 2022 18:05:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41614) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6S-0001h4-C1 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:28 -0400 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]:45024) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6Q-0002Y3-Km for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:28 -0400 Received: by mail-qt1-x82c.google.com with SMTP id f26so3490394qto.11 for ; Fri, 30 Sep 2022 15:03:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=6YmhwBNEkuM0BFWCxU5vS57JWawvJkZaQY6laYf14Ok=; b=A68L/ObdFP6GjSRgWpsuqYmjyX51OOHTpW6pCITLPNViOwdQBlGdiRuKpzm+nFy3db qFa0WxYCV02yQ+1I1Bp6wuYsSxF6+5WDDFkYqMR0VVgN7HWL7Ng3SNaNC8LpqOw8oB+W 8ZNONEEuX2N6ZgelRQZZ9o5mzRQVG0XYbNxHIsxWqMG6eZLy7oG+Jr8OlMgOby7ZQ+HE VH90pA/Phawd3qZPgTYgkOfvVY7nz4cifO6owrNaALsWle8l5xihMvhXgmhUSJeQiFQQ ksR7XMZjmh1wokfGvSU8i3w5suB95BgDPiuv/GQC+N56qIOzkjSigKx+pm4n8mWvwStf cHiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=6YmhwBNEkuM0BFWCxU5vS57JWawvJkZaQY6laYf14Ok=; b=g20Yby2q4zJbgMCCEp8a1n4/djDF6yjemxbSrOeUyKeID/Swg/CkRkzs+CAllOsxLp IgPpDAAGD3mF7okRzHbVAMngmd4VqBCpTRpNl9b2vfjkpLBzVaQBaKkGv/fzFsykHeIn bjB8IX3SCff9nbYHAeEHv7YLbA7Se/hC/LIdFDye+itDhHWbRDLiuBzxYlZVqNtbx/7Q MMBmu+Q7p7PBbaFz5/u+YZoWfbxeGFmRhscURM356T00x8e8SxGD93iuQoalwVTEVeS9 gKGzRVANhLOa8JoA9ZCQKit8ycWqMOmVjicpaoaI+z/ZbasvZ4dG+gaQ9TdOUz9lI7gy 5ZLQ== X-Gm-Message-State: ACrzQf0oeyr8Ic5ROKBWvcr7w/BqvWTgV1ovBtgaJxIq7/RX5Mxon/j4 RG9TCe+LUj/EMm4Segxp5qh06AdzPQF9Ag== X-Received: by 2002:ac8:4e94:0:b0:35d:5266:ac9c with SMTP id 20-20020ac84e94000000b0035d5266ac9cmr8860915qtp.177.1664575405971; Fri, 30 Sep 2022 15:03:25 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 5/9] target/arm: Remove gen_exception_internal_insn pc argument Date: Fri, 30 Sep 2022 15:03:08 -0700 Message-Id: <20220930220312.135327-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Since we always pass dc->pc_curr, fold the arithmetic to zero displacement. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/translate-a64.c | 6 +++--- target/arm/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2621b3b36a..005fd767fb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -340,9 +340,9 @@ static void gen_exception_internal(int excp) gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); } -static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) +static void gen_exception_internal_insn(DisasContext *s, int excp) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, 0); gen_exception_internal(excp); s->base.is_jmp = DISAS_NORETURN; } @@ -2219,7 +2219,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. */ if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, EXCP_SEMIHOST); } else { unallocated_encoding(s); } diff --git a/target/arm/translate.c b/target/arm/translate.c index f9d3128656..e0b1d415a2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1078,10 +1078,10 @@ static inline void gen_smc(DisasContext *s) s->base.is_jmp = DISAS_SMC; } -static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) +static void gen_exception_internal_insn(DisasContext *s, int excp) { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, 0); gen_exception_internal(excp); s->base.is_jmp = DISAS_NORETURN; } @@ -1173,7 +1173,7 @@ static inline void gen_hlt(DisasContext *s, int imm) */ if (semihosting_enabled(s->current_el != 0) && (imm == (s->thumb ? 0x3c : 0xf000))) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, EXCP_SEMIHOST); return; } @@ -6560,7 +6560,7 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) if (arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled(s->current_el == 0) && (a->imm == 0xab)) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, EXCP_SEMIHOST); } else { gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); } @@ -8766,7 +8766,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled(s->current_el == 0) && (a->imm == semihost_imm)) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, EXCP_SEMIHOST); } else { gen_update_pc(s, curr_insn_len(s)); s->svc_imm = a->imm; From patchwork Fri Sep 30 22:03:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610979 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1768224pvb; Fri, 30 Sep 2022 15:13:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM435l3yNcoiEEwHJXGO7foXNYVfnGxk12vKCDnk7vTG4a9RDpmINPmKb2Eu7uSf8YTMRzBk X-Received: by 2002:a05:622a:510:b0:35d:50dd:3062 with SMTP id l16-20020a05622a051000b0035d50dd3062mr8644193qtx.437.1664575988316; Fri, 30 Sep 2022 15:13:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664575988; cv=none; d=google.com; s=arc-20160816; b=q8CCkFkBnj/LgTeZJzIezhG7zcImWk1pJ6F3rbOmXtxbwrM+g7gghOz5Vc4npsV8A4 sbxHNHz2lAmHBNpQUNk5VcpqEbku75oPacvp5oe0+4MJ+wTOiWEHlX5Ln04OxJ6k17gF ifvGhCvFr7XYQJvguANf/gSQLEEPnkRvvWs9qvpRFdnbAfpCT1BKSm57xZzsKgdyCxeT yDf7bM5fhBF7B/n7sL0FypRK4JZmY+PfnRErXg/SBNsc/zK2ckZ45xCztat8S6Ym/Otk GElev+L4hmMC7eROjcjS78jEJLKQxb71cd4MYxg25s6xLVplbKVzChYuHydBRXq0plij jjaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3hKb/je4nMUKelmVIMgrIA0fdH/qZbe18AKzmaatg8o=; b=gQSQEhFyDCioodkiqZqI+n3/JDvsQhASdePC6JXaQ1jBjS5h5mBjy+NYOvJSeYJ3pb UUD2HPMNg7ewWtbSdkA7ZnsYn6f1cznWkN3Ue7gn+kUUjIWM88Uezh4CcHrj97nL4XXV EUxpSYn6ryucSu4azBgzd3ro4dsMGrByiG5ZR2wxB5E0+p/ZrJPtzoZu1XGrJkWSpzlV TnSJwkOosHvMmPcDH9Kv1NzNIy9TNhb0XeuIfPuF/guRbvBQKGXgDm/mGObFCmcogxar NUTDPML0XY3fn5lsJ8fQUe14271zQcL3E2+uk2IbxMT3yG4gmYttRqPNhLkrQleCb5Mo 6Srg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yy6MxWq1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h15-20020a05620a400f00b006bb5c2c817bsi2230440qko.497.2022.09.30.15.13.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:13:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yy6MxWq1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeOFn-0008PU-T1 for patch@linaro.org; Fri, 30 Sep 2022 18:13:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6U-0001lN-Dv for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:30 -0400 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]:40515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6S-0002Zd-Ix for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:30 -0400 Received: by mail-qv1-xf2c.google.com with SMTP id h10so1924814qvq.7 for ; Fri, 30 Sep 2022 15:03:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=3hKb/je4nMUKelmVIMgrIA0fdH/qZbe18AKzmaatg8o=; b=yy6MxWq1YV0tj9Nk8BFm7dLU5pvB2Q/au1KarvkTXo0lT3HgyiTou1MaoKbLO74uC5 NS0IuDbpH3xCHDx1jzleAMwXyfYW79hamLMWEORgAGeNGktYOZsHik0ApNlGHyyW2DfW 9dIFh6PfUqiNY4lA4e+ze+igYUNpyy03jKBVxYfaNuRgJqhYgUenPRbntbMPrzsA3+CB PDJ3OHbxfTdSP6UA62boQWn78hIX0q2XIh3vObCJlc/Q6DkWFoGTJEzyfBU/LCezZ+QX H85og6OFTl9/4obet+U4EbGJhlWZ0x2NNfhbeyHiUnS+BEWyw1hPnVu1Vu3yJ7Qf3Q7N JsyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=3hKb/je4nMUKelmVIMgrIA0fdH/qZbe18AKzmaatg8o=; b=EO2skJLxINu0fhyPySxqOvsKOh2/AAn5FWty2mI+NgRhx0HBEGj/KjyosZlylXDoPI KfIINFCvw5UleVndjogcdZrl22C9pjBBj82bObi31trmuD8K+f0ZsPaJ5nVsyjKN5Xmm K4yqYGFGncY3Uzp//WQeyvn9mqOjEF3pLH8aMgHGxByiGOqzFlzg4CJNZ7GDhwMGYv8Z n7X9X3kSUPVxkvbE1PdWi2+9ojrTUCw/stPXZrxsZOERsozzn48QLJeu+hMx9B+MJvlq StudNL4nuFFZl0DS7SmtPZaPC6qvphxH2giUL3bwT7ClROc6h+xv6aP5TVpHAsVSpCqQ fw1w== X-Gm-Message-State: ACrzQf1uHqAXp6NkpiRkS9jKpJx6yTNT8ipF7rwCfcr1dxPkPyrWim56 TKbRGpaBIqXU7E/rzre0Y+oBTkuF8GO1qA== X-Received: by 2002:a05:6214:2307:b0:46e:5fbc:3c30 with SMTP id gc7-20020a056214230700b0046e5fbc3c30mr8547009qvb.21.1664575407578; Fri, 30 Sep 2022 15:03:27 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 6/9] target/arm: Change gen_jmp* to work on displacements Date: Fri, 30 Sep 2022 15:03:09 -0700 Message-Id: <20220930220312.135327-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e0b1d415a2..fd35db8c8c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -270,6 +270,12 @@ static uint32_t read_pc(DisasContext *s) return s->pc_curr + (s->thumb ? 4 : 8); } +/* The pc_curr difference for an architectural jump. */ +static target_long jmp_diff(DisasContext *s, target_long diff) +{ + return diff + (s->thumb ? 4 : 8); +} + /* Set a variable to the value of a CPU register. */ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { @@ -2596,7 +2602,7 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, int n, int diff) +static void gen_goto_tb(DisasContext *s, int n, target_long diff) { target_ulong dest = s->pc_curr + diff; @@ -2612,10 +2618,8 @@ static void gen_goto_tb(DisasContext *s, int n, int diff) } /* Jump, specifying which TB number to use if we gen_goto_tb() */ -static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) +static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno) { - int diff = dest - s->pc_curr; - if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. */ gen_update_pc(s, diff); @@ -2657,9 +2661,9 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) } } -static inline void gen_jmp(DisasContext *s, uint32_t dest) +static inline void gen_jmp(DisasContext *s, target_long diff) { - gen_jmp_tb(s, dest, 0); + gen_jmp_tb(s, diff, 0); } static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) @@ -8326,7 +8330,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) static bool trans_B(DisasContext *s, arg_i *a) { - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8341,14 +8345,14 @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) return true; } arm_skip_unless(s, a->cond); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } static bool trans_BL(DisasContext *s, arg_i *a) { tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8368,7 +8372,8 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); store_cpu_field_constant(!s->thumb, thumb); - gen_jmp(s, (read_pc(s) & ~3) + a->imm); + /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ + gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm); return true; } @@ -8529,10 +8534,10 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * when we take this upcoming exit from this TB, so gen_jmp_tb() is OK. */ } - gen_jmp_tb(s, s->base.pc_next, 1); + gen_jmp_tb(s, curr_insn_len(s), 1); gen_set_label(nextlabel); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8612,7 +8617,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) if (a->f) { /* Loop-forever: just jump back to the loop start */ - gen_jmp(s, read_pc(s) - a->imm); + gen_jmp(s, jmp_diff(s, -a->imm)); return true; } @@ -8643,7 +8648,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tcg_temp_free_i32(decr); } /* Jump back to the loop start */ - gen_jmp(s, read_pc(s) - a->imm); + gen_jmp(s, jmp_diff(s, -a->imm)); gen_set_label(loopend); if (a->tp) { @@ -8651,7 +8656,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); } /* End TB, continuing to following insn */ - gen_jmp_tb(s, s->base.pc_next, 1); + gen_jmp_tb(s, curr_insn_len(s), 1); return true; } @@ -8750,7 +8755,7 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, tmp, 0, s->condlabel); tcg_temp_free_i32(tmp); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } From patchwork Fri Sep 30 22:03:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610981 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1770643pvb; Fri, 30 Sep 2022 15:18:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Rjzv10c19Dup7cnsLuKrpzuh1MSChdvPA786OzUN+mbkD+lICN2Agpy/84FoOZas/+4Y8 X-Received: by 2002:a05:6214:20e5:b0:4aa:b01f:471f with SMTP id 5-20020a05621420e500b004aab01f471fmr8754492qvk.38.1664576331757; Fri, 30 Sep 2022 15:18:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664576331; cv=none; d=google.com; s=arc-20160816; b=QpPjCkysO/Xs3+FTE4RfprfppHXf+GcmHtvHO5i8w1KZy/L2jU2HSCSVwTOxYSrGV5 VfH7a5+BO7qe/V4v7IXu3JYlRs8TOX5FEy48u7r9FK3adB1xnupQDo2pzU5p2gIldHWq zLIoHJPApA6q/J4k3M1emXebrr0Mrjq002sjfrG2qeLyj+Os1AIxsPksomZ5BMft+D9F a8NJJhTzpPdsPD9LVZQmacrW7JUEEaR1IKElo5WdEtwhRIecmeJyarDQ8G8xXjpPxnJN 783aA23VH6dha9V2q1I069EBD9OxytxVYXcnDZmx+xb8tJBGDZ/7wwOpkTJVe8S3VIvU l9rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hvGMsQzzrx+sQNIbudB82iz6OLqksguoV+s5DVfw4Xw=; b=QaURcSEZZhx9A5h78uTfvsMUmUMnFeQyv51Wim0NRaH8dSJf9esY7Vj6uejIc3wEKL JPf/nlsLlW4YBWpDIkmLp/DvYVJrP2yl0BpmHhW38ExmGmC7XpHDIz18lTS4ZduQ9KsV xBy/N7nINjazD5Y9JrloprTbcCY+QG/QmdTOtq0ZIwTp/s/n1ebxSe7QPXzVj3K1gmu9 wokhmv5q0Ua8BoJovX5e8TMXG3aB9DQHeYUTFObZmPfJ21zmdcgXa2wYYcpKAbvUzpWy T/TyZH2mt+9BtQ0hSErEECHaf7fvK9Ure3gG2C+L06ZUO8XVLqsAhkSnOALhWp1Sr+ZK /Arw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eiaoGbG4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gw15-20020a0562140f0f00b004acbf8f20bcsi497214qvb.492.2022.09.30.15.18.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:18:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eiaoGbG4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeOLL-0004J8-9j for patch@linaro.org; Fri, 30 Sep 2022 18:18:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6b-00025F-AC for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:37 -0400 Received: from mail-qv1-xf35.google.com ([2607:f8b0:4864:20::f35]:41609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6U-0002a9-Fj for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:36 -0400 Received: by mail-qv1-xf35.google.com with SMTP id l14so3627535qvq.8 for ; Fri, 30 Sep 2022 15:03:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=hvGMsQzzrx+sQNIbudB82iz6OLqksguoV+s5DVfw4Xw=; b=eiaoGbG450p/2PA7qXJpqyzZs4PMTJa8rAvZ+khC+reyG6yeLvAHLGKxEaXBMXY/tX qliOHqPBH9/IRNB/N2zd8By82qWXe+GoipPCwrtbw5fIi1nUslUkOdyzjIid4MyCfZ3Q LNwlovEr7wCen3Bjvb14wlS0cvQrG3PZbQwr3TFZXB+/7gfcVLnd8ZfE0+m/06J5lirP zRNwvSBvaC1Lf6+qS80V6IwlH2CtKhGPqBmAzDejAQxwj2ZIWYi+QpOgYCOhQbnJJFgW TWMI9fAEHYgfnAdx8VCOLBgFRL5xexpF6gtMnSVP4VkFBmngs9P5BZFhU1gPkggkTkf4 wH4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=hvGMsQzzrx+sQNIbudB82iz6OLqksguoV+s5DVfw4Xw=; b=z1TgA1MMhCkr/K7PiydLdV9nDDMe4k5sHWW13lxfF6O1b1C/R+IxbFn3ACuG/rVTog ZuV7WQNM/w8Zk832DyQJieoc7eWHrP+e6f+ZEOFhLrsLru+fPkHgLlSwT9BNh2cLywet 8J85R7EIUe3EGI50st9Ae/mjt+Tv5uZDED3HkqpLp0H3LicN2WJfOZeTjl6yZ35OqZbu DB7Xs8jV0Ws6FfwPswtRLrjP0fDCHhdZqElmH5Ag856a80gtuf8lCKQcC0mOVTYbg3H7 8Iz1MDGaI8qk8qpAeOffI1eiIV9aBvUShMbIYjXb0eKB6/EColAEirJ5usPQKVp7wdpq QCOg== X-Gm-Message-State: ACrzQf1PoS1d7E46I8tiG8OMnwHVR7DVvKRmi4T6uYiuNRZ1p8WGG1im yVzO/1inWp5DjLd9hsy7RvRk6FMJOfcapA== X-Received: by 2002:a05:6214:27c1:b0:473:85c9:3eeb with SMTP id ge1-20020a05621427c100b0047385c93eebmr8830144qvb.53.1664575409138; Fri, 30 Sep 2022 15:03:29 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 7/9] target/arm: Introduce gen_pc_plus_diff for aarch64 Date: Fri, 30 Sep 2022 15:03:10 -0700 Message-Id: <20220930220312.135327-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 005fd767fb..28a417fb2b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,14 @@ static void reset_btype(DisasContext *s) } } +static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff) +{ + tcg_gen_movi_i64(dest, s->pc_curr + diff); +} + void gen_a64_update_pc(DisasContext *s, target_long diff) { - tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_pc, diff); } /* @@ -1368,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) if (insn & (1U << 31)) { /* BL Branch with link */ - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); } /* B Branch / BL Branch with link */ @@ -2309,11 +2314,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; case 8: /* BRAA */ @@ -2336,11 +2347,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } else { dst = cpu_reg(s, rn); } - gen_a64_set_pc(s, dst); /* BLRAA also needs to load return address */ if (opc == 9) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; case 4: /* ERET */ @@ -2908,7 +2925,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) tcg_rt = cpu_reg(s, rt); - clean_addr = tcg_constant_i64(s->pc_curr + imm); + clean_addr = new_tmp_a64(s); + gen_pc_plus_diff(s, clean_addr, imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -4252,23 +4270,22 @@ static void disas_ldst(DisasContext *s, uint32_t insn) static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { unsigned int page, rd; - uint64_t base; - uint64_t offset; + int64_t offset; page = extract32(insn, 31, 1); /* SignExtend(immhi:immlo) -> offset */ offset = sextract64(insn, 5, 19); offset = offset << 2 | extract32(insn, 29, 2); rd = extract32(insn, 0, 5); - base = s->pc_curr; if (page) { /* ADRP (page based) */ - base &= ~0xfff; offset <<= 12; + /* The page offset is ok for TARGET_TB_PCREL. */ + offset -= s->pc_curr & 0xfff; } - tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); + gen_pc_plus_diff(s, cpu_reg(s, rd), offset); } /* From patchwork Fri Sep 30 22:03:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610977 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1767039pvb; Fri, 30 Sep 2022 15:10:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4EI23LF9st3XXW9WHv5Bn42rwSFFpt8uS8uI1Zwneq+bhCg6JXm+HQjpgGATmUgPlmtmAN X-Received: by 2002:a05:620a:987:b0:6cb:cdf2:ee34 with SMTP id x7-20020a05620a098700b006cbcdf2ee34mr7452932qkx.429.1664575814154; Fri, 30 Sep 2022 15:10:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664575814; cv=none; d=google.com; s=arc-20160816; b=ngJ14X47RrSuOW4xL9Nz2HF/bljAlnUQGJEhZnZR4iffVKNiRy/Hm78n4YGFrC6G/U xgn2yCrzXqLzUhhBwddh4F6nfEjhLg9mS/rY1Ii+OFCUI/PL2T4a4GBJetwFjGXUUyqp CZXvpMUMOEm8pEUsnMmoyXxnj0tnUQyP2YyVdfZe5sa0L0h/9FD5dv/HPw+9s+OfFTbK YOX/bCdgedcAEZr8wO8fc+4WEjthx284nGfwmRY9FKvxgExwg6G4Q8y3z5idZour89Ab HwgTSMSgT6HMqlynqbTZQMo506MUijhiN0XM4e90me80GnHryh4WjrkkzZE6wWSIzVfu Dhzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XYRaFM7NBrkMyyb5R6XrzLrGa558v90pQOaMAn7lGPk=; b=abmp9JO20HUCekAMZYdvmMuhA1oLSqFEgbKjK3A+AI1pJRxdpALosk6ekNS/+x4yIf ruU/Knqc9lEb+m6ubNjsVFLjVfmo7l8Bsw6LhRM1orrQuOJeH3dKL5ojgWm3WvTTVciF GRYrQchtCj3a+AJrQUzxt0avHK05IQLVwalACSEv32sNDE4oOVXFTgwArqh4fkCM9JOj 4tmO1mzi7yHalKkokLBUEWLsnXejA5t1GNmRo4idZehpHPrpnd8MCHn3ta/HkHvGp7cK DGL5fOhuKcX5LfEzUBmIDrMOrsdpsl8cXvkOyQvWkR2xxO55YiQ1lYe/s0+CVbYGavND 0tKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rI6yTkKj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f14-20020ac8014e000000b0035ced7a27c0si1795629qtg.568.2022.09.30.15.10.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:10:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rI6yTkKj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeOCz-0001bd-MW for patch@linaro.org; Fri, 30 Sep 2022 18:10:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6Y-0001xj-OW for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:34 -0400 Received: from mail-qv1-xf30.google.com ([2607:f8b0:4864:20::f30]:45905) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6W-0002aT-T4 for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:34 -0400 Received: by mail-qv1-xf30.google.com with SMTP id m18so3622198qvo.12 for ; Fri, 30 Sep 2022 15:03:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=XYRaFM7NBrkMyyb5R6XrzLrGa558v90pQOaMAn7lGPk=; b=rI6yTkKjofz8jEr9XLfNhWVOBExlrXv/bvy9Ps5Oq3kW3b4e7ChbvYn8HZAmrLE6Ox f1Hqyc9CXBY/ETROk3RBeASrGPIxzzgB1ASOouXy+gJQKnqWUpfXQQLo3hvajTRX84qQ 5inH7n1LO54jzEJUSvPdC0nFe+zITo9p2z/545v1ft66A3+4jxUMH8TMQGTwlpgsoKmc Aphvnp/z96pTDX9tQsOkmsFIw+5lGcODobV846xYqShWSZ7uRI7FVeTd2DVMCvEqUbWs jAwLIBcIA40Iw3gEvjDAVYMf897Gjcw+jNGEvKJtgvLLKjWtEES22mPPrEHKr5UlX+zm QgNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=XYRaFM7NBrkMyyb5R6XrzLrGa558v90pQOaMAn7lGPk=; b=lINdkI/GKv4EGeViwl3aA+TMtEXaM5D53VHD3BND63h7d6+b3oWoyg94JwAUMFIx1f +bbokk6GbwUlVwiBIq9v0HaIP/oGkPHiJi38LUqRAUg/FS9dEfznH5DlwOKV2g0bmylP 8ifM3xPvzw3PMaCV7WdEvYabIBTaWCsrzyrpqnOmWqlSVeu3q6n0W2DBmis09xsTDh7z OtiIkoDxGoesknvenGUxaDTl/h5OSyurunnhNQ+kYsvZMLvd2A61PazFkDXpW+oa6oe4 cThNysRLef2g0WWYDlJ7MMVoGQ3JuzmGO8JBTrlL/9nDEuyzwR6rj9WYWkJiGSsB6Ieu 8OHw== X-Gm-Message-State: ACrzQf1acf+CJMidZYn8iFP4MSSsAHYFAZYxezx8cApiHW9s+hSEDehg ARFy0QsBDLy/vVyOKBmP851QIebDY/JI5g== X-Received: by 2002:a05:6214:21a5:b0:4af:b677:7429 with SMTP id t5-20020a05621421a500b004afb6777429mr5700033qvc.60.1664575410834; Fri, 30 Sep 2022 15:03:30 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 8/9] target/arm: Introduce gen_pc_plus_diff for aarch32 Date: Fri, 30 Sep 2022 15:03:11 -0700 Message-Id: <20220930220312.135327-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f30; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fd35db8c8c..050da9e740 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -276,11 +276,16 @@ static target_long jmp_diff(DisasContext *s, target_long diff) return diff + (s->thumb ? 4 : 8); } +static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff) +{ + tcg_gen_movi_i32(var, s->pc_curr + diff); +} + /* Set a variable to the value of a CPU register. */ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { if (reg == 15) { - tcg_gen_movi_i32(var, read_pc(s)); + gen_pc_plus_diff(s, var, jmp_diff(s, 0)); } else { tcg_gen_mov_i32(var, cpu_R[reg]); } @@ -296,7 +301,8 @@ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) TCGv_i32 tmp = tcg_temp_new_i32(); if (reg == 15) { - tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs); + /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ + gen_pc_plus_diff(s, tmp, (read_pc(s) & ~3) - s->pc_curr + ofs); } else { tcg_gen_addi_i32(tmp, cpu_R[reg], ofs); } @@ -1159,7 +1165,7 @@ void unallocated_encoding(DisasContext *s) /* Force a TB lookup after an instruction that changes the CPU state. */ void gen_lookup_tb(DisasContext *s) { - tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); + gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s)); s->base.is_jmp = DISAS_EXIT; } @@ -6483,7 +6489,7 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return false; } tmp = load_reg(s, a->rm); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_bx(s, tmp); return true; } @@ -8351,7 +8357,7 @@ static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) static bool trans_BL(DisasContext *s, arg_i *a) { - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8370,7 +8376,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) if (s->thumb && (a->imm & 2)) { return false; } - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); store_cpu_field_constant(!s->thumb, thumb); /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm); @@ -8380,7 +8386,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) { assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + gen_pc_plus_diff(s, cpu_R[14], jmp_diff(s, a->imm << 12)); return true; } @@ -8390,7 +8396,7 @@ static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a) assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8406,7 +8412,7 @@ static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a) tmp = tcg_temp_new_i32(); tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8729,10 +8735,11 @@ static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) tcg_gen_add_i32(addr, addr, tmp); gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); - tcg_temp_free_i32(addr); tcg_gen_add_i32(tmp, tmp, tmp); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + gen_pc_plus_diff(s, addr, jmp_diff(s, 0)); + tcg_gen_add_i32(tmp, tmp, addr); + tcg_temp_free_i32(addr); store_reg(s, 15, tmp); return true; } From patchwork Fri Sep 30 22:03:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 610980 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1769825pvb; Fri, 30 Sep 2022 15:16:35 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4t5FTP5Qka4O++owgCpx64ZJJM+M+pUrmNBIGepmknLWv4SfJ5Av0EUpYjuaCB+2H0YrAG X-Received: by 2002:a0c:c3cf:0:b0:4af:b677:7428 with SMTP id p15-20020a0cc3cf000000b004afb6777428mr5760274qvi.102.1664576195512; Fri, 30 Sep 2022 15:16:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664576195; cv=none; d=google.com; s=arc-20160816; b=R3gRmlnvvslUETU6t9hx2xCdJedxcw213HzHUuKEuIuh7+zclFd5VYBBGdUdktBgxp kSnW7dUXfWeVSWIjJ8D9grWpH7UY0N8NPDKvQsVh2tF+HNsLbeCixXVEmotVLBfydAgu upHp0yVIAvZxyl61JdOd0bf18dM0iwLaS+lvqbe8+ddfXEbdORWqsn4bT8qod+yOqACZ vYKp69Blsm5eTC8o9S5dla9mEgYkdpLoToxjmXFlbzzEvJaiYEGDeryAGCtnS7qnHqFm jl6MMi2/joCSgiuLX7rTQ4MhnZEiab/CuRhegG9libwpiYefwBPNPBVqZEEagLqIMzLx Ouhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/CcgGI12plS/lfJEOR9586DslscxVOBysCaDTBeg4l8=; b=hU50G5DuGJbOVYo3sV8ZvEPKjKXgGsLKv+IG2H6LbkXdqHRL3W1Ol9W6bxsOB/M9Vm d6datlFJBC3o/w+FztMz71aU6y8BaT2qMUKmZPO05xrEOB7/DoBGNDaB6B/+lSzXi7AZ Zqhz7Lc8VESN3og3LxB3x8QvR7eGVo59CG12j7rfAAUwA3KQ/ukBx78c6dk62PKbDlEj 5pgj72dOmntR6H8I0YeAsiVowtB/j95nVmX7eVgPH+RhABdJ/d59l63qUYRTcmfIk5Kd eqiJ5xEEVOf1ExyOrn92pcHk5uV+G/GtHvq35nlNOGGdtDNR0Kgyp68URWB5MYtHPepF C3iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aVmqx8Uc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ci17-20020a05622a261100b0035bb169319bsi1775643qtb.512.2022.09.30.15.16.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 30 Sep 2022 15:16:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aVmqx8Uc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oeOJ9-0002Vv-2J for patch@linaro.org; Fri, 30 Sep 2022 18:16:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oeO6a-000243-Ol for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:36 -0400 Received: from mail-qk1-x72d.google.com ([2607:f8b0:4864:20::72d]:45892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oeO6X-0002an-Tk for qemu-devel@nongnu.org; Fri, 30 Sep 2022 18:03:36 -0400 Received: by mail-qk1-x72d.google.com with SMTP id i17so3652068qkk.12 for ; Fri, 30 Sep 2022 15:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=/CcgGI12plS/lfJEOR9586DslscxVOBysCaDTBeg4l8=; b=aVmqx8UcUP0L1WrKPbww8Z+13UZa3SeIlVoWzPe6fktMdLJ1KoO2gx1qRs0Xs2tD3w IrW+fFsDDjGO6j8LerAW6MYyQlA1ZUTsLg9FnUONXa2T9HBctXJ5+QkcrvOF/CeFn+Aq Dg7vToXF4z4wZd5mcYEuVHx2/iv4pnjs5suV5OxZ8ERX9tTqnWlsy8slsQz93y++klFG OWa/bXWIrAn1LxpEpdVK87wp7zeigl3ZbNawKjMIGSnzCBa4O6goXaV4qw9/dblc3LRK lK0Sk9LPkrXzIA1NpMqG0mpJlC9JT0RhZufZDZ/56fi4Bt1S3LZCZBKwNIerGNj78FNa pycw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=/CcgGI12plS/lfJEOR9586DslscxVOBysCaDTBeg4l8=; b=Kv83FJ4HO1SD1zWDQReCWeQadWH95M21sqCwxIoBpqieknfatkpdxox9V3VbJ31RGq Jo7oXDgel4nIHVhHd2CtmYm1JgSPuxxzRkGAZa2v9kBC5jlR4NlH/WuLUme8LNEuY9kr gJy4wjotOeIxG60AFdw5UjGxj/M9osKB01gir30V7qs6BA86/0xqketcirIDWxDVoHaJ BHmCHnxLoaRzedmtFN+4av63qock0f9CY1+ai2b6mlJW0ZYFoJOhZTA1veEuzoc7WvB1 jJGv7HdxLRaaNplEfSV8KT6L99wuAiILYK98XQ06912xt45bfVYIHD7ZjDYehLDK/Z6b kW3w== X-Gm-Message-State: ACrzQf1sdwWu4Y4fQEOkHXKLESa56OoQwuUIxaoiWi1KnxYr9T5t4UeI wWFpzBpGm49mzkTeRXY01veBvTs2HYQPPw== X-Received: by 2002:a05:620a:2809:b0:6bc:5e42:fef9 with SMTP id f9-20020a05620a280900b006bc5e42fef9mr7765371qkp.278.1664575412742; Fri, 30 Sep 2022 15:03:32 -0700 (PDT) Received: from stoup.. ([2605:ef80:80a1:5a60:d0d7:468b:5667:114b]) by smtp.gmail.com with ESMTPSA id o15-20020a05620a22cf00b006bb78d095c5sm3196055qki.79.2022.09.30.15.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Sep 2022 15:03:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 9/9] target/arm: Enable TARGET_TB_PCREL Date: Fri, 30 Sep 2022 15:03:12 -0700 Message-Id: <20220930220312.135327-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220930220312.135327-1-richard.henderson@linaro.org> References: <20220930220312.135327-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 1 + target/arm/translate.h | 19 ++++++++++++ target/arm/cpu.c | 23 +++++++------- target/arm/translate-a64.c | 37 ++++++++++++++++++----- target/arm/translate.c | 62 ++++++++++++++++++++++++++++++-------- 5 files changed, 112 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..29c5fc4241 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -30,6 +30,7 @@ */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 +# define TARGET_TB_PCREL 1 #endif #define NB_MMU_MODES 15 diff --git a/target/arm/translate.h b/target/arm/translate.h index 4aa239e23c..41d14cc067 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -12,6 +12,25 @@ typedef struct DisasContext { /* The address of the current instruction being translated. */ target_ulong pc_curr; + /* + * For TARGET_TB_PCREL, the full value of cpu_pc is not known + * (although the page offset is known). For convenience, the + * translation loop uses the full virtual address that triggered + * the translation is used, from base.pc_start through pc_curr. + * For efficiency, we do not update cpu_pc for every instruction. + * Instead, pc_save has the value of pc_curr at the time of the + * last update to cpu_pc, which allows us to compute the addend + * needed to bring cpu_pc current: pc_curr - pc_save. + * If cpu_pc now contains the destiation of an indirect branch, + * pc_save contains -1 to indicate that relative updates are no + * longer possible. + */ + target_ulong pc_save; + /* + * Similarly, pc_cond_save contains the value of pc_save at the + * beginning of an AArch32 conditional instruction. + */ + target_ulong pc_cond_save; target_ulong page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 94ca6f163f..0bc5e9b125 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -76,17 +76,18 @@ static vaddr arm_cpu_get_pc(CPUState *cs) void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - /* - * It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - */ - if (is_a64(env)) { - env->pc = tb_pc(tb); - } else { - env->regs[15] = tb_pc(tb); + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + CPUARMState *env = cs->env_ptr; + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc = tb_pc(tb); + } else { + env->regs[15] = tb_pc(tb); + } } } #endif /* CONFIG_TCG */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 28a417fb2b..57cfc9f1a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -150,12 +150,18 @@ static void reset_btype(DisasContext *s) static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff) { - tcg_gen_movi_i64(dest, s->pc_curr + diff); + assert(s->pc_save != -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i64(dest, s->pc_curr + diff); + } } void gen_a64_update_pc(DisasContext *s, target_long diff) { gen_pc_plus_diff(s, cpu_pc, diff); + s->pc_save = s->pc_curr + diff; } /* @@ -209,6 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) * then loading an address into the PC will clear out any tag. */ gen_top_byte_ignore(s, cpu_pc, src, s->tbii); + s->pc_save = -1; } /* @@ -347,16 +354,22 @@ static void gen_exception_internal(int excp) static void gen_exception_internal_insn(DisasContext *s, int excp) { + target_ulong pc_save = s->pc_save; + gen_a64_update_pc(s, 0); gen_exception_internal(excp); s->base.is_jmp = DISAS_NORETURN; + s->pc_save = pc_save; } static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { + target_ulong pc_save = s->pc_save; + gen_a64_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp = DISAS_NORETURN; + s->pc_save = pc_save; } static void gen_step_complete_exception(DisasContext *s) @@ -385,11 +398,16 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest) static void gen_goto_tb(DisasContext *s, int n, int64_t diff) { - uint64_t dest = s->pc_curr + diff; + target_ulong pc_save = s->pc_save; - if (use_goto_tb(s, dest)) { - tcg_gen_goto_tb(n); - gen_a64_update_pc(s, diff); + if (use_goto_tb(s, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_a64_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_a64_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); s->base.is_jmp = DISAS_NORETURN; } else { @@ -401,6 +419,7 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff) s->base.is_jmp = DISAS_NORETURN; } } + s->pc_save = pc_save; } static void init_tmp_a64_array(DisasContext *s) @@ -14707,7 +14726,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->isar = &arm_cpu->isar; dc->condjmp = 0; - + dc->pc_save = dc->base.pc_first; dc->aarch64 = true; dc->thumb = false; dc->sctlr_b = 0; @@ -14789,8 +14808,12 @@ static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_arg = dc->base.pc_next; - tcg_gen_insn_start(dc->base.pc_next, 0, 0); + if (TARGET_TB_PCREL) { + pc_arg &= ~TARGET_PAGE_MASK; + } + tcg_gen_insn_start(pc_arg, 0, 0); dc->insn_start = tcg_last_op(); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 050da9e740..b4b82dc4a5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -164,6 +164,7 @@ void arm_gen_condlabel(DisasContext *s) if (!s->condjmp) { s->condlabel = gen_new_label(); s->condjmp = 1; + s->pc_cond_save = s->pc_save; } } @@ -278,7 +279,12 @@ static target_long jmp_diff(DisasContext *s, target_long diff) static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff) { - tcg_gen_movi_i32(var, s->pc_curr + diff); + assert(s->pc_save != -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i32(var, s->pc_curr + diff); + } } /* Set a variable to the value of a CPU register. */ @@ -321,6 +327,7 @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var) */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); s->base.is_jmp = DISAS_JUMP; + s->pc_save = -1; } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) { /* For M-profile SP bits [1:0] are always zero */ tcg_gen_andi_i32(var, var, ~3); @@ -786,7 +793,8 @@ void gen_set_condexec(DisasContext *s) void gen_update_pc(DisasContext *s, target_long diff) { - tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_R[15], diff); + s->pc_save = s->pc_curr + diff; } /* Set PC and Thumb state from var. var is marked as dead. */ @@ -796,6 +804,7 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); + s->pc_save = -1; } /* @@ -1118,6 +1127,8 @@ static void gen_exception(int excp, uint32_t syndrome) static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_el) { + target_ulong pc_save = s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1126,6 +1137,7 @@ static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff, } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp = DISAS_NORETURN; + s->pc_save = pc_save; } void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, @@ -1138,6 +1150,8 @@ void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, void gen_exception_insn(DisasContext *s, target_long pc_diff, int excp, uint32_t syn) { + target_ulong pc_save = s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1146,6 +1160,7 @@ void gen_exception_insn(DisasContext *s, target_long pc_diff, } gen_exception(excp, syn); s->base.is_jmp = DISAS_NORETURN; + s->pc_save = pc_save; } static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) @@ -2610,11 +2625,14 @@ static void gen_goto_ptr(void) */ static void gen_goto_tb(DisasContext *s, int n, target_long diff) { - target_ulong dest = s->pc_curr + diff; - - if (translator_use_goto_tb(&s->base, dest)) { - tcg_gen_goto_tb(n); - gen_update_pc(s, diff); + if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); } else { gen_update_pc(s, diff); @@ -2626,10 +2644,13 @@ static void gen_goto_tb(DisasContext *s, int n, target_long diff) /* Jump, specifying which TB number to use if we gen_goto_tb() */ static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno) { + target_ulong pc_save = s->pc_save; + if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. */ gen_update_pc(s, diff); s->base.is_jmp = DISAS_JUMP; + s->pc_save = pc_save; return; } switch (s->base.is_jmp) { @@ -2665,6 +2686,7 @@ static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno) */ g_assert_not_reached(); } + s->pc_save = pc_save; } static inline void gen_jmp(DisasContext *s, target_long diff) @@ -9326,7 +9348,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->isar = &cpu->isar; dc->condjmp = 0; - + dc->pc_save = dc->base.pc_first; dc->aarch64 = false; dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; @@ -9481,13 +9503,17 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) * fields here. */ uint32_t condexec_bits; + target_ulong pc_arg = dc->base.pc_next; + if (TARGET_TB_PCREL) { + pc_arg &= ~TARGET_PAGE_MASK; + } if (dc->eci) { condexec_bits = dc->eci << 4; } else { condexec_bits = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); } - tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); + tcg_gen_insn_start(pc_arg, condexec_bits, 0); dc->insn_start = tcg_last_op(); } @@ -9530,7 +9556,10 @@ static bool arm_check_ss_active(DisasContext *dc) static void arm_post_translate_insn(DisasContext *dc) { - if (dc->condjmp && !dc->base.is_jmp) { + if (dc->condjmp && dc->base.is_jmp == DISAS_NEXT) { + if (dc->pc_save != dc->pc_cond_save) { + gen_update_pc(dc, dc->pc_cond_save - dc->pc_save); + } gen_set_label(dc->condlabel); dc->condjmp = 0; } @@ -9860,6 +9889,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) if (dc->condjmp) { /* "Condition failed" instruction codepath for the branch/trap insn */ + dc->pc_save = dc->pc_cond_save; gen_set_label(dc->condlabel); gen_set_condexec(dc); if (unlikely(dc->ss_active)) { @@ -9922,11 +9952,19 @@ void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, target_ulong *data) { if (is_a64(env)) { - env->pc = data[0]; + if (TARGET_TB_PCREL) { + env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + env->pc = data[0]; + } env->condexec_bits = 0; env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; } else { - env->regs[15] = data[0]; + if (TARGET_TB_PCREL) { + env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; + } else { + env->regs[15] = data[0]; + } env->condexec_bits = data[1]; env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; }