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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.39.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:52 -0800 Message-Id: <20190223023957.18865-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This was defined at some point before ARMv8.4, and will shortly be used by new processor descriptions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 84ae6849c2..c57f8e9ba8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -863,6 +863,7 @@ struct ARMCPU { uint32_t reset_sctlr; uint32_t id_pfr0; uint32_t id_pfr1; + uint32_t id_pfr2; uint32_t id_dfr0; uint64_t pmceid0; uint64_t pmceid1; diff --git a/target/arm/helper.c b/target/arm/helper.c index a018eb23fe..8903cc13d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6092,10 +6092,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = 0 }, + .resetvalue = cpu->id_pfr2 }, { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, From patchwork Sat Feb 23 02:39:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159092 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2442460jaa; Fri, 22 Feb 2019 18:43:27 -0800 (PST) X-Google-Smtp-Source: AHgI3IZQcZjbcNr1V8exepGKgRMJX7y/AuEurZJWZzbimSvXp9s1X9BXthQGHGpNQZp1yFNYFaGA X-Received: by 2002:a0d:d891:: with SMTP id a139mr5884451ywe.365.1550889807083; Fri, 22 Feb 2019 18:43:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550889807; cv=none; d=google.com; s=arc-20160816; b=x+FmEWodSC/k1ij8s1auvey8i/jl/fwx260QORMzXhBTUUSU/sBdQugVmpxi0o58X4 yfFXKTMmc67IH0kgWwrabIMGKivLBAW7H0N2UyMo/jSDfpGLhJqADPVtPTNarYyQKWNs PmpaxkDi5lzo2YZ+g0Xq8OSVcDb4KWnRyjPJEyTTjXQEfqYa08AKhtHYWUWaHmg2XtQy U/1ALdhtUOYKFjMzrClGoplkETGCRqX4KKWRacAw/x+Lrd2KqnvnJsDaZPuzUy3/jJK6 69mPVeVHddtVD2kE6T/2l7eM1KnIZMqXq9EQYf7ffxwAWkbcEo8JyRVotWgPESfms3vp 4ouA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=G4evj0XBLDZtPvZuW0tTZFLLxSmrGZzJJB60I33Ox90=; b=nUHjY17QRrYDZbd7D854G+GLZkDshS9fWQrjctM+HGIu7MW3SRlEKkfO+LpwRzXF/I 9UexPQk2UGGtPCWUxe0VLtBUD1txeAnnzj0p/UB/44yP3fKVK8e8vOopCJq19pl4GMan QQm3Oq/Pk/yudHLstHxJEKHB4yvm5VWshKQgfvnebrGbpbVhScTizLUpDV84X/5RMZoL l+DRga28V53la5zYfrv+i0lSCU/kwhxwgJS0B8LY7iXTSCfzr2IxtdTnRoDDTGBokuj5 El3mCAOKinph7mJ+ompGeQAIgkCrSMVNxBF4q1x9vobuKP7Py6eJq03NtQd4gE4XEmNh Iiqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Cei4nqcM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:53 -0800 Message-Id: <20190223023957.18865-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PATCH 2/6] target/arm: Define cortex-a73 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are new field definitions, CSV2 and CSV3, that do not yet appear in the main ARM ARM. Define the ID_AA64PF0 versions, since we already define the rest of those bits. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ hw/arm/virt.c | 1 + target/arm/cpu64.c | 63 +++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 62 insertions(+), 4 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c57f8e9ba8..c2899f0bed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1694,6 +1694,8 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SBSS, 4, 4) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d..c69a734878 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -173,6 +173,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a73"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eff0f164dd..d34aa3af75 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -51,7 +51,8 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) } #endif -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { +/* These extra registers are used by (most of?) the cortex-a* series. */ +static const ARMCPRegInfo cortex_aXX_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, @@ -149,7 +150,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } static void aarch64_a53_initfn(Object *obj) @@ -203,7 +204,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } static void aarch64_a72_initfn(Object *obj) @@ -255,7 +256,60 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + +static void aarch64_a73_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a73"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr = 0x411fd090; + cpu->revidr = 0x00000000; + cpu->reset_fpsid = 0x41034091; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x12111111; + cpu->isar.mvfr2 = 0x00000043; + cpu->ctr = 0x84448004; + cpu->reset_sctlr = 0x00c50838; + cpu->id_pfr0 = 0x00010131; + cpu->id_pfr1 = 0x00011011; + cpu->id_pfr2 = 0x00000001; + cpu->id_dfr0 = 0x03010066; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10201105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02102211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x00011121; + cpu->isar.id_aa64pfr0 = 0x1100000000002222ull; + cpu->id_aa64dfr0 = 0x10305106; + cpu->isar.id_aa64isar0 = 0x00011120; + cpu->isar.id_aa64mmfr0 = 0x00101122; + cpu->dbgdidr = 0x3516d000; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, @@ -378,6 +432,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, + { .name = "cortex-a73", .initfn = aarch64_a73_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, { .name = NULL } }; From patchwork Sat Feb 23 02:39:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159091 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2442311jaa; Fri, 22 Feb 2019 18:43:09 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ/TdFatE6XroFPXzcdNcI7qtp3ZJwdXU/Zyqjs9dkI9AlOywQlHNwN91Egap6DLc5ZEAg7 X-Received: by 2002:a25:61d1:: with SMTP id v200mr6033827ybb.517.1550889789439; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:54 -0800 Message-Id: <20190223023957.18865-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 3/6] target/arm: Implement ID_AA64MMFR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This was res0 before ARMv8.2, but will shortly be used by new processor definitions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 15 +++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 19 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c2899f0bed..02642a7db3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -855,6 +855,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8903cc13d8..fbdca9324b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6052,10 +6052,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64mmfr1 }, - { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr2 }, { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e3ba149248..c3d421b53b 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -542,6 +542,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); /* * Note that if AArch32 support is not present in the host, From patchwork Sat Feb 23 02:39:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159090 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2441031jaa; Fri, 22 Feb 2019 18:40:38 -0800 (PST) X-Google-Smtp-Source: AHgI3IbJBRaIiR+KBN+JvFHsReEpZ3e0CVZYdFqMn0VNVOtWcD7tpEpUML6IVHTgUF/ZR+foDHjm X-Received: by 2002:a0d:d906:: with SMTP id b6mr5864632ywe.366.1550889638802; Fri, 22 Feb 2019 18:40:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550889638; cv=none; d=google.com; s=arc-20160816; b=ano5WM5CelrBARZJihNuRGtH37Rphm3R763CNyHsrLU2FESvfH/DwN9QiFKjYwsZAf jvLRARCBQv3Sl2of2+4hDdwMegsDiE2mkCoMpbBOQUVmnsZTRFg3mdC3VzW8F8MNccq6 J8lVApucFF8SAFcNbVNB1ch2rCJMLZI8BOGYKzw0NbKGUYOO4mN8hXWf7oQfckXXT7jo pFqp99F7phhv4K81sLhtNOklvYfLdY4fREvIRt3oCwUCwbNVl5TqVe1odr0jK5bwgFb0 D6I/iwR8eShIc+afyltmJUdHS4RIOnvrPes2hJXq3rmzD1/nCuD9So7Iun+Ztzqdrmlf e9/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Xd+XJs977OpsIpeqRhkdr9DT8C+H7Lvg/r4UMKerwuM=; b=h0hceImLZ9pRryBbgsXEdCjwXChR0Jx7gOdkUBK5fY4Luvvo1T/xE2B8RjqAfo5H9f dd83/EcgIpTPGwwR9GA4VngMyRM9STKwsGWLY6wGzgGpszUp91+Xx6KMkHfV5l3VIGHM h7NZe/waMSJbSxRr2m2CURrxV752gqUqMnMW8ADkwENbphVZ/oMMpQAVKkqHdrDmfgBN zzQfbJsRywG/wmxX0MBmoxiF93JFYGBOl2diAm242mKNHNcx0tdwVAWV43+0f5clszP3 jyGnmfUu07L0BcT7R9R/kpzXcDdzpi3WDv4As3gOAS610YURy1gZCjl7XOxElhWZzeHW lIyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rPHAUNYM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:55 -0800 Message-Id: <20190223023957.18865-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- hw/arm/virt.c | 1 + target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) -- 2.17.2 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c69a734878..06a155724c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -174,6 +174,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a73"), + ARM_CPU_TYPE_NAME("cortex-a75"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d34aa3af75..325e0ecf17 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } +static void aarch64_a75_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a75"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr = 0x413fd0a1; + cpu->revidr = 0x00000000; + cpu->reset_fpsid = 0x410340a2; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x13211111; + cpu->isar.mvfr2 = 0x00000043; + cpu->ctr = 0x84448004; + cpu->reset_sctlr = 0x00c50838; /* ??? can't find it in a75 trm */ + cpu->id_pfr0 = 0x00010131; + cpu->id_pfr1 = 0x00011011; + cpu->id_pfr2 = 0x00000001; + cpu->id_dfr0 = 0x04010088; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10201105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02122211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x00011121; + cpu->isar.id_isar6 = 0x00000010; + cpu->isar.id_aa64pfr0 = 0x1100000010112222ull; + cpu->id_aa64dfr0 = 0x10305408; + cpu->isar.id_aa64isar0 = 0x10211120; + cpu->isar.id_aa64isar1 = 0x00100001; + cpu->isar.id_aa64mmfr0 = 0x00101124; + cpu->isar.id_aa64mmfr1 = 0x10212122; + cpu->isar.id_aa64mmfr2 = 0x00001011; + cpu->dbgdidr = 0x3518d000; + cpu->clidr = 0x08200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -433,6 +490,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "cortex-a73", .initfn = aarch64_a73_initfn }, + { .name = "cortex-a75", .initfn = aarch64_a75_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, { .name = NULL } }; From patchwork Sat Feb 23 02:39:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159093 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2443362jaa; Fri, 22 Feb 2019 18:45:05 -0800 (PST) X-Google-Smtp-Source: AHgI3IamuuoRZC5WpFGUKS2Y6a3y+WHx7vD/92ULQAfoHUTGk1ePLFatoQQrnFNGVDmhohWL1GQP X-Received: by 2002:a81:6f0b:: with SMTP id k11mr5843259ywc.245.1550889905654; Fri, 22 Feb 2019 18:45:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550889905; cv=none; d=google.com; s=arc-20160816; b=Y4DpPpeQmYDucPFWQZbmJVuwDyVOby/fKsZej/NO98UV+hxnCWUDZLh8q4hXfxQiD+ GTbECnc1LgTGzUDFQnMXBmhXWUt1fKHMDr+o11BNsZq5d+DEBe2gKt4SemMSLkG//+Qo NB1WvchopdEml3I0EpdL15UY3T4rvvQfSidilSj9+PhEIHAM9EKdJ1x/FcL3yjpeYeNy erjI0HczewCEb2VujdA9ZvcfxHKBbjJCGCfnNVWm+DaqMmXFCful/giltlXh8OJVjTLQ ETC2ZAoD/sizVTkWJuq19Uos7vaGqvkN4Whn+KkhxAM+KUj3lbj8/B0QS5k1ky3/c+x1 y7ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sUYZ7XjtkLfBE/tI/sYkmY8y2UOkS0ZMT+YWEatnPQk=; b=E3fI76V9jTiuS4oLo/9FoonuIj9Z8u/408bnRhuL0I8iuAwTdzWKnfBsGZMQSHcrBo d4Fwm+sCjFu/mjXJ2wqCBd0MvM6+tJpTwvB8Eu5Fr1VPGEL+eF6hRF1jKzzHLUlzhROr ZH1CxCv0gu2LKgMgwvqdF3lVQ7DntKesOBYKe7xeugXDLSfD82pVq7HbnOKLBlwojbiG ShSsAp5d0hVZmWmIj5OORzfThBBr9Hwg69v/3xfjTHBttPUUIMvRpUY2XM5Udg8iYJpP 7Xn8US1oG83RV4/jUoh/rQB7Sk3xlKn49Ip1Oc20zrF8RSuEWCbDogmOsx3h9q7vbpw5 jfvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zDNZ+mWx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:56 -0800 Message-Id: <20190223023957.18865-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only perform the assert when both registers exist. Extract the variables from ID_AA64DFR0_EL1 for AArch64. Signed-off-by: Richard Henderson --- target/arm/helper.c | 58 +++++++++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 20 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index fbdca9324b..1d8c8998c4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5544,32 +5544,50 @@ static void define_debug_regs(ARMCPU *cpu) /* Define v7 and v8 architectural debug registers. * These are just dummy implementations for now. */ - int i; - int wrps, brps, ctx_cmps; - ARMCPRegInfo dbgdidr = { - .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL0_R, .accessfn = access_tda, - .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, - }; + int i, wrps, brps, ctx_cmps; + bool have_aa32; - /* Note that all these register fields hold "number of Xs minus 1". */ - brps = extract32(cpu->dbgdidr, 24, 4); - wrps = extract32(cpu->dbgdidr, 28, 4); - ctx_cmps = extract32(cpu->dbgdidr, 20, 4); - - assert(ctx_cmps <= brps); - - /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties + /* + * The DBGDIDR and ID_AA64DFR0_EL1 define various properties * of the debug registers such as number of breakpoints; * check that if they both exist then they agree. + * + * Note that all these register fields hold "number of Xs minus 1". */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); - } + brps = extract32(cpu->id_aa64dfr0, 12, 4); + wrps = extract32(cpu->id_aa64dfr0, 20, 4); + ctx_cmps = extract32(cpu->id_aa64dfr0, 28, 4); - define_one_arm_cp_reg(cpu, &dbgdidr); + /* + * There are cpus with aarch32 only at EL0, and which do not + * have the 32-bit system registers. + */ + have_aa32 + = (FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2 || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL2) >= 2 || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3) >= 2); + if (have_aa32) { + assert(extract32(cpu->dbgdidr, 24, 4) == brps); + assert(extract32(cpu->dbgdidr, 28, 4) == wrps); + assert(extract32(cpu->dbgdidr, 20, 4) == ctx_cmps); + } + } else { + have_aa32 = true; + brps = extract32(cpu->dbgdidr, 24, 4); + wrps = extract32(cpu->dbgdidr, 28, 4); + ctx_cmps = extract32(cpu->dbgdidr, 20, 4); + } + assert(ctx_cmps <= brps); + + if (have_aa32) { + ARMCPRegInfo dbgdidr = { + .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, + .opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tda, + .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, + }; + define_one_arm_cp_reg(cpu, &dbgdidr); + } define_arm_cp_regs(cpu, debug_cp_reginfo); if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { From patchwork Sat Feb 23 02:39:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159094 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2443508jaa; Fri, 22 Feb 2019 18:45:18 -0800 (PST) X-Google-Smtp-Source: AHgI3IZgS0+HFZHSor2S9rgYSyqwN3PSzeVMgPpBZ31aw38a4lgaEev5WOMN/E1RIB1Ys//bN1Vj X-Received: by 2002:a0d:e2cb:: with SMTP id l194mr5938216ywe.391.1550889918343; Fri, 22 Feb 2019 18:45:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550889918; cv=none; d=google.com; s=arc-20160816; b=K0Uqvnoc5x3zgFim3AWsGz1Yt9PgMX4U6J2ARINa9eCzQ/m+fTFn0IV/zqIWGsDnPn e5Mwy0vp3LTVxVI6ZDOwfSoepx48l8oFK8uZdpWp/MU6KkUWlIUYamKUuIRi54Cr2kSP DqfLmSJa0jZhSLSQyUxI7mM7cta2cUoZ02wDlDrddPCrxesdpek7CboYjyQ+/aY6lMWG AsCZJlxJlCKU4z/q29ItjBYOCqQrmtWZnLcp4Ed7POeeSt8F5GezRQdvYfNPfMQl9Kt7 1dTsIT5QyZEwsuvs5FAoybBI5sW1feNeUV1uFCHj8WLYuSR+QulsAZklIVvJVFL4yRv0 kRSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ApecW2tzZdNPkYdCnWki8u37VxQldFNP8bVX7A4sOco=; b=QOj/o4mElH8/3DjTYlsHPk4RebWOf8gfA41x/m43dcFcCjLTxn7PNbDNIVVL7n6G7f nEZ1AHo+FbYjdWXx5B9ekFtb85aB0S6/HrTlOM7XCAjKF8ZKpXdesVQNBf2vf5Q+sGLP GOpgHI+lLpel30LYvitG1zzs1/SEM/GBPLio+7lPnDogRAkXnTQiX/m0138qalyxhf3t X43Y+i3B7jCkT9pR4iNDBhu+rrrEknFeOFeaC8a4nLWIciMUDFDuu2LpoO4CrY8fMtwO aX9smzVIzhqN86t7z36GrooXBvzRXq3xTfE9KJCjXSaYG6Oz/qxg2TmpnvvTK/Sx5no3 T2UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fD6mpQYR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:57 -0800 Message-Id: <20190223023957.18865-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [RFC 6/6] target/arm: Define cortex-a76 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- hw/arm/virt.c | 1 + target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) -- 2.17.2 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 06a155724c..4495ce8918 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -175,6 +175,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a73"), ARM_CPU_TYPE_NAME("cortex-a75"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 325e0ecf17..4a92d7656a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -369,6 +369,63 @@ static void aarch64_a75_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* + * Note that the A76 only supports AA32 at EL0, so the + * AA32-only EL1 id registers do not exist. + */ + cpu->midr = 0x413fd0b1; + cpu->revidr = 0x00000000; + cpu->ctr = 0x8444C004; + cpu->reset_sctlr = 0x30d50838; + cpu->id_pfr0 = 0x10010131; + cpu->id_pfr1 = 0x10010000; + cpu->id_pfr2 = 0x00000011; + cpu->id_dfr0 = 0x04010088; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10201105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02122211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x00011121; + cpu->isar.id_isar6 = 0x00000010; + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; + cpu->id_aa64dfr0 = 0x10305408; + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; + cpu->isar.id_aa64isar1 = 0x00100001; + cpu->isar.id_aa64mmfr0 = 0x00101122; + cpu->isar.id_aa64mmfr1 = 0x10212122; + cpu->isar.id_aa64mmfr2 = 0x00001011; + cpu->clidr = 0x08200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -491,6 +548,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "cortex-a73", .initfn = aarch64_a73_initfn }, { .name = "cortex-a75", .initfn = aarch64_a75_initfn }, + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, { .name = NULL } };