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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts Date: Wed, 5 Oct 2022 20:43:56 -0700 Message-Id: <20221006034421.1179141-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace tcg_const_* with tcg_constant_* in contexts where the free to remove is nearby. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 408 +++++++++++++---------------------- 1 file changed, 145 insertions(+), 263 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1d2dddab1c..890d1f1db3 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -171,8 +171,6 @@ static uint64_t inline_branch_miss[CC_OP_MAX]; static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { - TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -181,9 +179,7 @@ static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) pc |= 0x80000000; } assert(!(s->base.tb->flags & FLAG_MASK_64)); - tmp = tcg_const_i64(pc); - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); + tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); } static TCGv_i64 psw_addr; @@ -348,11 +344,8 @@ static void per_branch(DisasContext *s, bool to_next) tcg_gen_movi_i64(gbea, s->base.pc_next); if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 next_pc = to_next ? tcg_const_i64(s->pc_tmp) : psw_addr; + TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; gen_helper_per_branch(cpu_env, gbea, next_pc); - if (to_next) { - tcg_temp_free_i64(next_pc); - } } #endif } @@ -370,9 +363,8 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, gen_set_label(lab); } else { - TCGv_i64 pc = tcg_const_i64(s->base.pc_next); + TCGv_i64 pc = tcg_constant_i64(s->base.pc_next); tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - tcg_temp_free_i64(pc); } #endif } @@ -426,23 +418,17 @@ static int get_mem_index(DisasContext *s) static void gen_exception(int excp) { - TCGv_i32 tmp = tcg_const_i32(excp); - gen_helper_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_exception(cpu_env, tcg_constant_i32(excp)); } static void gen_program_exception(DisasContext *s, int code) { - TCGv_i32 tmp; - /* Remember what pgm exeption this was. */ - tmp = tcg_const_i32(code); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); - tcg_temp_free_i32(tmp); + tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + offsetof(CPUS390XState, int_pgm_code)); - tmp = tcg_const_i32(s->ilen); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen)); - tcg_temp_free_i32(tmp); + tcg_gen_st_i32(tcg_constant_i32(s->ilen), cpu_env, + offsetof(CPUS390XState, int_pgm_ilen)); /* update the psw */ update_psw_addr(s); @@ -461,9 +447,7 @@ static inline void gen_illegal_opcode(DisasContext *s) static inline void gen_data_exception(uint8_t dxc) { - TCGv_i32 tmp = tcg_const_i32(dxc); - gen_helper_data_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_data_exception(cpu_env, tcg_constant_i32(dxc)); } static inline void gen_trap(DisasContext *s) @@ -584,13 +568,13 @@ static void gen_op_calc_cc(DisasContext *s) switch (s->cc_op) { default: - dummy = tcg_const_i64(0); + dummy = tcg_constant_i64(0); /* FALLTHRU */ case CC_OP_ADD_64: case CC_OP_SUB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - local_cc_op = tcg_const_i32(s->cc_op); + local_cc_op = tcg_constant_i32(s->cc_op); break; case CC_OP_CONST0: case CC_OP_CONST1: @@ -660,13 +644,6 @@ static void gen_op_calc_cc(DisasContext *s) tcg_abort(); } - if (local_cc_op) { - tcg_temp_free_i32(local_cc_op); - } - if (dummy) { - tcg_temp_free_i64(dummy); - } - /* We now have cc in cc_op as constant */ set_cc_static(s); } @@ -1284,9 +1261,9 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, Most commonly we're single-stepping or some other condition that disables all use of goto_tb. Just update the PC and exit. */ - TCGv_i64 next = tcg_const_i64(s->pc_tmp); + TCGv_i64 next = tcg_constant_i64(s->pc_tmp); if (is_imm) { - cdest = tcg_const_i64(dest); + cdest = tcg_constant_i64(dest); } if (c->is_64) { @@ -1296,21 +1273,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } else { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 z = tcg_const_i64(0); + TCGv_i64 z = tcg_constant_i64(0); tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); tcg_gen_extu_i32_i64(t1, t0); tcg_temp_free_i32(t0); tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); per_branch_cond(s, TCG_COND_NE, t1, z); tcg_temp_free_i64(t1); - tcg_temp_free_i64(z); } - if (is_imm) { - tcg_temp_free_i64(cdest); - } - tcg_temp_free_i64(next); - ret = DISAS_PC_UPDATED; } @@ -1394,10 +1365,9 @@ static DisasJumpType op_addc64(DisasContext *s, DisasOps *o) { compute_carry(s); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero); tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); return DISAS_NEXT; } @@ -2077,9 +2047,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); break; default: - vl = tcg_const_i32(l); + vl = tcg_constant_i32(l); gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); - tcg_temp_free_i32(vl); set_cc_static(s); return DISAS_NEXT; } @@ -2099,11 +2068,9 @@ static DisasJumpType op_clcl(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t2 = tcg_const_i32(r2); + t1 = tcg_constant_i32(r1); + t2 = tcg_constant_i32(r2); gen_helper_clcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -2120,11 +2087,9 @@ static DisasJumpType op_clcle(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_clcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -2141,24 +2106,22 @@ static DisasJumpType op_clclu(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_clclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_clm(DisasContext *s, DisasOps *o) { - TCGv_i32 m3 = tcg_const_i32(get_field(s, m3)); + TCGv_i32 m3 = tcg_constant_i32(get_field(s, m3)); TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, o->in1); gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); set_cc_static(s); tcg_temp_free_i32(t1); - tcg_temp_free_i32(m3); return DISAS_NEXT; } @@ -2217,8 +2180,8 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) /* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */ addr = get_address(s, 0, b2, d2); - t_r1 = tcg_const_i32(r1); - t_r3 = tcg_const_i32(r3); + t_r1 = tcg_constant_i32(r1); + t_r3 = tcg_constant_i32(r3); if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); } else if (HAVE_CMPXCHG128) { @@ -2228,8 +2191,6 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) ret = DISAS_NORETURN; } tcg_temp_free_i64(addr); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r3); set_cc_static(s); return ret; @@ -2238,14 +2199,13 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) static DisasJumpType op_csst(DisasContext *s, DisasOps *o) { int r3 = get_field(s, r3); - TCGv_i32 t_r3 = tcg_const_i32(r3); + TCGv_i32 t_r3 = tcg_constant_i32(r3); if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2); } else { gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2); } - tcg_temp_free_i32(t_r3); set_cc_static(s); return DISAS_NEXT; @@ -2343,9 +2303,9 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) m3 = 0; } - tr1 = tcg_const_i32(r1); - tr2 = tcg_const_i32(r2); - chk = tcg_const_i32(m3); + tr1 = tcg_constant_i32(r1); + tr2 = tcg_constant_i32(r2); + chk = tcg_constant_i32(m3); switch (s->insn->data) { case 12: @@ -2370,9 +2330,6 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) g_assert_not_reached(); } - tcg_temp_free_i32(tr1); - tcg_temp_free_i32(tr2); - tcg_temp_free_i32(chk); set_cc_static(s); return DISAS_NEXT; } @@ -2380,15 +2337,11 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_diag(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); - TCGv_i32 func_code = tcg_const_i32(get_field(s, i2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + TCGv_i32 func_code = tcg_constant_i32(get_field(s, i2)); gen_helper_diag(cpu_env, r1, r3, func_code); - - tcg_temp_free_i32(func_code); - tcg_temp_free_i32(r3); - tcg_temp_free_i32(r1); return DISAS_NEXT; } #endif @@ -2494,18 +2447,13 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) update_cc_op(s); if (r1 == 0) { - v1 = tcg_const_i64(0); + v1 = tcg_constant_i64(0); } else { v1 = regs[r1]; } - ilen = tcg_const_i32(s->ilen); + ilen = tcg_constant_i32(s->ilen); gen_helper_ex(cpu_env, ilen, v1, o->in2); - tcg_temp_free_i32(ilen); - - if (r1 == 0) { - tcg_temp_free_i64(v1); - } return DISAS_PC_CC_UPDATED; } @@ -2657,12 +2605,11 @@ static DisasJumpType op_idte(DisasContext *s, DisasOps *o) TCGv_i32 m4; if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 = tcg_const_i32(get_field(s, m4)); + m4 = tcg_constant_i32(get_field(s, m4)); } else { - m4 = tcg_const_i32(0); + m4 = tcg_constant_i32(0); } gen_helper_idte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } @@ -2671,12 +2618,11 @@ static DisasJumpType op_ipte(DisasContext *s, DisasOps *o) TCGv_i32 m4; if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 = tcg_const_i32(get_field(s, m4)); + m4 = tcg_constant_i32(get_field(s, m4)); } else { - m4 = tcg_const_i32(0); + m4 = tcg_constant_i32(0); } gen_helper_ipte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } @@ -2732,16 +2678,12 @@ static DisasJumpType op_msa(DisasContext *s, DisasOps *o) g_assert_not_reached(); }; - t_r1 = tcg_const_i32(r1); - t_r2 = tcg_const_i32(r2); - t_r3 = tcg_const_i32(r3); - type = tcg_const_i32(s->insn->data); + t_r1 = tcg_constant_i32(r1); + t_r2 = tcg_constant_i32(r2); + t_r3 = tcg_constant_i32(r3); + type = tcg_constant_i32(s->insn->data); gen_helper_msa(cc_op, cpu_env, t_r1, t_r2, t_r3, type); set_cc_static(s); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r2); - tcg_temp_free_i32(t_r3); - tcg_temp_free_i32(type); return DISAS_NEXT; } @@ -3002,10 +2944,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o) tcg_gen_extu_i32_i64(t, t32); tcg_temp_free_i32(t32); - z = tcg_const_i64(0); + z = tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); tcg_temp_free_i64(t); - tcg_temp_free_i64(z); } return DISAS_NEXT; @@ -3014,11 +2955,10 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_lctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -3026,11 +2966,10 @@ static DisasJumpType op_lctl(DisasContext *s, DisasOps *o) static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lctlg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -3090,11 +3029,10 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) static DisasJumpType op_lam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -3304,9 +3242,6 @@ static DisasJumpType op_lcbb(DisasContext *s, DisasOps *o) static DisasJumpType op_mc(DisasContext *s, DisasOps *o) { -#if !defined(CONFIG_USER_ONLY) - TCGv_i32 i2; -#endif const uint16_t monitor_class = get_field(s, i2); if (monitor_class & 0xff00) { @@ -3315,9 +3250,8 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps *o) } #if !defined(CONFIG_USER_ONLY) - i2 = tcg_const_i32(monitor_class); - gen_helper_monitor_call(cpu_env, o->addr1, i2); - tcg_temp_free_i32(i2); + gen_helper_monitor_call(cpu_env, o->addr1, + tcg_constant_i32(monitor_class)); #endif /* Defaults to a NOP. */ return DISAS_NEXT; @@ -3381,9 +3315,9 @@ static DisasJumpType op_movx(DisasContext *s, DisasOps *o) static DisasJumpType op_mvc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvc(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3395,9 +3329,9 @@ static DisasJumpType op_mvcrl(DisasContext *s, DisasOps *o) static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvcin(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3413,11 +3347,9 @@ static DisasJumpType op_mvcl(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t2 = tcg_const_i32(r2); + t1 = tcg_constant_i32(r1); + t2 = tcg_constant_i32(r2); gen_helper_mvcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -3434,11 +3366,9 @@ static DisasJumpType op_mvcle(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_mvcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3455,11 +3385,9 @@ static DisasJumpType op_mvclu(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_mvclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3492,49 +3420,45 @@ static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o) static DisasJumpType op_mvn(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvn(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } static DisasJumpType op_mvo(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvo(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2)); gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mvst(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2)); gen_helper_mvst(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mvz(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvz(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3622,13 +3546,12 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOps *o) static DisasJumpType op_nabs(DisasContext *s, DisasOps *o) { - TCGv_i64 z, n; - z = tcg_const_i64(0); - n = tcg_temp_new_i64(); + TCGv_i64 z = tcg_constant_i64(0); + TCGv_i64 n = tcg_temp_new_i64(); + tcg_gen_neg_i64(n, o->in2); tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); tcg_temp_free_i64(n); - tcg_temp_free_i64(z); return DISAS_NEXT; } @@ -3653,9 +3576,9 @@ static DisasJumpType op_nabsf128(DisasContext *s, DisasOps *o) static DisasJumpType op_nc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3687,9 +3610,9 @@ static DisasJumpType op_negf128(DisasContext *s, DisasOps *o) static DisasJumpType op_oc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3739,9 +3662,9 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o) static DisasJumpType op_pack(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_pack(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3755,9 +3678,8 @@ static DisasJumpType op_pka(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l2); + l = tcg_constant_i32(l2); gen_helper_pka(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3771,9 +3693,8 @@ static DisasJumpType op_pku(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l2); + l = tcg_constant_i32(l2); gen_helper_pku(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -4020,9 +3941,8 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o) } s->pc_tmp &= mask; - tsam = tcg_const_i64(sam); + tsam = tcg_constant_i64(sam); tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); - tcg_temp_free_i64(tsam); /* Always exit the TB, since we (may have) changed execution mode. */ return DISAS_TOO_MANY; @@ -4083,12 +4003,11 @@ static DisasJumpType op_servc(DisasContext *s, DisasOps *o) static DisasJumpType op_sigp(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3); set_cc_static(s); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } #endif @@ -4357,21 +4276,19 @@ static DisasJumpType op_stckc(DisasContext *s, DisasOps *o) static DisasJumpType op_stctg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stctg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } static DisasJumpType op_stctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -4598,11 +4515,10 @@ static DisasJumpType op_st64(DisasContext *s, DisasOps *o) static DisasJumpType op_stam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -4660,7 +4576,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) int r1 = get_field(s, r1); int r3 = get_field(s, r3); int size = s->insn->data; - TCGv_i64 tsize = tcg_const_i64(size); + TCGv_i64 tsize = tcg_constant_i64(size); while (1) { if (size == 8) { @@ -4675,7 +4591,6 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) r1 = (r1 + 1) & 15; } - tcg_temp_free_i64(tsize); return DISAS_NEXT; } @@ -4684,8 +4599,8 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) int r1 = get_field(s, r1); int r3 = get_field(s, r3); TCGv_i64 t = tcg_temp_new_i64(); - TCGv_i64 t4 = tcg_const_i64(4); - TCGv_i64 t32 = tcg_const_i64(32); + TCGv_i64 t4 = tcg_constant_i64(4); + TCGv_i64 t32 = tcg_constant_i64(32); while (1) { tcg_gen_shl_i64(t, regs[r1], t32); @@ -4698,8 +4613,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) } tcg_temp_free_i64(t); - tcg_temp_free_i64(t4); - tcg_temp_free_i64(t32); return DISAS_NEXT; } @@ -4718,26 +4631,20 @@ static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) static DisasJumpType op_srst(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_srst(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_srstu(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_srstu(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } @@ -4795,10 +4702,9 @@ static DisasJumpType op_subb64(DisasContext *s, DisasOps *o) * Borrow is {0, -1}, so add to subtract; replicate the * borrow input to produce 128-bit -1 for the addition. */ - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src); tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); return DISAS_NEXT; } @@ -4810,13 +4716,11 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o) update_psw_addr(s); update_cc_op(s); - t = tcg_const_i32(get_field(s, i1) & 0xff); + t = tcg_constant_i32(get_field(s, i1) & 0xff); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); - tcg_temp_free_i32(t); - t = tcg_const_i32(s->ilen); + t = tcg_constant_i32(s->ilen); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); - tcg_temp_free_i32(t); gen_exception(EXCP_SVC); return DISAS_NORETURN; @@ -4873,18 +4777,18 @@ static DisasJumpType op_tprot(DisasContext *s, DisasOps *o) static DisasJumpType op_tp(DisasContext *s, DisasOps *o) { - TCGv_i32 l1 = tcg_const_i32(get_field(s, l1) + 1); + TCGv_i32 l1 = tcg_constant_i32(get_field(s, l1) + 1); + gen_helper_tp(cc_op, cpu_env, o->addr1, l1); - tcg_temp_free_i32(l1); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_tr(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_tr(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -4899,27 +4803,27 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps *o) static DisasJumpType op_trt(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_trtr(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); - TCGv_i32 sizes = tcg_const_i32(s->insn->opc & 3); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); + TCGv_i32 sizes = tcg_constant_i32(s->insn->opc & 3); TCGv_i32 tst = tcg_temp_new_i32(); int m3 = get_field(s, m3); @@ -4938,9 +4842,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) } gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); - tcg_temp_free_i32(sizes); tcg_temp_free_i32(tst); set_cc_static(s); return DISAS_NEXT; @@ -4948,19 +4849,19 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) static DisasJumpType op_ts(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(0xff); + TCGv_i32 t1 = tcg_constant_i32(0xff); + tcg_gen_atomic_xchg_i32(t1, o->in2, t1, get_mem_index(s), MO_UB); tcg_gen_extract_i32(cc_op, t1, 7, 1); - tcg_temp_free_i32(t1); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_unpk(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_unpk(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -4974,9 +4875,8 @@ static DisasJumpType op_unpka(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l1); + l = tcg_constant_i32(l1); gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -4991,9 +4891,8 @@ static DisasJumpType op_unpku(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l1); + l = tcg_constant_i32(l1); gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -5012,7 +4911,7 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o) /* If the addresses are identical, this is a store/memset of zero. */ if (b1 == b2 && d1 == d2 && (l + 1) <= 32) { - o->in2 = tcg_const_i64(0); + o->in2 = tcg_constant_i64(0); l++; while (l >= 8) { @@ -5045,9 +4944,8 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o) /* But in general we'll defer to a helper. */ o->in2 = get_address(s, 0, b2, d2); - t32 = tcg_const_i32(l); + t32 = tcg_constant_i32(l); gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2); - tcg_temp_free_i32(t32); set_cc_static(s); return DISAS_NEXT; } @@ -5112,46 +5010,39 @@ static DisasJumpType op_zero2(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_clp(DisasContext *s, DisasOps *o) { - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_clp(cpu_env, r2); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_pcilg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_pcistg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_stpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -5164,38 +5055,31 @@ static DisasJumpType op_sic(DisasContext *s, DisasOps *o) static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_rpcit(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_mpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -6316,9 +6200,8 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) if (unlikely(s->ex_value)) { /* Drop the EX data now, so that it's clear on exception paths. */ - TCGv_i64 zero = tcg_const_i64(0); - tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value)); - tcg_temp_free_i64(zero); + tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, + offsetof(CPUS390XState, ex_value)); /* Extract the values saved by EXECUTE. */ insn = s->ex_value & 0xffffffffffff0000ull; @@ -6444,9 +6327,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 addr = tcg_const_i64(s->base.pc_next); + TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); gen_helper_per_ifetch(cpu_env, addr); - tcg_temp_free_i64(addr); } #endif From patchwork Thu Oct 6 03:43:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612881 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1208903pvb; Wed, 5 Oct 2022 21:04:57 -0700 (PDT) X-Google-Smtp-Source: AMsMyM66zseeASz/ooNJeGifuPM4tb9LwTBoOMZfKBPwGFsgDUWenWcm4LgY25zi5+lBksuoDj/N X-Received: by 2002:a05:6214:1cc7:b0:4af:6573:c056 with SMTP id g7-20020a0562141cc700b004af6573c056mr2332306qvd.103.1665029097735; Wed, 05 Oct 2022 21:04:57 -0700 (PDT) ARC-Seal: i=1; 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 02/26] target/s390x: Use tcg_constant_* for DisasCompare Date: Wed, 5 Oct 2022 20:43:57 -0700 Message-Id: <20221006034421.1179141-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 890d1f1db3..ec43bd7a1f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -830,7 +830,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) c->is_64 = false; c->u.s32.a = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case CC_OP_LTGT_32: case CC_OP_LTUGTU_32: @@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_NZ: case CC_OP_FLOGR: c->u.s64.a = cc_dst; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; break; case CC_OP_LTGT_64: @@ -859,14 +859,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_TM_64: case CC_OP_ICM: c->u.s64.a = tcg_temp_new_i64(); - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); break; case CC_OP_ADDU: case CC_OP_SUBU: c->is_64 = true; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; switch (mask) { case 8 | 2: @@ -889,65 +889,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) switch (mask) { case 0x8 | 0x4 | 0x2: /* cc != 3 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; case 0x8 | 0x4 | 0x1: /* cc != 2 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8 | 0x2 | 0x1: /* cc != 1 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ cond = TCG_COND_EQ; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x8 | 0x4: /* cc < 2 */ cond = TCG_COND_LTU; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8: /* cc == 0 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x2 | 0x1: /* cc != 0 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ cond = TCG_COND_NE; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x4: /* cc == 1 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2 | 0x1: /* cc > 1 */ cond = TCG_COND_GTU; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2: /* cc == 2 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x1: /* cc == 3 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; default: /* CC is masked by something else: (8 >> cc) & mask. */ cond = TCG_COND_NE; c->g1 = false; - c->u.s32.a = tcg_const_i32(8); - c->u.s32.b = tcg_const_i32(0); - tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op); + c->u.s32.a = tcg_temp_new_i32(); + c->u.s32.b = tcg_constant_i32(0); + tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask); break; } @@ -1604,7 +1604,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, regs[r1], 1); store_reg32_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1628,7 +1628,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, t, 1); store_reg32h_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1649,7 +1649,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a = regs[r1]; - c.u.s64.b = tcg_const_i64(0); + c.u.s64.b = tcg_constant_i64(0); return help_branch(s, &c, is_imm, imm, o->in2); } From patchwork Thu Oct 6 03:43:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612871 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1204269pvb; Wed, 5 Oct 2022 20:52:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6PIgb7ZrCn1YkjKXh1Y5xs4u7yqiFMOxGKKxYCm+kLFJSMo4GrbDuOY/ffBmXY23MAvPSH X-Received: by 2002:a05:620a:404c:b0:6d9:4c49:9d5f with SMTP id i12-20020a05620a404c00b006d94c499d5fmr1986849qko.708.1665028361233; Wed, 05 Oct 2022 20:52:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665028361; cv=none; d=google.com; s=arc-20160816; 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 03/26] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Date: Wed, 5 Oct 2022 20:43:58 -0700 Message-Id: <20221006034421.1179141-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Return a constant or NULL, which means the free may be removed from all callers of fpinst_extract_m34. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index ec43bd7a1f..f8cfddc181 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1775,7 +1775,7 @@ static TCGv_i32 fpinst_extract_m34(DisasContext *s, bool m3_with_fpe, return NULL; } - return tcg_const_i32(deposit32(m3, 4, 4, m4)); + return tcg_constant_i32(deposit32(m3, 4, 4, m4)); } static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o) @@ -1786,7 +1786,6 @@ static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1799,7 +1798,6 @@ static DisasJumpType op_cfdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1812,7 +1810,6 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1825,7 +1822,6 @@ static DisasJumpType op_cgeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1838,7 +1834,6 @@ static DisasJumpType op_cgdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1851,7 +1846,6 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1864,7 +1858,6 @@ static DisasJumpType op_clfeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1877,7 +1870,6 @@ static DisasJumpType op_clfdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1890,7 +1882,6 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1903,7 +1894,6 @@ static DisasJumpType op_clgeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1916,7 +1906,6 @@ static DisasJumpType op_clgdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1929,7 +1918,6 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1942,7 +1930,6 @@ static DisasJumpType op_cegb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cegb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1954,7 +1941,6 @@ static DisasJumpType op_cdgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cdgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1966,7 +1952,6 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cxgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return_low128(o->out2); return DISAS_NEXT; } @@ -1979,7 +1964,6 @@ static DisasJumpType op_celgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_celgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1991,7 +1975,6 @@ static DisasJumpType op_cdlgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cdlgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2003,7 +1986,6 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cxlgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return_low128(o->out2); return DISAS_NEXT; } @@ -2466,7 +2448,6 @@ static DisasJumpType op_fieb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_fieb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2478,7 +2459,6 @@ static DisasJumpType op_fidb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_fidb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2491,7 +2471,6 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOps *o) } gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m34); return_low128(o->out2); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2766,7 +2745,6 @@ static DisasJumpType op_ledb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_ledb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2778,7 +2756,6 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2790,7 +2767,6 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_lexb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } From patchwork Thu Oct 6 03:43:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612870 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1204159pvb; Wed, 5 Oct 2022 20:52:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4x5Nn8l82dpr20aJZusNOQibebp3MhrNGeCUD54hdNcuitZcgouY1GdTen3HywEOex5tw/ X-Received: by 2002:ac8:58cf:0:b0:35c:c69b:4aa1 with SMTP id u15-20020ac858cf000000b0035cc69b4aa1mr2002190qta.355.1665028338104; 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc Date: Wed, 5 Oct 2022 20:43:59 -0700 Message-Id: <20221006034421.1179141-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In most cases, this is a simple local allocate and free replaced by tcg_constant_*. In three cases, a variable temp was initialized with a constant value -- reorg to localize the constant. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate_vx.c.inc | 45 +++++++++++++---------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc index 3526ba3e3b..cdb192454f 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -319,12 +319,10 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a, static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, uint64_t b) { - TCGv_i64 bl = tcg_const_i64(b); - TCGv_i64 bh = tcg_const_i64(0); + TCGv_i64 bl = tcg_constant_i64(b); + TCGv_i64 bh = tcg_constant_i64(0); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(bh); } static DisasJumpType op_vbperm(DisasContext *s, DisasOps *o) @@ -609,9 +607,8 @@ static DisasJumpType op_vlei(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - tmp = tcg_const_i64((int16_t)get_field(s, i2)); + tmp = tcg_constant_i64((int16_t)get_field(s, i2)); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1107,11 +1104,13 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) static DisasJumpType op_vst(DisasContext *s, DisasOps *o) { - TCGv_i64 tmp = tcg_const_i64(16); + TCGv_i64 tmp; /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64(16)); + tmp = tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); @@ -1270,9 +1269,10 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) } /* Probe write access before actually modifying memory */ - tmp = tcg_const_i64((v3 - v1 + 1) * 16); - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64((v3 - v1 + 1) * 16)); + tmp = tcg_temp_new_i64(); for (;; v1++) { read_vec_element_i64(tmp, v1, 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); @@ -1359,7 +1359,7 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o) static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) { const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; - TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); + TCGv_i64 msb_mask = tcg_constant_i64(dup_const(es, 1ull << msb_bit_nr)); TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); @@ -1416,7 +1416,7 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, { TCGv_i64 th = tcg_temp_new_i64(); TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(tl, th, al, zero, bl, zero); tcg_gen_add2_i64(tl, th, th, zero, ah, zero); @@ -1425,7 +1425,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) @@ -1455,15 +1454,14 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) { TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 th = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); /* extract the carry only */ tcg_gen_extract_i64(tl, cl, 0, 1); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); + tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero); tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } static DisasJumpType op_vac(DisasContext *s, DisasOps *o) @@ -1484,7 +1482,7 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, { TCGv_i64 tl = tcg_temp_new_i64(); TCGv_i64 th = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_andi_i64(tl, cl, 1); tcg_gen_add2_i64(tl, th, tl, zero, al, zero); @@ -1495,7 +1493,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_temp_free_i64(tl); tcg_temp_free_i64(th); - tcg_temp_free_i64(zero); } static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) @@ -1597,14 +1594,13 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) { TCGv_i64 dh = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); tcg_temp_free_i64(dh); - tcg_temp_free_i64(zero); } static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) @@ -2440,7 +2436,7 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, { TCGv_i64 th = tcg_temp_new_i64(); TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_sub2_i64(tl, th, al, zero, bl, zero); tcg_gen_andi_i64(th, th, 1); @@ -2452,7 +2448,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) @@ -2572,11 +2567,12 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - sumh = tcg_const_i64(0); + sumh = tcg_temp_new_i64(); suml = tcg_temp_new_i64(); - zero = tcg_const_i64(0); + zero = tcg_constant_i64(0); tmpl = tcg_temp_new_i64(); + tcg_gen_mov_i64(sumh, zero); read_vec_element_i64(suml, get_field(s, v3), max_idx, es); for (idx = 0; idx <= max_idx; idx++) { read_vec_element_i64(tmpl, get_field(s, v2), idx, es); @@ -2587,7 +2583,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) tcg_temp_free_i64(sumh); tcg_temp_free_i64(suml); - tcg_temp_free_i64(zero); tcg_temp_free_i64(tmpl); return DISAS_NEXT; } From patchwork Thu Oct 6 03:44:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612874 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1205548pvb; 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 05/26] target/s390x: Change help_goto_direct to work on displacements Date: Wed, 5 Oct 2022 20:44:00 -0700 Message-Id: <20221006034421.1179141-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f8cfddc181..b6e4005670 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1145,8 +1145,10 @@ struct DisasInsn { /* ====================================================================== */ /* Miscellaneous helpers, used by several operations. */ -static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) +static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { + uint64_t dest = s->base.pc_next + disp; + if (dest == s->pc_tmp) { per_branch(s, true); return DISAS_NEXT; @@ -1169,7 +1171,8 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { DisasJumpType ret; - uint64_t dest = s->base.pc_next + (int64_t)imm * 2; + int64_t disp = (int64_t)imm * 2; + uint64_t dest = s->base.pc_next + disp; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1185,7 +1188,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (c->cond == TCG_COND_ALWAYS) { - ret = help_goto_direct(s, dest); + ret = help_goto_direct(s, disp); goto egress; } } else { @@ -1558,7 +1561,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) static DisasJumpType op_basi(DisasContext *s, DisasOps *o) { pc_to_link_info(o->out, s, s->pc_tmp); - return help_goto_direct(s, s->base.pc_next + (int64_t)get_field(s, i2) * 2); + return help_goto_direct(s, (int64_t)get_field(s, i2) * 2); } static DisasJumpType op_bc(DisasContext *s, DisasOps *o) From patchwork Thu Oct 6 03:44:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612878 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1206578pvb; Wed, 5 Oct 2022 20:59:23 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4onpy3R+Q1j8TAlR5cDxZZKVNXL2/NICEU1s70QB+Zty4skLJYUzDcmTWoDw28cLDAU/yQ X-Received: by 2002:ac8:5e10:0:b0:392:f65a:292e with SMTP id h16-20020ac85e10000000b00392f65a292emr2042927qtx.407.1665028763029; Wed, 05 Oct 2022 20:59:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665028763; cv=none; d=google.com; s=arc-20160816; b=xkN2MFepQD2FOr9r3k4yM80Cxecpxdc9W0T0l0qwbRg6UxtqvwokTm7Li7j+/6wrte yP5nkMLg3qMtn4h/yA5F4bXx9BPMUNhVhkoVYnBh91Phj1vW9Fti0M3+ECFbmi4OT0eO 4yAe8QAwR8KKoDb/M6oq/WFBWe2jaMSkm0vPZ55KBEzuwGteHzJF6wDZca1gZlthE+hM jLicUM5MQoXoMnr7oJoTZkPciOp5l/1jQlifPewNNuKJEW+rr395vWAiKtrHqJIvbcNA Wj+YbSXPKW6mb76Fq26JdQq0JHNNPbu/PA5lLkE+KkFYJzV5iyX6jDpvBqISx8Mez3c7 BPqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TLniamy6RaDceg5E0CUD7LIlTHkR5S1SB06UOtygodc=; b=I4Irnap6MKOMLh2nX54K6a0MI0hb9XKNF+AmpYPhV3WsUEhHmMhUE2jMzTgul32pez avbju3M8meDjUBq6413g4C3ND1w8pXSOuE1eu+FLgCiqPWOBO1eaJMgN+yIk9BOJDvvt fMkxZJW2728ciXgQcp4zLDRIYn+ChLkV2bdk1JM61HyruLAewyFrsCx7CUaLSkEGLEmW oCCPQODOeI3wmqk/SNUFAkxqoChN15D53sfz8hToDxSj1blj6En6YBvzbWCFlAU5Ab42 7Unk6fLltInPyoGvC6qf1gLcPnfc2eX+Nqmq89GRDmstpsWTSY8waxUIbFnFo1SVYc6H DhNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="w9vt/YLy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 06/26] target/s390x: Introduce gen_psw_addr_disp Date: Wed, 5 Oct 2022 20:44:01 -0700 Message-Id: <20221006034421.1179141-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 69 ++++++++++++++++++++++++------------ 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index b6e4005670..47a9d87416 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -169,6 +169,11 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + tcg_gen_movi_i64(dest, s->base.pc_next + disp); +} + static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { if (s->base.tb->flags & FLAG_MASK_32) { @@ -334,18 +339,24 @@ static void return_low128(TCGv_i64 dest) static void update_psw_addr(DisasContext *s) { - /* psw.addr */ - tcg_gen_movi_i64(psw_addr, s->base.pc_next); + gen_psw_addr_disp(s, psw_addr, 0); } static void per_branch(DisasContext *s, bool to_next) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; - gen_helper_per_branch(cpu_env, gbea, next_pc); + if (to_next) { + TCGv_i64 next_pc = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, next_pc, s->ilen); + gen_helper_per_branch(cpu_env, gbea, next_pc); + tcg_temp_free_i64(next_pc); + } else { + gen_helper_per_branch(cpu_env, gbea, psw_addr); + } } #endif } @@ -358,20 +369,23 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, TCGLabel *lab = gen_new_label(); tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); gen_helper_per_branch(cpu_env, gbea, psw_addr); gen_set_label(lab); } else { - TCGv_i64 pc = tcg_constant_i64(s->base.pc_next); + TCGv_i64 pc = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, pc, 0); tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); + tcg_temp_free_i64(pc); } #endif } static void per_breaking_event(DisasContext *s) { - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); } static void update_cc_op(DisasContext *s) @@ -1147,21 +1161,19 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { - uint64_t dest = s->base.pc_next + disp; - - if (dest == s->pc_tmp) { + if (disp == s->ilen) { per_branch(s, true); return DISAS_NEXT; } - if (use_goto_tb(s, dest)) { + if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); per_breaking_event(s); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); per_branch(s, false); return DISAS_PC_UPDATED; } @@ -1219,14 +1231,14 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch not taken. */ tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 0); /* Branch taken. */ gen_set_label(lab); per_breaking_event(s); tcg_gen_goto_tb(1); - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 1); ret = DISAS_NORETURN; @@ -1249,12 +1261,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch not taken. */ update_cc_op(s); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 0); gen_set_label(lab); if (is_imm) { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); } per_breaking_event(s); ret = DISAS_PC_UPDATED; @@ -1264,9 +1276,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, Most commonly we're single-stepping or some other condition that disables all use of goto_tb. Just update the PC and exit. */ - TCGv_i64 next = tcg_constant_i64(s->pc_tmp); + TCGv_i64 next = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, next, s->ilen); if (is_imm) { - cdest = tcg_constant_i64(dest); + cdest = tcg_temp_new_i64(); + gen_psw_addr_disp(s, cdest, disp); } if (c->is_64) { @@ -1285,6 +1300,10 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, tcg_temp_free_i64(t1); } + tcg_temp_free_i64(next); + if (is_imm) { + tcg_temp_free_i64(cdest); + } ret = DISAS_PC_UPDATED; } @@ -5827,7 +5846,8 @@ static void in2_a2(DisasContext *s, DisasOps *o) static void in2_ri2(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2); + o->in2 = tcg_temp_new_i64(); + gen_psw_addr_disp(s, o->in2, (int64_t)get_field(s, i2) * 2); } #define SPEC_in2_ri2 0 @@ -6306,8 +6326,11 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); + TCGv_i64 addr = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, addr, 0); gen_helper_per_ifetch(cpu_env, addr); + tcg_temp_free_i64(addr); } #endif @@ -6428,7 +6451,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (s->base.tb->flags & FLAG_MASK_PER) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); } /* Call the helper to check for a possible PER exception. */ From patchwork Thu Oct 6 03:44:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612888 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1211148pvb; Wed, 5 Oct 2022 21:11:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM69gHoEDQvQHtZciFibEIWMpVkMz7QsuOafzB9G50gzIoo7Dy+ohWryTTF1E96WmICD0nMZ X-Received: by 2002:a05:620a:1b89:b0:6ce:8b2b:7f0e with SMTP id dv9-20020a05620a1b8900b006ce8b2b7f0emr1980681qkb.15.1665029501188; Wed, 05 Oct 2022 21:11:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029501; cv=none; d=google.com; s=arc-20160816; b=Vj4uLB7PQq+SFyhaMWnDuRhDeo4Fx05BKtt0mY2S+F7Qzw0pOtpJ6HgR9j1ct01Ycl JT0MZXg/pCpFGFiojV0EN9mCNUlUWp8vLuju6VSVTlnxfRNpYwqxI2l1+ezgmZ7UcSVX lasWgyQF8wyIl+kKHpCHE27IKEh7Wx3Jb1LEOuPXVO1XYmA0Ew+vBzKaC5VAqi1a8NMH UVR8jB6KzFyJdazj9tEMzwh9/+aohrfONoIA1dbfyp4f6ya9cQBwk2owvqo49MP6PT+T 0dOh7WYpcVcHG6QN4uDWQ4c1VXOePJW+kMBRIRVoa0+Aop6YVF4fGqBUViWheWhYJD7f C4Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1X+qhN7JnZScxVTpZC+V5LOihnVucXwspU7Ku+85/ug=; b=WVPC4w5uEeAOX6f/TPVezoS3JzMjr8tUHUa0UIqB1hkYe0ZcGc4nN5KxmPMmhLIwq2 qZdRMarXFkZaVJdZA2YpRy+n0XCjkZlXD/x1h56r044lpXomOFZezMS4lw8cNkKbe5ch XE1uSo8c3inTrJNJpB49JaHPi8zMOSSaXz7Q9tbMV8Vx/D/z/6nmDT+Z5DTInN4mt2sX yTbeLNiicEsm0P2nF6ddqB+YlIjFnC0/kL7HktR9xpiTe14WcLD4u+qvM12XsgCYqHtV GE/r+coLLAAn+xfc57IdsMrSdY8m5+a4nWBfh34JNt2tAjqdqJ1Vszr2S2vYNlH3h4uS ul9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ab7xa3B6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 07/26] target/s390x: Remove pc argument to pc_to_link_into Date: Wed, 5 Oct 2022 20:44:02 -0700 Message-Id: <20221006034421.1179141-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All callers pass s->pc_tmp. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 47a9d87416..7c98a72ddd 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -174,8 +174,10 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) tcg_gen_movi_i64(dest, s->base.pc_next + disp); } -static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { + uint64_t pc = s->pc_tmp; + if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -1534,7 +1536,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o) static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); if (o->in2) { tcg_gen_mov_i64(psw_addr, o->in2); per_branch(s, false); @@ -1549,7 +1551,7 @@ static void save_link_info(DisasContext *s, DisasOps *o) TCGv_i64 t; if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); return; } gen_op_calc_cc(s); @@ -1579,7 +1581,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) static DisasJumpType op_basi(DisasContext *s, DisasOps *o) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); return help_goto_direct(s, (int64_t)get_field(s, i2) * 2); } From patchwork Thu Oct 6 03:44:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612884 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1210063pvb; Wed, 5 Oct 2022 21:08:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7n66/QPVOH6xxv1R+NudT/aAE1P86duWEX+uyzA8a1PxynTlXn4kXnl9LXGj1Vl36x9h24 X-Received: by 2002:a05:6214:c4e:b0:4b1:aa37:f4c1 with SMTP id r14-20020a0562140c4e00b004b1aa37f4c1mr2259469qvj.107.1665029298245; Wed, 05 Oct 2022 21:08:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029298; cv=none; d=google.com; s=arc-20160816; b=TCgOQSmv68kjJ6WTBGnjkO+Ng7TRHh9KPzKJmg6e/hrGohW4Uuh8Moe5vyBT/9uhh9 oyBAkIVDx6KY6wB282IrvwuyHjF4CSBEumJGp0kngW213wN3e2X69pfKor5AiFhrjQnZ ZCm8Ad+gpFtZX1afV9Xz53w1eUa2m6kMiz/ILi987GhIp8/xfJ3xEddUuyhSSZbxD/yY JaY6y0Saaf3OJVV4eg0RLTJ0MQlUHL1B2o1vDLjfJfwgTRXCJUJjFSjWcN2HwdNen8WU LZTJyaiXC/HkfzSOgfCpGvyT9lNVQFJ6YokU2wZjwJCc39cM3xDJ4a/xDed6fPjrPxSx Ja4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LsDZbHydcTU+7tcU++exijoc1WAx3468SMsmfORvMzo=; b=pqvsQg19XERfmsL+leCJXCrpn0m5B+3OFT75yrFf/BKhZQcTHvGO9bZQ57EonQi/ud dGdHy2gP0MDGLsQtD1BLK9bzLRxIwbO90snM48I3lzbUKmYjs3rq0PrXQvrP86Pttc9A jWCpjydLyag5iwNHtJDdd5GUHD5G78dUAOtiHFl/kpQvjhKzB1pg+qck69tgJYNXDaPj Aj/EH6WtaZX9qjTDx+Im9/gfmdf1XnyIzV4fMQhI3XQb5cKiXxa857DA6jGOE2kv6bhb Fo38Uog2CPOyqCpiV4TIgDaWahRk2OAUO6OmMMNKRiyqWpVh5KpFtpeYYV3erHHOusZT woZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N5PA4meb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 08/26] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Date: Wed, 5 Oct 2022 20:44:03 -0700 Message-Id: <20221006034421.1179141-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is slightly more complicated that a straight displacement for 31 and 24-bit modes. Dont bother with a cant-happen assert. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 7c98a72ddd..4c3ea958d7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -176,17 +176,20 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { - uint64_t pc = s->pc_tmp; + TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { - if (s->base.tb->flags & FLAG_MASK_64) { - tcg_gen_movi_i64(out, pc); - return; - } - pc |= 0x80000000; + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; } - assert(!(s->base.tb->flags & FLAG_MASK_64)); - tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); + tcg_temp_free_i64(tmp); } static TCGv_i64 psw_addr; From patchwork Thu Oct 6 03:44:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612875 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1205852pvb; Wed, 5 Oct 2022 20:57:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM52cwiHrJvDxZz8EvR0Hf+dQjR2CWmrAKNn72+85Ha0yWSGG89weJ/q/q415Q+5H7VU+DVh X-Received: by 2002:a05:620a:2057:b0:6e6:f4d:980b with SMTP id d23-20020a05620a205700b006e60f4d980bmr142067qka.544.1665028637678; Wed, 05 Oct 2022 20:57:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665028637; cv=none; d=google.com; s=arc-20160816; b=V33nwU5CeeuTAIplLE2HTSOQw3ml5qnhh0cDRxziGl3zN6vfzhe6uhN0Uh/mUTijNl +xHXf/h4tv4uslQu7ggAGtuWbkumH2bVhIbqsgODlkR0fTkC0GX0rSly55+B24l+LMAj ewQwb+AGH55xIlONlA6hiYYxD+9EZnIhgas0HZ7UllAodmue4BcVbjDrn8EOz1kySw/T bCTBuxQ6RzZSpunHfWhu/Se/FaJX9ZUcCXvxMBjZAbtlqfsWoqMFY5Kr3ogzFt8+0L6p P7iMGokReYqV2TEdAHFTQ0qxQ2M67RbAp5ceiZiPxL6AzE2zpxVmOrzWEY0nCXBrOhQP lgzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OUhdzli6FBB0g0/N3o8278Y1+i086FpwK4jH+sK5zo0=; b=uzODuV0DqpGvT7OOauUoIjNZzhgv0JZMUeUCKZxYPXj/tYJj0frBwzmtRWXeTGU2Wd vQE00Bh2sWH74rst6ECh9Xs1oeIdgme5NpPIQMkYiWd6S6fK9sngcXgbuW8Gac8GNKup oDZ7vsZCF3HjJ+2f2zkly97HvZ38PozoZLxJk5yfJRyNN0WQn4jYDPHf9FQZqQ9ux6lM XqBt5B1kD6Cy4lp6r+65CKsTZL6LXsMGbbR0T8vExMqNq0xylzYbS/NzocwhISox+Eaw 4ZaSDghCiQ4VX7ihIr0SwQ3ggJ6R8KxXfR1Pxg4FIpgLK3Pg10jDMT28tB93fUTxialr u7JQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P1qiqaGV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info Date: Wed, 5 Oct 2022 20:44:04 -0700 Message-Id: <20221006034421.1179141-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Trivial but non-mechanical conversion away from pc_tmp. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 4c3ea958d7..ad73a64b05 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1558,9 +1558,11 @@ static void save_link_info(DisasContext *s, DisasOps *o) return; } gen_op_calc_cc(s); - tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); - tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp); t = tcg_temp_new_i64(); + tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); + gen_psw_addr_disp(s, t, s->ilen); + tcg_gen_or_i64(o->out, o->out, t); + tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30); tcg_gen_shri_i64(t, psw_mask, 16); tcg_gen_andi_i64(t, t, 0x0f000000); tcg_gen_or_i64(o->out, o->out, t); From patchwork Thu Oct 6 03:44:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612879 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1207581pvb; Wed, 5 Oct 2022 21:01:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5GGYOzgMnwwJbhoAEKxuHoHrFgjelUUrx8RpZeKVYz/KcFev0r+i0/UOJsdqcyuQH1mMXt X-Received: by 2002:a37:6d7:0:b0:6e3:e03c:b61c with SMTP id 206-20020a3706d7000000b006e3e03cb61cmr1901179qkg.251.1665028897870; Wed, 05 Oct 2022 21:01:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665028897; cv=none; d=google.com; s=arc-20160816; b=af95NFqdY2zobO2Beu3pYhT49s4qklNvUPnlvnfwNwJCQsByGvTKV/l0eGNOmSVd9p teCAhi9XZ8hYn+aMsAJs2Oct+DCn82zIp+sUvH49v0zeXL6wsQBBz5ZFpSZlAkcdbQWg blFAj152msIWCXspbFNTLW5C8piUMXnGt0UXcNdNqLjvmN3q6g8kT7s2qRdp4OfZECL+ ymrTZNJvrzHvYQDLdfzlUKg/3tll2BUVK62+nPQS5/dCf9N/rD9zK2Kqb5MlwEeunnGO 0678wNhCW1gGgXWyjBiCtBgrYLoP31dXvGTnRWk7jqz+gP6przPF4vQi4lEXUnauV6iB +3oQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cdk+wqhXrtt2egBbh65dqBvCP5p2fyN7igj25PdmOsY=; b=dHftqLS9F+CiqKFZbnPbpANW2Z/7n0hIYAMk6RIUSXRfIq/L2aozb+LzimO4+22gbE mZeVAW++50bP0XzkFhJsGvjf2OOEiMpZIH0MfadldIqPWnjd25JXt6UoCntDEsqblVBS l+GYniTJ2rOGpHqqbiNXeH9desLH5BboZE4XJDCdSwp01NUef0zdyawxBAnaeXPI5Qb5 GcKrlZZ2thGTzrK+5YwHqVQuM10DkjFBQ1+kTQ1Kl6S49WlQv4EWXKsgVl0HV46+ErcI DP/9LhZzngPAgEy3QpeH2lGeFgEZzMCz/b/SrSww8WpU5SyRC2P3R8hzoimhiAQK8F5c 462w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YJbQNcKf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 10/26] target/s390x: Use gen_psw_addr_disp in op_sam Date: Wed, 5 Oct 2022 20:44:05 -0700 Message-Id: <20221006034421.1179141-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Complicated because we may now require a runtime jump. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 40 +++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index ad73a64b05..2ea3feb803 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -3922,7 +3922,7 @@ static DisasJumpType op_sacf(DisasContext *s, DisasOps *o) static DisasJumpType op_sam(DisasContext *s, DisasOps *o) { int sam = s->insn->data; - TCGv_i64 tsam; + TCGLabel *fault = NULL; uint64_t mask; switch (sam) { @@ -3937,20 +3937,36 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o) break; } - /* Bizarre but true, we check the address of the current insn for the - specification exception, not the next to be executed. Thus the PoO - documents that Bad Things Happen two bytes before the end. */ - if (s->base.pc_next & ~mask) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - s->pc_tmp &= mask; + /* + * Bizarre but true, we check the address of the current insn for the + * specification exception, not the next to be executed. Thus the PoO + * documents that Bad Things Happen two bytes before the end. + */ + if (mask != -1) { + TCGv_i64 t = tcg_temp_new_i64(); + fault = gen_new_label(); - tsam = tcg_constant_i64(sam); - tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); + gen_psw_addr_disp(s, t, 0); + tcg_gen_andi_i64(t, t, ~mask); + tcg_gen_brcondi_i64(TCG_COND_NE, t, 0, fault); + tcg_temp_free_i64(t); + } + + update_cc_op(s); + + tcg_gen_deposit_i64(psw_mask, psw_mask, tcg_constant_i64(sam), 31, 2); + + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_andi_i64(psw_addr, psw_addr, mask); /* Always exit the TB, since we (may have) changed execution mode. */ - return DISAS_TOO_MANY; + tcg_gen_lookup_and_goto_ptr(); + + if (mask != -1) { + gen_set_label(fault); + gen_program_exception(s, PGM_SPECIFICATION); + } + return DISAS_NORETURN; } static DisasJumpType op_sar(DisasContext *s, DisasOps *o) From patchwork Thu Oct 6 03:44:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612885 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1210163pvb; Wed, 5 Oct 2022 21:08:39 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4fQR/mmfbLOm9B+CLj6Q0DodtBrXIiVKeZVx93WnHX++sC6IpYQ+Xv4pZWWR2e3urqH0NL X-Received: by 2002:a05:6214:1cc5:b0:4af:91d5:8d1a with SMTP id g5-20020a0562141cc500b004af91d58d1amr2278170qvd.70.1665029319182; Wed, 05 Oct 2022 21:08:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029319; cv=none; d=google.com; s=arc-20160816; b=j8RPn/MByCifksoii321Fm76kge3y0B0q1Zt12JWZxp6yBy6UA18OMJdRBy+7TQYt4 Dy9zsmjnZ3GhAVSGLOM6FH20cFuRvAh79WPN1SwEY795ICRJKanDe/LCB63O9tqPjcf/ fUI+oKZgDIB+u0pcNiMT6OAdKSheestE0zsXYC3ep/MBllS0YZyy9j9gWXWPkOY7wDGs fZ3XW0v820pi7/YA8+DBeXLdURkULCk6Lq5Elua5EC9Mya7tziJ5GEKBEyCF93PzwBDp auSw5URPXmdYXiZtJl7O3rj9iD8RWvZZJx3MClQP2McEEnZK/vZ5AIUgz8LK7NRCdSoK sWdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HK7ix9AO/8mxB8DbXZV83BhAtiM36n+x9LjSZXjhklE=; b=iRM2Q+6kTn8YYK/LZk/Hwxf+4b+ocgnbwSz2fIsgfy7daMaYNJZ9ZR6gA1bFTjhuzg paJm1Bd6IPbLHPCx8lLKEjTi/tsBmyf7OR+2EQfID1TU2ZM/x3UVg45dK/E1Qkn1ycNi /Nv9kyN1f56qzWSzIN69LYyWahka8a7Ul/x6Xb/T6DSiujSFdhv5a1vW+znmUVAFCHdJ +6jtRMPJrIDzEU1pVrVSw3KbSUnkLu2QzYrkARPTbDWH3MuYaNra900cgXLAxNMXfsFy Nj21cyH3jW6+zR5aY0rpc2K+4Uc05ndRc/xDQos31Z0aOsH3IiFJdcOEVUDvZymXiUzs dhQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="pmQtu/EQ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 11/26] target/s390x: Use ilen instead in branches Date: Wed, 5 Oct 2022 20:44:06 -0700 Message-Id: <20221006034421.1179141-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the remaining uses of pc_tmp, and remove the variable. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2ea3feb803..67c86996e9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -141,12 +141,6 @@ struct DisasContext { TCGOp *insn_start; DisasFields fields; uint64_t ex_value; - /* - * During translate_one(), pc_tmp is used to determine the instruction - * to be executed after base.pc_next - e.g. next sequential instruction - * or a branch target. - */ - uint64_t pc_tmp; uint32_t ilen; enum cc_op cc_op; bool exit_to_mainloop; @@ -1198,7 +1192,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (is_imm) { - if (dest == s->pc_tmp) { + if (disp == s->ilen) { /* Branch to next. */ per_branch(s, true); ret = DISAS_NEXT; @@ -1222,7 +1216,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } } - if (use_goto_tb(s, s->pc_tmp)) { + if (use_goto_tb(s, s->base.pc_next + s->ilen)) { if (is_imm && use_goto_tb(s, dest)) { /* Both exits can use goto_tb. */ update_cc_op(s); @@ -6247,7 +6241,6 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) g_assert_not_reached(); } } - s->pc_tmp = s->base.pc_next + ilen; s->ilen = ilen; /* We can't actually determine the insn format until we've looked up @@ -6484,7 +6477,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) out: /* Advance to the next instruction. */ - s->base.pc_next = s->pc_tmp; + s->base.pc_next += s->ilen; return ret; } From patchwork Thu Oct 6 03:44:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612883 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1209473pvb; Wed, 5 Oct 2022 21:06:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7aJKYD72pQvXio5GOJ8MRomxNmXrPYw8gNIiEo2sTT55RI960QjEbsVlHeZ94tnGXgB54e X-Received: by 2002:ae9:f717:0:b0:6e5:f9b1:27ee with SMTP id s23-20020ae9f717000000b006e5f9b127eemr238131qkg.173.1665029197352; Wed, 05 Oct 2022 21:06:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029197; cv=none; d=google.com; s=arc-20160816; b=NoNorMGpd2UYzG8/pn/39nYqHDBqyKouiC4THkuz0zUL9v1zwpqE0+GZn0Kp0TX12F ImfdX9DuhS5oF7fbpinBs8jmKwHrGZZe/HeM10N4R2vmcHNZG2zMcL7Ld5ay+Nu77kzn UdSJM/+Sp4jl4xkQhwldshPzwZHhwg1hUXqKYF83tmncvcb39xWe+M/O0Qoa9z/6h4Da eIz0mRSuv+ydYDj8ETTMOmSLx/yjk9sooWQDeUCLAPpBYIua+glD0IclCir5/9E5FweK 2O/FFIuRlZyyrf4kOwbzfGPHqKzUG+Y+6mRRN6PaG1VLdcVpblOwn7UkvxYNMVnci4OX U34Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MQwqk3aIYqNZS+g6VsRklK9PY/N9SMW46xNvH4pbJm0=; b=z18PtoCuMtxzNkGpBHgUaUH7V20Fzif+Rg/rBLmflioceUC8K4h5NAyL4LyDuooRh0 puSUUkEXKfTk8O+eAmzSCtPd+gDD6H84MzwKav516zpTmiL30xqrHWEan2nnemTKVD2d bdVWIgihJEdwOs7LtjeW2KkSZhk8MW6Rlhow452YLYPN2jnMqILiXlq1rIc0eQ7I+C84 jKsxpLrhzW7dfHF7i1NamIbVPuPxOdFQns2hPEZjZNMZ3VQr1mR7ww8jX66lv6dbqjAY fjoNDLYQh0bBeZzya6ZYEkS2D5qxS0cXurn/Dtc6qfqJkZO+ZyfKEAD2scYWPm/Hd/PN s3HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HHdvb2Yp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state Date: Wed, 5 Oct 2022 20:44:07 -0700 Message-Id: <20221006034421.1179141-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Masking after the fact in s390x_tr_init_disas_context provides incorrect information to tb_lookup. Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 13 +++++++------ target/s390x/tcg/translate.c | 6 ------ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7d6d01325b..b5c99bc694 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -379,17 +379,18 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) } static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) + target_ulong *cs_base, uint32_t *pflags) { - *pc = env->psw.addr; - *cs_base = env->ex_value; - *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + int flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->cregs[0] & CR0_AFP) { - *flags |= FLAG_MASK_AFP; + flags |= FLAG_MASK_AFP; } if (env->cregs[0] & CR0_VECTOR) { - *flags |= FLAG_MASK_VECTOR; + flags |= FLAG_MASK_VECTOR; } + *pflags = flags; + *cs_base = env->ex_value; + *pc = (flags & FLAG_MASK_64 ? env->psw.addr : env->psw.addr & 0x7fffffff); } /* PER bits from control register 9 */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 67c86996e9..9ee8146b87 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6485,12 +6485,6 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - /* 31-bit mode */ - if (!(dc->base.tb->flags & FLAG_MASK_64)) { - dc->base.pc_first &= 0x7fffffff; - dc->base.pc_next = dc->base.pc_first; - } - dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; dc->exit_to_mainloop = (dc->base.tb->flags & FLAG_MASK_PER) || dc->ex_value; From patchwork Thu Oct 6 03:44:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612891 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1212160pvb; Wed, 5 Oct 2022 21:14:20 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5BLey1fjZta9mCZwNE4+IfSetdxWv7lfJ+JcEjQ6it7i9TIzsppwhAu3ZNGjmyTAO1Xnmr X-Received: by 2002:a05:622a:211:b0:38f:562a:b495 with SMTP id b17-20020a05622a021100b0038f562ab495mr2049795qtx.669.1665029660123; Wed, 05 Oct 2022 21:14:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029660; cv=none; d=google.com; s=arc-20160816; b=yFVFwSrEcW2mn/IMCKVPHYstffXgrHOK7283/EuLCx4PMuDgYQjb2Juj3Gsq4iAQM9 Vr67+8Mfvw0okTfr5adCbHVjp162nLJg1lpeqxzS2oPm/N5pp/o2nZBXfeYkeXfz8ibS mauuQ649XHWOcRku1S0J3+TvXiLg94XY6msbtnrSrJvpvkcuEGxOvpAqXa+EByBHeOpq hd9OS3Vsp5ENepP5Zd41GDNpZadoe6doeb0cS6zp4+GhEOlxkpTMesH8vShoqw8VQZ+e Rv2uJ1nvsO1bjJ04XvPoEEPY8rtJqlOfM3rB38YWX5Kyvbu2Rk5AaR+gXx7W5E3SyRTO Vjvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PPwEeI49pnflxdKGnZ8Gfig20CEjMBpku/FXWfTvjk4=; b=RQ7qOwerM+yxrBIEfjSpAiAI9BZzOAqjMTIO9ekJ4Z5akCpq+jxKBEVKI1AmDvQzg6 5PX1Pc0rezjzylqqYylJqrkIvrcdr1rD6j7ZZWxxYjnu5ILAX35I5Ts/3zmhIPFmLEzk at4k1J0zJ6iiAEbFKYusTsffKxBu3ZYhoeMt0YTxbkickwCzGuA+r40zq2Y+D/3A/gtO E/mFPhuMj2+pGDRaBxcm4zO37fxPAgyyQTnWz6fbIcolfkKBlwZhPSssbD6OM8M4TQXv Wug8TNyFkIwXGNSkhlutvcDRaNnGiLnvUqFPWRxTBitsHDeyrwjb4vmZftkU6CXtlYBZ 2Qlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="pp/G1ToJ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 13/26] target/s390x: Add disp argument to update_psw_addr Date: Wed, 5 Oct 2022 20:44:08 -0700 Message-Id: <20221006034421.1179141-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to update_psw_addr_disp at the same time. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 9ee8146b87..a20c3bc4f0 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -336,9 +336,9 @@ static void return_low128(TCGv_i64 dest) tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); } -static void update_psw_addr(DisasContext *s) +static void update_psw_addr_disp(DisasContext *s, int64_t disp) { - gen_psw_addr_disp(s, psw_addr, 0); + gen_psw_addr_disp(s, psw_addr, disp); } static void per_branch(DisasContext *s, bool to_next) @@ -444,7 +444,7 @@ static void gen_program_exception(DisasContext *s, int code) offsetof(CPUS390XState, int_pgm_ilen)); /* update the psw */ - update_psw_addr(s); + update_psw_addr_disp(s, 0); /* Save off cc. */ update_cc_op(s); @@ -1168,11 +1168,11 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) update_cc_op(s); per_breaking_event(s); tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, disp); + update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - gen_psw_addr_disp(s, psw_addr, disp); + update_psw_addr_disp(s, disp); per_branch(s, false); return DISAS_PC_UPDATED; } @@ -2448,7 +2448,7 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); if (r1 == 0) { @@ -3175,7 +3175,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o) /* In a parallel context, stop the world and single step. */ if (tb_cflags(s->base.tb) & CF_PARALLEL) { - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); gen_exception(EXCP_ATOMIC); return DISAS_NORETURN; @@ -4490,7 +4490,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); if (s->base.tb->flags & FLAG_MASK_PER) { - update_psw_addr(s); + update_psw_addr_disp(s, 0); gen_helper_per_store_real(cpu_env); } return DISAS_NEXT; @@ -4728,7 +4728,7 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o) { TCGv_i32 t; - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); t = tcg_constant_i32(get_field(s, i1) & 0xff); @@ -6467,7 +6467,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (s->base.tb->flags & FLAG_MASK_PER) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - gen_psw_addr_disp(s, psw_addr, s->ilen); + update_psw_addr_disp(s, s->ilen); } /* Call the helper to check for a possible PER exception. */ @@ -6534,7 +6534,7 @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_NORETURN: break; case DISAS_TOO_MANY: - update_psw_addr(dc); + update_psw_addr_disp(dc, 0); /* FALLTHRU */ case DISAS_PC_UPDATED: /* Next TB starts off with CC_OP_DYNAMIC, so make sure the From patchwork Thu Oct 6 03:44:09 2022 Content-Type: text/plain; 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 14/26] target/s390x: Don't set gbea for user-only Date: Wed, 5 Oct 2022 20:44:09 -0700 Message-Id: <20221006034421.1179141-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The rest of the per_* functions have this ifdef; this one seemed to be missing. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a20c3bc4f0..868895b9ae 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -384,7 +384,9 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, static void per_breaking_event(DisasContext *s) { +#ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); +#endif } static void update_cc_op(DisasContext *s) From patchwork Thu Oct 6 03:44:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612886 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1210425pvb; Wed, 5 Oct 2022 21:09:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6KzS29EEvZmT9JSa4+6zUQqdoCbjVwRbGKo3q/iAWO2YGMZe7Xtqki2bAccvOBJSgHj4W+ X-Received: by 2002:a05:6214:3011:b0:4b1:be7e:3f93 with SMTP id ke17-20020a056214301100b004b1be7e3f93mr2405422qvb.48.1665029369322; Wed, 05 Oct 2022 21:09:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029369; cv=none; d=google.com; s=arc-20160816; b=QJaSj2bDxwpvvQeiLH4s+rvVZLBIs514P3TNlbBFi2YGp/YCgXzD6R01j3HHl63V4A l+M7D0Lp1wZ+cq7ED7PIYT+RklE9l0Q0s7us3miIZQKLgQeHyQL4sNwm1mgusst89DEK 3Rt54gPfaIXuVCKEZItxrZQ9E0Fu2X2w8ljVRAZ3bB5YAIpCkW3+oFpn8isDtdKClal1 6UlROoAxuuvwLbz7G0YqeuwzsWvfHQf9uKKkK+QcIvxggJDfwJzcpIuc3gNmGy8fIJ7K 64en5QIDFUsn9sz32RHju8ObHXLbZh4AhVzAkOz0ISiJvG50Kb3MpCgJmYBkwQOgiqd+ Zzeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OTnwC3I8LADyA6oY2sKnptmoUlM1a+IpjL6VUPaeMMw=; b=JEz0LnIEuy18woCVsZEkz7jYibN2JNx21XtjnC0aALcDil3HzTjLVTaXaIpACTqdqm RQYjIwwuKFIIsPM8voAGm0B0pWRRL++K0UDmD2drIlhCxya1GfSDIACwvbblT8dQmGLp DZRfF1oVR8GRexjeUx5WC+asJD0ea7UX5/b4RwG0TrmT4QFeY+LCxAoMeeVfFYbyPiGX +VtLwwboSQPxoyKX7RVJbrY9wy+cHeyFUvTBu+soWQScQCPLJ9jGqe4+s0X55n3aRp4m Usfp9V0usu8xKgvXzBOFK3q1QJHgzHVmA74dEsFeO+pqw+4WmwMFnoB5244CcDzkmQj1 YA+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r4FmGQeJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 15/26] target/s390x: Introduce per_enabled Date: Wed, 5 Oct 2022 20:44:10 -0700 Message-Id: <20221006034421.1179141-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the test of FLAG_MASK_PER to a helper. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 868895b9ae..cd311b4b2a 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -341,12 +341,21 @@ static void update_psw_addr_disp(DisasContext *s, int64_t disp) gen_psw_addr_disp(s, psw_addr, disp); } +static inline bool per_enabled(DisasContext *s) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + return unlikely(s->base.tb->flags & FLAG_MASK_PER); +#endif +} + static void per_branch(DisasContext *s, bool to_next) { #ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { if (to_next) { TCGv_i64 next_pc = tcg_temp_new_i64(); @@ -364,7 +373,7 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2) { #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { TCGLabel *lab = gen_new_label(); tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); @@ -665,7 +674,7 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (unlikely(s->base.tb->flags & FLAG_MASK_PER)) { + if (per_enabled(s)) { return false; } return translator_use_goto_tb(&s->base, dest); @@ -4491,7 +4500,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { update_psw_addr_disp(s, 0); gen_helper_per_store_real(cpu_env); } @@ -6343,7 +6352,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { TCGv_i64 addr = tcg_temp_new_i64(); gen_psw_addr_disp(s, addr, 0); @@ -6466,7 +6475,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { update_psw_addr_disp(s, s->ilen); @@ -6489,7 +6498,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; - dc->exit_to_mainloop = (dc->base.tb->flags & FLAG_MASK_PER) || dc->ex_value; + dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value; } static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) From patchwork Thu Oct 6 03:44:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612894 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1213318pvb; Wed, 5 Oct 2022 21:17:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM684fC1u8y3l/VEkHH3YxL7IPyovCLB1Z5VcLWxsdmYm5OQDkXiekrzZigruOBZmvplT2+2 X-Received: by 2002:a05:620a:440d:b0:6ce:c800:c319 with SMTP id v13-20020a05620a440d00b006cec800c319mr2019703qkp.331.1665029838239; Wed, 05 Oct 2022 21:17:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029838; cv=none; d=google.com; s=arc-20160816; b=kCtqkUB8H0soiXWXWh7HGXodFNCSUHKKl8xh9EDJLBmsFLAvpu/k9I3yry8lppcSkT AzNVcWY90oD6P6Q+7pwZ8gZqO+nBBzkgGD/1/10ZyPK6IuVSuT3wzNkMELgpMj0TVV5a fZF4H3sQ3GIYOhfXM+I6HutNWm4pG30WwrCyVY+oqfA3725/86/BQ962kBBVBR4Vygpk 6TsTx7l51s8QrjfF3UP3degGit0tLj8yF2IH311XBQZ0iccJYIK8uv9qIKG1eHfLMEMS jB4Hu73Bp3BYi1ew0odDm6F9cS7KCimymHYeVB/O4a2bqvzapDOYSSXvtAFUzMEDV7xp Pjng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7HI+xpPxCIX6BauxWntrNZ0C5lHr5ZXLxWzQGdsbbe4=; b=wD0LSlo/zPJUq7VyxW2oww8IeE8MCWFwd0SIfpcQ91YK+CoPFcfIYmgu+gJxjor37t +1wu2NZqljJ6WHDr7s032pxNNc+GLoFQ6J8moJfCpkehj/pkeDBFL9Nb0piNZVPmk0jy e+LaXoTNCfrBUjzCRMUwBr4mmK90nV/4Pfx7c92FXRCoPL0fGN1HVhWJAZTGz3nw1Bve v2mqYrmu6jQxl8CnwMVdXSPiRirJHsPzYwg7B3PfZHxfQh10QjVlajAgDaBBFFaKMHNF r8ePOTaFCRVoV9YC29ORESog7lsF9nxEi5NHj8CRCYL7YXlTfrw46lJU/9irxVzErgni X9Gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cZjtz7zv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 16/26] target/s390x: Disable conditional branch-to-next for PER Date: Wed, 5 Oct 2022 20:44:11 -0700 Message-Id: <20221006034421.1179141-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For PER, we require a conditional call to helper_per_branch for the conditional branch. Fold the remaining optimization into a call to helper_goto_direct, which will take care of the remaining gbea adjustment. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index cd311b4b2a..fc6b04e23e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1203,13 +1203,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (is_imm) { - if (disp == s->ilen) { - /* Branch to next. */ - per_branch(s, true); - ret = DISAS_NEXT; - goto egress; - } - if (c->cond == TCG_COND_ALWAYS) { + /* + * Do not optimize a conditional branch if PER enabled, because we + * still need a conditional call to helper_per_branch. + */ + if (c->cond == TCG_COND_ALWAYS + || (disp == s->ilen && !per_enabled(s))) { ret = help_goto_direct(s, disp); goto egress; } From patchwork Thu Oct 6 03:44:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612890 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1211580pvb; Wed, 5 Oct 2022 21:12:50 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7Vibg2/50ajt5rSo8kk3VE/adRYKI6NA8Y4nNgRpd16g6/pxoHA6oGcvIGn25GN0vPLz7N X-Received: by 2002:ac8:5953:0:b0:35b:ab1a:ff09 with SMTP id 19-20020ac85953000000b0035bab1aff09mr2110665qtz.144.1665029570050; Wed, 05 Oct 2022 21:12:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029570; cv=none; d=google.com; s=arc-20160816; b=s/awTanLyv2rPcWBcUAZHeu+Ai04jAAuFZLUbmfQVaGp2rwuunX8ssWTCaWkB33ioy AtSgzuA3OpDNKHF50qqIvBlMHbRNWaEn2ryLwQA/4qMQd3ky6GhZ8998hyTVQ1YN5NKv 9RZ6y8OxA5jFyhWLH1zq2a2vSKMEBcoiv1C3+F5/Nsaqtiak37Z6dwdVtbzEsC0qHNhD eZAyA1AnNKX9tVS8WqLjmsuEvokIXSG7aXvrfrHIie5dOm2y0+Qz4w5Jc3wWXX+CuwFW x0uXWchiZLFU8VBR7THRIXCSTA0jqUZpcFkskyuRedgp28sFn69DlMOCZEyj1yyG5n6y qX1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=B458Afawec85XoXWpbjPbqxmo9p/Fje9hPN8wU9nu7E=; b=ZQ5JpJkx96kGUfZcJHG+jxurD8lVV+v/i0JZ3lgehmRlxbbTjjj2MHL1pU/ZlXLq4t eGBH6zqSz9dR98e21bnCoF6Sf5agutc7OfBTLes2iunpRBe6YpuH7j4GPV7iEycBNHvn 6X+K/IHToQqiWQbVIOZWHi4jo+oFkrR8ox6gLJBtqOle8vNEkdpcYpVvhRI5W6IggAGR TXXExBPnJa4nM57wfbJzi5uGpfEMstPvNyETbEie3LchG9n52B56ZHFAaQl85NXxQJcr YE1sHC6cbg9dw/jQF4naCEW6iMuk32WiDRijIVpliul5kTiRIkU5o9dWO79tQb5QBxrv QgtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j8UnLD2a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 17/26] target/s390x: Introduce help_goto_indirect Date: Wed, 5 Oct 2022 20:44:12 -0700 Message-Id: <20221006034421.1179141-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a small helper to handle unconditional indirect jumps. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index fc6b04e23e..712f6d5795 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1189,6 +1189,13 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) } } +static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) +{ + tcg_gen_mov_i64(psw_addr, dest); + per_branch(s, false); + return DISAS_PC_UPDATED; +} + static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { @@ -1219,9 +1226,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (c->cond == TCG_COND_ALWAYS) { - tcg_gen_mov_i64(psw_addr, cdest); - per_branch(s, false); - ret = DISAS_PC_UPDATED; + ret = help_goto_indirect(s, cdest); goto egress; } } @@ -1545,9 +1550,7 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { pc_to_link_info(o->out, s); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } @@ -1580,9 +1583,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) { save_link_info(s, o); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } From patchwork Thu Oct 6 03:44:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612898 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1214436pvb; Wed, 5 Oct 2022 21:20:33 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4AWFTdaGVxtLgB7FQnuN+o5M39foxOhXTz875Hvy4ty4wJd6fmziy63ErhAZFDm+qKqZv1 X-Received: by 2002:a05:620a:488c:b0:6e4:eb0a:4a2f with SMTP id ea12-20020a05620a488c00b006e4eb0a4a2fmr1642119qkb.228.1665030033634; Wed, 05 Oct 2022 21:20:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665030033; cv=none; d=google.com; s=arc-20160816; b=Q6QDTszdHBQpOuUmvLW4PoRikDdDTeccqi91F+w9z2RoZb2bJqkVNxKpnr+bK6d78S jQaZMAF9RiiVpvyx+n7OecrcuXzyKjAYpwYN1g7E2brkv+Jxw1FWT1XDQWerr5lxglIk rJaHd8fFc70iNYC2CPRERdh4CjzMLEekODhmNn5xnYm61Xqn/qVMAJ1xy1DUGC267d7A Opid3sd5F/QEnZG7phcq2Ze/JvnjcapWWS2M+mR5hX126XIV6uRbJ0S8IOFSQA4iNDzJ 0r/R/DanRQE+fi3HKTvTqJfwvLjuiMuRhPmsEoC3jXh+74M2pE0BatNzZinAqg57UkQg JIAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OGKK8ii462fh2FYHuqVoO8HNQ7SQYpLXPO2c0Erkaco=; b=PvHu/j7B1HSIVz8pNkNvJ/bKnWwrR/c4E+aEd4d+YjgGnD0NQjAB8fiOLvPzCUMtTW ZXDL4OO5sYJxteESzl4SbADEkNEwKkzmTqq/V53yC+apFmNlS2qqGC4oLihalNRtr5c+ 6bxJUthJyTLTzuUAf7YwVKfYXSHtOFxLOUNQPrHZjy31VQykTvW2Ko5eo4Oo9MQXlE1r cbLUoJ+vRsQUU884L8kmoaynCsHxCTN0An6jmWOSFiCbGSFXY6gJiVqUC0tt8jtbA6rM QojRZMMxtp06abhA9yVxonFGAsoAJAxo0/sBWOKIeb2MCunkhkXmPI18JLMpz1cbBNvO 0lwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FbfBCOT+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 18/26] target/s390x: Split per_branch Date: Wed, 5 Oct 2022 20:44:13 -0700 Message-Id: <20221006034421.1179141-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split into per_branch_dest and per_branch_disp, which can be used for direct and indirect. In preperation for TARGET_TB_PCREL, call per_branch_* before indirect branches. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 712f6d5795..bd2ee1c96e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -350,21 +350,25 @@ static inline bool per_enabled(DisasContext *s) #endif } -static void per_branch(DisasContext *s, bool to_next) +static void per_branch_dest(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); + if (s->base.tb->flags & FLAG_MASK_PER) { + gen_helper_per_branch(cpu_env, gbea, dest); + } +#endif +} - if (per_enabled(s)) { - if (to_next) { - TCGv_i64 next_pc = tcg_temp_new_i64(); - - gen_psw_addr_disp(s, next_pc, s->ilen); - gen_helper_per_branch(cpu_env, gbea, next_pc); - tcg_temp_free_i64(next_pc); - } else { - gen_helper_per_branch(cpu_env, gbea, psw_addr); - } +static void per_branch_disp(DisasContext *s, int64_t disp) +{ +#ifndef CONFIG_USER_ONLY + gen_psw_addr_disp(s, gbea, 0); + if (s->base.tb->flags & FLAG_MASK_PER) { + TCGv_i64 dest = tcg_temp_new_i64(); + gen_psw_addr_disp(s, dest, disp); + gen_helper_per_branch(cpu_env, gbea, dest); + tcg_temp_free_i64(dest); } #endif } @@ -1172,7 +1176,7 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { if (disp == s->ilen) { - per_branch(s, true); + per_branch_disp(s, disp); return DISAS_NEXT; } if (use_goto_tb(s, s->base.pc_next + disp)) { @@ -1184,7 +1188,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) return DISAS_NORETURN; } else { update_psw_addr_disp(s, disp); - per_branch(s, false); + per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } } @@ -1192,7 +1196,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { tcg_gen_mov_i64(psw_addr, dest); - per_branch(s, false); + per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } From patchwork Thu Oct 6 03:44:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612900 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1215560pvb; Wed, 5 Oct 2022 21:23:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4AjdW3LMxPRDP5e6AQTIq9EgJVV6tK+BrMwCtqDyEWVWZYPs/IU//qOBN0WroNWAHWfmbz X-Received: by 2002:a05:622a:1185:b0:35c:e2c4:7a4e with SMTP id m5-20020a05622a118500b0035ce2c47a4emr2110289qtk.241.1665030238570; Wed, 05 Oct 2022 21:23:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665030238; cv=none; d=google.com; s=arc-20160816; b=Gzu269zliFkoPAxHjmGHdWR9hSowIgnrCVhACNdzsbPabY2GIO+S17gBjAo9c/K8Kk Ru1AP8k0RX5VeW1dKRXWHlIjB/3+rCjkKPrII/PBSBdbbq8Kf2WO5do8RjFhrtZc8Uut NJhwJdMP/asuY/43LrrYbu9Vvo56V6Bdz0cqm8YoF2vJMoHY+hlOYG0b9QXHtNtEqyLG MjOw1j95F30zSvzP0HvBgiRuoOOsOiujm/3WvYMuc5KSownLK12EvHav5/zsWfq+wSS1 XkG3pxtJ28UsKiEd+z+WaxDNFRyHNZ06hbXUmIsh06r+cmiVYHU2r0n9JWlsImyDx2dR s0FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BdEUNGwh82f979hGOsFFOfn9g+TbBS52GY9ZiM+BpZc=; b=bW+7O6yndGcE7dhfihatU2XV5Sm4DkNJC7cVovn7o6DSMwsff22vQYt0zESVtf0d+c LJufePWG+T8cEdmrywOLyo12hCyOksRovegX3NCHE5qcToII7zlBBPpjp0owtchBa1WM RGzFnlTWCq8s6P4s69zczdVgtsElI+DtNgUZpfTVA55KHixRqrVWuwDMSSiniRAZjRT/ i4Z1YBwp6te2Go+H1Ywio0bQg1XKTIyTbamH5HvhULzj2xjs3vwdkPrYKnryusC0XBKG h8xe3YMEbsU9YvRboWUCkSWgXiDT4BnA/1fTMdM+SkJUQEBrXKkeCqRk6mXA2YXHJiZn 3RFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N59DgHX9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 19/26] target/s390x: Simplify help_branch Date: Wed, 5 Oct 2022 20:44:14 -0700 Message-Id: <20221006034421.1179141-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Always use a tcg branch, instead of movcond. The movcond was not a bad idea before PER was added, but since then we have either 2 or 3 actions to perform on each leg of the branch, and multiple movcond is inefficient. Reorder the taken branch to be fallthrough of the tcg branch. This will be helpful later with TARGET_TB_PCREL. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 154 ++++++++++------------------------- 1 file changed, 44 insertions(+), 110 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bd2ee1c96e..498dc2930d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -373,28 +373,6 @@ static void per_branch_disp(DisasContext *s, int64_t disp) #endif } -static void per_branch_cond(DisasContext *s, TCGCond cond, - TCGv_i64 arg1, TCGv_i64 arg2) -{ -#ifndef CONFIG_USER_ONLY - if (per_enabled(s)) { - TCGLabel *lab = gen_new_label(); - tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); - - gen_psw_addr_disp(s, gbea, 0); - gen_helper_per_branch(cpu_env, gbea, psw_addr); - - gen_set_label(lab); - } else { - TCGv_i64 pc = tcg_temp_new_i64(); - - gen_psw_addr_disp(s, pc, 0); - tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - tcg_temp_free_i64(pc); - } -#endif -} - static void per_breaking_event(DisasContext *s) { #ifndef CONFIG_USER_ONLY @@ -1205,7 +1183,6 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, { DisasJumpType ret; int64_t disp = (int64_t)imm * 2; - uint64_t dest = s->base.pc_next + disp; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1235,96 +1212,53 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } } - if (use_goto_tb(s, s->base.pc_next + s->ilen)) { - if (is_imm && use_goto_tb(s, dest)) { - /* Both exits can use goto_tb. */ - update_cc_op(s); + update_cc_op(s); - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, s->ilen); - tcg_gen_exit_tb(s->base.tb, 0); - - /* Branch taken. */ - gen_set_label(lab); - per_breaking_event(s); - tcg_gen_goto_tb(1); - gen_psw_addr_disp(s, psw_addr, disp); - tcg_gen_exit_tb(s->base.tb, 1); - - ret = DISAS_NORETURN; - } else { - /* Fallthru can use goto_tb, but taken branch cannot. */ - /* Store taken branch destination before the brcond. This - avoids having to allocate a new local temp to hold it. - We'll overwrite this in the not taken case anyway. */ - if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); - } - - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - update_cc_op(s); - tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, s->ilen); - tcg_gen_exit_tb(s->base.tb, 0); - - gen_set_label(lab); - if (is_imm) { - gen_psw_addr_disp(s, psw_addr, disp); - } - per_breaking_event(s); - ret = DISAS_PC_UPDATED; - } - } else { - /* Fallthru cannot use goto_tb. This by itself is vanishingly rare. - Most commonly we're single-stepping or some other condition that - disables all use of goto_tb. Just update the PC and exit. */ - - TCGv_i64 next = tcg_temp_new_i64(); - - gen_psw_addr_disp(s, next, s->ilen); - if (is_imm) { - cdest = tcg_temp_new_i64(); - gen_psw_addr_disp(s, cdest, disp); - } - - if (c->is_64) { - tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b, - cdest, next); - per_branch_cond(s, c->cond, c->u.s64.a, c->u.s64.b); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 z = tcg_constant_i64(0); - tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); - tcg_gen_extu_i32_i64(t1, t0); - tcg_temp_free_i32(t0); - tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); - per_branch_cond(s, TCG_COND_NE, t1, z); - tcg_temp_free_i64(t1); - } - - tcg_temp_free_i64(next); - if (is_imm) { - tcg_temp_free_i64(cdest); - } - ret = DISAS_PC_UPDATED; + /* + * Store taken branch destination before the brcond. This + * avoids having to allocate a new local temp to hold it. + * We'll overwrite this in the not taken case anyway. + */ + if (!is_imm) { + tcg_gen_mov_i64(psw_addr, cdest); } + lab = gen_new_label(); + if (c->is_64) { + tcg_gen_brcond_i64(tcg_invert_cond(c->cond), + c->u.s64.a, c->u.s64.b, lab); + } else { + tcg_gen_brcond_i32(tcg_invert_cond(c->cond), + c->u.s32.a, c->u.s32.b, lab); + } + + /* Branch taken. */ + if (is_imm) { + gen_psw_addr_disp(s, psw_addr, disp); + } + per_branch_dest(s, psw_addr); + + if (is_imm && use_goto_tb(s, s->base.pc_next + disp)) { + tcg_gen_goto_tb(0); + tcg_gen_exit_tb(s->base.tb, 0); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + + gen_set_label(lab); + + /* Branch not taken. */ + if (use_goto_tb(s, s->base.pc_next + s->ilen)) { + tcg_gen_goto_tb(1); + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_exit_tb(s->base.tb, 1); + } else { + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_lookup_and_goto_ptr(); + } + + ret = DISAS_NORETURN; + egress: free_compare(c); return ret; From patchwork Thu Oct 6 03:44:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612893 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1213111pvb; Wed, 5 Oct 2022 21:16:47 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6drnpIlPzzBPpT8lltxkqC5gmDsmBMU55Ce+nF7enYNBUJpdrMEwYpztzpIlTnzhL16Ncs X-Received: by 2002:ac8:7d92:0:b0:35c:be77:5e2b with SMTP id c18-20020ac87d92000000b0035cbe775e2bmr2018219qtd.505.1665029807840; Wed, 05 Oct 2022 21:16:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029807; cv=none; d=google.com; s=arc-20160816; b=XUKEJDxGH8dbhXjAH4N7nKu100585F0oG8Q9Ire2k1eI8CJ+iJ9unPfdPcMgNt49cX 1IBbeE3aZzDlBF4jNi3AMummHjWzK80piapDLWUaMABVUUyAgE346a/GGeQzWxWFuSrJ XSIkJbBLYC1OppcIh3X6rCv3cQ8ZDRFhHm4MH0LrM5mA9a3WK4iQuLScnFV0CZxGZEfu qRT1n2xJsde/Ck1xBqpOd4GTtiCeuSGPCiL8zQeDTH2qG3qUWIIw+9qM1XQ1e7HioM+r BayYXlIdrZMvSs7Qrx6IW6O0MwcPNAaJt17U68TafLsJrg1QNh5oo6T+HaorCrDMZhi4 5+Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5HalDKM2t7tQ28RoBBhE3f7ultMsCTeXd5L6wovkjbQ=; b=xzYO8E45zANhUWdXDUZWcJbSDBP6vSn22/nu3VsvCXPrTQyfSCcBeBqvQyTi/hPoLs EDlv2a8PgZHXEQWDJEMQ6amMregLQRXXIFsrJqlfS+mjnxYO0WCAy8C8Gd87+VD9rDja AnoRIYzMzrf3RP3vB43Atcig9QEIrLTbpIfX0C1dUtnbdWrm3i0bMJvrebvUJ8ZSRiiW SCPfxQx6eFOvg8ekb2oHhKkBWW75yJUIYvAMzSAxfIAQkOBvsL45cWwgc/2WxaqdCVoL SkzI6mJaJfczPHqPM4vZLrZjvmTmq00ctcE/4pwquMlDhIyHnRX82vwfrackRTOUx5GM KynA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NRH5JQDW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 20/26] target/s390x: Split per_breaking_event from per_branch_* Date: Wed, 5 Oct 2022 20:44:15 -0700 Message-Id: <20221006034421.1179141-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to update gbea before other updates to psw_addr, which will be important for TARGET_TB_PCREL. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 498dc2930d..a2315ac73e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -353,7 +353,6 @@ static inline bool per_enabled(DisasContext *s) static void per_branch_dest(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY - gen_psw_addr_disp(s, gbea, 0); if (s->base.tb->flags & FLAG_MASK_PER) { gen_helper_per_branch(cpu_env, gbea, dest); } @@ -363,7 +362,6 @@ static void per_branch_dest(DisasContext *s, TCGv_i64 dest) static void per_branch_disp(DisasContext *s, int64_t disp) { #ifndef CONFIG_USER_ONLY - gen_psw_addr_disp(s, gbea, 0); if (s->base.tb->flags & FLAG_MASK_PER) { TCGv_i64 dest = tcg_temp_new_i64(); gen_psw_addr_disp(s, dest, disp); @@ -1153,13 +1151,14 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { + per_breaking_event(s); + if (disp == s->ilen) { per_branch_disp(s, disp); return DISAS_NEXT; } if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); - per_breaking_event(s); tcg_gen_goto_tb(0); update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); @@ -1173,6 +1172,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { + per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; @@ -1233,6 +1233,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } /* Branch taken. */ + per_breaking_event(s); if (is_imm) { gen_psw_addr_disp(s, psw_addr, disp); } From patchwork Thu Oct 6 03:44:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612897 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1214181pvb; Wed, 5 Oct 2022 21:19:49 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4GDaOA0FkvZFZ1fGV7pqLBhOEGFz1y7CEmL+KMFcfyYOCyXx8yp15jcf3egHzTjy41Khe5 X-Received: by 2002:a05:620a:15d2:b0:6cf:2d38:9c0d with SMTP id o18-20020a05620a15d200b006cf2d389c0dmr1997316qkm.426.1665029989273; Wed, 05 Oct 2022 21:19:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029989; cv=none; d=google.com; s=arc-20160816; b=WShOVkiqzBfZIuKIq3ETkF9uojkzFfZibPFxp6ZYt23TDqM/hUQA+Z45nlRRjLqH0R CrvWDG84nu7aVjwweuUkyBoJ+B2xxLeozy+scMFfrw+tJ19O+BTZ6ZgmTBq9HyeztmdZ ROS6HfzVxi7vClWQQH2mAoddIzlFvbKUIx7Nmvlk39ApP7hBsgEqJnCk8cK076AaICuu UxAeT2sCL/rFRCt0709EV05HqpKgEFPNQMoGi1iLWVHA9tvH5QX2zFOhXU8M1xla/hY8 srYL9f8IpclJ6/bquGSNQ0VoQ0PRP10hFMWL/tUSchP60mkmq0+oMIuAcGfQ+gCPZxYK Gukw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4KnyaNg03Q9A36I/gIWbI9OfpLPWp7gded3zO91Ecgk=; b=ySapPxPWu9u/MtcFx2v6URGWMoNEIzPm5gccMQLvvIu41boJAFY9i6+S86ZzWHhiQB kNASKmTgIKqv6ScNNW3WAy6DlHIqrbRmmZYXxOYSek9beVck4acijzwR/bS7qCrvYojT xQpe1CeQjz+2GwFeol1FDxJAK4/55byS0YZEqjOkZ0HUDOHWrq1GWgbhEs6Lv+Op9p9X 2062jTmBnM59Q+IReGpBiBc0Vn6eb20UVjx6hU0hIBH8xyxpzbDI9Alo8wP7Mr5TAmAd 29Q8gQKsOgcayL8OqwLbZWVZJe5JlX7xQInB3jgKCpRAX3lnyUFQUw8wSZojU5blXg41 GRZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=su22LA51; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 21/26] target/s390x: Remove PER check from use_goto_tb Date: Wed, 5 Oct 2022 20:44:16 -0700 Message-Id: <20221006034421.1179141-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While it is common for the PC update to happen in the shadow of a goto_tb, it is not required to be there. By moving it before the goto_tb, we can also place the call to helper_per_branch there, and then afterward chain to the next tb. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a2315ac73e..e6c7c2a6ae 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -654,9 +654,6 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (per_enabled(s)) { - return false; - } return translator_use_goto_tb(&s->base, dest); } @@ -1157,15 +1154,16 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) per_branch_disp(s, disp); return DISAS_NEXT; } + + update_psw_addr_disp(s, disp); + per_branch_dest(s, psw_addr); + if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); tcg_gen_goto_tb(0); - update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - update_psw_addr_disp(s, disp); - per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } } From patchwork Thu Oct 6 03:44:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612895 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1214022pvb; Wed, 5 Oct 2022 21:19:23 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4l10Rwdfkr1iIXu5QZq7RYaWHgF+RwXVd2ErbUWzrjQAHMv4t7zwvDFCg/O9vhqbkjzdCM X-Received: by 2002:a05:622a:549:b0:35d:4b6f:9ab3 with SMTP id m9-20020a05622a054900b0035d4b6f9ab3mr2095061qtx.187.1665029963035; Wed, 05 Oct 2022 21:19:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029963; cv=none; d=google.com; s=arc-20160816; b=qQ0oeaGFcFmvY9d6U+sGy2U/C9mGT7NqB5OFbVKXQ1xyI9jcac43fp8jXPRfEz9BI3 xHkS/PMX6FNFqaKi184p3WEjWilAhoA8+tixrfNF61oWHEl5+4GYY9Up3HARsPNvoE3P sAMkRBiVOQf0mbztBEzRBkpm9YtOBSM+3evWw3XZ7/GgT7J/KuiRy1keGeRM50mIfmFv jBcTPPVsxOVHf1+op7nA2muyabJO7a202HsWSbHuGkt2FMcNJTcQn7joosX05K59d0A+ tcAOJJTU3HQm80Fsbrw+9xruivXEBxt2HIemX7sD8in1qOpN/p6REOUcuXfO40Cj0jB2 YiAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=msqK3kGUwRR1FwwwLv+55zHEqiPImyBWT8EbA4E7iuA=; b=pFFmPoEVlvJjsJwUEHI0xRp2+b4oAd18wbZAUq0FrkDfP+kK7sen3vw1CZEBEIqt4u X/u48Gqjy+SUjWXgTQYTZDQE8UrGUDXnsojxmYjcAXCjtLh/clrsRO5dI7iJ5jllh/i/ AfPE6djElXpPipupMZIEO3GMhTTEjbRFfkBR3xAanUqx5nIoHzO/yQ2sIoFN1bzFvCHJ 3PLQ9NR1UrksPjF26qBBWhEVdc88V+KYLkoXdfDCFPQOzKSWxCV038DVEXdgRQ/BEU1O 7HnKpUG/KGZkQ+zTpChlP8dAiNBY5XmAxIlWoTtk2r7mY1K1OB9lqUyb0qxuGM3dmxjD v/uQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/ZMQvOZ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 22/26] target/s390x: Pass original r2 register to BCR Date: Wed, 5 Oct 2022 20:44:17 -0700 Message-Id: <20221006034421.1179141-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not modify any general-purpose registers in BCR, which means that we may be able to avoid saving the value across a branch. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 10 ++++++++++ target/s390x/tcg/insn-data.def | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index e6c7c2a6ae..b27e34f712 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5704,6 +5704,16 @@ static void in2_r2_nz(DisasContext *s, DisasOps *o) } #define SPEC_in2_r2_nz 0 +static void in2_r2_o_nz(DisasContext *s, DisasOps *o) +{ + int r2 = get_field(s, r2); + if (r2 != 0) { + o->in2 = regs[r2]; + o->g_in2 = true; + } +} +#define SPEC_in2_r2_o_nz 0 + static void in2_r2_8s(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); diff --git a/target/s390x/tcg/insn-data.def b/target/s390x/tcg/insn-data.def index 6382ceabfc..79f9202ab2 100644 --- a/target/s390x/tcg/insn-data.def +++ b/target/s390x/tcg/insn-data.def @@ -121,7 +121,7 @@ /* BRANCH INDIRECT ON CONDITION */ C(0xe347, BIC, RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0) /* BRANCH ON CONDITION */ - C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0) + C(0x0700, BCR, RR_b, Z, 0, r2_o_nz, 0, 0, bc, 0) C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0) /* BRANCH RELATIVE ON CONDITION */ C(0xa704, BRC, RI_c, Z, 0, 0, 0, 0, bc, 0) From patchwork Thu Oct 6 03:44:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612896 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1214071pvb; Wed, 5 Oct 2022 21:19:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6nuNci9YbxggJUq+HcyqPv9anaVOfbCoRn0Gte3RGTLrZU5ka2tXZa+wsB7xhhPQjMApyH X-Received: by 2002:a05:620a:4046:b0:6e1:14b0:86fd with SMTP id i6-20020a05620a404600b006e114b086fdmr1975800qko.536.1665029970117; Wed, 05 Oct 2022 21:19:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029970; cv=none; d=google.com; s=arc-20160816; b=JAyGtY4UFsNoeFDA2/8Lr05luFCzueQ9u4kIxHmomS6xDxUSnLyk52/8IQPj2IR1Hj cTvnO9YL5AHI34Em2EXhI2vtD4OBSTt/l4a+kDUSQhNXOjhX566VZOWqLiK2IJ29fWAl Vu03HtytO6xrOkL4enMZJ6IiUrpI7aq88uJTmIhdrV7xRUk+vxtbYAUpV4h8YsGsMxS1 weYcqVoOTwkYAO7f9AI/oELRasrjeIS42J/wFB3uHpQGOt19btx3Ee3hUYMfOcIS6n3O x81pT8kbKNSIBGAtW9qePm3V7kPnV4IEJTAL2kj+j82Exso4IWrxo12J5C1bET3V12Ho OTNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ItYGoEM5/8BiRF2Ujhf2XO86m4pNgvcvreca63BmeJc=; b=yRDNSsg1z2zh5znEBz+28i6GnsvlnHzp6ww3kyDWjUUVhRy/2PjU6CCjfrNrc9R3EW NWle8KK7cnw432O6e2ciX2yHk974nlxnjv7em+SxLLrcErkF5RFHzwyWjCFjxw4mfIhj Hm2SnozWdsjlutt7ajik7f69D3yr/3IAnomNe6pPwlTssttuZczmZMQ38NdWfNtio/EE DhBqoYo9IUmesa6luRjq6GipLivfzf0j1igs+gdjJ8MOPbYdnkw6qVdsnDc/WPL7oiCV 0ACGmAQ9yOGSouWegO/KHCcUye/6f6a/Zf92oY70R7S7NHVF+k7MJmuy3ErIBZpFqo3S OD8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=adhuwO5B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal Date: Wed, 5 Oct 2022 20:44:18 -0700 Message-Id: <20221006034421.1179141-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- include/tcg/tcg.h | 14 +++++++------- tcg/tcg.c | 20 +++++++++++++++----- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d84bae6e3f..e01a47ec20 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -846,7 +846,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); -TCGTemp *tcg_temp_new_internal(TCGType, bool); +TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind kind); void tcg_temp_free_internal(TCGTemp *); TCGv_vec tcg_temp_new_vec(TCGType type); TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); @@ -880,13 +880,13 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, static inline TCGv_i32 tcg_temp_new_i32(void) { - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_NORMAL); return temp_tcgv_i32(t); } static inline TCGv_i32 tcg_temp_local_new_i32(void) { - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_LOCAL); return temp_tcgv_i32(t); } @@ -899,13 +899,13 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, static inline TCGv_i64 tcg_temp_new_i64(void) { - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_NORMAL); return temp_tcgv_i64(t); } static inline TCGv_i64 tcg_temp_local_new_i64(void) { - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_LOCAL); return temp_tcgv_i64(t); } @@ -918,13 +918,13 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, static inline TCGv_ptr tcg_temp_new_ptr(void) { - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_NORMAL); return temp_tcgv_ptr(t); } static inline TCGv_ptr tcg_temp_local_new_ptr(void) { - TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_LOCAL); return temp_tcgv_ptr(t); } diff --git a/tcg/tcg.c b/tcg/tcg.c index 612a12f58f..acdbd5a9a2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -942,14 +942,24 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, return ts; } -TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) +TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind) { TCGContext *s = tcg_ctx; - TCGTempKind kind = temp_local ? TEMP_LOCAL : TEMP_NORMAL; TCGTemp *ts; int idx, k; - k = type + (temp_local ? TCG_TYPE_COUNT : 0); + switch (kind) { + case TEMP_NORMAL: + k = 0; + break; + case TEMP_LOCAL: + k = TCG_TYPE_COUNT; + break; + default: + g_assert_not_reached(); + } + k += type; + idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS); if (idx < TCG_MAX_TEMPS) { /* There is already an available temp with the right type. */ @@ -1008,7 +1018,7 @@ TCGv_vec tcg_temp_new_vec(TCGType type) } #endif - t = tcg_temp_new_internal(type, 0); + t = tcg_temp_new_internal(type, TEMP_NORMAL); return temp_tcgv_vec(t); } @@ -1019,7 +1029,7 @@ TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) tcg_debug_assert(t->temp_allocated != 0); - t = tcg_temp_new_internal(t->base_type, 0); + t = tcg_temp_new_internal(t->base_type, TEMP_NORMAL); return temp_tcgv_vec(t); } From patchwork Thu Oct 6 03:44:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612892 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1213009pvb; Wed, 5 Oct 2022 21:16:26 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Qds3C4C/m2O/m1HGfecvUEXKtpFki/acWf/Az2yUYFltuWPTfZQBDeFkI2Yo4uzsRE+fS X-Received: by 2002:ac8:584a:0:b0:35c:bf11:9e42 with SMTP id h10-20020ac8584a000000b0035cbf119e42mr2034830qth.425.1665029786724; Wed, 05 Oct 2022 21:16:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029786; cv=none; d=google.com; s=arc-20160816; b=y9gqrbck+ws/+WwjAe5aZ0KF9sKmpPF9/et2xxNqo6oQoLk8I/zUApA7AxjdmFm6d9 pyjq54qGUx1zYpFK3cY//s78l0Uh4giKOr2JeHBvxnDSD14OQ8oJ7JyQGv8sI/Xu/Ths dVVwnmX9yaSBwnrsyXv5/Ec8ttfaC7nhZhJpy7QljDguvvZEHuPapOx17ydQTvLLKZkQ 9kHJzOq/9CEQFusOpa2ZwizyJSgTiUyzJQEJafwZDpcGC9Wu1BAaZ+kHXVlC0DDaZL7w TmN/vsZn2f9NakUGK6TQtPTI1Xvx3mW1C+Z0Zt7N4ssgIIBAWvc0CU3hE3bV4fOWoXC8 UYWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5D15v8p3bWjvQ/ElUGF1Bxd02HbXzPE0732wE/uoaww=; b=gepOyzh/hsDd9dexW0qaD0ygCrYaEIbpl3R7617OgnuTwnqLgWscQ1H/SnhC1QFbgE f+j0qfy8YgbjxwQnjTXq67swyZj5/CvVoUPCKZRdiS01vr1hlyfReZnIOfQ0St0M1DQZ eVAnj1tYDWSITpVX7DYzSXhhq8hoG1RQGsbsuCfP3YAQzsZxFJClvyJ3bFJOFXuMn5Al ztYSAkhOpx3TC4P59UVN3v8JABiT3McnPYryd5Omd406SJ0whHyuUmK1MwOduatlPqLF t4SC+BwQOu4DeWwgSZJqBH6Wyi4kREYorftrXLL58ons12h44AaHqmdG6atKB3Js5U6O sFXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CzW9ySwN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_* Date: Wed, 5 Oct 2022 20:44:19 -0700 Message-Id: <20221006034421.1179141-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow targets to allocate extended-basic-block temps. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- include/tcg/tcg-op.h | 2 ++ include/tcg/tcg.h | 20 +++++++++++++++++++- tcg/tcg.c | 16 ++++------------ 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 209e168305..0ebbee6e24 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -848,6 +848,7 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_temp_new() tcg_temp_new_i32() #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_local_new() tcg_temp_local_new_i32() +#define tcg_temp_ebb_new() tcg_temp_ebb_new_i32() #define tcg_temp_free tcg_temp_free_i32 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 @@ -855,6 +856,7 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_temp_new() tcg_temp_new_i64() #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_local_new() tcg_temp_local_new_i64() +#define tcg_temp_ebb_new() tcg_temp_ebb_new_i64() #define tcg_temp_free tcg_temp_free_i64 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e01a47ec20..3835711d52 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -609,7 +609,7 @@ struct TCGContext { #endif GHashTable *const_table[TCG_TYPE_COUNT]; - TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; + TCGTempSet free_temps[TCG_TYPE_COUNT * 3]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ QTAILQ_HEAD(, TCGOp) ops, free_ops; @@ -890,6 +890,12 @@ static inline TCGv_i32 tcg_temp_local_new_i32(void) return temp_tcgv_i32(t); } +static inline TCGv_i32 tcg_temp_ebb_new_i32(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB); + return temp_tcgv_i32(t); +} + static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, const char *name) { @@ -909,6 +915,12 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return temp_tcgv_i64(t); } +static inline TCGv_i64 tcg_temp_ebb_new_i64(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB); + return temp_tcgv_i64(t); +} + static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, const char *name) { @@ -928,6 +940,12 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(void) return temp_tcgv_ptr(t); } +static inline TCGv_ptr tcg_temp_ebb_new_ptr(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB); + return temp_tcgv_ptr(t); +} + #if defined(CONFIG_DEBUG_TCG) /* If you call tcg_clear_temp_count() at the start of a section of * code which is not supposed to leak any TCG temporaries, then diff --git a/tcg/tcg.c b/tcg/tcg.c index acdbd5a9a2..7aa6cc3451 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -948,17 +948,8 @@ TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind) TCGTemp *ts; int idx, k; - switch (kind) { - case TEMP_NORMAL: - k = 0; - break; - case TEMP_LOCAL: - k = TCG_TYPE_COUNT; - break; - default: - g_assert_not_reached(); - } - k += type; + assert(kind >= TEMP_NORMAL && kind <= TEMP_LOCAL); + k = TCG_TYPE_COUNT * kind + type; idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS); if (idx < TCG_MAX_TEMPS) { @@ -1046,6 +1037,7 @@ void tcg_temp_free_internal(TCGTemp *ts) */ return; case TEMP_NORMAL: + case TEMP_EBB: case TEMP_LOCAL: break; default: @@ -1063,7 +1055,7 @@ void tcg_temp_free_internal(TCGTemp *ts) ts->temp_allocated = 0; idx = temp_idx(ts); - k = ts->base_type + (ts->kind == TEMP_NORMAL ? 0 : TCG_TYPE_COUNT); + k = ts->base_type + ts->kind * TCG_TYPE_COUNT; set_bit(idx, s->free_temps[k].l); } From patchwork Thu Oct 6 03:44:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612889 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1211501pvb; Wed, 5 Oct 2022 21:12:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7HWmHgIjPrPV0BXrXlU17pKyNMOtC/Es12Du9xj8O5o8FzEgYe87dP2NYQJZ8mEQ5IF6Xf X-Received: by 2002:a05:620a:1593:b0:6e4:32f9:10e6 with SMTP id d19-20020a05620a159300b006e432f910e6mr1839396qkk.767.1665029557697; Wed, 05 Oct 2022 21:12:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665029557; cv=none; d=google.com; s=arc-20160816; b=lnlnNRgH419ZfECZnPQXchErXyeR/1cyQxjPGGWl0+bto2qtOzlx1A42y6uCsyTcHm p4Rvl8M0FqOrdMW8yT9Bw0GEb9us5G0K0DFP/mOu/zVQnAoKvfofAjZpFIsUWZFtsy4K tmF/+Sh1+juF7b+Hookn0AYfGJuUm3D7xmIYA7p3vWZYCDTA03QUYq71kIh3hfHTSs3n ZpitO9PgvxtyMykndL8CSZfmj2ZU1IznwkWLHLIZQyGNTCBJOYUdhr8ah0sPkIk14sRc LaqD3lsf+X/3NGMPwpPpV9Wo0moy1c/CxkHXoaQyZ+U8EN1uzVVfOgkCh9qwHpVq9eEN nUNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dymtBTjNDFvkVseJCTMJpwyHfk/v6x0F+7yT+M5DpeU=; b=eGys0Tnd8VSDUIrbxP59InuF8Zu/PKqXKG+hh3ZM+U+2l+47Q53ZxJqj0nGpW72XL7 TgTEXqwN9YSE4VVhUcLruj0jOMTDKKTwlWmGSDXfr1MKT3E8Uu7Dibdjti5p/ECjILNC GnQqk3/JdA3tQh9/WMj3LmxSWgvRLVbkI0A0k6VOp8WC0Uh4sHdnufPKyACnC/B6u1A/ DBD0VgromSjRtwaxx00ezOxCzTGTnVGhCfTovM2mq7ADRZgF/mgDVJ79o2bMbGODBQIB 0VO9XChYNh4/GInXA7JWt4jiCbYNG6wlJ0SGIjlvwgd2rHiRqX9T1C0xNulK8SZIhBbM K/Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oRn4GGuY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 25/26] tcg: Introduce tcg_temp_is_normal_* Date: Wed, 5 Oct 2022 20:44:20 -0700 Message-Id: <20221006034421.1179141-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow targets to determine if a given temp will die across a branch. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- include/tcg/tcg-op.h | 2 ++ include/tcg/tcg.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 0ebbee6e24..4b06895a32 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -850,6 +850,7 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_temp_local_new() tcg_temp_local_new_i32() #define tcg_temp_ebb_new() tcg_temp_ebb_new_i32() #define tcg_temp_free tcg_temp_free_i32 +#define tcg_temp_is_normal tcg_temp_is_normal_i32 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else @@ -858,6 +859,7 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_temp_local_new() tcg_temp_local_new_i64() #define tcg_temp_ebb_new() tcg_temp_ebb_new_i64() #define tcg_temp_free tcg_temp_free_i64 +#define tcg_temp_is_normal tcg_temp_is_normal_i64 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 #endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 3835711d52..0659c465da 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -871,6 +871,21 @@ static inline void tcg_temp_free_vec(TCGv_vec arg) tcg_temp_free_internal(tcgv_vec_temp(arg)); } +static inline bool tcg_temp_is_normal_i32(TCGv_i32 arg) +{ + return tcgv_i32_temp(arg)->kind == TEMP_NORMAL; +} + +static inline bool tcg_temp_is_normal_i64(TCGv_i64 arg) +{ + return tcgv_i64_temp(arg)->kind == TEMP_NORMAL; +} + +static inline bool tcg_temp_is_normal_ptr(TCGv_ptr arg) +{ + return tcgv_ptr_temp(arg)->kind == TEMP_NORMAL; +} + static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, const char *name) { From patchwork Thu Oct 6 03:44:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612899 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1215511pvb; Wed, 5 Oct 2022 21:23:49 -0700 (PDT) X-Google-Smtp-Source: AMsMyM505iir2ovlaB9o3lUsIeaTt7w8d2kBkdjjqdAHLGXh9PH7z1jHLewfv8yVP3uN0JF3EaiJ X-Received: by 2002:a05:622a:1316:b0:35b:b629:5247 with SMTP id v22-20020a05622a131600b0035bb6295247mr2077673qtk.275.1665030229796; Wed, 05 Oct 2022 21:23:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665030229; cv=none; d=google.com; s=arc-20160816; b=hu401DI5YG4E5YdHrDJW6zg08GKhsrpd+8AAHIACS4XcJ7GKBIZl7C1Ic8lToDRmZt wRiUjs2tkmMnsJbjW0D5UJMy2nhFwZC7sBOCAuNeVsxoTg6/Bc/AD8dlOTLqVX2ApV83 S98cxfUDjQawDkV09up5Jk8uIztCV8DrmK4kjJnSefxqPjsP9CyjtdXVblHJz31jNgX7 Eq2t/iamOPrnx9XSDuRPwei6CxDB/LAmdJQT+BFgqWOCcBjhLeyHyYaEvZpWoXAJx/mA B2Bri7kq7TCM0f9b250YdwP2xOuGWWOPnRy9a2Y+41Dsw/56HB5MOa/XJgSjg2c5ky30 5GNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1Q41KTfEeoa+dlW3TQe8h7vnXWIPJTTZEuUzFK2vahQ=; b=OagGwDjBYj88fX9T3Vzwg8yHGp/9Qxo6fLnI0gV669Rzj1QPdlOxQ2hVwQVSDCocAz QKq6+nUUc2/NHy9y65QhzlgH7tq/EIUnYeYl4+iZg1goH7dpDMFlks0x7ZCpX/qyIRtz TohqB+4VjYmUZ+vdTvvDkNWo0ils9Cs8VmQ+LB6OF6kv2gs2oV9XUeqiaEhaW/bufXCU H9/tr3edh8GSXfgj4QQ92s5Gv0mMnJLv20YxJUoxyZuXihMeItf1CmNYlqKx5UJK3eT5 kuy6IiudO1lYtico40KqWrHMqVGo3SF/ZqTyjYYVnNXEnVnC87hy9Low4LTIjeXydbfG RP/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MhYUUJay; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id y6-20020a17090ad0c600b00205f4f7a3b3sm1905086pjw.21.2022.10.05.20.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:44:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org Subject: [PATCH 26/26] target/s390x: Enable TARGET_TB_PCREL Date: Wed, 5 Oct 2022 20:44:21 -0700 Message-Id: <20221006034421.1179141-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006034421.1179141-1-richard.henderson@linaro.org> References: <20221006034421.1179141-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/s390x/cpu-param.h | 1 + target/s390x/cpu.c | 12 +++++ target/s390x/tcg/translate.c | 88 +++++++++++++++++++++++------------- 3 files changed, 69 insertions(+), 32 deletions(-) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index bf951a002e..467ecade8c 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -13,5 +13,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 #define NB_MMU_MODES 4 +#define TARGET_TB_PCREL 1 #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index df00040e95..e77849dd50 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -35,6 +35,7 @@ #include "fpu/softfloat-helpers.h" #include "disas/capstone.h" #include "sysemu/tcg.h" +#include "exec/exec-all.h" #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; @@ -81,6 +82,16 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) return r; } +static void s390_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + S390CPU *cpu = S390_CPU(cs); + cpu->env.psw.addr = tb_pc(tb); + } +} + static void s390_cpu_set_pc(CPUState *cs, vaddr value) { S390CPU *cpu = S390_CPU(cs); @@ -272,6 +283,7 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, + .synchronize_from_tb = s390_cpu_synchronize_from_tb, #ifdef CONFIG_USER_ONLY .record_sigsegv = s390_cpu_record_sigsegv, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index b27e34f712..c33dcc115d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -139,6 +139,7 @@ struct DisasContext { DisasContextBase base; const DisasInsn *insn; TCGOp *insn_start; + target_ulong pc_save; DisasFields fields; uint64_t ex_value; uint32_t ilen; @@ -163,29 +164,6 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif -static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) -{ - tcg_gen_movi_i64(dest, s->base.pc_next + disp); -} - -static void pc_to_link_info(TCGv_i64 out, DisasContext *s) -{ - TCGv_i64 tmp; - - if (s->base.tb->flags & FLAG_MASK_64) { - gen_psw_addr_disp(s, out, s->ilen); - return; - } - - tmp = tcg_temp_new_i64(); - gen_psw_addr_disp(s, tmp, s->ilen); - if (s->base.tb->flags & FLAG_MASK_32) { - tcg_gen_ori_i64(tmp, tmp, 0x80000000); - } - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); -} - static TCGv_i64 psw_addr; static TCGv_i64 psw_mask; static TCGv_i64 gbea; @@ -336,9 +314,39 @@ static void return_low128(TCGv_i64 dest) tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); } +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + assert(s->pc_save != -1); + if (TARGET_TB_PCREL) { + disp += s->base.pc_next - s->pc_save; + tcg_gen_addi_i64(dest, psw_addr, disp); + } else { + tcg_gen_movi_i64(dest, s->base.pc_next + disp); + } +} + +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) +{ + TCGv_i64 tmp; + + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; + } + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); + tcg_temp_free_i64(tmp); +} + static void update_psw_addr_disp(DisasContext *s, int64_t disp) { gen_psw_addr_disp(s, psw_addr, disp); + s->pc_save = s->base.pc_next + disp; } static inline bool per_enabled(DisasContext *s) @@ -1172,6 +1180,7 @@ static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); + s->pc_save = -1; per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } @@ -1181,6 +1190,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, { DisasJumpType ret; int64_t disp = (int64_t)imm * 2; + TCGv_i64 cdest_save = NULL; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1213,12 +1223,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, update_cc_op(s); /* - * Store taken branch destination before the brcond. This - * avoids having to allocate a new local temp to hold it. - * We'll overwrite this in the not taken case anyway. + * Save taken branch destination across the brcond if required. */ - if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); + if (!is_imm && tcg_temp_is_normal_i64(cdest)) { + cdest_save = tcg_temp_ebb_new_i64(); + tcg_gen_mov_i64(cdest_save, cdest); + cdest = cdest_save; } lab = gen_new_label(); @@ -1234,6 +1244,11 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, per_breaking_event(s); if (is_imm) { gen_psw_addr_disp(s, psw_addr, disp); + } else { + tcg_gen_mov_i64(psw_addr, cdest); + } + if (cdest_save) { + tcg_temp_free_i64(cdest_save); } per_branch_dest(s, psw_addr); @@ -1247,15 +1262,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, gen_set_label(lab); /* Branch not taken. */ + gen_psw_addr_disp(s, psw_addr, s->ilen); if (use_goto_tb(s, s->base.pc_next + s->ilen)) { tcg_gen_goto_tb(1); - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 1); } else { - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_lookup_and_goto_ptr(); } + s->pc_save = -1; ret = DISAS_NORETURN; egress: @@ -6443,6 +6458,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + dc->pc_save = dc->base.pc_first; dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value; @@ -6455,9 +6471,13 @@ static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_arg = dc->base.pc_next; + if (TARGET_TB_PCREL) { + pc_arg &= ~TARGET_PAGE_MASK; + } /* Delay the set of ilen until we've read the insn. */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); dc->insn_start = tcg_last_op(); } @@ -6548,7 +6568,11 @@ void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, { int cc_op = data[1]; - env->psw.addr = data[0]; + if (TARGET_TB_PCREL) { + env->psw.addr = (env->psw.addr & TARGET_PAGE_MASK) | data[0]; + } else { + env->psw.addr = data[0]; + } /* Update the CC opcode if it is not already up-to-date. */ if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {