From patchwork Fri Oct 7 13:20:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Milen Mitkov \(Consultant\)" X-Patchwork-Id: 613854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A33AC43217 for ; Fri, 7 Oct 2022 13:20:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229757AbiJGNUp (ORCPT ); Fri, 7 Oct 2022 09:20:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229505AbiJGNUn (ORCPT ); Fri, 7 Oct 2022 09:20:43 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EA8D77557; Fri, 7 Oct 2022 06:20:40 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 297CUkH8011996; Fri, 7 Oct 2022 13:20:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=VVBWLDJWzxKWEBoO3RFDtmyWDMLtDs6lN/0vE9sIJD4=; b=SsrHG0RSDmE/oEFxxj+kuvuOAwIy7tr7Q2P1qz4hvhR9Jov28pbDTFdr1OSvSNDTSMnf F2gBb6xsY+2x849LV+rP74S7Dpg74MRGTJtuubuYvL8/wuSH4miaksSoZiQnP68DFyBM H3KT1k99yfS4Yy2cVRKSUR4XVfrUqA7A3BaSd9oNinyEbGY+dNs5B1/AtTp97iOSifd6 S6XPHBWP0vfaCTaMHhAzWMpFzCINmVEAxLLnByIHhWCcsTR3VZPKdmVrbCMKr8dtVgGy f6BNUfYokDs1Ec5/tKTWZHxU6nZeIVNXKFsU42BSCyJ3GoI3LAmwb0bmUCvldf75ovUA HA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k1wnbk2ta-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Oct 2022 13:20:32 +0000 Received: from nasanex01a.na.qualcomm.com ([10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 297DKVJ6002224 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Oct 2022 13:20:31 GMT Received: from mmitkov.eu.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 7 Oct 2022 06:20:28 -0700 From: To: , , , , , CC: , , , , , , , , Milen Mitkov Subject: [PATCH v3 1/4] media: camss: sm8250: Virtual channels for CSID Date: Fri, 7 Oct 2022 16:20:06 +0300 Message-ID: <20221007132009.1886-2-quic_mmitkov@quicinc.com> X-Mailer: git-send-email 2.37.3.windows.1 In-Reply-To: <20221007132009.1886-1-quic_mmitkov@quicinc.com> References: <20221007132009.1886-1-quic_mmitkov@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: iQt5SXOpadGMp6kcGuamYP1EJk5VyT3B X-Proofpoint-ORIG-GUID: iQt5SXOpadGMp6kcGuamYP1EJk5VyT3B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-06_05,2022-10-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210070080 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Milen Mitkov CSID hardware on SM8250 can demux up to 4 simultaneous streams based on virtual channel (vc) or datatype (dt). The CSID subdevice entity now has 4 source ports that can be enabled/disabled and thus can control which virtual channels are enabled. Datatype demuxing not tested. In order to keep a valid internal state of the subdevice, implicit format propagation from the sink to the source pads has been preserved. However, the format on each source pad can be different and in that case it must be configured explicitly. CSID's s_stream is called when any stream is started or stopped. It will call configure_streams() that will rewrite IRQ settings to HW. When multiple streams are running simultaneously there is an issue when writing IRQ settings for one stream while another is still running, thus avoid re-writing settings if they were not changed in link setup, or by fully powering off the CSID hardware. Signed-off-by: Milen Mitkov Reviewed-by: Robert Foss --- .../platform/qcom/camss/camss-csid-gen2.c | 54 ++++++++++++------- .../media/platform/qcom/camss/camss-csid.c | 44 ++++++++++----- .../media/platform/qcom/camss/camss-csid.h | 11 +++- 3 files changed, 74 insertions(+), 35 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c index 2031bde13a93..0f8ac29d038d 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -334,13 +334,14 @@ static const struct csid_format csid_formats[] = { }, }; -static void csid_configure_stream(struct csid_device *csid, u8 enable) +static void __csid_configure_stream(struct csid_device *csid, u8 enable, u8 vc) { struct csid_testgen_config *tg = &csid->testgen; u32 val; u32 phy_sel = 0; u8 lane_cnt = csid->phy.lane_cnt; - struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_SRC]; + /* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */ + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc]; const struct csid_format *format = csid_get_fmt_entry(csid->formats, csid->nformats, input_format->code); @@ -351,8 +352,7 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) phy_sel = csid->phy.csiphy_id; if (enable) { - u8 vc = 0; /* Virtual Channel 0 */ - u8 dt_id = vc * 4; + u8 dt_id = vc; if (tg->enabled) { /* Config Test Generator */ @@ -395,42 +395,42 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) val |= format->data_type << RDI_CFG0_DATA_TYPE; val |= vc << RDI_CFG0_VIRTUAL_CHANNEL; val |= dt_id << RDI_CFG0_DT_ID; - writel_relaxed(val, csid->base + CSID_RDI_CFG0(0)); + writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc)); /* CSID_TIMESTAMP_STB_POST_IRQ */ val = 2 << RDI_CFG1_TIMESTAMP_STB_SEL; - writel_relaxed(val, csid->base + CSID_RDI_CFG1(0)); + writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc)); val = 1; - writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(0)); + writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc)); val = 0; - writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(0)); + writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc)); val = 1; - writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(0)); + writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc)); val = 0; - writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(0)); + writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc)); val = 1; - writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(0)); + writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc)); val = 0; - writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(0)); + writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc)); val = 1; - writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(0)); + writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc)); val = 0; - writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(0)); + writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc)); val = 0; - writel_relaxed(val, csid->base + CSID_RDI_CTRL(0)); + writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc)); - val = readl_relaxed(csid->base + CSID_RDI_CFG0(0)); + val = readl_relaxed(csid->base + CSID_RDI_CFG0(vc)); val |= 1 << RDI_CFG0_ENABLE; - writel_relaxed(val, csid->base + CSID_RDI_CFG0(0)); + writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc)); } if (tg->enabled) { @@ -456,7 +456,16 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) val = HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD; else val = HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD; - writel_relaxed(val, csid->base + CSID_RDI_CTRL(0)); + writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i; + /* Loop through all enabled VCs and configure stream for each */ + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) + if (csid->phy.en_vc & BIT(i)) + __csid_configure_stream(csid, enable, i); } static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) @@ -502,6 +511,7 @@ static irqreturn_t csid_isr(int irq, void *dev) struct csid_device *csid = dev; u32 val; u8 reset_done; + int i; val = readl_relaxed(csid->base + CSID_TOP_IRQ_STATUS); writel_relaxed(val, csid->base + CSID_TOP_IRQ_CLEAR); @@ -510,8 +520,12 @@ static irqreturn_t csid_isr(int irq, void *dev) val = readl_relaxed(csid->base + CSID_CSI2_RX_IRQ_STATUS); writel_relaxed(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR); - val = readl_relaxed(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(0)); - writel_relaxed(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(0)); + /* Read and clear IRQ status for each enabled RDI channel */ + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) + if (csid->phy.en_vc & BIT(i)) { + val = readl_relaxed(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel_relaxed(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + } val = 1 << IRQ_CMD_CLEAR; writel_relaxed(val, csid->base + CSID_IRQ_CMD); diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 88f188e0f750..20c22564e0f9 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -209,6 +209,8 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) } csid->ops->hw_version(csid); + + csid->phy.need_vc_update = true; } else { disable_irq(csid->irq); camss_disable_clocks(csid->nclocks, csid->clock); @@ -249,7 +251,10 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable) return -ENOLINK; } - csid->ops->configure_stream(csid, enable); + if (csid->phy.need_vc_update) { + csid->ops->configure_stream(csid, enable); + csid->phy.need_vc_update = false; + } return 0; } @@ -460,6 +465,7 @@ static int csid_set_format(struct v4l2_subdev *sd, { struct csid_device *csid = v4l2_get_subdevdata(sd); struct v4l2_mbus_framefmt *format; + int i; format = __csid_get_format(csid, sd_state, fmt->pad, fmt->which); if (format == NULL) @@ -468,14 +474,14 @@ static int csid_set_format(struct v4l2_subdev *sd, csid_try_format(csid, sd_state, fmt->pad, &fmt->format, fmt->which); *format = fmt->format; - /* Propagate the format from sink to source */ + /* Propagate the format from sink to source pads */ if (fmt->pad == MSM_CSID_PAD_SINK) { - format = __csid_get_format(csid, sd_state, MSM_CSID_PAD_SRC, - fmt->which); + for (i = MSM_CSID_PAD_FIRST_SRC; i < MSM_CSID_PADS_NUM; ++i) { + format = __csid_get_format(csid, sd_state, i, fmt->which); - *format = fmt->format; - csid_try_format(csid, sd_state, MSM_CSID_PAD_SRC, format, - fmt->which); + *format = fmt->format; + csid_try_format(csid, sd_state, i, format, fmt->which); + } } return 0; @@ -738,7 +744,6 @@ static int csid_link_setup(struct media_entity *entity, struct csid_device *csid; struct csiphy_device *csiphy; struct csiphy_lanes_cfg *lane_cfg; - struct v4l2_subdev_format format = { 0 }; sd = media_entity_to_v4l2_subdev(entity); csid = v4l2_get_subdevdata(sd); @@ -761,11 +766,22 @@ static int csid_link_setup(struct media_entity *entity, lane_cfg = &csiphy->cfg.csi2->lane_cfg; csid->phy.lane_cnt = lane_cfg->num_data; csid->phy.lane_assign = csid_get_lane_assign(lane_cfg); + } + /* Decide which virtual channels to enable based on which source pads are enabled */ + if (local->flags & MEDIA_PAD_FL_SOURCE) { + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct csid_device *csid = v4l2_get_subdevdata(sd); + struct device *dev = csid->camss->dev; + + if (flags & MEDIA_LNK_FL_ENABLED) + csid->phy.en_vc |= BIT(local->index - 1); + else + csid->phy.en_vc &= ~BIT(local->index - 1); - /* Reset format on source pad to sink pad format */ - format.pad = MSM_CSID_PAD_SRC; - format.which = V4L2_SUBDEV_FORMAT_ACTIVE; - csid_set_format(&csid->subdev, NULL, &format); + csid->phy.need_vc_update = true; + + dev_dbg(dev, "%s: Enabled CSID virtual channels mask 0x%x\n", + __func__, csid->phy.en_vc); } return 0; @@ -816,6 +832,7 @@ int msm_csid_register_entity(struct csid_device *csid, struct v4l2_subdev *sd = &csid->subdev; struct media_pad *pads = csid->pads; struct device *dev = csid->camss->dev; + int i; int ret; v4l2_subdev_init(sd, &csid_v4l2_ops); @@ -852,7 +869,8 @@ int msm_csid_register_entity(struct csid_device *csid, } pads[MSM_CSID_PAD_SINK].flags = MEDIA_PAD_FL_SINK; - pads[MSM_CSID_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; + for (i = MSM_CSID_PAD_FIRST_SRC; i < MSM_CSID_PADS_NUM; ++i) + pads[i].flags = MEDIA_PAD_FL_SOURCE; sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; sd->entity.ops = &csid_media_ops; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index f06040e44c51..d4b48432a097 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -19,8 +19,13 @@ #include #define MSM_CSID_PAD_SINK 0 -#define MSM_CSID_PAD_SRC 1 -#define MSM_CSID_PADS_NUM 2 +#define MSM_CSID_PAD_FIRST_SRC 1 +#define MSM_CSID_PADS_NUM 5 + +#define MSM_CSID_PAD_SRC (MSM_CSID_PAD_FIRST_SRC) + +/* CSID hardware can demultiplex up to 4 outputs */ +#define MSM_CSID_MAX_SRC_STREAMS 4 #define DATA_TYPE_EMBEDDED_DATA_8BIT 0x12 #define DATA_TYPE_YUV420_8BIT 0x18 @@ -81,6 +86,8 @@ struct csid_phy_config { u8 csiphy_id; u8 lane_cnt; u32 lane_assign; + u32 en_vc; + u8 need_vc_update; }; struct csid_device; From patchwork Fri Oct 7 13:20:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Milen Mitkov \(Consultant\)" X-Patchwork-Id: 613203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A8F4C433FE for ; Fri, 7 Oct 2022 13:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229658AbiJGNUj (ORCPT ); Fri, 7 Oct 2022 09:20:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229527AbiJGNUi (ORCPT ); Fri, 7 Oct 2022 09:20:38 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A59276745; Fri, 7 Oct 2022 06:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1665148837; x=1696684837; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LzJ5AnU8KIaIpzYDWipeQelOn0D6aKSXwsxm4gvi9Vk=; b=Q3loK3foTfqySULeCTvgl81ySxxUlPPKrW4V60GX4sJivx/aR0/VyvyM 6z33iD6yeSUM2fRNMc2ib9QTagUt7+tlRJKl4AJh9KUbqYzXB2ayV4+eW WlSnt9czXoKsfG3gqIhIVDJwcG5/o0QP9JR/jFXcGviDuZy0YjsHwrShr s=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 07 Oct 2022 06:20:36 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2022 06:20:36 -0700 Received: from mmitkov.eu.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 7 Oct 2022 06:20:31 -0700 From: To: , , , , , CC: , , , , , , , , Milen Mitkov Subject: [PATCH v3 2/4] media: camss: vfe: Reserve VFE lines on stream start and link to CSID Date: Fri, 7 Oct 2022 16:20:07 +0300 Message-ID: <20221007132009.1886-3-quic_mmitkov@quicinc.com> X-Mailer: git-send-email 2.37.3.windows.1 In-Reply-To: <20221007132009.1886-1-quic_mmitkov@quicinc.com> References: <20221007132009.1886-1-quic_mmitkov@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Milen Mitkov For multiple virtual channels support, each VFE line can be in either ON, RESERVED or OFF states. This allows the starting and stopping of a VFE line independently of other active VFE lines. Also, link the CSID entity's source ports to corresponding VFE lines. Signed-off-by: Milen Mitkov Reviewed-by: Robert Foss --- drivers/media/platform/qcom/camss/camss-vfe.c | 7 +++++++ drivers/media/platform/qcom/camss/camss.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index a26e4a5d87b6..cd8ac0478cf1 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -738,8 +738,10 @@ static int vfe_set_stream(struct v4l2_subdev *sd, int enable) struct vfe_line *line = v4l2_get_subdevdata(sd); struct vfe_device *vfe = to_vfe(line); int ret; + int i; if (enable) { + line->output.state = VFE_OUTPUT_RESERVED; ret = vfe->ops->vfe_enable(line); if (ret < 0) dev_err(vfe->camss->dev, @@ -749,6 +751,11 @@ static int vfe_set_stream(struct v4l2_subdev *sd, int enable) if (ret < 0) dev_err(vfe->camss->dev, "Failed to disable vfe outputs\n"); + + /* At least one VFE line remains, return -EBUSY to avoid premature pipeline stop */ + for (i = 0; i < vfe->line_num; i++) + if (vfe->line[i].output.state != VFE_OUTPUT_OFF) + return -EBUSY; } return ret; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 1118c40886d5..63653ac3e056 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1320,7 +1320,7 @@ static int camss_register_entities(struct camss *camss) struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; ret = media_create_pad_link(&csid->entity, - MSM_CSID_PAD_SRC, + MSM_CSID_PAD_FIRST_SRC + j, &vfe->entity, MSM_VFE_PAD_SINK, 0); From patchwork Fri Oct 7 13:20:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Milen Mitkov \(Consultant\)" X-Patchwork-Id: 613853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2EBBC433FE for ; Fri, 7 Oct 2022 13:20:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229721AbiJGNUu (ORCPT ); Fri, 7 Oct 2022 09:20:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229694AbiJGNUs (ORCPT ); Fri, 7 Oct 2022 09:20:48 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CCFF89CF5; Fri, 7 Oct 2022 06:20:47 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 297CwRJu021302; Fri, 7 Oct 2022 13:20:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=1E+1dDXbic24VF9Ysyx+Na68vnd9vt3s3vZwkyjb2hQ=; b=ZBnxyyNvtRI0MEloTpIISffIhq8AOGP49Y3FQL5T5F2B6XkF+31zMFSc7QWOYYe49Jbq d/tNZUfYZi/v21qubwi8Lfl3JOtN8ZcJ7QTXxMoA2sOOm7qaBWkrhn3duiBMivqlhw2j 7KlUZDPKVpvs7Wi3yxO+3USFPnYEb2nZY8zqgmu4cHOO/9hRq+Si6pubZnC0HKCNhBOU 1Noz4LFueF+YDCgA2veQKSxWdegqCjXCYrxQV0kYT4ixLoivB/mwA1GSFSNnEQlYL4PC f1wHCt/2fFz/Ke8ZeMb+GYWhPI3dCjoizB++5lelTo6EsD++3qZmfiVpd48lCnNU3sGv cA== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k2206j8tx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Oct 2022 13:20:40 +0000 Received: from nasanex01a.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 297DKeTf016999 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Oct 2022 13:20:40 GMT Received: from mmitkov.eu.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 7 Oct 2022 06:20:36 -0700 From: To: , , , , , CC: , , , , , , , , Milen Mitkov Subject: [PATCH v3 3/4] media: camss: vfe-480: Multiple outputs support for SM8250 Date: Fri, 7 Oct 2022 16:20:08 +0300 Message-ID: <20221007132009.1886-4-quic_mmitkov@quicinc.com> X-Mailer: git-send-email 2.37.3.windows.1 In-Reply-To: <20221007132009.1886-1-quic_mmitkov@quicinc.com> References: <20221007132009.1886-1-quic_mmitkov@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 664Nzd6Ya1pg3xrTkdhDoLuK9zBV49CL X-Proofpoint-ORIG-GUID: 664Nzd6Ya1pg3xrTkdhDoLuK9zBV49CL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-06_05,2022-10-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 phishscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210070080 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Milen Mitkov On SM8250 each VFE supports at least 3 RDI channels, or 4 in case of VFE-Lite, so add appropriate IRQ setup and handling. Signed-off-by: Milen Mitkov Reviewed-by: Robert Foss --- .../media/platform/qcom/camss/camss-vfe-480.c | 61 ++++++++++++------- 1 file changed, 40 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-480.c b/drivers/media/platform/qcom/camss/camss-vfe-480.c index 129585110393..537dede334be 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-480.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-480.c @@ -94,6 +94,8 @@ static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) #define RDI_WM(n) ((IS_LITE ? 0 : 23) + (n)) #define RDI_COMP_GROUP(n) ((IS_LITE ? 0 : 11) + (n)) +#define MAX_VFE_OUTPUT_LINES 4 + static u32 vfe_hw_version(struct vfe_device *vfe) { u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION); @@ -171,12 +173,26 @@ static inline void vfe_reg_update_clear(struct vfe_device *vfe, static void vfe_enable_irq_common(struct vfe_device *vfe) { - /* enable only the IRQs used: rup and comp_done irqs for RDI0 */ + /* enable reset ack IRQ and top BUS status IRQ */ writel_relaxed(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ, vfe->base + VFE_IRQ_MASK(0)); - writel_relaxed(BUS_IRQ_MASK_0_RDI_RUP(vfe, 0) | - BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(0)), - vfe->base + VFE_BUS_IRQ_MASK(0)); +} + +static void vfe_enable_lines_irq(struct vfe_device *vfe) +{ + u32 bus_irq_mask; + int i; + + for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) { + /* Enable IRQ for newly added lines, but also keep already running lines's IRQ */ + if (vfe->line[i].output.state == VFE_OUTPUT_RESERVED || + vfe->line[i].output.state == VFE_OUTPUT_ON) { + bus_irq_mask |= BUS_IRQ_MASK_0_RDI_RUP(vfe, i) + | BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i)); + } + } + + writel_relaxed(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0)); } static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id); @@ -193,6 +209,7 @@ static irqreturn_t vfe_isr(int irq, void *dev) { struct vfe_device *vfe = dev; u32 status; + int i; status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0)); writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0)); @@ -207,11 +224,14 @@ static irqreturn_t vfe_isr(int irq, void *dev) writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0)); writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL); - if (status & BUS_IRQ_MASK_0_RDI_RUP(vfe, 0)) - vfe_isr_reg_update(vfe, 0); + /* Loop through all WMs IRQs */ + for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) { + if (status & BUS_IRQ_MASK_0_RDI_RUP(vfe, i)) + vfe_isr_reg_update(vfe, i); - if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(0))) - vfe_isr_wm_done(vfe, 0); + if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i))) + vfe_isr_wm_done(vfe, i); + } } return IRQ_HANDLED; @@ -234,24 +254,23 @@ static int vfe_get_output(struct vfe_line *line) struct vfe_device *vfe = to_vfe(line); struct vfe_output *output; unsigned long flags; - int wm_idx; spin_lock_irqsave(&vfe->output_lock, flags); output = &line->output; - if (output->state != VFE_OUTPUT_OFF) { + if (output->state > VFE_OUTPUT_RESERVED) { dev_err(vfe->camss->dev, "Output is running\n"); goto error; } output->wm_num = 1; - wm_idx = vfe_reserve_wm(vfe, line->id); - if (wm_idx < 0) { - dev_err(vfe->camss->dev, "Can not reserve wm\n"); - goto error_get_wm; - } - output->wm_idx[0] = wm_idx; + /* Correspondence between VFE line number and WM number. + * line 0 -> RDI 0, line 1 -> RDI1, line 2 -> RDI2, line 3 -> PIX/RDI3 + * Note this 1:1 mapping will not work for PIX streams. + */ + output->wm_idx[0] = line->id; + vfe->wm_output_map[line->id] = line->id; output->drop_update_idx = 0; @@ -259,11 +278,9 @@ static int vfe_get_output(struct vfe_line *line) return 0; -error_get_wm: - vfe_release_wm(vfe, output->wm_idx[0]); - output->state = VFE_OUTPUT_OFF; error: spin_unlock_irqrestore(&vfe->output_lock, flags); + output->state = VFE_OUTPUT_OFF; return -EINVAL; } @@ -279,7 +296,7 @@ static int vfe_enable_output(struct vfe_line *line) vfe_reg_update_clear(vfe, line->id); - if (output->state != VFE_OUTPUT_OFF) { + if (output->state > VFE_OUTPUT_RESERVED) { dev_err(vfe->camss->dev, "Output is not in reserved state %d\n", output->state); spin_unlock_irqrestore(&vfe->output_lock, flags); @@ -360,6 +377,8 @@ static int vfe_enable(struct vfe_line *line) vfe->stream_count++; + vfe_enable_lines_irq(vfe); + mutex_unlock(&vfe->stream_lock); ret = vfe_get_output(line); @@ -548,7 +567,7 @@ static const struct camss_video_ops vfe_video_ops_480 = { static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) { vfe->video_ops = vfe_video_ops_480; - vfe->line_num = 1; + vfe->line_num = MAX_VFE_OUTPUT_LINES; } const struct vfe_hw_ops vfe_ops_480 = { From patchwork Fri Oct 7 13:20:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Milen Mitkov \(Consultant\)" X-Patchwork-Id: 613201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B0F4C433FE for ; Fri, 7 Oct 2022 13:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229816AbiJGNUz (ORCPT ); Fri, 7 Oct 2022 09:20:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229710AbiJGNUv (ORCPT ); Fri, 7 Oct 2022 09:20:51 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 714FC89CF5; Fri, 7 Oct 2022 06:20:50 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 297BWf7l020691; Fri, 7 Oct 2022 13:20:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=GrTtXyw3LwMpYy+O6xjoKOXG8mtQt9xYXSfxY5dD+M4=; b=c6dcABtoKdEfjDoMGlssFzdrxtCybtcOsUavrJCsIXjSu9qhZG6xso9LkAdQdXMRV0mm K5EkNDoFFC8IpAYYhPUEa8wg7RYgst3IxhV9NOMTad2KB+N4ykoP44CqCBEfHDENZ6Cs lj079px9jgEPHhFjvRb/xXOZT6OypUCOvU7Ntu1ksWkY/cDauWlIxFbGu/Jz0WFOC8Tk KA4Ykkg4Zrh3zy1TO7pQjQBpT0k2Qe8WJlPvGQvmb8YylJH4gU8mG766ub37kYvWELMx CppDiQ8AoaZMdV1Jx5QZ730T0xB7R9NYcfh/Rbchr5Oc1BxRuSq83T+7G/GcZnorgOw2 QA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k295e99ac-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Oct 2022 13:20:44 +0000 Received: from nasanex01a.na.qualcomm.com ([10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 297DKiaS002292 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Oct 2022 13:20:44 GMT Received: from mmitkov.eu.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 7 Oct 2022 06:20:40 -0700 From: To: , , , , , CC: , , , , , , , , Milen Mitkov Subject: [PATCH v3 4/4] media: camss: sm8250: Pipeline starting and stopping for multiple virtual channels Date: Fri, 7 Oct 2022 16:20:09 +0300 Message-ID: <20221007132009.1886-5-quic_mmitkov@quicinc.com> X-Mailer: git-send-email 2.37.3.windows.1 In-Reply-To: <20221007132009.1886-1-quic_mmitkov@quicinc.com> References: <20221007132009.1886-1-quic_mmitkov@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: RgVzmC03SAbXBcfmB7IoK2VjbpUUuj6G X-Proofpoint-GUID: RgVzmC03SAbXBcfmB7IoK2VjbpUUuj6G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-06_05,2022-10-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 mlxlogscore=776 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210070080 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Milen Mitkov Use the multistream series function video_device_pipeline_alloc_start to allows multiple clients of the same pipeline. If any of the entities in the pipeline doesn't return success at stop (e.g. if a VFE line remains running), the full pipeline won't be stopped. This allows for stopping and starting streams at any point without disrupting the other running streams. Signed-off-by: Milen Mitkov Reviewed-by: Robert Foss --- .../media/platform/qcom/camss/camss-video.c | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c index 81fb3a5bc1d5..b042faf3dcda 100644 --- a/drivers/media/platform/qcom/camss/camss-video.c +++ b/drivers/media/platform/qcom/camss/camss-video.c @@ -353,6 +353,7 @@ static int video_get_subdev_format(struct camss_video *video, fmt.pad = pad; fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + fmt.stream = 0; ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); if (ret) @@ -493,9 +494,11 @@ static int video_start_streaming(struct vb2_queue *q, unsigned int count) struct v4l2_subdev *subdev; int ret; - ret = video_device_pipeline_start(vdev, &video->pipe); - if (ret < 0) + ret = video_device_pipeline_alloc_start(vdev); + if (ret < 0) { + dev_err(video->camss->dev, "Failed to start media pipeline: %d\n", ret); return ret; + } ret = video_check_format(video); if (ret < 0) @@ -536,6 +539,7 @@ static void video_stop_streaming(struct vb2_queue *q) struct media_entity *entity; struct media_pad *pad; struct v4l2_subdev *subdev; + int ret; entity = &vdev->entity; while (1) { @@ -550,7 +554,18 @@ static void video_stop_streaming(struct vb2_queue *q) entity = pad->entity; subdev = media_entity_to_v4l2_subdev(entity); - v4l2_subdev_call(subdev, video, s_stream, 0); + ret = v4l2_subdev_call(subdev, video, s_stream, 0); + + if (ret == -EBUSY) { + /* Don't stop if other instances of the pipeline are still running */ + dev_dbg(video->camss->dev, "Video pipeline still used, don't stop streaming.\n"); + return; + } + + if (ret) { + dev_err(video->camss->dev, "Video pipeline stop failed: %d\n", ret); + return; + } } video_device_pipeline_stop(vdev);