From patchwork Wed Feb 27 01:05:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159246 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851451jad; Tue, 26 Feb 2019 17:06:04 -0800 (PST) X-Google-Smtp-Source: AHgI3IYledEhdkCAvYdXtpJXHjh0ZqlalJGR7sUEGPUh5uwwggQUSsYwWHyS2w78ehsGQr4SJXJO X-Received: by 2002:a62:1d0e:: with SMTP id d14mr13096801pfd.73.1551229564531; Tue, 26 Feb 2019 17:06:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229564; cv=none; d=google.com; s=arc-20160816; b=aU0v4McDh9K6Xoz5o0uf0fWh03LjNFune3GXExcJv/VG93prwFbVpoH2RM7Ug+7iMK /TCdO+lfCVKESBf9sezSa73C1f/YTaJa5wXDwJ2mqLIfnExRvLUIE2sPFM/fTa6LU9n0 Ai5co9O9IYbZBzU7eM4FqufFLwU19aB2H6Vbq55m2ONVOe1nY+ks3Bv3ELxXwhGPoFvh NsmpZh2snnFUii9vyenhQPAs4X1tFVwMyq3n2a+K6iZIBIiUZaom4OhXYiBv7RmQVEA2 drXlWnC5Ku/YPQ4O1qrC99+fSKANfD0vTPTl2g5sPtlFhHa33hbENDCoLx3wzHSJgiLf mX0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=YNiAxIrEGkGHKVWYMjOqFSPhmIBPv9WfOXl4w9iSBpQ=; b=IM8VDZs5zb4iq0dj9Pa1d/0nBM96s7UEcaQjD4KWPcrOmd7C54h4sCvmyqSYpIasyz e5ba0B++WiVry9Qjg3Nxx1xwHJxwdbfPRioUImFQQ5byNR5UPRzHvyKZdGFJ7kqZ9YcD fFFa6ur47l1BR53sTMOZLx4RV3WzgBL3+XClMkqxFKdOsQ+mFD+2UK/YQWUFZQ14J7rO kDf3PW9IP8TQLY3JDaAx5bk5nSgXZSnYMM1HVGO1W+Aws4KpifxHxGIk6EBNXYwW/zNs 0KmCAF3mi7CfxUl/MGlIIAOgG/diXhVt/c9C7xHDsfUwB/S0yNHYXOPS3DGhGbj1S4n8 ab5w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j9si1344694pgq.317.2019.02.26.17.06.04; Tue, 26 Feb 2019 17:06:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729510AbfB0BGC (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:02 -0500 Received: from foss.arm.com ([217.140.101.70]:55586 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729446AbfB0BGC (ORCPT ); Tue, 26 Feb 2019 20:06:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 87320EBD; Tue, 26 Feb 2019 17:06:01 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D660B3F5C1; Tue, 26 Feb 2019 17:06:00 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton , Jonathan Corbet , linux-doc@vger.kernel.org Subject: [PATCH v5 01/10] arm64: Provide a command line to disable spectre_v2 mitigation Date: Tue, 26 Feb 2019 19:05:35 -0600 Message-Id: <20190227010544.597579-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are various reasons, including bencmarking, to disable spectrev2 mitigation on a machine. Provide a command-line to do so. Signed-off-by: Jeremy Linton Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org --- Documentation/admin-guide/kernel-parameters.txt | 8 ++++---- arch/arm64/kernel/cpu_errata.c | 13 +++++++++++++ 2 files changed, 17 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Suzuki K Poulose Reviewed-by: Andre Przywara diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 858b6c0b9a15..4d4d6a9537ae 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2842,10 +2842,10 @@ check bypass). With this option data leaks are possible in the system. - nospectre_v2 [X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2 - (indirect branch prediction) vulnerability. System may - allow data leaks with this option, which is equivalent - to spectre_v2=off. + nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for + the Spectre variant 2 (indirect branch prediction) + vulnerability. System may allow data leaks with this + option. nospec_store_bypass_disable [HW] Disable all mitigations for the Speculative Store Bypass vulnerability diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 9950bb0cbd52..d2b2c69d31bb 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -220,6 +220,14 @@ static void qcom_link_stack_sanitization(void) : "=&r" (tmp)); } +static bool __nospectre_v2; +static int __init parse_nospectre_v2(char *str) +{ + __nospectre_v2 = true; + return 0; +} +early_param("nospectre_v2", parse_nospectre_v2); + static void enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) { @@ -231,6 +239,11 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) if (!entry->matches(entry, SCOPE_LOCAL_CPU)) return; + if (__nospectre_v2) { + pr_info_once("spectrev2 mitigation disabled by command line option\n"); + return; + } + if (psci_ops.smccc_version == SMCCC_VERSION_1_0) return; From patchwork Wed Feb 27 01:05:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159247 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851501jad; Tue, 26 Feb 2019 17:06:07 -0800 (PST) X-Google-Smtp-Source: AHgI3IZUH1pR3+uUKhOkz9qHU2i/eHTC8ZG0tiHqw8EA3g+XcZ4g8WBjAMjFSdFzGN5eiJGVzc9/ X-Received: by 2002:a63:d70a:: with SMTP id d10mr322136pgg.286.1551229567357; Tue, 26 Feb 2019 17:06:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229567; cv=none; d=google.com; s=arc-20160816; b=R+NYg0JBEyJS8t6GZCo5ItZFc2JidfuseRdEWH5pD95emsxWsaDcKf7b5gldQnOZqj UBMaTDBhZPqnn8Tbnfa4JX3fNpqn6OARg4HhHHu2aNfntAVk0FKFvSOkOeyQIcvHjCYY fE7lKKF47W62oK4YoJHD9rMA0w1G6QOEMAILXtwjVzVlRKjs1xdg/Eecf5Q5fC9tT5AU 5DfOejw9RWdV1+0JipHJwLBPuKKh6p/0ZOZ8wLxeHRiDhUPZMd5MZ3+E9ow8QfCrcTaQ qQVjNUbpIrXAtVdXj0SKORIG3mq9aNE928OMdWGOEL1yyjkAdNPZHfgMszEJh1pK3DTZ E8YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=z+wqWVaVf19XwPrsAbS9T1Y+l/CVn/R028F7RLLoYgQ=; b=ujImoo3nwQzquu+RYdU9Pidiihp17lUN6UKMVNGzuw8q4iWxWzcLvTGAmAHaTClGHy ae55Ojx0o2aNhpR5nGvUONEMD+eRlrWwJhxgOmV1Vf9EHfKRxuPONBIYNEwOaQdMGUiW m/hG6mFgckyto+SO8eLZfqs58cXuiqg2mDAnAbTMYIV14BcTGp5OPSjcrmrU+vgzC6lp FLwsoBfrXO/KM0k6Zbv/P4mafFDkgJolrqWpGO9Jx5OTv8PjHTMn6lF7JVY/BgsQdnxl 6h7Y4CHIj68N8YvI4P2l3xTco1HC+LnWeBWLm7Zw6nLf9tNy9Q+EkNUGNlP+i55pVyiH UJAA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j9si1344694pgq.317.2019.02.26.17.06.07; Tue, 26 Feb 2019 17:06:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729538AbfB0BGG (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:06 -0500 Received: from foss.arm.com ([217.140.101.70]:55600 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729446AbfB0BGD (ORCPT ); Tue, 26 Feb 2019 20:06:03 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 020EA169E; Tue, 26 Feb 2019 17:06:03 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 51C823F5C1; Tue, 26 Feb 2019 17:06:02 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Mian Yousaf Kaukab , Jeremy Linton Subject: [PATCH v5 02/10] arm64: add sysfs vulnerability show for spectre v1 Date: Tue, 26 Feb 2019 19:05:36 -0600 Message-Id: <20190227010544.597579-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mian Yousaf Kaukab spectre v1, has been mitigated, and the mitigation is always active. Signed-off-by: Mian Yousaf Kaukab Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.20.1 Acked-by: Suzuki K Poulose Reviewed-by: Andre Przywara diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index d2b2c69d31bb..ad58958becb6 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -755,3 +755,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { { } }; + +ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "Mitigation: __user pointer sanitization\n"); +} From patchwork Wed Feb 27 01:05:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159248 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851540jad; Tue, 26 Feb 2019 17:06:10 -0800 (PST) X-Google-Smtp-Source: AHgI3IbdBQTqO1ZegVio1dyqR7ltjHo2qzRA2QDRy7uvZ27t8RAhWLx+zXw1CO6QrKxOvlKwvTnm X-Received: by 2002:aa7:90c7:: with SMTP id k7mr28396418pfk.186.1551229570905; Tue, 26 Feb 2019 17:06:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229570; cv=none; d=google.com; s=arc-20160816; b=nOJwcocalrm5ESf37vk0DBOvfc1JEm+8a8osD6NSO01DpgKLr9I1iVOnjKk4xsNnV8 D4boDGTWxMCzPrMu3YznCihyqzQDM+CVmRqEVjTrvCs9Own9ye8NVQEu6nDk12Rw02oh bkSI6BLYNQLYkHF8ZWsEyRAoaWccFkP0zdNKgBwOOVG5aEb+ZAKt4+/M3+HpuhxVoUeZ /YkK/+dUFVPe2HE9lBGdMbyadD3K8DbDlfF9cqnUxFoUsiq3Ubo8kPOkWR4pHJ5uGALP mOJFV7xtTqoMzm06sb8msvQm/xM8HKR6SXuH59KdiDW8dcL7KrgUXMKvnFNUhtCPbMZA 2ztg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=z1r/QKrHcBwjhXMYGdKplJx/Olghvnm/44qxeFA5sCo=; b=G7ESMezLPIS2vX4hbXrHv/oUVkaHqglia83YBALJrBTs4cI5krgJ8eKj3LH/jZf3KM xhcy7S796P0YFF92NsyreJxmWdKGBSt8npZrHoUap0CBy22OS2OA0JbqWBxYCgZ/0E9J sMf7YBYmKuJ9AXyUX/EKyTJZtDj1S7RH0PfDHmZyG2Ldj7EqIKGC5kfVG+Bc2lP1cEYi FLwltknY2VXiny0ddIoLmT2ch3sjptWqCUk3fPcyg2/diTLOA6XVkY5A8h6Inp2aQA7/ eu1/t9+6zWBFugct6WrMG63S5uUOb/0Qa7gBnw9634aKqDrDXWyyFd1FM9/HNKtFnc59 uVlg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t18si11728444pgv.285.2019.02.26.17.06.10; Tue, 26 Feb 2019 17:06:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729565AbfB0BGJ (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:09 -0500 Received: from foss.arm.com ([217.140.101.70]:55616 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729520AbfB0BGE (ORCPT ); Tue, 26 Feb 2019 20:06:04 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 45A0616A3; Tue, 26 Feb 2019 17:06:04 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A59A83F5C1; Tue, 26 Feb 2019 17:06:03 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 03/10] arm64: add sysfs vulnerability show for meltdown Date: Tue, 26 Feb 2019 19:05:37 -0600 Message-Id: <20190227010544.597579-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Display the mitigation status if active, otherwise assume the cpu is safe unless it doesn't have CSV3 and isn't in our whitelist. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpufeature.c | 47 ++++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 10 deletions(-) -- 2.20.1 Reviewed-by: Suzuki K Poulose diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f6d84e2c92fe..d31bd770acba 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -944,7 +944,7 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) return has_cpuid_feature(entry, scope); } -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +static bool __meltdown_safe = true; static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, @@ -963,6 +963,16 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, { /* sentinel */ } }; char const *str = "command line option"; + bool meltdown_safe; + + meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); + + /* Defer to CPU feature registers */ + if (has_cpuid_feature(entry, scope)) + meltdown_safe = true; + + if (!meltdown_safe) + __meltdown_safe = false; /* * For reasons that aren't entirely clear, enabling KPTI on Cavium @@ -974,6 +984,11 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, __kpti_forced = -1; } + if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { + pr_info_once("kernel page table isolation disabled by CONFIG\n"); + return false; + } + /* Forced? */ if (__kpti_forced) { pr_info_once("kernel page table isolation forced %s by %s\n", @@ -985,14 +1000,10 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) return kaslr_offset() > 0; - /* Don't force KPTI for CPUs that are not vulnerable */ - if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list)) - return false; - - /* Defer to CPU feature registers */ - return !has_cpuid_feature(entry, scope); + return !meltdown_safe; } +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 static void kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) { @@ -1022,6 +1033,13 @@ kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) return; } +#else +static void +kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) +{ +} +#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ + static int __init parse_kpti(char *str) { @@ -1035,7 +1053,6 @@ static int __init parse_kpti(char *str) return 0; } early_param("kpti", parse_kpti); -#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ #ifdef CONFIG_ARM64_HW_AFDBM static inline void __cpu_enable_hw_dbm(void) @@ -1286,7 +1303,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .field_pos = ID_AA64PFR0_EL0_SHIFT, .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, }, -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 { .desc = "Kernel page table isolation (KPTI)", .capability = ARM64_UNMAP_KERNEL_AT_EL0, @@ -1302,7 +1318,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = unmap_kernel_at_el0, .cpu_enable = kpti_install_ng_mappings, }, -#endif { /* FP/SIMD is not implemented */ .capability = ARM64_HAS_NO_FPSIMD, @@ -2063,3 +2078,15 @@ static int __init enable_mrs_emulation(void) } core_initcall(enable_mrs_emulation); + +ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, + char *buf) +{ + if (arm64_kernel_unmapped_at_el0()) + return sprintf(buf, "Mitigation: KPTI\n"); + + if (__meltdown_safe) + return sprintf(buf, "Not affected\n"); + + return sprintf(buf, "Vulnerable\n"); +} From patchwork Wed Feb 27 01:05:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159255 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3852181jad; Tue, 26 Feb 2019 17:06:48 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ5laO5Zt7/7kh/+5O9e65YpJSj3ruhEMporbp+oiKrEQVPcyQVqD6pBKxM8Bco5rI1CjXL X-Received: by 2002:a63:b0b:: with SMTP id 11mr302735pgl.187.1551229608168; Tue, 26 Feb 2019 17:06:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229608; cv=none; d=google.com; s=arc-20160816; b=ba8SeNZvJr4ib8nQni8lsKW2UlCvdOZ6RsH0TrysKAWGeQWECbX6PFdnU3jTAsLSUE Qj6AjRNBwb+bvb31dQPxRuxutySm/Tonumsk/YgPobGz2Rsmqynn1Fl9BekLBg6Zac4R aN+l4IfuVVDODA5dQnMqqs968aonqYSP3wbO4ScG+/h73vNohV+abBlnuvl/hHp9XNmm H+fz42acAuUpWye5YyXSG5g8ml7Bm5fH8CWzQiPwH1LnPBfQrk7vvz8gB6/dw2jpD+iu lv+6k57qJdX4tR4zr60+UCgwPu0VoSj47AeacgumCw8+eZ8u1ww9ts00RU1TGkYxRXmn +Nnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=hSvFS2ejWnfmqwLxq/yEFitZzn8bvqc4fompeS8TsKk=; b=O4biJUdMwG/r50lMKy11IJEWLJkx6zfqdjH8+GdbWuuUJDn1mLA/l2t2q4R6cUoob+ TBaJSwuucRkPX2+C4tGv+ZqM42hkLkD1TFjfl0FN/mzxT2J/gCXY86nEENNoKaotVnuq 5bp2/jkILleYauvO/b+aftW5DI2zrci4451fUQeDWNfo5/MJMK0jJDsH+gwYehdLWudO mKA0ASKe49poTpr+wMOWan1vuLYcUgxWXekZYx/NE4yyoplaSOwDjv8rh6YjS0G9Q9VV 8LTGz1s7waA9jK+W05TUiuc5F/ljfFfDH1LYJNr0wmKvRtINITNA5XA1IQYklQ9m/Jf7 tpAA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f5si10631617plf.275.2019.02.26.17.06.47; Tue, 26 Feb 2019 17:06:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729718AbfB0BGq (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:46 -0500 Received: from foss.arm.com ([217.140.101.70]:55630 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729518AbfB0BGG (ORCPT ); Tue, 26 Feb 2019 20:06:06 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 746BD1713; Tue, 26 Feb 2019 17:06:05 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D5E093F5C1; Tue, 26 Feb 2019 17:06:04 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 04/10] arm64: Advertise mitigation of Spectre-v2, or lack thereof Date: Tue, 26 Feb 2019 19:05:38 -0600 Message-Id: <20190227010544.597579-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier We currently have a list of CPUs affected by Spectre-v2, for which we check that the firmware implements ARCH_WORKAROUND_1. It turns out that not all firmwares do implement the required mitigation, and that we fail to let the user know about it. Instead, let's slightly revamp our checks, and rely on a whitelist of cores that are known to be non-vulnerable, and let the user know the status of the mitigation in the kernel log. Signed-off-by: Marc Zyngier [This makes more sense in front of the sysfs patch] [Pick pieces of that patch into this and move it earlier] Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 108 +++++++++++++++++---------------- 1 file changed, 56 insertions(+), 52 deletions(-) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index ad58958becb6..c8972255b365 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -131,9 +131,9 @@ static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); } -static void __install_bp_hardening_cb(bp_hardening_cb_t fn, - const char *hyp_vecs_start, - const char *hyp_vecs_end) +static void install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) { static DEFINE_RAW_SPINLOCK(bp_lock); int cpu, slot = -1; @@ -177,23 +177,6 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, } #endif /* CONFIG_KVM_INDIRECT_VECTORS */ -static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, - bp_hardening_cb_t fn, - const char *hyp_vecs_start, - const char *hyp_vecs_end) -{ - u64 pfr0; - - if (!entry->matches(entry, SCOPE_LOCAL_CPU)) - return; - - pfr0 = read_cpuid(ID_AA64PFR0_EL1); - if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) - return; - - __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); -} - #include #include #include @@ -228,31 +211,27 @@ static int __init parse_nospectre_v2(char *str) } early_param("nospectre_v2", parse_nospectre_v2); -static void -enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +/* + * -1: No workaround + * 0: No workaround required + * 1: Workaround installed + */ +static int detect_harden_bp_fw(void) { bp_hardening_cb_t cb; void *smccc_start, *smccc_end; struct arm_smccc_res res; u32 midr = read_cpuid_id(); - if (!entry->matches(entry, SCOPE_LOCAL_CPU)) - return; - - if (__nospectre_v2) { - pr_info_once("spectrev2 mitigation disabled by command line option\n"); - return; - } - if (psci_ops.smccc_version == SMCCC_VERSION_1_0) - return; + return -1; switch (psci_ops.conduit) { case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 < 0) - return; + return -1; cb = call_hvc_arch_workaround_1; /* This is a guest, no need to patch KVM vectors */ smccc_start = NULL; @@ -263,23 +242,23 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 < 0) - return; + return -1; cb = call_smc_arch_workaround_1; smccc_start = __smccc_workaround_1_smc_start; smccc_end = __smccc_workaround_1_smc_end; break; default: - return; + return -1; } if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) || ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) cb = qcom_link_stack_sanitization; - install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); + install_bp_hardening_cb(cb, smccc_start, smccc_end); - return; + return 1; } #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ @@ -521,24 +500,49 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) CAP_MIDR_RANGE_LIST(midr_list) #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR - /* - * List of CPUs where we need to issue a psci call to - * harden the branch predictor. + * List of CPUs that do not need any Spectre-v2 mitigation at all. */ -static const struct midr_range arm64_bp_harden_smccc_cpus[] = { - MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), - MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), - MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), - MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR), - MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER), - {}, +static const struct midr_range spectre_v2_safe_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + { /* sentinel */ } }; +static bool __maybe_unused +check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) +{ + int need_wa; + + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + + /* If the CPU has CSV2 set, we're safe */ + if (cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64PFR0_EL1), + ID_AA64PFR0_CSV2_SHIFT)) + return false; + + /* Alternatively, we have a list of unaffected CPUs */ + if (is_midr_in_range_list(read_cpuid_id(), spectre_v2_safe_list)) + return false; + + /* Fallback to firmware detection */ + need_wa = detect_harden_bp_fw(); + if (!need_wa) + return false; + + /* forced off */ + if (__nospectre_v2) { + pr_info_once("spectrev2 mitigation disabled by command line option\n"); + return false; + } + + if (need_wa < 0) + pr_warn_once("ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware\n"); + + return (need_wa > 0); +} + #endif #ifdef CONFIG_HARDEN_EL2_VECTORS @@ -717,8 +721,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = { #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - .cpu_enable = enable_smccc_arch_workaround_1, - ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus), + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + .matches = check_branch_predictor, }, #endif #ifdef CONFIG_HARDEN_EL2_VECTORS From patchwork Wed Feb 27 01:05:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159253 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851939jad; Tue, 26 Feb 2019 17:06:33 -0800 (PST) X-Google-Smtp-Source: AHgI3IaX8xAlYNvEzUrqjDfjakrwaC0b1TgpI4imX7uJDLiSnrzkksxr7CF87BNrsYQPzsfF3Wjr X-Received: by 2002:aa7:8743:: with SMTP id g3mr28468553pfo.109.1551229593647; Tue, 26 Feb 2019 17:06:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229593; cv=none; d=google.com; s=arc-20160816; b=1IZCgHjrnBsro6nZvNL8lHLQ1WWxGpcHXSbotKgrFJVsInPGjrMyvTtErV2mO6HxKl /ZGGJ/olaW4VUXz2AhyACur/XZi1WfYNM5s+Zjl4s+L0hBD4ZAfEFcXYNKPXaIf0SGak DsmUcwxyz9FNgqc1Bpsuv1HmHOt4Zm6RYbgwgpuiUeJiqMSfwhAc4N4tNJs/XlKpF1QK IlUcZDatUoH4EGeHoUb0S74tHgO03l3l7sqcU69NGHTZUhy7FofXeuMFxvZN+RE5M9i8 2j5C1jYjw8X6eGHOynQpdxPkucBIRjRF4cYStjC7J7N5hWAmMyDhf9W7vrpbJ1cT370X PsAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id a6si13664738pgc.137.2019.02.26.17.06.33; Tue, 26 Feb 2019 17:06:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729686AbfB0BGc (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:32 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55642 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729542AbfB0BGH (ORCPT ); Tue, 26 Feb 2019 20:06:07 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BFAA4174E; Tue, 26 Feb 2019 17:06:06 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2D1F93F5C1; Tue, 26 Feb 2019 17:06:06 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 05/10] arm64: Use firmware to detect CPUs that are not affected by Spectre-v2 Date: Tue, 26 Feb 2019 19:05:39 -0600 Message-Id: <20190227010544.597579-6-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier The SMCCC ARCH_WORKAROUND_1 service can indicate that although the firmware knows about the Spectre-v2 mitigation, this particular CPU is not vulnerable, and it is thus not necessary to call the firmware on this CPU. Let's use this information to our benefit. Signed-off-by: Marc Zyngier Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index c8972255b365..77f021e78a28 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -230,22 +230,36 @@ static int detect_harden_bp_fw(void) case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); - if ((int)res.a0 < 0) + switch ((int)res.a0) { + case 1: + /* Firmware says we're just fine */ + return 0; + case 0: + cb = call_hvc_arch_workaround_1; + /* This is a guest, no need to patch KVM vectors */ + smccc_start = NULL; + smccc_end = NULL; + break; + default: return -1; - cb = call_hvc_arch_workaround_1; - /* This is a guest, no need to patch KVM vectors */ - smccc_start = NULL; - smccc_end = NULL; + } break; case PSCI_CONDUIT_SMC: arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); - if ((int)res.a0 < 0) + switch ((int)res.a0) { + case 1: + /* Firmware says we're just fine */ + return 0; + case 0: + cb = call_smc_arch_workaround_1; + smccc_start = __smccc_workaround_1_smc_start; + smccc_end = __smccc_workaround_1_smc_end; + break; + default: return -1; - cb = call_smc_arch_workaround_1; - smccc_start = __smccc_workaround_1_smc_start; - smccc_end = __smccc_workaround_1_smc_end; + } break; default: From patchwork Wed Feb 27 01:05:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159249 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851600jad; Tue, 26 Feb 2019 17:06:14 -0800 (PST) X-Google-Smtp-Source: AHgI3IamK2COYoFvBEs07NovAJQqAXvRavWUg3tqxsIvN8dyA95ajVSCOJhPDNTDBDvdMv4JaReM X-Received: by 2002:a63:6545:: with SMTP id z66mr336138pgb.182.1551229574097; Tue, 26 Feb 2019 17:06:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229574; cv=none; d=google.com; s=arc-20160816; b=QKcfGh3B5cfm8JLE25d5DWOrGULSJIc1tKtucrpdZVq0sVToHVI5+QyeAscBfJ8+0C 9H6xPcT/yJkWBA9NDjClWCRhrQoz/Y7sgcLVAvkLkXasaaCGZAq2QaWyQ6eeYVKRKmgF XjbuH6LCjlOc1saT7Gyq+vTaXznAYEguOYzt16blhriWlwxY8daWIAyLs45SDKBWEwxJ bbJuCwsb2PklUwDa1Juz8iE6HUePmO5NZv+GR/ASrnDGCNISL6ejDHJ1bArOLRr8WGt6 d5K8XPz9k9rfuRzH/ftEbGOMC1StUGv1m2hDiqTOPthS14KIOj5deJIGmf9PTMkRzq8y hJnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=B4KmVAyBGsNqk96L4NwaeWOrYyawyIIrtKGfDXtk61U=; b=MDERbJOu31/5hg0P7gmydacl2ysHkyzo6PBOYx2lQYu9eMBFeUsfck25T9CKIqFT/q ogdo2xuonjE3bai+rVt2JMdyr5NzEnumSSGUeHm1JUFB9wqm2/fevjBuQAsb1KxQv/Ya 9vTnhDIkZ0KSFwaoEHkDb2FjZ9ayY7nOpIUm3MGePYKSKSZ3cMaCtwdD/2BAVJIZEubp mXNh28cTXA0F8SofAdNb6+mLrwWDHVqntwkMt7tQdBPy/quUdVqXVsQa0zBEEv3Umv1w 18Ho9NOTK76z+e4oYa+HwJyYrhVBqXvF2dDXV0wVHw6I0geluQ/A3lYNjzWAPtdNRZrK amjA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t18si11728444pgv.285.2019.02.26.17.06.12; Tue, 26 Feb 2019 17:06:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729587AbfB0BGL (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:11 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55654 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729560AbfB0BGI (ORCPT ); Tue, 26 Feb 2019 20:06:08 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E86C619BF; Tue, 26 Feb 2019 17:06:07 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 552CC3F5C1; Tue, 26 Feb 2019 17:06:07 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 06/10] arm64: Always enable spectrev2 vulnerability detection Date: Tue, 26 Feb 2019 19:05:40 -0600 Message-Id: <20190227010544.597579-7-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sysfs patches need to display machine vulnerability status regardless of kernel config. Prepare for that by breaking out the vulnerability/mitigation detection code from the logic which implements the mitigation. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 77f021e78a28..a27e1ee750e1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -109,12 +109,12 @@ cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused) atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1); -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR #include #include DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + #ifdef CONFIG_KVM_INDIRECT_VECTORS extern char __smccc_workaround_1_smc_start[]; extern char __smccc_workaround_1_smc_end[]; @@ -270,11 +270,11 @@ static int detect_harden_bp_fw(void) ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) cb = qcom_link_stack_sanitization; - install_bp_hardening_cb(cb, smccc_start, smccc_end); + if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) + install_bp_hardening_cb(cb, smccc_start, smccc_end); return 1; } -#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); @@ -513,7 +513,6 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ CAP_MIDR_RANGE_LIST(midr_list) -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR /* * List of CPUs that do not need any Spectre-v2 mitigation at all. */ @@ -545,6 +544,11 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) if (!need_wa) return false; + if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) { + pr_warn_once("spectrev2 mitigation disabled by configuration\n"); + return false; + } + /* forced off */ if (__nospectre_v2) { pr_info_once("spectrev2 mitigation disabled by command line option\n"); @@ -557,8 +561,6 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) return (need_wa > 0); } -#endif - #ifdef CONFIG_HARDEN_EL2_VECTORS static const struct midr_range arm64_harden_el2_vectors[] = { @@ -732,13 +734,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), }, #endif -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = check_branch_predictor, }, -#endif #ifdef CONFIG_HARDEN_EL2_VECTORS { .desc = "EL2 vector hardening", From patchwork Wed Feb 27 01:05:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159254 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3852002jad; Tue, 26 Feb 2019 17:06:37 -0800 (PST) X-Google-Smtp-Source: AHgI3Ibte3b79gj1xjCBbki3LUiYuWe7bgvumEEi6Lpt8BQEj07meBY+qgskplIzMsus2Mi3DizG X-Received: by 2002:a63:d49:: with SMTP id 9mr306927pgn.27.1551229597414; Tue, 26 Feb 2019 17:06:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229597; cv=none; d=google.com; s=arc-20160816; b=VfycA+TV6TF+/EeJ76gqAepDgEaz49Bxuwlb5qR9VUNbRdwsRsgMM950z3PyvjRHe9 4wKL/gv0jQrgH/dlMixst5vTi0OpJpHC3V4mzfSgOiOPyDzKBYgUqmF5DPmP3uhp8hkA DmCdjJ8JAUeffowTu25vJeYIDHt1J3EgLV6sNNYdcYLY+eCCzXa2af42gR97ZVJnOsS6 yvRdLHT8Er/IX8rSHm1Rv/NUZbgkAxJ4b/2Edq9OUyvtwOZOqHn9p2iG4qWtOTEqEwhQ QEOC+bca0Bwkq2d30H0r/l7Tibf3Kd6nW5pwhLaU8ulxcd8+Xb2mpGNd7o3gxkUF/WQo PzKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Z4xGFeXPWqEvCribVErp1TtD/jZLGHSb5E5XsELMTiE=; b=iBzJGbsFPeL6Ki9GAp2Y5EUp/WtkgntSjR0FOmqfFHBPb+44G3B6nJ7clddpIzg1o0 0iGkDJ9gnbOBiIHEySYO6qwruc3od6ReIxrrbYiysW3N+eaaiJwSrqFyRI3bzSb08eNF zLreyW3TguGFHqB6aUupReRqJW6cw2mxe6hJGPN4hqIFZpZZ1KTvoxhNF5XKyS7oqHYA f8OLXRdfs87dmIM8hoNQMl/cKNhCGmHBj2fh6JJIFxCokyOX60D5KmKTV7Kw7hJ3x5e7 W7vI+qzkW0kRlcq9O/XP2EJ12SW/Gm/sh2oqmxigRxtJDoakekKUHqW5ayei8y8yp55i w9ng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d186si14371572pfg.50.2019.02.26.17.06.37; Tue, 26 Feb 2019 17:06:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729660AbfB0BGb (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:31 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55672 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729564AbfB0BGJ (ORCPT ); Tue, 26 Feb 2019 20:06:09 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 18F9280D; Tue, 26 Feb 2019 17:06:09 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7ABD03F5C1; Tue, 26 Feb 2019 17:06:08 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 07/10] arm64: add sysfs vulnerability show for spectre v2 Date: Tue, 26 Feb 2019 19:05:41 -0600 Message-Id: <20190227010544.597579-8-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add code to track whether all the cores in the machine are vulnerable, and whether all the vulnerable cores have been mitigated. Once we have that information we can add the sysfs stub and provide an accurate view of what is known about the machine. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a27e1ee750e1..0f6e8f5d67bc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -513,6 +513,10 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ CAP_MIDR_RANGE_LIST(midr_list) +/* Track overall mitigation state. We are only mitigated if all cores are ok */ +static bool __hardenbp_enab = true; +static bool __spectrev2_safe = true; + /* * List of CPUs that do not need any Spectre-v2 mitigation at all. */ @@ -523,6 +527,10 @@ static const struct midr_range spectre_v2_safe_list[] = { { /* sentinel */ } }; +/* + * Track overall bp hardening for all heterogeneous cores in the machine. + * We are only considered "safe" if all booted cores are known safe. + */ static bool __maybe_unused check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) { @@ -544,19 +552,25 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope) if (!need_wa) return false; + __spectrev2_safe = false; + if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) { pr_warn_once("spectrev2 mitigation disabled by configuration\n"); + __hardenbp_enab = false; return false; } /* forced off */ if (__nospectre_v2) { pr_info_once("spectrev2 mitigation disabled by command line option\n"); + __hardenbp_enab = false; return false; } - if (need_wa < 0) + if (need_wa < 0) { pr_warn_once("ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware\n"); + __hardenbp_enab = false; + } return (need_wa > 0); } @@ -779,3 +793,15 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, { return sprintf(buf, "Mitigation: __user pointer sanitization\n"); } + +ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, + char *buf) +{ + if (__spectrev2_safe) + return sprintf(buf, "Not affected\n"); + + if (__hardenbp_enab) + return sprintf(buf, "Mitigation: Branch predictor hardening\n"); + + return sprintf(buf, "Vulnerable\n"); +} From patchwork Wed Feb 27 01:05:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159252 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851805jad; Tue, 26 Feb 2019 17:06:26 -0800 (PST) X-Google-Smtp-Source: AHgI3IanamRYIkiWn0kWdFcGI7TdsoY5PkmvY21gLTMeHfQVttfvv02CJSHvhXbxM7CI2/dvsH7d X-Received: by 2002:a65:6294:: with SMTP id f20mr335038pgv.174.1551229586713; Tue, 26 Feb 2019 17:06:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229586; cv=none; d=google.com; s=arc-20160816; b=dwakIJ0L+b5RWJ11iPLmouqLTgsTwyZ4uuJdwpVIyUajmXLlYMvTkqCytErZ14OMn8 sODjwaN4FQU6+hXh4OE28DhHZBaF8o1scFTMfrRA/9cAjJj5vqXIpnAYlNg8PB9b+lbh sUkCunVpbfjC4t2RZZ5PM6ReJFoUOjczMBOWBzL63wtPilqVvQo4VJEKMss5tEctYRh0 34mmFf4+qViuNVStIrHSgzYyqUBV8a4Vco+DsRDOufrO61C3BnTYsOWhMl7KWRrpDXmS YnDRr24moYwfCC46RVgGdaFtVfHVa9zfRxNh7zZlchdLxgxrKSzRBdjOSr9x2bsH2CWo sOmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=o/SlX8GwP6cqPa1kuJHcBkWplEHk+7HEkeYTTmFOUhY=; b=bWdtHQTBGJ3H7lYQ+6NSzIwWv0Ahv0JYFrdodjAiAECx2fhtQbfTCOG7CJYRcBHUj2 ZuGeW4zBxSG3h5NPFwbdOuHEezHudqRetpqFNGOM+eFxiZaM2vU4rs4f8e7lxvv3zDTr WuBuMOzIFnoEUsrWkzNoLV2/dPg8AeVpiCbBuhnJfJl7znlDwf0bkpt01sYk4hVpNj3A N/DwRz5YaMejrWKz+LwjfWhOhaiHFgBnYfJEd03k46sExJabtYB8C6DhvlZwCdvt9n/6 IrBYFCoTmrrGyAC1gdmZbOhYmWKX6yndKQW5qsBW1Iv8PzOpOUjR3B2PggAFvh0gQzFG SblQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a6si13664738pgc.137.2019.02.26.17.06.26; Tue, 26 Feb 2019 17:06:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729641AbfB0BGY (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:24 -0500 Received: from foss.arm.com ([217.140.101.70]:55682 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729574AbfB0BGK (ORCPT ); Tue, 26 Feb 2019 20:06:10 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 38EE01A25; Tue, 26 Feb 2019 17:06:10 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9A28D3F5C1; Tue, 26 Feb 2019 17:06:09 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 08/10] arm64: Always enable ssb vulnerability detection Date: Tue, 26 Feb 2019 19:05:42 -0600 Message-Id: <20190227010544.597579-9-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ssb detection logic is necessary regardless of whether the vulnerability mitigation code is built into the kernel. Break it out so that the CONFIG option only controls the mitigation logic and not the vulnerability detection. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/cpufeature.h | 4 ---- arch/arm64/kernel/cpu_errata.c | 11 +++++++---- 2 files changed, 7 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index dfcfba725d72..c2b60a021437 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -628,11 +628,7 @@ static inline int arm64_get_ssbd_state(void) #endif } -#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state); -#else -static inline void arm64_set_ssbd_mitigation(bool state) {} -#endif extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0f6e8f5d67bc..5f5611d17dc1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -276,7 +276,6 @@ static int detect_harden_bp_fw(void) return 1; } -#ifdef CONFIG_ARM64_SSBD DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; @@ -347,6 +346,7 @@ void __init arm64_enable_wa2_handling(struct alt_instr *alt, *updptr = cpu_to_le32(aarch64_insn_gen_nop()); } +#ifdef CONFIG_ARM64_SSBD void arm64_set_ssbd_mitigation(bool state) { if (this_cpu_has_cap(ARM64_SSBS)) { @@ -371,6 +371,12 @@ void arm64_set_ssbd_mitigation(bool state) break; } } +#else +void arm64_set_ssbd_mitigation(bool state) +{ + pr_info_once("SSBD, disabled by kernel configuration\n"); +} +#endif /* CONFIG_ARM64_SSBD */ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, int scope) @@ -468,7 +474,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } -#endif /* CONFIG_ARM64_SSBD */ static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) @@ -760,14 +765,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors), }, #endif -#ifdef CONFIG_ARM64_SSBD { .desc = "Speculative Store Bypass Disable", .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, }, -#endif #ifdef CONFIG_ARM64_ERRATUM_1188873 { /* Cortex-A76 r0p0 to r2p0 */ From patchwork Wed Feb 27 01:05:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159250 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851657jad; Tue, 26 Feb 2019 17:06:17 -0800 (PST) X-Google-Smtp-Source: AHgI3IaaCmg0dkt5OrAMo7b+snrm502TcP5WSsXSPHQbj/5GvGIuUGTutqZW4QqLAtyE9Qt8dKqy X-Received: by 2002:a17:902:42e4:: with SMTP id h91mr29673017pld.18.1551229577005; Tue, 26 Feb 2019 17:06:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229576; cv=none; d=google.com; s=arc-20160816; b=TtqFpbYiofnNMxomIb2Iv7Zng4FgDa3nQFAyGFejJqFZAtIdKLrrNKS0OnRHCq8Cy/ E7OaSTJHLeE86Z+eRWCe0tldUNs6ieHzkjSivr2KJMymFmwCSHuNw87aGroZRaizvXoP pbE7qxP3hiLkQxwbIsP56HxW030fW9lAb/+R4vKlfEaswHd3JRpZKS0Bcpb8Txsno/BN b30/ILpa1yYrL8m2OM+6kze9WD1SwXAgYotczOjoFiNl2v+MfFv/G88i4zEmqgmeXadM wVVy7R1zVcz7kDIuDQoW6lD3+lxM2jSKAdA1A++CzJ9ctzYNhVw3lSlNE3Hk9uPR7z2q djDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=ko7VOjYkTxEk3ajFDcWnP8ZT8qL1w1mPzsQLYQE0gl8=; b=QK0wA+IqHPUMfSBxfN4f2ZykA3OlGcvd9/t3j+wa/n9LlGrit+xbNUF0xEtEwMpH4e TzUqMfmr555bU+jL5Gr/0WvlsTMz8YDIp22S0mX3M9sXK1L9zqSl6CeTVUMLlnXjzORD aRbNkNB5AI/gI0PkCZpk8BZnZPo6B85RwXuT9ZLK15kQDScwRiTC5ep2ScGmzWGPFDQ3 7SK48+Acnb9RG/6/5dJT3MGSRzTNQ+h8MDf81tl+gOHJZmmOW/f83eLYLDVmZ4PYqqtY erEXx2U6m+bAtPzg4jrSK5rOw++AkT3wK/U4uDd85iTOfGjTzqV6SP3630is9yZfGqs/ qo/g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f89si10836843plb.20.2019.02.26.17.06.16; Tue, 26 Feb 2019 17:06:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729607AbfB0BGP (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:15 -0500 Received: from foss.arm.com ([217.140.101.70]:55694 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729580AbfB0BGL (ORCPT ); Tue, 26 Feb 2019 20:06:11 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 54DBA1AED; Tue, 26 Feb 2019 17:06:11 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B66793F5C1; Tue, 26 Feb 2019 17:06:10 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v5 09/10] arm64: add sysfs vulnerability show for speculative store bypass Date: Tue, 26 Feb 2019 19:05:43 -0600 Message-Id: <20190227010544.597579-10-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return status based on ssbd_state and the arm64 SSBS feature. If the mitigation is disabled, or the firmware isn't responding then return the expected machine state based on a new blacklist of known vulnerable cores. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpu_errata.c | 43 ++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.20.1 diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 5f5611d17dc1..e1b03f643799 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -279,6 +279,7 @@ static int detect_harden_bp_fw(void) DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; +static bool __ssb_safe = true; static const struct ssbd_options { const char *str; @@ -387,6 +388,9 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list)) + __ssb_safe = false; + if (this_cpu_has_cap(ARM64_SSBS)) { required = false; goto out_printmsg; @@ -420,6 +424,7 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, ssbd_state = ARM64_SSBD_UNKNOWN; return false; + /* machines with mixed mitigation requirements must not return this */ case SMCCC_RET_NOT_REQUIRED: pr_info_once("%s mitigation not required\n", entry->desc); ssbd_state = ARM64_SSBD_MITIGATED; @@ -475,6 +480,16 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } +/* known vulnerable cores */ +static const struct midr_range arm64_ssb_cpus[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), + {}, +}; + static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) { @@ -770,6 +785,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, + .midr_range_list = arm64_ssb_cpus, }, #ifdef CONFIG_ARM64_ERRATUM_1188873 { @@ -808,3 +824,30 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, return sprintf(buf, "Vulnerable\n"); } + +ssize_t cpu_show_spec_store_bypass(struct device *dev, + struct device_attribute *attr, char *buf) +{ + /* + * Two assumptions: First, ssbd_state reflects the worse case + * for hetrogenous machines, and that if SSBS is supported its + * supported by all cores. + */ + switch (ssbd_state) { + case ARM64_SSBD_MITIGATED: + return sprintf(buf, "Not affected\n"); + + case ARM64_SSBD_KERNEL: + case ARM64_SSBD_FORCE_ENABLE: + if (cpus_have_cap(ARM64_SSBS)) + return sprintf(buf, "Not affected\n"); + if (IS_ENABLED(CONFIG_ARM64_SSBD)) + return sprintf(buf, + "Mitigation: Speculative Store Bypass disabled\n"); + } + + if (__ssb_safe) + return sprintf(buf, "Not affected\n"); + + return sprintf(buf, "Vulnerable\n"); +} From patchwork Wed Feb 27 01:05:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 159251 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp3851678jad; Tue, 26 Feb 2019 17:06:19 -0800 (PST) X-Google-Smtp-Source: AHgI3Ib3o5ruAHzPfF+6ga+EgM2/JSjpGXKBGLfV27rjhgBZnI0w9Wy5xDHrG3lFG62GkwBK49lX X-Received: by 2002:a63:e206:: with SMTP id q6mr300480pgh.87.1551229579015; Tue, 26 Feb 2019 17:06:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551229579; cv=none; d=google.com; s=arc-20160816; b=FhhWuGmbMK9QYmVB6llt6/oO24uOBBui063gTgtnE/TsoGL2N2rmf/PbCeZH4maD2y Cn1JlWVqB+bk0BNTk+QLqHLCSUz/9ebueA9LYU5gEHpTTVYhSdP83GP2NOP2TYenFQDi tbfY7e0+Xtstvl3kci0/U2NwJrmw8s/MIUGSQk/EO2Xbu5pJM6Qcyko94biOrfrn73Pl Omcop+mGX604y28Ah0IrGG1qwjRDrtLmCi7d69wRymjwrtU8I2CnC0vvBsnG/CTqo889 KitX+q1z3bnvTMga2H+S9VoLuRYAlRQhyxk3a2+sQWo6snq0LiJWnvedmA+fDEGWxt6Q 7o6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=OPOdIOneyBTPnMvi3raAXLtTTCTnmaPtJcMVjIhabX4=; b=bQWzCf5s5C26xS1pcH5rLpIWxONb0+4nSUP9RHS3Wq3hqiZ2J/2LPxA7w6nrpMI321 SCov2eciuvvCgJIz8QRvo//fMc3vFZTbW7bWsy3TTfhg/F7uP6LGiDslh6d5ErwohdN7 9Z/C1U0tpN/cWgLHeMQ9SmfNeTvuUdndrc/OOu3+3WWO3sEbjQwJZJszrnbveiS/l7lH AjDg74stao9g7Kf5mLcLt2RMAdRr0W2YkHuzZ4KjvtDi9ygSQF8DDU1Mm6ezsXEEEHpm 8XkT901wNGrDMbnOqi8aC3iBL9WuoUK3pNhtIeBGZ4Om87Edf8C38olEbMn599Hdwg0Q hURg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f89si10836843plb.20.2019.02.26.17.06.18; Tue, 26 Feb 2019 17:06:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729624AbfB0BGR (ORCPT + 31 others); Tue, 26 Feb 2019 20:06:17 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:55698 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729560AbfB0BGM (ORCPT ); Tue, 26 Feb 2019 20:06:12 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89E271B55; Tue, 26 Feb 2019 17:06:12 -0800 (PST) Received: from beelzebub.austin.arm.com (beelzebub.austin.arm.com [10.118.12.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D90E53F5C1; Tue, 26 Feb 2019 17:06:11 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Mian Yousaf Kaukab , Jeremy Linton Subject: [PATCH v5 10/10] arm64: enable generic CPU vulnerabilites support Date: Tue, 26 Feb 2019 19:05:44 -0600 Message-Id: <20190227010544.597579-11-jeremy.linton@arm.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190227010544.597579-1-jeremy.linton@arm.com> References: <20190227010544.597579-1-jeremy.linton@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mian Yousaf Kaukab Enable CPU vulnerabilty show functions for spectre_v1, spectre_v2, meltdown and store-bypass. Signed-off-by: Mian Yousaf Kaukab Signed-off-by: Jeremy Linton --- arch/arm64/Kconfig | 1 + 1 file changed, 1 insertion(+) -- 2.20.1 Reviewed-by: Andre Przywara diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a4168d366127..be9872ee1d61 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -88,6 +88,7 @@ config ARM64 select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS_BROADCAST select GENERIC_CPU_AUTOPROBE + select GENERIC_CPU_VULNERABILITIES select GENERIC_EARLY_IOREMAP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_MULTI_HANDLER