From patchwork Wed Feb 27 07:00:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 159276 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp4088900jad; Tue, 26 Feb 2019 22:59:51 -0800 (PST) X-Google-Smtp-Source: AHgI3IZBjecIMrvEBsW/51cqBDw3VuMCgvYkGUA9oLmi2fPvOoe6Hk4cZI/TGUr9Aj2y5Z9FTwxS X-Received: by 2002:a62:1342:: with SMTP id b63mr163020pfj.7.1551250791256; Tue, 26 Feb 2019 22:59:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551250791; cv=none; d=google.com; s=arc-20160816; b=jnzRtxZtSJjzhDxEC1szqCQJ7g2LV39kococYeZ7trdD/G3GR/9+JEjqSum3l6IcCP KLGrYqKhGSG6QafApm9SrgSFXMpTQ1ymO3ZROmRk5G7s7wR/BfJqCIPfxn4imNdhU/7z yLX8t3cRA6AF3riNwpt+9oT+OCghmNNtQyok4vBG67y6Ta4BtT0Bti2+GfYZ8D5i4E9f WRCVDzgEHZdIeZpMSW4dHcgFj56BJJ61U78kNUeN0M01NrHWap5peU7SEz4rYNm2OXds /z7Om/E0+MTEGnSGSOTBRvustZf7OYQ5nIesU7owHIHlKjtuwDjv0/wc01lQqVRvLaiv omxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=MnpOjV/SNe6sQfK3nZ3ll5DmkqSi2WszLWuZJmb/Hwk=; b=WlC6gHvWomGg+exaALYbPbtBwNn7j3rJmOyOaYV5hzQLOb80yEoTMdGwfBO7Pxdq7U sw2OE0QxN0/TuVatjSySTyXPNY1ANzroQEsVl2ULTyad/bTdhdksNvJcPZoQnPcHcG+U WkJV++MQMO5Nm2Tjts7pDmCQFj7pTpbQaNz8BBccS6e0WseJH8na/sZCkzbvHfVCkS/l d+RMvFcsXY86ousEADBpA0CFoMdN3++R5lxAzGBFFwYO5dJbVTy+Phi3fTGbCWp8YHx2 JJwi6vA8Leh2lAHThQpzJJNd+cr0cAWNmoOm9UtJzfXIUQZ7FoquuIpf9TY/WnlLS4KN Zt6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RJ4/ULr6"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f30si14552898plf.393.2019.02.26.22.59.51; Tue, 26 Feb 2019 22:59:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RJ4/ULr6"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727189AbfB0G7u (ORCPT + 7 others); Wed, 27 Feb 2019 01:59:50 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:46906 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726484AbfB0G7u (ORCPT ); Wed, 27 Feb 2019 01:59:50 -0500 Received: by mail-pl1-f195.google.com with SMTP id c17so4354615plz.13 for ; Tue, 26 Feb 2019 22:59:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MnpOjV/SNe6sQfK3nZ3ll5DmkqSi2WszLWuZJmb/Hwk=; b=RJ4/ULr6kCR3Wf0u4VCRXQs44ee4owE4NZSWETDPbZphtp43x6BgQm29dg47lUq5iY rmOPMJ7vSalrG8zab3uq1S8VHzWYW4ErwdswKvpY/Bx5i2IENz9E+T5EFMupEh8QQVJE pYXwKog9RhfSpz1fFXXGLVM8aTUEl2yPUMD9jzz2zskaMR+Jke5qbsTofS+pKRBDjHeh c57xPGM8RnIm9V3lnXdKQ07Ebho+qXJSTXIHTA4cJm6rumcfa1vRS5u/A6jELX2pIIhb jdLYuU67AV0tZ53o4Rj3HCj9tUBReet4sOmR98YFeznew/dvYxZ20pZnGehnYJ+xyGVT 6VKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MnpOjV/SNe6sQfK3nZ3ll5DmkqSi2WszLWuZJmb/Hwk=; b=iJIbSMOywAQ3kCJDPDKVbJ2T2SZmqOxDWS+U7I4xVb+FIsDNVMk0Io+19+vrTSgBeL uH8FI2sdQlw5WLQpl4tdXuc/2Yk1oQ6qkDVPF2S6lxN4Ov2OyWV0kXTKzWEVsdxACyBx aKPR2NSZs1pr3zKaTHadIXoxuuxCmGx4BGJnOFCy94ASdizKiOq9B3g3HY561tn48jH7 RHaxonxtUhtSodOLpY8SYZ1XItRiqdJ98RsE8fnL/ji60ULLr1DOmIqWgXN3GUkHYA7a lZQw8eCbMDU+xfU2rnuaK/CyqQmgz7LHwHfXxrcjn7GsAJRBEvLBFK2UD7H4yWvDnniq Px8Q== X-Gm-Message-State: AHQUAua0LWpvfjSQnmwlreGl3y4q0+jSpQV/G5qaLxAvAExEynq4bKnf bh9TVuU3jBZ1tes3TlZaRIP/Lw== X-Received: by 2002:a17:902:bd96:: with SMTP id q22mr622404pls.7.1551250789467; Tue, 26 Feb 2019 22:59:49 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id o6sm36475061pgo.27.2019.02.26.22.59.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Feb 2019 22:59:48 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown , Rob Herring , Mark Rutland Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] arm64: dts: qcom: sdm845: Add GEN2 PCIe controller and PHY Date: Tue, 26 Feb 2019 23:00:22 -0800 Message-Id: <20190227070022.31975-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190226070525.22453-1-bjorn.andersson@linaro.org> References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SDM845 sports two PCIe controller/phy pairs; one GEN2 and one GEN3. Add the nodes for the GEN2 pair. Signed-off-by: Bjorn Andersson --- Changes since v1: - "reg" is spelled without a 't' arch/arm64/boot/dts/qcom/sdm845.dtsi | 103 +++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5308f1671824..35887fedfd0e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1024,6 +1024,109 @@ }; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + reg = <0 0x01c00000 0 0x2000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, + <0x100 &apps_smmu 0x1c11 0x1>, + <0x200 &apps_smmu 0x1c12 0x1>, + <0x300 &apps_smmu 0x1c13 0x1>, + <0x400 &apps_smmu 0x1c14 0x1>, + <0x500 &apps_smmu 0x1c15 0x1>, + <0x600 &apps_smmu 0x1c16 0x1>, + <0x700 &apps_smmu 0x1c17 0x1>, + <0x800 &apps_smmu 0x1c18 0x1>, + <0x900 &apps_smmu 0x1c19 0x1>, + <0xa00 &apps_smmu 0x1c1a 0x1>, + <0xb00 &apps_smmu 0x1c1b 0x1>, + <0xc00 &apps_smmu 0x1c1c 0x1>, + <0xd00 &apps_smmu 0x1c1d 0x1>, + <0xe00 &apps_smmu 0x1c1e 0x1>, + <0xf00 &apps_smmu 0x1c1f 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sdm845-qmp-pcie-phy"; + reg = <0 0x01c06000 0 0x18c>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0 0x01c06200 0 0x128>, + <0 0x01c06400 0 0x1fc>, + <0 0x01c06800 0 0x218>, + <0 0x01c06600 0 0x70>; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0";