From patchwork Tue Oct 11 19:02:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 614408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42F92C4332F for ; Tue, 11 Oct 2022 19:04:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229641AbiJKTEr (ORCPT ); Tue, 11 Oct 2022 15:04:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229872AbiJKTEn (ORCPT ); Tue, 11 Oct 2022 15:04:43 -0400 Received: from mail-qk1-x72f.google.com (mail-qk1-x72f.google.com [IPv6:2607:f8b0:4864:20::72f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6B14C30 for ; Tue, 11 Oct 2022 12:04:37 -0700 (PDT) Received: by mail-qk1-x72f.google.com with SMTP id m6so4026367qkm.4 for ; Tue, 11 Oct 2022 12:04:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=0m4Z+4+FCGc7HbY9Z2fgPJugNdaCKUvzg3JKXxvmUR0=; b=kmc11stgLJRII0cVJ7VL6lBKyUVlUsme3zecN+9lmS4tWdbHIqBEoLgAMOgIM3ThDb xan8zs2Mros1EcZx7aITm69GvwmJYcdGspiCoYu4egt2S6p1fp+Wd3eTDIDfGNjy0weR r0ytWink0vB2nlM2dS1OxuYcpFz4vQZl6tPiBw5rD4YDBYAVHb1Oi5t/dVUogQyJglpo +70IjBD5NjifzF3EmkoyJQqRllyWUm3T8AzaWr2j0iRDO58s+Ag/fPxJcP99uMQH0BNq WAkF+C9PyBJmUJWEZPIIdoexE9dPC3uBOBdfdDfpBVLoXYl1598DZxCDrLrxw7Q4MWCV bmeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0m4Z+4+FCGc7HbY9Z2fgPJugNdaCKUvzg3JKXxvmUR0=; b=PWukQ1JqeE/enCt3wkEYScIbGfnSg/NxHjlWBkSpxLI6C4GU8ea9BDPPu+nAyx+ZOK 0zeZaxJggLvMWhvmBV1PDO29ozSUApQroRwBr0kTzFpj3JcQfsouonY73r/Tvlyubgo/ gh9MGP3plbi6kDL2iMU8J+C+hWR4UlJmlKCpEKVnPrUVMuCJSQWkJuZnB6rt0LEmZHOG s9B6kA1FEEv8p4bSnlt7Fp0bp3eu0xJhnKZNbVX+SNcbQrhJVqE7y3fElvkQLPoiP71X 5Yz4QnmUIzDxDnLVRLLTnfx0RlNjBbzKRmJaSXeD/35N/AeHHHfAO42lbZsj5nm2wwLv DjTw== X-Gm-Message-State: ACrzQf26VtxUe4Hf9cZKkvUsw7vrL7xGgWJ/NOlxYuPgFq3PYiZKt9Dp 9QjcJUZ2Hfrg7NnW/bF3FjdNSFnHHPC5AA== X-Google-Smtp-Source: AMsMyM6WEyQyDwvOtDQ67NgwureRA5KlNOsRDgSUOCP3t+fLwRsMI8SJqBA7MMDWhdsmqmT3ZYHR4w== X-Received: by 2002:a05:620a:2b42:b0:6ed:f368:c717 with SMTP id dp2-20020a05620a2b4200b006edf368c717mr6142164qkb.154.1665515076868; Tue, 11 Oct 2022 12:04:36 -0700 (PDT) Received: from krzk-bin.home (cpe-72-225-192-120.nyc.res.rr.com. [72.225.192.120]) by smtp.gmail.com with ESMTPSA id i14-20020a05620a248e00b006bba46e5eeasm14527185qkn.37.2022.10.11.12.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 12:04:36 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 1/4] arm64: dts: qcom: sdm630: add UART pin functions Date: Tue, 11 Oct 2022 15:02:28 -0400 Message-Id: <20221011190231.76784-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Configure UART1 and UART2 pins to respective functions in default state, otherwise the pins might stay as GPIOs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v1: 1. Add tags. --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e119060ac56c..bc7c341e793c 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -723,6 +723,7 @@ tlmm: pinctrl@3100000 { blsp1_uart1_default: blsp1-uart1-default { pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; drive-strength = <2>; bias-disable; }; @@ -735,6 +736,7 @@ blsp1_uart1_sleep: blsp1-uart1-sleep { blsp1_uart2_default: blsp1-uart2-default { pins = "gpio4", "gpio5"; + function = "blsp_uart2"; drive-strength = <2>; bias-disable; }; From patchwork Tue Oct 11 19:02:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 614941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80904C4332F for ; Tue, 11 Oct 2022 19:04:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230023AbiJKTEu (ORCPT ); Tue, 11 Oct 2022 15:04:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229971AbiJKTEp (ORCPT ); Tue, 11 Oct 2022 15:04:45 -0400 Received: from mail-qk1-x731.google.com (mail-qk1-x731.google.com [IPv6:2607:f8b0:4864:20::731]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B2F4101E for ; Tue, 11 Oct 2022 12:04:40 -0700 (PDT) Received: by mail-qk1-x731.google.com with SMTP id t25so2051634qkm.2 for ; Tue, 11 Oct 2022 12:04:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dE8hzsbFiS2HpDnMdFbB33qJkgqzciTCpdBEF4m3sf8=; b=axgcvptjFMOqgyJ2pu4sacBWLXitKO/idWP7efM5tinvkUnphIU/XUEKYyHNk8nZa1 TwT6XOQwR4i0oFJqE7J830LAbvYi+s3jKh94Spe9OS2fBaLUxhIIikdoQaz4bq5dFdZ9 x3ZLuJX7W4ZwQHVvL+kiPDGYSxvlVDmbXOmDPtkA7HoADfUaA0BnHTqpLBU6SX0khkE8 nd+e6JgnajRgjLeGeb2zOUlUV19FHq2Z1E4rsCa8ZNgG42znto4MiaikaNtW/RmZPqpk HGt2/Oup3NnJuf5WENF2e6Ct+eY4/mzKF1RA4fyBFImqN5/xUMPq0LCSzeMJep0r+jDO xwpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dE8hzsbFiS2HpDnMdFbB33qJkgqzciTCpdBEF4m3sf8=; b=7vtwogzkat4RWFcrleLLyJosrLYJj8yiwUlyVIZTmiUsOXDDNZrYm5RWCWlBSjUV5h D6237+X0Tzpx2FW57UaFiNAUazTo2DD9buPJHqBlSXhIm5GrrFeYP7krTVUiqLX3QKSF HvuJQU5chjXiyTjicIPyqQQOd6umVOFvCWrehvniMgPET7bbuyuAGDkwRKcnGaCa6lPR iCryr33twiEfWaMByGzadbEViWs0V9qJJ5Ddjvcc0wfXgkoprJOO//o814VLuhaTwyaf B90eS1JDOD82t/VLXmsemjA7WNGVVtWWS9HnJHJF19tm3IsQ24zcTIAykXX2Hxx4+e5x xXpA== X-Gm-Message-State: ACrzQf3xBGO05sx+c/wVPK6e4cuZypp4oddAtIFJ065SYiye1YyV99xv kvqXxK/YxFq/WD5XEOsILwRuGw== X-Google-Smtp-Source: AMsMyM4Z7vMjlNx9jTXMTsN4gN03gCG9IZkoyh5X129mF2Is1TZnRByfl/shy2INDW4wkiSz8BWRxg== X-Received: by 2002:a05:620a:4304:b0:6d4:56aa:430e with SMTP id u4-20020a05620a430400b006d456aa430emr18000023qko.483.1665515078656; Tue, 11 Oct 2022 12:04:38 -0700 (PDT) Received: from krzk-bin.home (cpe-72-225-192-120.nyc.res.rr.com. [72.225.192.120]) by smtp.gmail.com with ESMTPSA id i14-20020a05620a248e00b006bba46e5eeasm14527185qkn.37.2022.10.11.12.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 12:04:37 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 2/4] arm64: dts: qcom: sdm630: correct I2C8 pin functions Date: Tue, 11 Oct 2022 15:02:29 -0400 Message-Id: <20221011190231.76784-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011190231.76784-1-krzysztof.kozlowski@linaro.org> References: <20221011190231.76784-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The I2C8 pins are split into i2c8_a (GPIO30 and GPIO31) and i2c8_b (GPIO44 and GPIO52). Correct the name of function for I2C8 pins. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v1: 1. Add tags. --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index bc7c341e793c..796c19b9b2eb 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -885,14 +885,14 @@ i2c7_sleep: i2c7-sleep { i2c8_default: i2c8-default { pins = "gpio30", "gpio31"; - function = "blsp_i2c8"; + function = "blsp_i2c8_a"; drive-strength = <2>; bias-disable; }; i2c8_sleep: i2c8-sleep { pins = "gpio30", "gpio31"; - function = "blsp_i2c8"; + function = "blsp_i2c8_a"; drive-strength = <2>; bias-pull-up; }; From patchwork Tue Oct 11 19:02:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 614407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4313C43217 for ; Tue, 11 Oct 2022 19:04:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229757AbiJKTEv (ORCPT ); Tue, 11 Oct 2022 15:04:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229979AbiJKTEp (ORCPT ); Tue, 11 Oct 2022 15:04:45 -0400 Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51CED5FB9 for ; Tue, 11 Oct 2022 12:04:41 -0700 (PDT) Received: by mail-qv1-xf31.google.com with SMTP id o67so9114521qvo.13 for ; Tue, 11 Oct 2022 12:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OCrzZTkyGbZeavhMxP/y0D0DNb5GtgzKtML0oALkIig=; b=Ar8k0M0s/u9M2Mrry28hqTYCRI0T+kOUSasatR32AhsTHsgOH+Gfh+g53WoonS8Ju+ fGLTBjmCbQhcJ7iFTd4FbUDPWaivZ/pNY2CsmM1eBc+XfXpeM/Gj0o+qhOTcxV0dXxKZ 7fMvs0tzb+qhlH7CTD+TBdYE/2ws9PoP8D3w3zWP43s4uEahyJBUcFujPK5bcW67uaxy Uwpn3pEgoBwBb4scuPpfADaCy90w1Qx0Xg/gLR+8N8Y0UlDpboWPRRaAVpG9W8W6XdYw /QsKBZQYtuU1QtCRw45UoxpuHpL4deT/gxZznfv+0cblgpAOmKKrTvE7oQnE1KRLLNoY teTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OCrzZTkyGbZeavhMxP/y0D0DNb5GtgzKtML0oALkIig=; b=BgPYNYoKvxBCcJ5VcE8qB7sR6heIaNrAQ1mKfD2H4o8ETR7K7wRo6nWG5lton2zlse d7O6wnXbGbSBdO0GASIhLVvupm02vh2RjjGhM1Ck4SJEnE5iXc1UPJm2T5jcPG1Hq3vK 8qAP/3VTV/DhsaWNM0DS+iwqkDIRgzTMrkMWrPnl7i/lwXYjqTKlyIxB6NmUg+YL2Te0 IACJPGa6KqbxXXkFViURE28Rb3gArJNHyCUfWgqEEYdU3fFjg6xKx+x2Zr7dkOe4ANa1 9JuuOv7sBa1gLPNXC9OI1zhhjV7Vs6daUm0gLmhqKuh6kygivcVn3c4T8WldWOx7o8RW +wSA== X-Gm-Message-State: ACrzQf3VPnVMAMps0yGRZ9qsuyVjBhedUSiHyXwwI2BANHuIstrclzWb wpJ2u3/5w+hfpKM806jyTPLrNA== X-Google-Smtp-Source: AMsMyM5kb3I0Qm0ETwFg9XQ1S8V3EprPQMoycQmJLCU5wMw2KhQiAhwdpwOXAEr/uTgbyr4hhqODTA== X-Received: by 2002:a05:6214:29c5:b0:4b1:9c45:c6dc with SMTP id gh5-20020a05621429c500b004b19c45c6dcmr21019581qvb.2.1665515080369; Tue, 11 Oct 2022 12:04:40 -0700 (PDT) Received: from krzk-bin.home (cpe-72-225-192-120.nyc.res.rr.com. [72.225.192.120]) by smtp.gmail.com with ESMTPSA id i14-20020a05620a248e00b006bba46e5eeasm14527185qkn.37.2022.10.11.12.04.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 12:04:39 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 3/4] arm64: dts: qcom: sdm630: align TLMM pin configuration with DT schema Date: Tue, 11 Oct 2022 15:02:30 -0400 Message-Id: <20221011190231.76784-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011190231.76784-1-krzysztof.kozlowski@linaro.org> References: <20221011190231.76784-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. All nodes for GPIOs must also define the function property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v1: 1. Add tags. --- .../boot/dts/qcom/sda660-inforce-ifc6560.dts | 6 +- .../dts/qcom/sdm630-sony-xperia-nile.dtsi | 18 ++- arch/arm64/boot/dts/qcom/sdm630.dtsi | 121 ++++++++---------- .../sdm636-sony-xperia-ganges-mermaid.dts | 2 +- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 6 +- 5 files changed, 75 insertions(+), 78 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 28050bc5f081..f8f8a9f35e27 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -401,16 +401,18 @@ vreg_bob: bob { }; &sdc2_state_on { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; &sdc2_state_off { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-disable; drive-strength = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 09c07800793a..d604a9675508 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -577,16 +577,18 @@ vreg_l19a_3p3: l19 { }; &sdc2_state_on { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; &sdc2_state_off { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-disable; drive-strength = <2>; }; @@ -615,33 +617,35 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <8 4>; - ts_int_active: ts-int-active { + ts_int_active: ts-int-active-state { pins = "gpio45"; + function = "gpio"; drive-strength = <8>; bias-pull-up; }; - ts_lcd_id_active: ts-lcd-id-active { + ts_lcd_id_active: ts-lcd-id-active-state { pins = "gpio56"; + function = "gpio"; drive-strength = <8>; bias-disable; }; - imx300_vana_default: imx300-vana-default { + imx300_vana_default: imx300-vana-default-state { pins = "gpio50"; function = "gpio"; bias-disable; drive-strength = <2>; }; - imx219_vana_default: imx219-vana-default { + imx219_vana_default: imx219-vana-default-state { pins = "gpio51"; function = "gpio"; bias-disable; drive-strength = <2>; }; - cam_vdig_default: cam-vdig-default { + cam_vdig_default: cam-vdig-default-state { pins = "gpio52"; function = "gpio"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 796c19b9b2eb..41481493c1e5 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -721,35 +721,36 @@ tlmm: pinctrl@3100000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_uart1_default: blsp1-uart1-default { + blsp1_uart1_default: blsp1-uart1-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart1"; drive-strength = <2>; bias-disable; }; - blsp1_uart1_sleep: blsp1-uart1-sleep { + blsp1_uart1_sleep: blsp1-uart1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp1_uart2_default: blsp1-uart2-default { + blsp1_uart2_default: blsp1-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; drive-strength = <2>; bias-disable; }; - blsp2_uart1_default: blsp2-uart1-active { - tx-rts { + blsp2_uart1_default: blsp2-uart1-active-state { + tx-rts-pins { pins = "gpio16", "gpio19"; function = "blsp_uart5"; drive-strength = <2>; bias-disable; }; - rx { + rx-pins { /* * Avoid garbage data while BT module * is powered off or not driving signal @@ -760,7 +761,7 @@ rx { bias-pull-up; }; - cts { + cts-pins { /* Match the pull of the BT module */ pins = "gpio18"; function = "blsp_uart5"; @@ -769,15 +770,15 @@ cts { }; }; - blsp2_uart1_sleep: blsp2-uart1-sleep { - tx { + blsp2_uart1_sleep: blsp2-uart1-sleep-state { + tx-pins { pins = "gpio16"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - rx-cts-rts { + rx-cts-rts-pins { pins = "gpio17", "gpio18", "gpio19"; function = "gpio"; drive-strength = <2>; @@ -785,228 +786,216 @@ rx-cts-rts { }; }; - i2c1_default: i2c1-default { + i2c1_default: i2c1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; - i2c1_sleep: i2c1-sleep { + i2c1_sleep: i2c1-sleep-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-pull-up; }; - i2c2_default: i2c2-default { + i2c2_default: i2c2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - i2c2_sleep: i2c2-sleep { + i2c2_sleep: i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; drive-strength = <2>; bias-pull-up; }; - i2c3_default: i2c3-default { + i2c3_default: i2c3-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; drive-strength = <2>; bias-disable; }; - i2c3_sleep: i2c3-sleep { + i2c3_sleep: i2c3-sleep-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; drive-strength = <2>; bias-pull-up; }; - i2c4_default: i2c4-default { + i2c4_default: i2c4-default-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; - i2c4_sleep: i2c4-sleep { + i2c4_sleep: i2c4-sleep-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; drive-strength = <2>; bias-pull-up; }; - i2c5_default: i2c5-default { + i2c5_default: i2c5-default-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; - i2c5_sleep: i2c5-sleep { + i2c5_sleep: i2c5-sleep-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; drive-strength = <2>; bias-pull-up; }; - i2c6_default: i2c6-default { + i2c6_default: i2c6-default-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; - i2c6_sleep: i2c6-sleep { + i2c6_sleep: i2c6-sleep-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; drive-strength = <2>; bias-pull-up; }; - i2c7_default: i2c7-default { + i2c7_default: i2c7-default-state { pins = "gpio26", "gpio27"; function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; - i2c7_sleep: i2c7-sleep { + i2c7_sleep: i2c7-sleep-state { pins = "gpio26", "gpio27"; function = "blsp_i2c7"; drive-strength = <2>; bias-pull-up; }; - i2c8_default: i2c8-default { + i2c8_default: i2c8-default-state { pins = "gpio30", "gpio31"; function = "blsp_i2c8_a"; drive-strength = <2>; bias-disable; }; - i2c8_sleep: i2c8-sleep { + i2c8_sleep: i2c8-sleep-state { pins = "gpio30", "gpio31"; function = "blsp_i2c8_a"; drive-strength = <2>; bias-pull-up; }; - cci0_default: cci0_default { - pinmux { - pins = "gpio36","gpio37"; - function = "cci_i2c"; - }; - - pinconf { - pins = "gpio36","gpio37"; - bias-pull-up; - drive-strength = <2>; - }; + cci0_default: cci0-default-state { + pins = "gpio36","gpio37"; + function = "cci_i2c"; + bias-pull-up; + drive-strength = <2>; }; - cci1_default: cci1_default { - pinmux { - pins = "gpio38","gpio39"; - function = "cci_i2c"; - }; - - pinconf { - pins = "gpio38","gpio39"; - bias-pull-up; - drive-strength = <2>; - }; + cci1_default: cci1-default-state { + pins = "gpio38","gpio39"; + function = "cci_i2c"; + bias-pull-up; + drive-strength = <2>; }; - sdc1_state_on: sdc1-on { - clk { + sdc1_state_on: sdc1-on-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc1_state_off: sdc1-off { - clk { + sdc1_state_off: sdc1-off-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc2_state_on: sdc2-on { - clk { + sdc2_state_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_state_off: sdc2-off { - clk { + sdc2_state_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index 58f687fc49e0..9702e5f59a1d 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -19,7 +19,7 @@ / { }; &sdc2_state_on { - clk { + clk-pins { drive-strength = <14>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index a3559f6e34a5..270091db48fc 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -372,16 +372,18 @@ &pm660l_wled { }; &sdc2_state_on { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; &sdc2_state_off { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-disable; drive-strength = <2>; }; From patchwork Tue Oct 11 19:02:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 614940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC7D2C433F5 for ; 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[72.225.192.120]) by smtp.gmail.com with ESMTPSA id i14-20020a05620a248e00b006bba46e5eeasm14527185qkn.37.2022.10.11.12.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 12:04:41 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v2 4/4] dt-bindings: pinctrl: qcom, sdm630: convert to dtschema Date: Tue, 11 Oct 2022 15:02:31 -0400 Message-Id: <20221011190231.76784-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011190231.76784-1-krzysztof.kozlowski@linaro.org> References: <20221011190231.76784-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert Qualcomm SDM630 and SDM660 pin controller bindings to DT schema. Keep the parsing of pin configuration subnodes consistent with other Qualcomm schemas (children named with '-state' suffix, their children with '-pins'). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson --- Changes since v1: 1. Add tags. 2. Adjust a bit bindings description to match other bindings. 3. Add tlmm label to example, because it is used in gpio-ranges. --- .../bindings/pinctrl/qcom,sdm630-pinctrl.yaml | 188 +++++++++++++++++ .../bindings/pinctrl/qcom,sdm660-pinctrl.txt | 191 ------------------ 2 files changed, 188 insertions(+), 191 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml new file mode 100644 index 000000000000..bd4fd8404aa4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM630 and SDM660 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + enum: + - qcom,sdm630-pinctrl + - qcom,sdm660-pinctrl + + reg: + maxItems: 3 + + reg-names: + items: + - const: south + - const: center + - const: north + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 57 + + gpio-line-names: + maxItems: 114 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm630-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm630-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdm630-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, + atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1, + atest_tsens, atest_tsens2, atest_usb1, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, + atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0, + bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b, + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, + blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a, + blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, + blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1, + blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1, + gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c, + isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync, + mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte, + nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0, + phase_flag1, phase_flag10, phase_flag11, phase_flag12, + phase_flag13, phase_flag14, phase_flag15, phase_flag16, + phase_flag17, phase_flag18, phase_flag19, phase_flag2, + phase_flag20, phase_flag21, phase_flag22, phase_flag23, + phase_flag24, phase_flag25, phase_flag26, phase_flag27, + phase_flag28, phase_flag29, phase_flag3, phase_flag30, + phase_flag31, phase_flag4, phase_flag5, phase_flag6, + phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem, + pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b, + qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, + qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2, + qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7, + qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk, + qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3, + qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu, + ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk, + uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout, + vsense_data0, vsense_data1, vsense_mode, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1 ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + tlmm: pinctrl@3100000 { + compatible = "qcom,sdm630-pinctrl"; + reg = <0x03100000 0x400000>, + <0x03500000 0x400000>, + <0x03900000 0x400000>; + reg-names = "south", "center", "north"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 114>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_uart1_default: blsp2-uart1-active-state { + tx-rts-pins { + pins = "gpio16", "gpio19"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio17"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-pull-up; + }; + + cts-pins { + pins = "gpio18"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt deleted file mode 100644 index be034d329e10..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt +++ /dev/null @@ -1,191 +0,0 @@ -Qualcomm Technologies, Inc. SDM660 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -SDM660 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,sdm660-pinctrl" or - "qcom,sdm630-pinctrl". - -- reg: - Usage: required - Value type: - Definition: the base address and size of the north, center and south - TLMM tiles. - -- reg-names: - Usage: required - Value type: - Definition: names for the cells of reg, must contain "north", "center" - and "south". - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- gpio-ranges: - Usage: required - Value type: - Definition: Specifies the mapping between gpio controller and - pin-controller pins. - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio113, - Supports mux, bias and drive-strength - sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk, - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, - atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1, - atest_tsens, atest_tsens2, atest_usb1, atest_usb10, - atest_usb11, atest_usb12, atest_usb13, atest_usb2, - atest_usb20, atest_usb21, atest_usb22, atest_usb23, - audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, - blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, - blsp_i2c8_a, blsp_i2c8_b, blsp_spi1, blsp_spi2, blsp_spi3, - blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi4, blsp_spi5, - blsp_spi6, blsp_spi7, blsp_spi8_a, blsp_spi8_b, - blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, blsp_uart2, - blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1, - blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, - cci_i2c, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, - gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c, - isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync, - mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte, - nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0, - phase_flag1, phase_flag10, phase_flag11, phase_flag12, - phase_flag13, phase_flag14, phase_flag15, phase_flag16, - phase_flag17, phase_flag18, phase_flag19, phase_flag2, - phase_flag20, phase_flag21, phase_flag22, phase_flag23, - phase_flag24, phase_flag25, phase_flag26, phase_flag27, - phase_flag28, phase_flag29, phase_flag3, phase_flag30, - phase_flag31, phase_flag4, phase_flag5, phase_flag6, - phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, - pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, - pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, - qdss_cti1_b, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, - qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, - qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, - qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, - qspi_clk, qspi_cs, qspi_data0, qspi_data1, qspi_data2, - qspi_data3, qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, - sp_cmu, ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, - uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, - uim2_data, uim2_present, uim2_reset, uim_batt, vfr_1, - vsense_clkout, vsense_data0, vsense_data1, vsense_mode, - wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1 - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@3100000 { - compatible = "qcom,sdm660-pinctrl"; - reg = <0x3100000 0x200000>, - <0x3500000 0x200000>, - <0x3900000 0x200000>; - reg-names = "south", "center", "north"; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 114>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - };