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[209.132.180.67]) by mx.google.com with ESMTP id d37si18027945pla.71.2019.02.28.04.24.34; Thu, 28 Feb 2019 04:24:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="FHv5/3Qs"; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727983AbfB1MYd (ORCPT + 15 others); Thu, 28 Feb 2019 07:24:33 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:40207 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727045AbfB1MYd (ORCPT ); Thu, 28 Feb 2019 07:24:33 -0500 Received: by mail-wr1-f66.google.com with SMTP id q1so21746651wrp.7 for ; Thu, 28 Feb 2019 04:24:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=s/+Bl7ZGzK0cL5xDzP2iXR4sdWkOPpcYJr4QjVnhB2E=; b=FHv5/3QsYZsBwUeIBgPR5t5jkcQPpkYT+0oAjA7sbdOf4GNbAOAXyYZaek77Q/BZGG LSxBO4H40P62B2pFtiUD+8j6gk3Sx34QrrVN97TdKxBOSY/AIEMElPDoguGzfKhXJ2P4 vVaH4hWmMpTdfW4dRlm+augjxfvQDhyoLLoT34K6NUkIdZF5f+qC8li/NDl7q6zORycZ t2/7KRKNLG/ZpBG6aPazAXpLWTwe64YeuwzJWmqW03jMeWJqWf2Ql2o6XdU32sNxwZ+2 SBOvSz9CTpT9AamQgVf3+/RHljoufsLmDSbMattOmjLqxl+cYXPWz6tye1zkGcFz+8Nf cKgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=s/+Bl7ZGzK0cL5xDzP2iXR4sdWkOPpcYJr4QjVnhB2E=; b=riKZgLNd7Rd68fyeaHIk+NnHOMZkaU/ObPAq3AUKmPcoBW/ERvcfBTGaLxGph9DdRN HAM0jAkR8+WHa/PLRkQKb7zvbsrZMPSp9LsajqbnySjj+3JQ1FXjHfUp2y0V7rFcYBW1 /8xTIpmP6XjZ578ZdRjGhHdJSFIq6BSZy+cp99lDO1JfYqLdhbhUGxQNfelwJHNxXfhn wRr0FP5BoCXHdDGsejRWFLP9O3P5UdteBEnL+i0beRBUNplytj/sSyj5Fvpsn53aizu9 ZDXTMHbqvVgUjEsQSek2ImsMD01Yp3Q6qPVnmvno2KNUeCqWjfNBlvFgATNGTjpRm+GL /xeg== X-Gm-Message-State: APjAAAXj9tBeYfk2Gb49iZxhhVMkzhYg6tCwChOCdX2ljFSjYL4CQSrL KVPQ1h5+5uunwYOo0KjI7deZLg== X-Received: by 2002:adf:df0d:: with SMTP id y13mr5951104wrl.69.1551356670903; Thu, 28 Feb 2019 04:24:30 -0800 (PST) Received: from localhost ([49.248.54.130]) by smtp.gmail.com with ESMTPSA id s3sm24901915wrt.81.2019.02.28.04.24.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Feb 2019 04:24:30 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v2 08/24] drivers: thermal: tsens: Rename constants to prepare to merge with tsens-8974 Date: Thu, 28 Feb 2019 17:50:58 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some #defines in tsens-v_0_1.c clash with those in tsens-8974.c. Prefix them with 8916 to avoid the clash so we can merge the two files. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-v0_1.c | 88 +++++++++++++++---------------- 1 file changed, 44 insertions(+), 44 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index d4ad4082c800..30909594b1cf 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -7,37 +7,37 @@ #include "tsens.h" /* eeprom layout data for 8916 */ -#define BASE0_MASK 0x0000007f -#define BASE1_MASK 0xfe000000 -#define BASE0_SHIFT 0 -#define BASE1_SHIFT 25 - -#define S0_P1_MASK 0x00000f80 -#define S1_P1_MASK 0x003e0000 -#define S2_P1_MASK 0xf8000000 -#define S3_P1_MASK 0x000003e0 -#define S4_P1_MASK 0x000f8000 - -#define S0_P2_MASK 0x0001f000 -#define S1_P2_MASK 0x07c00000 -#define S2_P2_MASK 0x0000001f -#define S3_P2_MASK 0x00007c00 -#define S4_P2_MASK 0x01f00000 - -#define S0_P1_SHIFT 7 -#define S1_P1_SHIFT 17 -#define S2_P1_SHIFT 27 -#define S3_P1_SHIFT 5 -#define S4_P1_SHIFT 15 - -#define S0_P2_SHIFT 12 -#define S1_P2_SHIFT 22 -#define S2_P2_SHIFT 0 -#define S3_P2_SHIFT 10 -#define S4_P2_SHIFT 20 - -#define CAL_SEL_MASK 0xe0000000 -#define CAL_SEL_SHIFT 29 +#define MSM8916_BASE0_MASK 0x0000007f +#define MSM8916_BASE1_MASK 0xfe000000 +#define MSM8916_BASE0_SHIFT 0 +#define MSM8916_BASE1_SHIFT 25 + +#define MSM8916_S0_P1_MASK 0x00000f80 +#define MSM8916_S1_P1_MASK 0x003e0000 +#define MSM8916_S2_P1_MASK 0xf8000000 +#define MSM8916_S3_P1_MASK 0x000003e0 +#define MSM8916_S4_P1_MASK 0x000f8000 + +#define MSM8916_S0_P2_MASK 0x0001f000 +#define MSM8916_S1_P2_MASK 0x07c00000 +#define MSM8916_S2_P2_MASK 0x0000001f +#define MSM8916_S3_P2_MASK 0x00007c00 +#define MSM8916_S4_P2_MASK 0x01f00000 + +#define MSM8916_S0_P1_SHIFT 7 +#define MSM8916_S1_P1_SHIFT 17 +#define MSM8916_S2_P1_SHIFT 27 +#define MSM8916_S3_P1_SHIFT 5 +#define MSM8916_S4_P1_SHIFT 15 + +#define MSM8916_S0_P2_SHIFT 12 +#define MSM8916_S1_P2_SHIFT 22 +#define MSM8916_S2_P2_SHIFT 0 +#define MSM8916_S3_P2_SHIFT 10 +#define MSM8916_S4_P2_SHIFT 20 + +#define MSM8916_CAL_SEL_MASK 0xe0000000 +#define MSM8916_CAL_SEL_SHIFT 29 static int calibrate_8916(struct tsens_priv *priv) { @@ -54,27 +54,27 @@ static int calibrate_8916(struct tsens_priv *priv) if (IS_ERR(qfprom_csel)) return PTR_ERR(qfprom_csel); - mode = (qfprom_csel[0] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; + mode = (qfprom_csel[0] & MSM8916_CAL_SEL_MASK) >> MSM8916_CAL_SEL_SHIFT; dev_dbg(priv->dev, "calibration mode is %d\n", mode); switch (mode) { case TWO_PT_CALIB: - base1 = (qfprom_cdata[1] & BASE1_MASK) >> BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & S2_P2_MASK) >> S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; - p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; + base1 = (qfprom_cdata[1] & MSM8916_BASE1_MASK) >> MSM8916_BASE1_SHIFT; + p2[0] = (qfprom_cdata[0] & MSM8916_S0_P2_MASK) >> MSM8916_S0_P2_SHIFT; + p2[1] = (qfprom_cdata[0] & MSM8916_S1_P2_MASK) >> MSM8916_S1_P2_SHIFT; + p2[2] = (qfprom_cdata[1] & MSM8916_S2_P2_MASK) >> MSM8916_S2_P2_SHIFT; + p2[3] = (qfprom_cdata[1] & MSM8916_S3_P2_MASK) >> MSM8916_S3_P2_SHIFT; + p2[4] = (qfprom_cdata[1] & MSM8916_S4_P2_MASK) >> MSM8916_S4_P2_SHIFT; for (i = 0; i < priv->num_sensors; i++) p2[i] = ((base1 + p2[i]) << 3); /* Fall through */ case ONE_PT_CALIB2: - base0 = (qfprom_cdata[0] & BASE0_MASK); - p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; + base0 = (qfprom_cdata[0] & MSM8916_BASE0_MASK); + p1[0] = (qfprom_cdata[0] & MSM8916_S0_P1_MASK) >> MSM8916_S0_P1_SHIFT; + p1[1] = (qfprom_cdata[0] & MSM8916_S1_P1_MASK) >> MSM8916_S1_P1_SHIFT; + p1[2] = (qfprom_cdata[0] & MSM8916_S2_P1_MASK) >> MSM8916_S2_P1_SHIFT; + p1[3] = (qfprom_cdata[1] & MSM8916_S3_P1_MASK) >> MSM8916_S3_P1_SHIFT; + p1[4] = (qfprom_cdata[1] & MSM8916_S4_P1_MASK) >> MSM8916_S4_P1_SHIFT; for (i = 0; i < priv->num_sensors; i++) p1[i] = (((base0) + p1[i]) << 3); break; From patchwork Thu Feb 28 12:20:59 2019 Content-Type: text/plain; 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Merge the files to allow for better code reuse. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/Makefile | 2 +- drivers/thermal/qcom/tsens-8974.c | 236 ------------------------------ drivers/thermal/qcom/tsens-v0_1.c | 229 +++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.h | 8 +- 4 files changed, 236 insertions(+), 239 deletions(-) delete mode 100644 drivers/thermal/qcom/tsens-8974.c -- 2.17.1 diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 1f2fafd43dff..7fa3cadce760 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o tsens-8974.o tsens-8960.o tsens-v2.o +qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o tsens-8960.o tsens-v2.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o diff --git a/drivers/thermal/qcom/tsens-8974.c b/drivers/thermal/qcom/tsens-8974.c deleted file mode 100644 index 303157fd00be..000000000000 --- a/drivers/thermal/qcom/tsens-8974.c +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#include -#include "tsens.h" - -/* eeprom layout data for 8974 */ -#define BASE1_MASK 0xff -#define S0_P1_MASK 0x3f00 -#define S1_P1_MASK 0xfc000 -#define S2_P1_MASK 0x3f00000 -#define S3_P1_MASK 0xfc000000 -#define S4_P1_MASK 0x3f -#define S5_P1_MASK 0xfc0 -#define S6_P1_MASK 0x3f000 -#define S7_P1_MASK 0xfc0000 -#define S8_P1_MASK 0x3f000000 -#define S8_P1_MASK_BKP 0x3f -#define S9_P1_MASK 0x3f -#define S9_P1_MASK_BKP 0xfc0 -#define S10_P1_MASK 0xfc0 -#define S10_P1_MASK_BKP 0x3f000 -#define CAL_SEL_0_1 0xc0000000 -#define CAL_SEL_2 0x40000000 -#define CAL_SEL_SHIFT 30 -#define CAL_SEL_SHIFT_2 28 - -#define S0_P1_SHIFT 8 -#define S1_P1_SHIFT 14 -#define S2_P1_SHIFT 20 -#define S3_P1_SHIFT 26 -#define S5_P1_SHIFT 6 -#define S6_P1_SHIFT 12 -#define S7_P1_SHIFT 18 -#define S8_P1_SHIFT 24 -#define S9_P1_BKP_SHIFT 6 -#define S10_P1_SHIFT 6 -#define S10_P1_BKP_SHIFT 12 - -#define BASE2_SHIFT 12 -#define BASE2_BKP_SHIFT 18 -#define S0_P2_SHIFT 20 -#define S0_P2_BKP_SHIFT 26 -#define S1_P2_SHIFT 26 -#define S2_P2_BKP_SHIFT 6 -#define S3_P2_SHIFT 6 -#define S3_P2_BKP_SHIFT 12 -#define S4_P2_SHIFT 12 -#define S4_P2_BKP_SHIFT 18 -#define S5_P2_SHIFT 18 -#define S5_P2_BKP_SHIFT 24 -#define S6_P2_SHIFT 24 -#define S7_P2_BKP_SHIFT 6 -#define S8_P2_SHIFT 6 -#define S8_P2_BKP_SHIFT 12 -#define S9_P2_SHIFT 12 -#define S9_P2_BKP_SHIFT 18 -#define S10_P2_SHIFT 18 -#define S10_P2_BKP_SHIFT 24 - -#define BASE2_MASK 0xff000 -#define BASE2_BKP_MASK 0xfc0000 -#define S0_P2_MASK 0x3f00000 -#define S0_P2_BKP_MASK 0xfc000000 -#define S1_P2_MASK 0xfc000000 -#define S1_P2_BKP_MASK 0x3f -#define S2_P2_MASK 0x3f -#define S2_P2_BKP_MASK 0xfc0 -#define S3_P2_MASK 0xfc0 -#define S3_P2_BKP_MASK 0x3f000 -#define S4_P2_MASK 0x3f000 -#define S4_P2_BKP_MASK 0xfc0000 -#define S5_P2_MASK 0xfc0000 -#define S5_P2_BKP_MASK 0x3f000000 -#define S6_P2_MASK 0x3f000000 -#define S6_P2_BKP_MASK 0x3f -#define S7_P2_MASK 0x3f -#define S7_P2_BKP_MASK 0xfc0 -#define S8_P2_MASK 0xfc0 -#define S8_P2_BKP_MASK 0x3f000 -#define S9_P2_MASK 0x3f000 -#define S9_P2_BKP_MASK 0xfc0000 -#define S10_P2_MASK 0xfc0000 -#define S10_P2_BKP_MASK 0x3f000000 - -#define BKP_SEL 0x3 -#define BKP_REDUN_SEL 0xe0000000 -#define BKP_REDUN_SHIFT 29 - -#define BIT_APPEND 0x3 - -static int calibrate_8974(struct tsens_priv *priv) -{ - int base1 = 0, base2 = 0, i; - u32 p1[11], p2[11]; - int mode = 0; - u32 *calib, *bkp; - u32 calib_redun_sel; - - calib = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(calib)) - return PTR_ERR(calib); - - bkp = (u32 *)qfprom_read(priv->dev, "calib_backup"); - if (IS_ERR(bkp)) - return PTR_ERR(bkp); - - calib_redun_sel = bkp[1] & BKP_REDUN_SEL; - calib_redun_sel >>= BKP_REDUN_SHIFT; - - if (calib_redun_sel == BKP_SEL) { - mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT; - p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT; - p2[1] = (bkp[3] & S1_P2_BKP_MASK); - p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT; - p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT; - p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT; - p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT; - p2[6] = (calib[5] & S6_P2_BKP_MASK); - p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT; - p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT; - p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT; - p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT; - /* Fall through */ - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = bkp[0] & BASE1_MASK; - p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (bkp[1] & S4_P1_MASK); - p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT; - p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT; - p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT; - break; - } - } else { - mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT; - p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT; - p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT; - p2[2] = (calib[3] & S2_P2_MASK); - p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT; - p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT; - p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT; - p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT; - p2[7] = (calib[4] & S7_P2_MASK); - p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT; - p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT; - p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT; - /* Fall through */ - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = calib[0] & BASE1_MASK; - p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (calib[1] & S4_P1_MASK); - p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT; - p1[9] = (calib[2] & S9_P1_MASK); - p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT; - break; - } - } - - switch (mode) { - case ONE_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) - p1[i] += (base1 << 2) | BIT_APPEND; - break; - case TWO_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) { - p2[i] += base2; - p2[i] <<= 2; - p2[i] |= BIT_APPEND; - } - /* Fall through */ - case ONE_PT_CALIB2: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] += base1; - p1[i] <<= 2; - p1[i] |= BIT_APPEND; - } - break; - default: - for (i = 0; i < priv->num_sensors; i++) - p2[i] = 780; - p1[0] = 502; - p1[1] = 509; - p1[2] = 503; - p1[3] = 509; - p1[4] = 505; - p1[5] = 509; - p1[6] = 507; - p1[7] = 510; - p1[8] = 508; - p1[9] = 509; - p1[10] = 508; - break; - } - - compute_intercept_slope(priv, p1, p2, mode); - - return 0; -} - -static const struct tsens_ops ops_8974 = { - .init = init_common, - .calibrate = calibrate_8974, - .get_temp = get_temp_common, -}; - -const struct tsens_plat_data data_8974 = { - .num_sensors = 11, - .ops = &ops_8974, - .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, -}; diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 30909594b1cf..a6e26be1234f 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -39,6 +39,91 @@ #define MSM8916_CAL_SEL_MASK 0xe0000000 #define MSM8916_CAL_SEL_SHIFT 29 +/* eeprom layout data for 8974 */ +#define BASE1_MASK 0xff +#define S0_P1_MASK 0x3f00 +#define S1_P1_MASK 0xfc000 +#define S2_P1_MASK 0x3f00000 +#define S3_P1_MASK 0xfc000000 +#define S4_P1_MASK 0x3f +#define S5_P1_MASK 0xfc0 +#define S6_P1_MASK 0x3f000 +#define S7_P1_MASK 0xfc0000 +#define S8_P1_MASK 0x3f000000 +#define S8_P1_MASK_BKP 0x3f +#define S9_P1_MASK 0x3f +#define S9_P1_MASK_BKP 0xfc0 +#define S10_P1_MASK 0xfc0 +#define S10_P1_MASK_BKP 0x3f000 +#define CAL_SEL_0_1 0xc0000000 +#define CAL_SEL_2 0x40000000 +#define CAL_SEL_SHIFT 30 +#define CAL_SEL_SHIFT_2 28 + +#define S0_P1_SHIFT 8 +#define S1_P1_SHIFT 14 +#define S2_P1_SHIFT 20 +#define S3_P1_SHIFT 26 +#define S5_P1_SHIFT 6 +#define S6_P1_SHIFT 12 +#define S7_P1_SHIFT 18 +#define S8_P1_SHIFT 24 +#define S9_P1_BKP_SHIFT 6 +#define S10_P1_SHIFT 6 +#define S10_P1_BKP_SHIFT 12 + +#define BASE2_SHIFT 12 +#define BASE2_BKP_SHIFT 18 +#define S0_P2_SHIFT 20 +#define S0_P2_BKP_SHIFT 26 +#define S1_P2_SHIFT 26 +#define S2_P2_BKP_SHIFT 6 +#define S3_P2_SHIFT 6 +#define S3_P2_BKP_SHIFT 12 +#define S4_P2_SHIFT 12 +#define S4_P2_BKP_SHIFT 18 +#define S5_P2_SHIFT 18 +#define S5_P2_BKP_SHIFT 24 +#define S6_P2_SHIFT 24 +#define S7_P2_BKP_SHIFT 6 +#define S8_P2_SHIFT 6 +#define S8_P2_BKP_SHIFT 12 +#define S9_P2_SHIFT 12 +#define S9_P2_BKP_SHIFT 18 +#define S10_P2_SHIFT 18 +#define S10_P2_BKP_SHIFT 24 + +#define BASE2_MASK 0xff000 +#define BASE2_BKP_MASK 0xfc0000 +#define S0_P2_MASK 0x3f00000 +#define S0_P2_BKP_MASK 0xfc000000 +#define S1_P2_MASK 0xfc000000 +#define S1_P2_BKP_MASK 0x3f +#define S2_P2_MASK 0x3f +#define S2_P2_BKP_MASK 0xfc0 +#define S3_P2_MASK 0xfc0 +#define S3_P2_BKP_MASK 0x3f000 +#define S4_P2_MASK 0x3f000 +#define S4_P2_BKP_MASK 0xfc0000 +#define S5_P2_MASK 0xfc0000 +#define S5_P2_BKP_MASK 0x3f000000 +#define S6_P2_MASK 0x3f000000 +#define S6_P2_BKP_MASK 0x3f +#define S7_P2_MASK 0x3f +#define S7_P2_BKP_MASK 0xfc0 +#define S8_P2_MASK 0xfc0 +#define S8_P2_BKP_MASK 0x3f000 +#define S9_P2_MASK 0x3f000 +#define S9_P2_BKP_MASK 0xfc0000 +#define S10_P2_MASK 0xfc0000 +#define S10_P2_BKP_MASK 0x3f000000 + +#define BKP_SEL 0x3 +#define BKP_REDUN_SEL 0xe0000000 +#define BKP_REDUN_SHIFT 29 + +#define BIT_APPEND 0x3 + static int calibrate_8916(struct tsens_priv *priv) { int base0 = 0, base1 = 0, i; @@ -91,6 +176,138 @@ static int calibrate_8916(struct tsens_priv *priv) return 0; } +static int calibrate_8974(struct tsens_priv *priv) +{ + int base1 = 0, base2 = 0, i; + u32 p1[11], p2[11]; + int mode = 0; + u32 *calib, *bkp; + u32 calib_redun_sel; + + calib = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(calib)) + return PTR_ERR(calib); + + bkp = (u32 *)qfprom_read(priv->dev, "calib_backup"); + if (IS_ERR(bkp)) + return PTR_ERR(bkp); + + calib_redun_sel = bkp[1] & BKP_REDUN_SEL; + calib_redun_sel >>= BKP_REDUN_SHIFT; + + if (calib_redun_sel == BKP_SEL) { + mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; + mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; + + switch (mode) { + case TWO_PT_CALIB: + base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT; + p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT; + p2[1] = (bkp[3] & S1_P2_BKP_MASK); + p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT; + p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT; + p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT; + p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT; + p2[6] = (calib[5] & S6_P2_BKP_MASK); + p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT; + p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT; + p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT; + p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT; + /* Fall through */ + case ONE_PT_CALIB: + case ONE_PT_CALIB2: + base1 = bkp[0] & BASE1_MASK; + p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (bkp[1] & S4_P1_MASK); + p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT; + p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT; + p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT; + break; + } + } else { + mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; + mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; + + switch (mode) { + case TWO_PT_CALIB: + base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT; + p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT; + p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT; + p2[2] = (calib[3] & S2_P2_MASK); + p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT; + p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT; + p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT; + p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT; + p2[7] = (calib[4] & S7_P2_MASK); + p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT; + p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT; + p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT; + /* Fall through */ + case ONE_PT_CALIB: + case ONE_PT_CALIB2: + base1 = calib[0] & BASE1_MASK; + p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (calib[1] & S4_P1_MASK); + p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT; + p1[9] = (calib[2] & S9_P1_MASK); + p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT; + break; + } + } + + switch (mode) { + case ONE_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p1[i] += (base1 << 2) | BIT_APPEND; + break; + case TWO_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) { + p2[i] += base2; + p2[i] <<= 2; + p2[i] |= BIT_APPEND; + } + /* Fall through */ + case ONE_PT_CALIB2: + for (i = 0; i < priv->num_sensors; i++) { + p1[i] += base1; + p1[i] <<= 2; + p1[i] |= BIT_APPEND; + } + break; + default: + for (i = 0; i < priv->num_sensors; i++) + p2[i] = 780; + p1[0] = 502; + p1[1] = 509; + p1[2] = 503; + p1[3] = 509; + p1[4] = 505; + p1[5] = 509; + p1[6] = 507; + p1[7] = 510; + p1[8] = 508; + p1[9] = 509; + p1[10] = 508; + break; + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + static const struct tsens_ops ops_8916 = { .init = init_common, .calibrate = calibrate_8916, @@ -103,3 +320,15 @@ const struct tsens_plat_data data_8916 = { .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, .hw_ids = (unsigned int []){0, 1, 2, 4, 5 }, }; + +static const struct tsens_ops ops_8974 = { + .init = init_common, + .calibrate = calibrate_8974, + .get_temp = get_temp_common, +}; + +const struct tsens_plat_data data_8974 = { + .num_sensors = 11, + .ops = &ops_8974, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, +}; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 4d6a406f8dca..27b8f74829d9 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -116,8 +116,12 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo int init_common(struct tsens_priv *priv); int get_temp_common(struct tsens_priv *priv, int i, int *temp); -/* TSENS v1 targets */ -extern const struct tsens_plat_data data_8916, data_8974, data_8960; +/* TSENS target */ +extern const struct tsens_plat_data data_8960; + +/* TSENS v0.1 targets */ +extern const struct tsens_plat_data data_8916, data_8974; + /* TSENS v2 targets */ extern const struct tsens_plat_data data_8996, data_tsens_v2; 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[209.132.180.67]) by mx.google.com with ESMTP id s4si17862221pgh.540.2019.02.28.04.27.10; Thu, 28 Feb 2019 04:27:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dOyjeR8Z; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731313AbfB1M1K (ORCPT + 15 others); Thu, 28 Feb 2019 07:27:10 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:33101 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730852AbfB1M1J (ORCPT ); Thu, 28 Feb 2019 07:27:09 -0500 Received: by mail-wr1-f66.google.com with SMTP id i12so21788785wrw.0 for ; Thu, 28 Feb 2019 04:27:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=J8JlGYbgg/zRqWjBOjDxf78JZ4BdingiWMKoRwZVd2w=; b=dOyjeR8ZWcjQDTxl4nMMhZXXfodN/nAUp69zBcpmH3re2VKK+OphctBrYXp32q76Wz Qztyf30CuMRyIUPnFNN2ZYqPpXmjDsXLA/AdalLU/kJqcBJg/3ngx7K/A+j+w0wHTbXO kKd1tBL5FS6flTIRYzNFMGTqZHjD0oZxMyaswcY2am7JLWdA+Vt/uCJLZXG0ktr5AVYg TP/nIeMXGQoQgFU67iVGoA00B7I3+IjaRPmtQ4IlBdhBLGDqWrgk5Awtd9SFPCFaflBE soZw+RU177sBlwOLTH6RAafbjVF8CGWv9yDr7Ib4mtp9I+fR2SKADZMQgfcvBrKeC6Ik RsPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=J8JlGYbgg/zRqWjBOjDxf78JZ4BdingiWMKoRwZVd2w=; b=OXaVH/LUVmx8MkTmyXWzKWlS2XnBXw3hQstSCFzgJCYg+VwmszhezDjAu+X0cmjsq+ 2wfcn6XqPTj0iAVGaCEFxSu0SqA1/wOcEMsg+KZYjAYmITQ9TtAPsQTVQ7VpfjthouJl c9DlcR9GIRkx2hDNiulSptJR46M2djD/VR+5RAN4Bog64yDua2HwyzzgKHc1sUIw2JXo c8zrOBEhRkDlVJubz9KllH3xglA+F3eBftp7gmnkXCs8GXv0VwjOCkljS8dwSZeC1bxy GS6ZGu2j0heAmiR008CYip5RNnnY7KPhEnFGxJYdTqc2EdTHoUkoWe31mJd4RIUx4CJ5 VnIw== X-Gm-Message-State: APjAAAU1mecR5py41nomVI1fHLxTHpQeoFD1iWY9T3X+IPjPaN1rIyV7 mQQR1fP8/y3zZPGHJZk2G7a6qg== X-Received: by 2002:adf:f543:: with SMTP id j3mr5890814wrp.220.1551356827946; Thu, 28 Feb 2019 04:27:07 -0800 (PST) Received: from localhost ([49.248.54.130]) by smtp.gmail.com with ESMTPSA id i13sm18710218wrm.86.2019.02.28.04.27.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Feb 2019 04:27:07 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v2 12/24] drivers: thermal: tsens: Don't print error message on -EPROBE_DEFER Date: Thu, 28 Feb 2019 17:51:02 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We print a calibration failure message on -EPROBE_DEFER from nvmem/qfprom as follows: [ 3.003090] qcom-tsens 4a9000.thermal-sensor: version: 1.4 [ 3.005376] qcom-tsens 4a9000.thermal-sensor: tsens calibration failed [ 3.113248] qcom-tsens 4a9000.thermal-sensor: version: 1.4 This confuses people when, in fact, calibration succeeds later when nvmem/qfprom device is available. Don't print this message on a -EPROBE_DEFER. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b91a0b88d33c..057b33353ba3 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -159,7 +159,8 @@ static int tsens_probe(struct platform_device *pdev) if (priv->ops->calibrate) { ret = priv->ops->calibrate(priv); if (ret < 0) { - dev_err(dev, "tsens calibration failed\n"); + if (ret != -EPROBE_DEFER) + dev_err(dev, "tsens calibration failed\n"); return ret; } } From patchwork Thu Feb 28 12:21:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 159357 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp576540jad; Thu, 28 Feb 2019 04:27:17 -0800 (PST) X-Google-Smtp-Source: AHgI3IaWcCduHvkGzOV36otgESm+/XOhMBBJsbgiC1zY7VicLJ5HLtcg7DlIcktB7QXFz/la3DmL X-Received: by 2002:a62:be02:: with SMTP id l2mr7218027pff.55.1551356837093; Thu, 28 Feb 2019 04:27:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551356837; cv=none; d=google.com; s=arc-20160816; b=uIwSRDFOP1v08ajEPkok1v7e30xBSmWH03S/1v2vGXf3ycXEWXepSVo1kPJhfyeab1 6igLoXivXknISExKUtIsIgHpMIL1VtYObszZyWU18NFw9wwN6W2dhkGndHXiYqVPzWOg 6QwnP1Ts7RbF8AbGQKps+Qn2fVotlrX7mYeMMstsAYlPHch8++MQDycvYTCdg6Doz4y2 PjG7ptBwOi5JUC8TdLTC0SMRbayfKo+nJGUzTC0m8/Uo3qgq7fYMA3qqGhmhXqfyzWYO zSLLxIpyG9H0fznyFEJp3R97zARpISXNrTF8XotJN2oz1PNcGzKoWktMG1T2Vv4g1YL9 evoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=7ih+SAWN2J6Z2DTnoiDcjijOHCsTs+vEB5wC/EgIIos=; b=VnKO+3tQ184jx9VZWazs9qs66MyrE7bLkgif4pqIjDX6OjC3t2GF32kMnkmCEmh8Vp +YCVK+TVR3KtKimUDYlKS2rdVyhrXV5P8vTY5ff+CfeeXo9S7akMqPGd4dE7BmtZqpD1 YRym3KrYz5cJQrytweVEgkk0lJVaKLI07rJdag9aKEcDtdvCkbiye52pC/36Ujf4I6Rj 06xFnMwmF0DcIyF9XZCRftVV123OkugTM9r/4p797mcvU8a9KB3XXHiCqohf8RDAQ4HR 8h2yjM4CtSZa+DscQgKltofEQoJnd8iPdp2DMvrdkUOthzIcV1CExSUaZuGt3emeprhX ze6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yybSd720; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r23si16154398pgv.406.2019.02.28.04.27.16; Thu, 28 Feb 2019 04:27:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yybSd720; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731408AbfB1M1Q (ORCPT + 15 others); Thu, 28 Feb 2019 07:27:16 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:46602 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730829AbfB1M1P (ORCPT ); Thu, 28 Feb 2019 07:27:15 -0500 Received: by mail-wr1-f67.google.com with SMTP id i16so21693338wrs.13 for ; Thu, 28 Feb 2019 04:27:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=7ih+SAWN2J6Z2DTnoiDcjijOHCsTs+vEB5wC/EgIIos=; b=yybSd7203embm0NYsxNwm95uzUGP+CtRXYUpVnrMV6voOiY0xfoVISdxp0yynAcVRu fU8UD2J9H9uI8m9klpBCGZeuPKToibFTit6Ls+IqvKCb8jcD5aog+tR08vxrABM+yuoU alVSOh33ZYgI4kcRsijx0VcuUUh4gD3ooInN9ourrBZgcUBSPNIas/0IhpyXlMsSawjc QhO8bpQluxVBmpPmWJU56c0r0samQcP0PpnsPeCmiNT+cNuijKMi8mvZKhCFEWCMSbT0 mjWaz8mvy05xGERmuwrFCmiAY0ZHAWi7Cma1D2QSbi9YQsRaszDiKRPQCkNhnTvHJffW ohGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=7ih+SAWN2J6Z2DTnoiDcjijOHCsTs+vEB5wC/EgIIos=; b=mB+QNuJXMswUXZ++Iql9yVR/xzCy2tJtNuQ++JvdpWWADthMo0y3PNl1mBhk7nAStX vJpj5tX0HI4Ds2xAVZr6NrQawEsy9lJn4TWdS/4N6xpl9WEhfjDKNAiBoDBW5U430Xq1 qecvxBpEu4YvQ5LxwZ9B8tk1LnkqHanAETqvnyFlu69KhHIDavdKSEcsk3m4BTdxN79I yJihvNtGa3L7m2XHqeJ9lbDO7nT4c3PG3jnpfVKC9YJikHA2Kk/pQi9WNDZEe31Qbs5y 6UrpeoQimxNIm+Az3Plhog1oHUnfYig0tP2psdgw9WCP2dSjTxHuzIB+LYduMt8JH56C eouA== X-Gm-Message-State: APjAAAURDsLvqkbKa3Ca4S52M5VFCK54yOEwxr+hudi0k0ec8qIplhrY 05o9OH+iE8OfI3DRio+/QxLK7A== X-Received: by 2002:a5d:4412:: with SMTP id z18mr6125270wrq.111.1551356834053; Thu, 28 Feb 2019 04:27:14 -0800 (PST) Received: from localhost ([49.248.54.130]) by smtp.gmail.com with ESMTPSA id d206sm7905080wmc.11.2019.02.28.04.27.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Feb 2019 04:27:13 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v2 13/24] drivers: thermal: tsens: Track IP version Date: Thu, 28 Feb 2019 17:51:03 +0530 Message-Id: <4a91bf86d985129397312c25dec1f1f559c1ab53.1551355503.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Version information is available on some TSENS IP. Allow reading it by allocating memory for the regmap_field. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index aae3d71d7eed..8d632de2c7f8 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -155,6 +155,16 @@ int __init init_common(struct tsens_priv *priv) if (IS_ERR(priv->tm_map)) return PTR_ERR(priv->tm_map); + /* alloc regmap_fields in srot_map */ + if (priv->feat->ver_info) { + for (i = 0, j = VER_MAJOR; i < 2; i++, j++) { + priv->rf[j] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[j]); + if (IS_ERR(priv->rf[j])) + return PTR_ERR(priv->rf[j]); + } + } + priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_EN]); if (IS_ERR(priv->rf[TSENS_EN])) From patchwork Thu Feb 28 12:21:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 159359 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp576719jad; Thu, 28 Feb 2019 04:27:30 -0800 (PST) X-Google-Smtp-Source: APXvYqx8WCgq7tX3JlVzJJRx4yOY/VX8SscZL0lZ/hgYeikUZAiPwkNGOMraKcqvQh/TCmnV/gdH X-Received: by 2002:a17:902:9a5:: with SMTP id 34mr1061295pln.39.1551356850515; Thu, 28 Feb 2019 04:27:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551356850; cv=none; d=google.com; s=arc-20160816; b=ni6yuh5GwL82hoH+L4KbF7FvzfFOHY0WLP6mgvScdG4cA37yK/NX73Y5VRpsG+PXMA Cwc0hw9Y+s/y6NOE1tk0F38uG4JYYjauIeI9V62Ua+9rIB2/dDYWKBSUon+BBmAdzMi0 ERLVENgq2EwBJnAy5Swxvgg9X+4sQCLZAkyw4oyo16LTRfmGysbEVyGK1JeffH+56l3r IFORnfgtPeCkLMBLAngKAso2zWQ5VsuOEZX2vmaQN6rMzdsSXs62zSoDhijuTJl39dwr Y4DXt/Sgjw7HjelzyxbegRezy77+h6UbLSuOfCm9jhoaLy1hgnpunFKN7i1oOh5NOlfo selQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=5rNls9PJRn4v8yy/hG2zwnbZ+uPiqMw2tvNWVfaTE3s=; b=BVRiD13mVpsLcvb673GNunpsiBtW6QjlbsApliZll2Kwbns4ZUAZnRrS885aQPiROK UWAtbtSXVQtXQH+hbPqTPIU7SoKO3ncWXz165m/DcET7OcFC1S+mm6TtnMFqDQzShHFF 1IVriFw68ZrO1E1t2XTmcDf2FdsKzKtzXN1LKd3O67E2oMbGQCJkyGTMqYaok8QIzadr jafJLnIUOTpHGmttk5qZUXJViVpE2NuvyuJayizONEEQ/CwUiB3Lml9OVPWiplebMB1z lyRSmNem4uUJzefCVDXkeDvwGE+zVB2cqHV4TSRbiBuQtDe9hH8PQ3gRy+pHfYXhOs4J BteQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JNP+0LMs; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 023fed3352e3..a20725b1cc67 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -29,8 +29,8 @@ struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; int offset; - int id; - int hw_id; + unsigned int id; + unsigned int hw_id; int slope; u32 status; }; From patchwork Thu Feb 28 12:21:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 159363 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp577061jad; Thu, 28 Feb 2019 04:27:54 -0800 (PST) X-Google-Smtp-Source: AHgI3IanEGhD7QVkvDTik+9CaL3r7WyUW4pqV0KJqhINW6iE7U8Y+qsg6aUIsK/XahSv59StiIL/ X-Received: by 2002:a65:5788:: with SMTP id b8mr8025652pgr.8.1551356874870; Thu, 28 Feb 2019 04:27:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551356874; cv=none; d=google.com; s=arc-20160816; b=D7MSKRjSTfGrVE9VU2xjVGdeZ5hcaH98GcEX0wNdfoGML55xShC+1oDzQBAmR8/1zv MtuMeCWw9NGNy6pmFrmI7EtkpygChOtvFtc8EK/yTseeOKluLXk5FpwT9Hj3YjwCkjv9 YjBi+vgQFWfA2LZgchzNx1R31to+H5uUpME5BhEhWwvw9e5rhVeHhYnnZpbYyemGepkl nGB2NQWfI2+br9k7WfQDAfi9h5HzeTaOlUq9FmzicyyFMvsYDKX2ToHzAfJkJl+Z776n xalqMfL6nq+69TB/eEspfc7f+YbLrkfM6YaN+845NGjdlnlnw4K0M5FVLLuALP1rnO+m bKLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=vXTkCN9XQrYDU1nAIhEf80bjP3QRImM0rvZgjdrLpoM=; b=LF+3mcFpqtH8nweqso9RqRJCSwsIg0Wh+RSUIp11ZNVBtoj3dXowCuyXTEkYDUa9AC OXn0QGAY/Rnh9WOK824zawq4b62CWUn7pJdd0yGth3EbRRENdzq0DpWQOrPB6bwSPKWb SVEe8tMcKi7X8jCOQCJzTH1yayW29ExTw9gZaag0DHCX45JnddPOGfkhDZQi3QzO950U at9tQeonn4NTLv1VM2+pnr9mfLnELcWoMb7bg6XSRNzhfJQMHZTQPxpaoFeCxM4Ws6pN CFd1T9jO0pJa7CXudCAdogWyoVzjw1s1ThmbTgjSZVEeYR0U2Fys3bItMgPpliLnO/Mp Geuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zViCAUkU; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 7bab0e640806..5db1aa441910 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -129,10 +129,15 @@ int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp) if (ret) return ret; - mask = GENMASK(priv->fields[LAST_TEMP_0].msb, - priv->fields[LAST_TEMP_0].lsb); - /* Convert temperature from deciCelsius to milliCelsius */ - *temp = sign_extend32(last_temp, fls(mask) - 1) * 100; + if (priv->feat->adc) { + /* Convert temperature from ADC code to milliCelsius */ + *temp = code_to_degc(last_temp, s) * 1000; + } else { + mask = GENMASK(priv->fields[LAST_TEMP_0].msb, + priv->fields[LAST_TEMP_0].lsb); + /* Convert temperature from deciCelsius to milliCelsius */ + *temp = sign_extend32(last_temp, fls(mask) - 1) * 100; + } return 0; } From patchwork Thu Feb 28 12:21:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 159366 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp577338jad; Thu, 28 Feb 2019 04:28:14 -0800 (PST) X-Google-Smtp-Source: AHgI3Ibfw2wOtRDWRu3fTePVTsdOX1HXaY+RUy5+YY7zUStKPmvS3Yn5RQLhMLfvrkM3Es64HMjz X-Received: by 2002:a17:902:3143:: with SMTP id w61mr7897091plb.253.1551356893905; Thu, 28 Feb 2019 04:28:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551356893; cv=none; d=google.com; s=arc-20160816; b=WeljfL0X2IjpFDtpLoDov5gWv3Qk2AOUDu0syuxpMOsJNqzIjCEdZBe7qnkb9Zif4d oZzD2T48h0XNi0maSqRFnByfLovp/vvrDmZM7QrM3JVhKtN8GlTvjyJlmnahMYlYWROp p9XzUHb3OW9tfgfAMu+kZLFZzWFqMQRLTsejISwbMh9uJkeFEwv+3ep+i9jkho86Syer lq+HAdbgJodEg6d6FojtazHd15hAlz3Z3Ci5Bnt7wxn0Es+6lN+5VpDF0jBSP9kLWWgN gurMjbInomw0CrPP/TPXrs+orrS/GSv/EbC9p2ragfCIdKy3AIwZf7NkokqD3LNxjseF VSWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=aLsMVwtpgSOaGBz4AILnRl4PUyhZEZVIsjfHxCwTaGk=; b=fY9/xPMlLu+Uilq/mQ8KfXb8p848jwq2wpjIieB1zin91A8luQVz5fUkjqsXggOr/F cG/zqJ4XPPrenaqeSHxjwSuPFqnIxHiYtmmF1ZaQz0FlzBWCOUi/Fa3ZRltxS7QfvYla Qwf9inFZsGzuS+fFWLsYZkCjLozEETrVo6BQCdsOzyoUz5NrK4VFfMoKV3Z4u623TFAD TT/3I491pkTAUJjBQPPSL6AvSoIX+FzrodI/Cm4vqJa9WXZ9PZjg/EZe1XNN6Y/bP9iG /YVRg0HfqVjloouwCwGF9L9PA3y2QalAJdRR5hUec1bitxil9bERQsJtR4xWWNC8aIIz JgHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=liqYSAAa; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The calibration data is stored in an eeprom (qfprom) that is accessed through the nvmem framework. We add the qfprom node to allow the tsens sensors to be calibrated correctly. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9b5c16562bbe..57d14d8f0c90 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -253,6 +253,16 @@ reg = <0x00060000 0x6000>; }; + qfprom: qfprom@a4000 { + compatible = "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0x1f8 0x14>; + }; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -260,6 +270,16 @@ clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>,