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Mon, 17 Oct 2022 07:13:25 -0500 From: Amit Kumar Mahapatra To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Amit Kumar Mahapatra Subject: [PATCH 01/10] spi: Add stacked memories support in SPI core Date: Mon, 17 Oct 2022 17:42:40 +0530 Message-ID: <20221017121249.19061-2-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> References: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8E8:EE_|DS7PR12MB6008:EE_ X-MS-Office365-Filtering-Correlation-Id: 345be05d-2aac-465e-40f9-08dab0390ea9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xdSgCTQLbXmd8dFdQly8JOWii92tpvGOrJPxICvXEsnek460hrTFNDysSq/pn3O191qlDbQ5mm1QJ8ogN5IhdUeyYW3WGNX+WCDhVurLaNFuSXm5j8CNIhJCxVHPhQItLVkm6O47zR9SLHQ5icBLQAMkf9D3V/ZbjQxdDrQjUQcenGoTmymokqR67hsbsULLGAsLOInMEH7XRwEhLkKKud/f+Hs+Ox8qzpt3nrpiC1nqLtYmERcgx3tfU/VKIXPNslZ9WrfJ/xQhyLTFBGX2NL/18jlU70lRtVCyfe/morUEjaHxeEpB3O2B3NuJZTMjqHo1VvYUxr7N1dTBqFmDow2lrmfrlTBVi+7ovRej7eaM+bH/poPLwWQHxizS18kRfeSHDry/PT7r+rfYDRHqr8UxusykTBtrpwYSKSBkqKLhQ1qy8qvtUtFJKLYXky5aLgmZabVa/JlKSmLqd0+tRCBcdbwEZStw2XVKOQENaxTsjem1RJ3o9uCV6a9kPatkDuaa4RWs9bRWhrj6H9etqUsI6qulAxY3mmEOwqBU9aw/8zu/D1EaUdreOOplwkiOy6sMww9l6AWhOXmzxdWYWIv12byoLLAOlLNVRfGEfV9VFra63Ul9yeqiDjYLcDX16lf5H1hT2YAHCpq0dB55/QpAhvO2Hos5UZhD9XhfKasn0LcvoAErBf4lZ32VOawU0gebbhwCfRAHSNroPobuAQeFa/2A7TVT7Eeczqs9gqI8mFn90I5Z5GCN/B+YH2pqR3Qi2zVdz+t6vLx5JewxKBKDdI1jrleHjMkueCNDgn6DHhiBcB+bIXSvmf4cvsbKSmOpVMeMyDWsklnfEwc5LGIeQXriUByq2MgH0It6vvQgxPCS9xUhOQ2K3JPV19LMaA8AgL3JbG+1yVtI+7OukA== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6008 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For supporting multiple CS the SPI device need to be aware of all the CS values. So, the "chip_select" member in the spi_device structure is now an array that holds all the CS values. spi_device structure now has a "cs_index_mask" member. This acts as an index to the chip_select array. If nth bit of spi->cs_index_mask is set then the driver would assert spi->chip_select[n]. For supporting multiple CS via GPIO the cs_gpiod member of the spi_device structure is now an array that holds the gpio descriptor for each chipselect. Multi CS support using GPIO is not tested due to unavailability of necessary hardware setup. Signed-off-by: Amit Kumar Mahapatra --- drivers/spi/spi.c | 86 ++++++++++++++++++++++++----------------- include/linux/spi/spi.h | 16 +++++++- 2 files changed, 65 insertions(+), 37 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 8f97a3eacdea..1b1a891f4ccc 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -592,7 +592,7 @@ static void spi_dev_set_name(struct spi_device *spi) } dev_set_name(&spi->dev, "%s.%u", dev_name(&spi->controller->dev), - spi->chip_select); + spi->chip_select[0]); } static int spi_dev_check(struct device *dev, void *data) @@ -601,7 +601,8 @@ static int spi_dev_check(struct device *dev, void *data) struct spi_device *new_spi = data; if (spi->controller == new_spi->controller && - spi->chip_select == new_spi->chip_select) + spi->chip_select[0] == new_spi->chip_select[0] && + spi->chip_select[1] == new_spi->chip_select[1]) return -EBUSY; return 0; } @@ -616,7 +617,7 @@ static int __spi_add_device(struct spi_device *spi) { struct spi_controller *ctlr = spi->controller; struct device *dev = ctlr->dev.parent; - int status; + int status, idx; /* * We need to make sure there's no other device with this @@ -626,7 +627,7 @@ static int __spi_add_device(struct spi_device *spi) status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check); if (status) { dev_err(dev, "chipselect %d already in use\n", - spi->chip_select); + spi->chip_select[0]); return status; } @@ -636,8 +637,10 @@ static int __spi_add_device(struct spi_device *spi) return -ENODEV; } - if (ctlr->cs_gpiods) - spi->cs_gpiod = ctlr->cs_gpiods[spi->chip_select]; + if (ctlr->cs_gpiods) { + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) + spi->cs_gpiod[idx] = ctlr->cs_gpiods[spi->chip_select[idx]]; + } /* * Drivers may modify this initial i/o setup, but will @@ -677,13 +680,15 @@ int spi_add_device(struct spi_device *spi) { struct spi_controller *ctlr = spi->controller; struct device *dev = ctlr->dev.parent; - int status; + int status, idx; - /* Chipselects are numbered 0..max; validate. */ - if (spi->chip_select >= ctlr->num_chipselect) { - dev_err(dev, "cs%d >= max %d\n", spi->chip_select, - ctlr->num_chipselect); - return -EINVAL; + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { + /* Chipselects are numbered 0..max; validate. */ + if (spi->chip_select[idx] >= ctlr->num_chipselect) { + dev_err(dev, "cs%d >= max %d\n", spi->chip_select[idx], + ctlr->num_chipselect); + return -EINVAL; + } } /* Set the bus ID string */ @@ -700,12 +705,15 @@ static int spi_add_device_locked(struct spi_device *spi) { struct spi_controller *ctlr = spi->controller; struct device *dev = ctlr->dev.parent; + int idx; - /* Chipselects are numbered 0..max; validate. */ - if (spi->chip_select >= ctlr->num_chipselect) { - dev_err(dev, "cs%d >= max %d\n", spi->chip_select, - ctlr->num_chipselect); - return -EINVAL; + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { + /* Chipselects are numbered 0..max; validate. */ + if (spi->chip_select[idx] >= ctlr->num_chipselect) { + dev_err(dev, "cs%d >= max %d\n", spi->chip_select[idx], + ctlr->num_chipselect); + return -EINVAL; + } } /* Set the bus ID string */ @@ -749,7 +757,7 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr, WARN_ON(strlen(chip->modalias) >= sizeof(proxy->modalias)); - proxy->chip_select = chip->chip_select; + proxy->chip_select[0] = chip->chip_select; proxy->max_speed_hz = chip->max_speed_hz; proxy->mode = chip->mode; proxy->irq = chip->irq; @@ -953,29 +961,32 @@ static void spi_res_release(struct spi_controller *ctlr, struct spi_message *mes static void spi_set_cs(struct spi_device *spi, bool enable, bool force) { bool activate = enable; + u32 cs_num = __ffs(spi->cs_index_mask); + int idx; /* * Avoid calling into the driver (or doing delays) if the chip select * isn't actually changing from the last time this was called. */ - if (!force && ((enable && spi->controller->last_cs == spi->chip_select) || - (!enable && spi->controller->last_cs != spi->chip_select)) && + if (!force && ((enable && + spi->controller->last_cs == spi->chip_select[cs_num]) || + (!enable && + spi->controller->last_cs != spi->chip_select[cs_num])) && (spi->controller->last_cs_mode_high == (spi->mode & SPI_CS_HIGH))) return; trace_spi_set_cs(spi, activate); - spi->controller->last_cs = enable ? spi->chip_select : -1; + spi->controller->last_cs = enable ? spi->chip_select[cs_num] : -1; spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; - if ((spi->cs_gpiod || !spi->controller->set_cs_timing) && !activate) { + if ((spi->cs_gpiod[cs_num] || !spi->controller->set_cs_timing) && !activate) spi_delay_exec(&spi->cs_hold, NULL); - } if (spi->mode & SPI_CS_HIGH) enable = !enable; - if (spi->cs_gpiod) { + if (spi->cs_gpiod[cs_num]) { if (!(spi->mode & SPI_NO_CS)) { /* * Historically ACPI has no means of the GPIO polarity and @@ -988,10 +999,10 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force) * into account. */ if (has_acpi_companion(&spi->dev)) - gpiod_set_value_cansleep(spi->cs_gpiod, !enable); + gpiod_set_value_cansleep(spi->cs_gpiod[cs_num], !enable); else /* Polarity handled by GPIO library */ - gpiod_set_value_cansleep(spi->cs_gpiod, activate); + gpiod_set_value_cansleep(spi->cs_gpiod[cs_num], activate); } /* Some SPI masters need both GPIO CS & slave_select */ if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && @@ -1001,7 +1012,7 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force) spi->controller->set_cs(spi, !enable); } - if (spi->cs_gpiod || !spi->controller->set_cs_timing) { + if (spi->cs_gpiod[cs_num] || !spi->controller->set_cs_timing) { if (activate) spi_delay_exec(&spi->cs_setup, NULL); else @@ -2139,8 +2150,8 @@ void spi_flush_queue(struct spi_controller *ctlr) static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, struct device_node *nc) { - u32 value; - int rc; + u32 value, cs[SPI_CS_CNT_MAX] = {0}; + int rc, idx; /* Mode (clock phase/polarity/etc.) */ if (of_property_read_bool(nc, "spi-cpha")) @@ -2213,13 +2224,17 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, } /* Device address */ - rc = of_property_read_u32(nc, "reg", &value); - if (rc) { + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1, + SPI_CS_CNT_MAX); + if (rc < 0 || rc > ctlr->num_chipselect) { dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n", nc, rc); return rc; } - spi->chip_select = value; + for (idx = 0; idx < rc; idx++) + spi->chip_select[idx] = cs[idx]; + /* By default set the spi->cs_index_mask as 1 */ + spi->cs_index_mask = 0x01; /* Device speed */ if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@ -2333,7 +2348,7 @@ struct spi_device *spi_new_ancillary_device(struct spi_device *spi, strlcpy(ancillary->modalias, "dummy", sizeof(ancillary->modalias)); /* Use provided chip-select for ancillary device */ - ancillary->chip_select = chip_select; + ancillary->chip_select[0] = chip_select; /* Take over SPI mode/speed from SPI main device */ ancillary->max_speed_hz = spi->max_speed_hz; @@ -2580,7 +2595,7 @@ struct spi_device *acpi_spi_device_alloc(struct spi_controller *ctlr, spi->mode |= lookup.mode; spi->irq = lookup.irq; spi->bits_per_word = lookup.bits_per_word; - spi->chip_select = lookup.chip_select; + spi->chip_select[0] = lookup.chip_select; return spi; } @@ -3687,6 +3702,7 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) struct spi_controller *ctlr = spi->controller; struct spi_transfer *xfer; int w_size; + u32 cs_num = __ffs(spi->cs_index_mask); if (list_empty(&message->transfers)) return -EINVAL; @@ -3699,7 +3715,7 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) * cs_change is set for each transfer. */ if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits & SPI_CS_WORD) || - spi->cs_gpiod)) { + spi->cs_gpiod[cs_num])) { size_t maxsize; int ret; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index e6c73d5ff1a8..a7c2efedcc4c 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -19,6 +19,9 @@ #include #include +/* Max no. of CS supported per spi device */ +#define SPI_CS_CNT_MAX 2 + struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -163,6 +166,7 @@ extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); * deasserted. If @cs_change_delay is used from @spi_transfer, then the * two delays will be added up. * @pcpu_statistics: statistics for the spi_device + * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array * * A @spi_device is used to interchange data between an SPI slave * (usually a discrete chip) and CPU memory. @@ -178,7 +182,7 @@ struct spi_device { struct spi_controller *controller; struct spi_controller *master; /* Compatibility layer */ u32 max_speed_hz; - u8 chip_select; + u8 chip_select[SPI_CS_CNT_MAX]; u8 bits_per_word; bool rt; #define SPI_NO_TX BIT(31) /* No transmit wire */ @@ -199,7 +203,7 @@ struct spi_device { void *controller_data; char modalias[SPI_NAME_SIZE]; const char *driver_override; - struct gpio_desc *cs_gpiod; /* Chip select gpio desc */ + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */ struct spi_delay word_delay; /* Inter-word delay */ /* CS delays */ struct spi_delay cs_setup; @@ -209,6 +213,14 @@ struct spi_device { /* The statistics */ struct spi_statistics __percpu *pcpu_statistics; + /* + * Bit mask of the chipselect(s) that the driver need to use from + * the chipselect array.When the controller is capable to handle + * multiple chip selects & memories are connected in parallel + * then more than one bit need to be set in cs_index_mask. + */ + u32 cs_index_mask : 2; + /* * likely need more hooks for more protocol options affecting how * the controller talks to each chip, like: From patchwork Mon Oct 17 12:12:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mahapatra, Amit Kumar" X-Patchwork-Id: 615784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82D99C43219 for ; Mon, 17 Oct 2022 12:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230136AbiJQMPO (ORCPT ); Mon, 17 Oct 2022 08:15:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230253AbiJQMPJ (ORCPT ); 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Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4069 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For adding multi CS support & to prevent any existing driver from breaking, replaced all spi->chip_select references to spi->chip_select[0]. Signed-off-by: Amit Kumar Mahapatra --- drivers/net/ethernet/asix/ax88796c_main.c | 2 +- drivers/net/ethernet/davicom/dm9051.c | 2 +- drivers/net/ieee802154/ca8210.c | 2 +- drivers/net/wan/slic_ds26522.c | 2 +- drivers/net/wireless/marvell/libertas/if_spi.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/asix/ax88796c_main.c b/drivers/net/ethernet/asix/ax88796c_main.c index 6ba5b024a7be..65586ff24dfb 100644 --- a/drivers/net/ethernet/asix/ax88796c_main.c +++ b/drivers/net/ethernet/asix/ax88796c_main.c @@ -1006,7 +1006,7 @@ static int ax88796c_probe(struct spi_device *spi) ax_local->mdiobus->parent = &spi->dev; snprintf(ax_local->mdiobus->id, MII_BUS_ID_SIZE, - "ax88796c-%s.%u", dev_name(&spi->dev), spi->chip_select); + "ax88796c-%s.%u", dev_name(&spi->dev), spi->chip_select[0]); ret = devm_mdiobus_register(&spi->dev, ax_local->mdiobus); if (ret < 0) { diff --git a/drivers/net/ethernet/davicom/dm9051.c b/drivers/net/ethernet/davicom/dm9051.c index a523ddda7609..835674ad6ceb 100644 --- a/drivers/net/ethernet/davicom/dm9051.c +++ b/drivers/net/ethernet/davicom/dm9051.c @@ -1121,7 +1121,7 @@ static int dm9051_mdio_register(struct board_info *db) db->mdiobus->phy_mask = (u32)~BIT(1); db->mdiobus->parent = &spi->dev; snprintf(db->mdiobus->id, MII_BUS_ID_SIZE, - "dm9051-%s.%u", dev_name(&spi->dev), spi->chip_select); + "dm9051-%s.%u", dev_name(&spi->dev), spi->chip_select[0]); ret = devm_mdiobus_register(&spi->dev, db->mdiobus); if (ret) diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c index 42c0b451088d..f0ccf1cd79f4 100644 --- a/drivers/net/ieee802154/ca8210.c +++ b/drivers/net/ieee802154/ca8210.c @@ -2967,7 +2967,7 @@ static int ca8210_test_interface_init(struct ca8210_priv *priv) sizeof(node_name), "ca8210@%d_%d", priv->spi->master->bus_num, - priv->spi->chip_select + priv->spi->chip_select[0] ); test->ca8210_dfs_spi_int = debugfs_create_file( diff --git a/drivers/net/wan/slic_ds26522.c b/drivers/net/wan/slic_ds26522.c index 6063552cea9b..eb053a76fe52 100644 --- a/drivers/net/wan/slic_ds26522.c +++ b/drivers/net/wan/slic_ds26522.c @@ -211,7 +211,7 @@ static int slic_ds26522_probe(struct spi_device *spi) ret = slic_ds26522_init_configure(spi); if (ret == 0) - pr_info("DS26522 cs%d configured\n", spi->chip_select); + pr_info("DS26522 cs%d configured\n", spi->chip_select[0]); return ret; } diff --git a/drivers/net/wireless/marvell/libertas/if_spi.c b/drivers/net/wireless/marvell/libertas/if_spi.c index ff1c7ec8c450..074d6c1f0c2c 100644 --- a/drivers/net/wireless/marvell/libertas/if_spi.c +++ b/drivers/net/wireless/marvell/libertas/if_spi.c @@ -1051,7 +1051,7 @@ static int if_spi_init_card(struct if_spi_card *card) "spi->max_speed_hz=%d\n", card->card_id, card->card_rev, card->spi->master->bus_num, - card->spi->chip_select, + card->spi->chip_select[0], card->spi->max_speed_hz); err = if_spi_prog_helper_firmware(card, helper); if (err) From patchwork Mon Oct 17 12:12:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mahapatra, Amit Kumar" X-Patchwork-Id: 615783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08B39C4332F for ; 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Mon, 17 Oct 2022 07:14:57 -0500 From: Amit Kumar Mahapatra To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Amit Kumar Mahapatra Subject: [PATCH 05/10] iio: imu: Replace spi->chip_select references to spi->chip_select[0] Date: Mon, 17 Oct 2022 17:42:44 +0530 Message-ID: <20221017121249.19061-6-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> References: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT077:EE_|DM4PR12MB7645:EE_ X-MS-Office365-Filtering-Correlation-Id: b78af9a2-92fa-491c-4040-08dab03943c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gbNqnHIcDYOOSq/MVqFPrP1dtnh4ViEz8Y9E9eUYz98wpW90hXSIBBe4FjvCQCeNKOiRS0YK0KRFkIqqe+tCuQO+rF/Pt8YkUAIBOZYOdcRLMVQoLkxoNCzauEqvkVmv/g4oykyk8o5m04NRnwHWDeIXHoCKUNULes1mXWCg4E4eiOKknc+s3wjS0G5TeEjQPbFn/B3YZcWJQ3ROlmm9DVPrzv/pDbU7ueKlz7wyaonV1gozBgpTnYJmxS+oPzgAqfmo3SDESSqDLW8G969TUVhDVOTfyiFJVSuxwu84GuwdIbwtEwidnr79qwUDhf9ip43ufPsoqyNsKIsqvr1K2Qc+gSeJy7Fm+VMxVRifM0qfXQ9csKE3B5WwCkzE7m+CaCZN8nDlexUdxTZ+U57X0cLHQhx5TEPWFYmnkX7B+rAgN9bWPQpbM/relH33/ddPbudC3TtciCEntb0XUb+Nra4/qQGR1W1R3HhkErofiZNPXnUBhSYsTFOyoqS/hugpoQugVHKIrElIoM9FbTiSLoF4W+pE5aS7fZ5mMYde5mUqcUvQJZk6b6ZZNBJ/wK11PB1SyUyMggP7rXIKuAM9H7IJmeCZhsuhe3zDIatzRkU70aS2hYDwjtSb1qSsydph3x2LzGtODhqiykyL0Un/TIoza8mHo8Hm4EackjcBScbHkU/xwwPgz56oTNnQDaeJ0PqQCaLunC8gek6UMRxfTZ8VYqwrB5CA8FXgDCz53XX0Z+MuCdMkyQkxwNP/zvS9e6XL/BoF081G/qgnbyA6pq8u7eBgTalWBI/aWu/5EwiDyxgZFqzQlBZags2izOAtfbkAtM814Rqv2lsohEF3My+Ppf3POgKVBlvMn3nKlgVGBSsnDEwyVNKkBQbmp4VpqWYcIz31apdQJAvyA4fuUA== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Amit Kumar Mahapatra --- drivers/iio/imu/adis16400.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/imu/adis16400.c b/drivers/iio/imu/adis16400.c index 17bb0c40a149..aa7bfcee3510 100644 --- a/drivers/iio/imu/adis16400.c +++ b/drivers/iio/imu/adis16400.c @@ -466,7 +466,7 @@ static int adis16400_initial_setup(struct iio_dev *indio_dev) dev_info(&indio_dev->dev, "%s: prod_id 0x%04x at CS%d (irq %d)\n", indio_dev->name, prod_id, - st->adis.spi->chip_select, st->adis.spi->irq); + st->adis.spi->chip_select[0], st->adis.spi->irq); } /* use high spi speed if possible */ if (st->variant->flags & ADIS16400_HAS_SLOW_MODE) { From patchwork Mon Oct 17 12:12:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mahapatra, Amit Kumar" X-Patchwork-Id: 615782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EAD3C433FE for ; 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Mon, 17 Oct 2022 07:15:43 -0500 From: Amit Kumar Mahapatra To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Amit Kumar Mahapatra Subject: [PATCH 07/10] spi: spi-zynqmp-gqspi: Add stacked memories support in GQSPI driver Date: Mon, 17 Oct 2022 17:42:46 +0530 Message-ID: <20221017121249.19061-8-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> References: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT103:EE_|MW4PR12MB6874:EE_ X-MS-Office365-Filtering-Correlation-Id: 168266ee-b613-4b35-5fbb-08dab0395f1c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lUFDR5U8DYxStaYK3AfNFl0eRi4RodVP9hy2F95QaPiLb5yiwDk4oZmCCfLScEiMzfDyQmi2gc8ncUSgdIN5rtB7tn2yqwpm/61g7Xjun0zgcV0tnYDlBI+cooMJG/mMTBwGUE81VlUXUiwr0PwXcV0rJ9EbYfrNcMEODGWRQesKBRtcx18/uL2xRykSzCeI6le9/0ifmG/eYoo1/XcuYGMuPJXTAawCPLyJMnHEI4UFHRlmuN4h6GCx/MgFVZZsHsB8KDnRhSy8fXFHHbM7JupvAPnXNq3aff6HKVRxUR3k/cILa8oxW01qPzFA5Bk+rAb4Ut9o8vk2O0R3rEEMhjSoPuxi5EMzeG+jD6dKtnxZpifp1v2c3zztN3zae1O/EbIBjw6rU5dj+vzIONdiQeSZGz5Y2cnVkFtpIIVSyXqbd8Vmdsz7CKi3ts5wECh8siB51Qk4tb7yTcWCUfxyFl992wed3HbWhbaOgQctwaar4syL4JAAWJrYIEvk1ZkQhjVs6LiAnT6E86bUUy+kem0MTYmYTceVpm450O5AXOW05LzLasJZSNqsj6uATPMOYrIfqj28SrPa8kn+5i83eWS7oOgBLKNUE6FWvJtcYVL2qTfBeyPfnHLf6tJW/F+eaq1323A02BqCDq3rGzQAhjzFYEoCRLJP9aI/Duw2untewrzpsPawUewCMhGznnqQRP5+sfurizNXzhFVN4KLjp3LTHofXsWV5EYOPNQJQi1WbBJX7FHd+CkijrQ0K5iFHJbkQU2aYEdb+eYKE/GG1MCL0aZekdlh7/CHsy/8I9S0wvvjzlE5Q/EfnQpmOnM8tPTtC12I9td/do9B/tLe4G97USlzzrn3LqKyPJXShNmo7uXILSJ8SE3X0MjsBlPNc2B2RQxT7ZlWU64P7Pe00g== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6874 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GQSPI supports two chip select CS0 & CS1. Update the driver to assert/de-assert the appropriate chip select as per the bits set in qspi->cs_index_mask. Signed-off-by: Amit Kumar Mahapatra --- drivers/spi/spi-zynqmp-gqspi.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 35ff734fb82d..4759f704bf5c 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -156,6 +156,9 @@ #define GQSPI_FREQ_100MHZ 100000000 #define GQSPI_FREQ_150MHZ 150000000 +#define GQSPI_SELECT_LOWER_CS BIT(0) +#define GQSPI_SELECT_UPPER_CS BIT(1) + #define SPI_AUTOSUSPEND_TIMEOUT 3000 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; @@ -467,15 +470,17 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) genfifoentry |= GQSPI_GENFIFO_MODE_SPI; + if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_UPPER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } else if (qspi->cs_index_mask & GQSPI_SELECT_LOWER_CS) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_LOWER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } + genfifoentry |= xqspi->genfifobus; if (!is_high) { - if (!qspi->chip_select[0]) { - xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; - xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; - } else { - xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER; - xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER; - } - genfifoentry |= xqspi->genfifobus; genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; } else { From patchwork Mon Oct 17 12:12:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mahapatra, Amit Kumar" X-Patchwork-Id: 615781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6598DC43219 for ; Mon, 17 Oct 2022 12:17:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbiJQMRa (ORCPT ); Mon, 17 Oct 2022 08:17:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229947AbiJQMR3 (ORCPT ); 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Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5144 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In parallel mode all the chip selects are asserted/de-asserted simultaneously and each byte of data is stored in both devices, the even bits in one, the odd bits in the other. The split is automatically handled by the GQSPI controller. The GQSPI controller supports a maximum of two flashes connected in parallel mode. A "multi-cs-cap" flag is added in the spi controntroller data, through ctlr->multi-cs-cap the spi core will make sure that the controller is capable of handling multiple chip selects at once. Parallel memories support via GPIO is also added in spi core, but not tested due to unavailability of necessary hardware setup. Signed-off-by: Amit Kumar Mahapatra --- drivers/spi/spi.c | 153 ++++++++++++++++++++++++++++------------ include/linux/spi/spi.h | 12 ++++ 2 files changed, 118 insertions(+), 47 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 1b1a891f4ccc..2721db3b95e1 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -965,58 +965,113 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force) int idx; /* - * Avoid calling into the driver (or doing delays) if the chip select - * isn't actually changing from the last time this was called. + * In parallel mode all the chip selects are asserted/de-asserted + * at once */ - if (!force && ((enable && - spi->controller->last_cs == spi->chip_select[cs_num]) || - (!enable && - spi->controller->last_cs != spi->chip_select[cs_num])) && - (spi->controller->last_cs_mode_high == (spi->mode & SPI_CS_HIGH))) - return; - - trace_spi_set_cs(spi, activate); - - spi->controller->last_cs = enable ? spi->chip_select[cs_num] : -1; - spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; - - if ((spi->cs_gpiod[cs_num] || !spi->controller->set_cs_timing) && !activate) - spi_delay_exec(&spi->cs_hold, NULL); - - if (spi->mode & SPI_CS_HIGH) - enable = !enable; + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) == SPI_PARALLEL_CS_MASK) { + spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; + + if ((spi->cs_gpiod[0] || !spi->controller->set_cs_timing) && !activate) + spi_delay_exec(&spi->cs_hold, NULL); + + if (spi->mode & SPI_CS_HIGH) + enable = !enable; + + if (spi->cs_gpiod[0] && spi->cs_gpiod[1]) { + if (!(spi->mode & SPI_NO_CS)) { + /* + * Historically ACPI has no means of the GPIO polarity and + * thus the SPISerialBus() resource defines it on the per-chip + * basis. In order to avoid a chain of negations, the GPIO + * polarity is considered being Active High. Even for the cases + * when _DSD() is involved (in the updated versions of ACPI) + * the GPIO CS polarity must be defined Active High to avoid + * ambiguity. That's why we use enable, that takes SPI_CS_HIGH + * into account. + */ + if (has_acpi_companion(&spi->dev)) { + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) + gpiod_set_value_cansleep(spi->cs_gpiod[idx], + !enable); + } else { + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) + /* Polarity handled by GPIO library */ + gpiod_set_value_cansleep(spi->cs_gpiod[idx], + activate); + } + } + /* Some SPI masters need both GPIO CS & slave_select */ + if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && + spi->controller->set_cs) + spi->controller->set_cs(spi, !enable); + else if (spi->controller->set_cs) + spi->controller->set_cs(spi, !enable); + } - if (spi->cs_gpiod[cs_num]) { - if (!(spi->mode & SPI_NO_CS)) { - /* - * Historically ACPI has no means of the GPIO polarity and - * thus the SPISerialBus() resource defines it on the per-chip - * basis. In order to avoid a chain of negations, the GPIO - * polarity is considered being Active High. Even for the cases - * when _DSD() is involved (in the updated versions of ACPI) - * the GPIO CS polarity must be defined Active High to avoid - * ambiguity. That's why we use enable, that takes SPI_CS_HIGH - * into account. - */ - if (has_acpi_companion(&spi->dev)) - gpiod_set_value_cansleep(spi->cs_gpiod[cs_num], !enable); - else - /* Polarity handled by GPIO library */ - gpiod_set_value_cansleep(spi->cs_gpiod[cs_num], activate); + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) { + if (spi->cs_gpiod[idx] || !spi->controller->set_cs_timing) { + if (activate) + spi_delay_exec(&spi->cs_setup, NULL); + else + spi_delay_exec(&spi->cs_inactive, NULL); + } } - /* Some SPI masters need both GPIO CS & slave_select */ - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && - spi->controller->set_cs) + } else { + /* + * Avoid calling into the driver (or doing delays) if the chip select + * isn't actually changing from the last time this was called. + */ + if (!force && ((enable && spi->controller->last_cs == + spi->chip_select[cs_num]) || + (!enable && spi->controller->last_cs != + spi->chip_select[cs_num])) && + (spi->controller->last_cs_mode_high == + (spi->mode & SPI_CS_HIGH))) + return; + + trace_spi_set_cs(spi, activate); + + spi->controller->last_cs = enable ? spi->chip_select[cs_num] : -1; + spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH; + + if ((spi->cs_gpiod[cs_num] || !spi->controller->set_cs_timing) && !activate) + spi_delay_exec(&spi->cs_hold, NULL); + + if (spi->mode & SPI_CS_HIGH) + enable = !enable; + + if (spi->cs_gpiod[cs_num]) { + if (!(spi->mode & SPI_NO_CS)) { + /* + * Historically ACPI has no means of the GPIO polarity and + * thus the SPISerialBus() resource defines it on the per-chip + * basis. In order to avoid a chain of negations, the GPIO + * polarity is considered being Active High. Even for the cases + * when _DSD() is involved (in the updated versions of ACPI) + * the GPIO CS polarity must be defined Active High to avoid + * ambiguity. That's why we use enable, that takes SPI_CS_HIGH + * into account. + */ + if (has_acpi_companion(&spi->dev)) + gpiod_set_value_cansleep(spi->cs_gpiod[cs_num], !enable); + else + /* Polarity handled by GPIO library */ + gpiod_set_value_cansleep(spi->cs_gpiod[cs_num], activate); + } + /* Some SPI masters need both GPIO CS & slave_select */ + if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && + spi->controller->set_cs) + spi->controller->set_cs(spi, !enable); + } else if (spi->controller->set_cs) { spi->controller->set_cs(spi, !enable); - } else if (spi->controller->set_cs) { - spi->controller->set_cs(spi, !enable); - } + } - if (spi->cs_gpiod[cs_num] || !spi->controller->set_cs_timing) { - if (activate) - spi_delay_exec(&spi->cs_setup, NULL); - else - spi_delay_exec(&spi->cs_inactive, NULL); + if (spi->cs_gpiod[cs_num] || !spi->controller->set_cs_timing) { + if (activate) + spi_delay_exec(&spi->cs_setup, NULL); + else + spi_delay_exec(&spi->cs_inactive, NULL); + } } } @@ -2230,6 +2285,10 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n", nc, rc); return rc; + } else if ((of_property_read_bool(nc, "parallel-memories")) && + (!ctlr->multi_cs_cap)) { + dev_err(&ctlr->dev, "SPI controller doesn't support multi CS\n"); + return -EINVAL; } for (idx = 0; idx < rc; idx++) spi->chip_select[idx] = cs[idx]; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index a7c2efedcc4c..64070277cd6e 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -22,6 +22,9 @@ /* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX 2 +/* chip select mask */ +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1)) + struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -378,6 +381,8 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch * @bus_lock_spinlock: spinlock for SPI bus locking * @bus_lock_mutex: mutex for exclusion of multiple callers * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use + * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert + * more than one chip select at once. * @setup: updates the device mode and clocking records used by a * device's SPI controller; protocol code may call this. This * must fail if an unrecognized or unsupported mode is requested. @@ -567,6 +572,13 @@ struct spi_controller { /* Flag indicating that the SPI bus is locked for exclusive use */ bool bus_lock_flag; + /* + * Flag indicating that the spi-controller has multi chip select + * capability and can assert/de-assert more than one chip select + * at once. + */ + bool multi_cs_cap; + /* Setup mode and clock, etc (spi driver may call many times). * * IMPORTANT: this may be called when transfers to another From patchwork Mon Oct 17 12:12:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mahapatra, Amit Kumar" X-Patchwork-Id: 615780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2702EC43219 for ; Mon, 17 Oct 2022 12:19:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229725AbiJQMTo (ORCPT ); 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Mon, 17 Oct 2022 07:16:55 -0500 From: Amit Kumar Mahapatra To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Amit Kumar Mahapatra Subject: [PATCH 10/10] spi: spi-zynqmp-gqspi: Add parallel memories support in GQSPI driver Date: Mon, 17 Oct 2022 17:42:49 +0530 Message-ID: <20221017121249.19061-11-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> References: <20221017121249.19061-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT111:EE_|DM4PR12MB5325:EE_ X-MS-Office365-Filtering-Correlation-Id: 66b081e1-9fe6-4224-8b75-08dab03989bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ww/K/luUKbn2cK/1rk2xYUfgTKlAX3l67GjcllqynrcZ2ozkdw67tAbNlAe7f7IdWe/p5rT85UHRqBqTgbBEN3R6wJHnmwQQzrSFIyXgb9dtFLwZj6jRI34OcXElrlsMus83KR2Nfaq2fCSnPqpnnHQs8UirhMLEsAYl9NtQBdup2vfHu2QDUi9MuY2QB/f6FGgbfYepRVHVdnINGpAS4y7yn7E6HfXpgh488pAE8BQogJNEtGsmCOlSpqo2b5UErgJj8P2Hf7JbsUpibRGr9FD9PjRaRruQJURqVcM0X5wYu4H7DCFOBsT5ztCVdx22iT0okHN45GjUjgtTUtq6GQaEtQlYoFygVZ3x6PZa8Z/CQmAo2Q52LZTp4OT0ZH7N+ADUAMRuxUtBiuaiulW5P94PhmXwYlI4X3bkWBcmmivFtiHZ267XAd0RSfceOYZYIn07+KYfnqdzyFKSX4rJ5fYJQ4Cx5ouaf36UJUbOWlC7/UB5U/vFiZ3GRFOCI79cfp4+8Ezie/WVfgWlYDghZGRjnGa/ECXfcUx6qOcXtLhV7bFflKhoJeeE5YkIHnFyTwseN4vw4LecFYuS/U18WhWZLWgp28Mw/ADKsTIbMZL9ykuVtDTC7TdLOzPAn46f/9ynAEzyzTQCtQkoRtjLk69be2QQ1FqrhW95JgWlNESeQfKQ7xME84LO/HDzwVmPrf8eYInvRpwrD8u0oR95/lk93p9ou73NUd4y4NG/Tc+m4yn10+9pKQR2mSLqot//gHKxmoT/kG9LX1uN7m9LFCFdgSUkRW2xQkT0dYmui4DBYZ5rYd6pD/oKTgKyN4tDc9wnRYw619mpOfmGQUdh2bjoNok2f1uqCWO1bpp45NduSIi2STKLOC1oUQL2+aWagKcBrtc+pNoVfdlOefiwXQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT111.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5325 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org During GQSPI driver probe set ctlr->multi-cs-cap for enabling multi CS capability of the controller. In parallel mode the controller can either split the data between both the flash or can send the same data to both the flashes, this is determined by the STRIPE bit. While sending commands to the flashes the GQSPI driver send the same command to both the flashes by resetting the STRIPE bit, but while writing/reading data to & from the flash the GQSPI driver splits the data evenly between both the flashes by setting the STRIPE bit. Signed-off-by: Amit Kumar Mahapatra --- drivers/spi/spi-zynqmp-gqspi.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 4759f704bf5c..6574e0a9efa5 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -23,6 +23,7 @@ #include #include #include +#include /* Generic QSPI register offsets */ #define GQSPI_CONFIG_OFST 0x00000100 @@ -192,6 +193,7 @@ struct qspi_platform_data { * @op_lock: Operational lock * @speed_hz: Current SPI bus clock speed in hz * @has_tapdelay: Used for tapdelay register available in qspi + * @is_parallel: Used for multi CS support */ struct zynqmp_qspi { struct spi_controller *ctlr; @@ -214,8 +216,33 @@ struct zynqmp_qspi { struct mutex op_lock; u32 speed_hz; bool has_tapdelay; + bool is_parallel; }; +/** + * zynqmp_gqspi_update_stripe - For GQSPI controller data stripe capabilities + * @op: Pointer to mem ops + * Return: Status of the data stripe + * + * Returns true if data stripe need to be enabled, else returns false + */ +bool zynqmp_gqspi_update_stripe(const struct spi_mem_op *op) +{ + if (op->cmd.opcode == SPINOR_OP_BE_4K || + op->cmd.opcode == SPINOR_OP_BE_32K || + op->cmd.opcode == SPINOR_OP_CHIP_ERASE || + op->cmd.opcode == SPINOR_OP_SE || + op->cmd.opcode == SPINOR_OP_BE_32K_4B || + op->cmd.opcode == SPINOR_OP_SE_4B || + op->cmd.opcode == SPINOR_OP_BE_4K_4B || + op->cmd.opcode == SPINOR_OP_WRSR || + op->cmd.opcode == SPINOR_OP_BRWR || + op->cmd.opcode == SPINOR_OP_WRSR2) + return false; + + return true; +} + /** * zynqmp_gqspi_read - For GQSPI controller read operation * @xqspi: Pointer to the zynqmp_qspi structure @@ -470,7 +497,14 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) genfifoentry |= GQSPI_GENFIFO_MODE_SPI; - if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) { + if ((qspi->cs_index_mask & GQSPI_SELECT_LOWER_CS) && + (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS)) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_BOTH, + GQSPI_SELECT_FLASH_BUS_BOTH); + if (!xqspi->is_parallel) + xqspi->is_parallel = true; + } else if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) { zynqmp_gqspi_selectslave(xqspi, GQSPI_SELECT_FLASH_CS_UPPER, GQSPI_SELECT_FLASH_BUS_LOWER); @@ -1139,6 +1173,8 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, } if (op->data.nbytes) { + if (xqspi->is_parallel && zynqmp_gqspi_update_stripe(op)) + genfifoentry |= GQSPI_GENFIFO_STRIPE; reinit_completion(&xqspi->data_completion); if (op->data.dir == SPI_MEM_DATA_OUT) { xqspi->txbuf = (u8 *)op->data.buf.out; @@ -1334,6 +1370,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ctlr->dev.of_node = np; ctlr->auto_runtime_pm = true; + ctlr->multi_cs_cap = true; ret = devm_spi_register_controller(&pdev->dev, ctlr); if (ret) {