From patchwork Wed Oct 19 11:35:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 616430 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp223227pvb; Wed, 19 Oct 2022 04:37:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Zs4MSjHfWk6QlWz3zvV8HhFdTfQtbkdaTOA/2RuHCc88QnyC6WBZT9cSGHDxXpPit7TSx X-Received: by 2002:ac8:58d6:0:b0:39c:e89a:ac4b with SMTP id u22-20020ac858d6000000b0039ce89aac4bmr6009156qta.400.1666179449404; Wed, 19 Oct 2022 04:37:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666179449; cv=none; d=google.com; s=arc-20160816; b=AQbdMBiiCJfb1NH8kjkkLe2vwOUMDMypSuXr8dJl211nJXDRIWkBcKeObv0OmM5vHt xLN23VRRmqCTKKd3Xh9Y6eMZeBTlqqEYXHQhfLbrOgnhQHcoxIzBo8wVZbccTLYQNMsw AtTnwH2f+XYo6pYjpHqa1BBViPekwaXTU7uPWvrxFpcEEHcQtkkFjTWsap7Z+7lFYgGD s3iUuK+qnPUxW8Wvdjaf+QbMaHzV5KTQFgEgzq9EMPwunt7f0JqJYyTIcS3Sosy5+e2K bs5+BR034rngp51klmwPrMUuZJwbmkNjnhgEV237xZA2Mp2oMzEDk1cnqMy++MxtTHIP GxgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=tsapSoF+2oynfHGbiw474XF1GzJq1kAu8j4fOMy/y8E=; b=Vd331FbWM1yuCzdaItqd8DP4xcuLKvDOyEGpeiWiC7zSE6rlKnGOwWUhkqszrBkeQm Wz50hIHRUaJXmKW07e5/g6rXw9Ywj842DRLd+yW5N8r4Rs/N+loTYaae1Tk6/9jeJMzF yIikvmUZ+R7sJbObznPc3VhTEHc0Ofrf9p+nqiLhbrWto4dFmkCWaZ+OkM1QPBYcZ0aA S1pbQ+NTnAUWVWPuTqsYc+S0BsDtPumYjaR3DIEAF7BAtehxSr9NONDkLsH8pL/eaWbR W00xXcxkqCDD+FxtenYxbWc1kcVtfZCwF9ZFalhd3fWekmeDvYIpEWO6CeBc5ThsQOJE XGPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B42XMwSl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jm9-20020ad45ec9000000b004afaa9936cdsi8804249qvb.512.2022.10.19.04.37.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 Oct 2022 04:37:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B42XMwSl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ol7O4-000837-VM for patch@linaro.org; Wed, 19 Oct 2022 07:37:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ol7Mq-00081Z-Uk for qemu-devel@nongnu.org; Wed, 19 Oct 2022 07:36:14 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:44764) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ol7Mn-0005nf-58 for qemu-devel@nongnu.org; Wed, 19 Oct 2022 07:36:12 -0400 Received: by mail-wr1-x434.google.com with SMTP id r13so28432498wrj.11 for ; Wed, 19 Oct 2022 04:36:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=tsapSoF+2oynfHGbiw474XF1GzJq1kAu8j4fOMy/y8E=; b=B42XMwSl3GHlmnrFF5CIUiTl51B0kEFQs1szdrRgSkOm6HJQNXgZeBFhT5DY4GCwGY Up07XwHPOMcq+YEmcojtX96acNjoXQRR0FQrBvwcwOKoOzZtns5Vmf1Ac2NBHuo4iKcZ /jDvUn5lsmE7zGhlL56AMdeGAkljXHUwEjnj78qJglkSHm43ka8ysj9+1ZRlcEdbQOzM xWYsqqz0xYlYC/f0G5CpSu8QnmOqkWFMXQwzHCAfdslFvcSQimqjn2DFSl4Lu1AyltPD ryjJQq94pldUSnarH4iF/tmxxLVhH+p3bDrop6N069fi3lYqtCy1kDkHFArH5tUZBG3W AvOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=tsapSoF+2oynfHGbiw474XF1GzJq1kAu8j4fOMy/y8E=; b=Wbv3W/HOoGjBD0tz9UnUxPUm/Dbpo66SZ1q/Mgp5sYQNN5RV8PH9Ogo2+1fSSoeZ90 3kEhk7Ye4zgZZasTTLxr/aEajMLQxW/r5Ei5kjPgJZBMWzoFPZ3S954p0RAfT5sEVpiD 01CKVbjz1NHqVoXMm05PMlYlt9ObZZ/V3iKYvBYRd6iC1CyqJJBTenm5vGjZku09rVEF paSTB6ytqUIthy4eHJMJsDg88YVGIhrzk0KXhuWUR9ExGiGAtw03N3U5+n8TMd20j1LU i6Zc61GLfEyBAUXtRRw8/COdCbMCzdxRATyGUt+7vbcXlDK+X08Or6jidhd7u1BCmmI5 f74w== X-Gm-Message-State: ACrzQf14k6hlZ95yDyMtUZWJwJ11PSHm8OOU0nCKo1kpkkeFnu6w3vaR sEh+AZg7roKlizbxLwzjSS86BQ== X-Received: by 2002:a5d:5306:0:b0:22c:d927:fc8a with SMTP id e6-20020a5d5306000000b0022cd927fc8amr4752528wrv.700.1666179358985; Wed, 19 Oct 2022 04:35:58 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id az25-20020a05600c601900b003b497138093sm16935439wmb.47.2022.10.19.04.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 04:35:58 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DC1381FFB7; Wed, 19 Oct 2022 12:35:57 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , David Hildenbrand , Cornelia Huck , Thomas Huth , qemu-s390x@nongnu.org (open list:S390 TCG CPUs) Subject: [RFC PATCH] target/s390x: fake instruction loading when handling 'ex' Date: Wed, 19 Oct 2022 12:35:52 +0100 Message-Id: <20221019113552.1051940-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The s390x EXecute instruction is a bit weird as we synthesis the executed instruction from what we have stored in memory. When plugins are enabled this breaks because we detect the ld_code2() loading from a non zero offset without the rest of the instruction being there. Work around this with a special helper to inform the rest of the translator about the instruction so things stay consistent. Signed-off-by: Alex Bennée Cc: Richard Henderson --- include/exec/translator.h | 17 +++++++++++++++++ target/s390x/tcg/translate.c | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/include/exec/translator.h b/include/exec/translator.h index 3b77f5f4aa..156f568701 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -211,6 +211,23 @@ translator_ldq_swap(CPUArchState *env, DisasContextBase *db, return ret; } +/** + * translator_fake_ldw - fake instruction load + * @insn16: 2 byte instruction + * @pc: program counter of instruction + * + * This is a special case helper used where the instruction we are + * about to translate comes from somewhere else (e.g. being + * re-synthesised for s390x "ex"). It ensures we update other areas of + * the translator with details of the executed instruction. + */ + +static inline void translator_fake_ldw(uint16_t insn16, abi_ptr pc) +{ + plugin_insn_append(pc, &insn16, sizeof(insn16)); +} + + /* * Return whether addr is on the same page as where disassembly started. * Translators can use this to enforce the rule that only single-insn diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1d2dddab1c..a07b8b2d23 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6317,12 +6317,16 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) if (unlikely(s->ex_value)) { /* Drop the EX data now, so that it's clear on exception paths. */ TCGv_i64 zero = tcg_const_i64(0); + int i; tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value)); tcg_temp_free_i64(zero); /* Extract the values saved by EXECUTE. */ insn = s->ex_value & 0xffffffffffff0000ull; ilen = s->ex_value & 0xf; + for (i = 0; i < ilen; i += 2) { + translator_fake_ldw(extract64(insn, 48 - (i * 8), 16), pc + i); + } op = insn >> 56; } else { insn = ld_code2(env, s, pc);