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[209.51.188.17]) by mx.google.com with ESMTPS id d8-20020a05621421c800b004acd6af5b16si829384qvh.435.2022.10.20.08.16.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 20 Oct 2022 08:16:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oIOEqy8l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37676 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olXHK-0006bO-WB for patch@linaro.org; Thu, 20 Oct 2022 11:16:15 -0400 Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olXE2-0003hG-3W for patch@linaro.org; Thu, 20 Oct 2022 11:12:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olU7G-00044e-LH for qemu-devel@nongnu.org; Thu, 20 Oct 2022 07:53:38 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:39686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1olU71-0000va-Ae for qemu-devel@nongnu.org; Thu, 20 Oct 2022 07:53:38 -0400 Received: by mail-pj1-x102a.google.com with SMTP id o17-20020a17090aac1100b0020d98b0c0f4so3198533pjq.4 for ; Thu, 20 Oct 2022 04:53:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0N2X3V1riRQReX4ltI4ULsG1O5wdgfurbMkc7ES3gzU=; b=oIOEqy8lhREixIlMf4h7ABgBYyrAjtSKZUqccQGwczGS6LRyE+8NB5BDznXvxoCIrA LATMqO3ShRGsamPF/MWdZXa+Hx9RcEKILTZRgXZdklVAUgEQhDu8hnvCfj3rz8ogr4a9 hCBW9veFyunR6TQm7cP+f/FGe8YUDjaVBvZx0uyuH4KKNAfH5wB0qMFOJBeB5VHQWqY4 yOuqR2eubPUocAMIRoF4HVuQtYRvD02n89hfNEHEGL7/Or0+cPAXHRI9nJVM6cg+xqSg kwiutXi0YJIOKzl45rtNXv/zskR1K6oQeUb0ZyaIShmYU1fkEy4putJa2TgGpkML4jLr qd3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0N2X3V1riRQReX4ltI4ULsG1O5wdgfurbMkc7ES3gzU=; b=kVO0xKPIH6tZASG0VbdespM993n1jzNbl69FUqnNiF6d61D0pMhRJ6+sBKhanwywG5 GysVnKaSjfJlAUC77ZkZKxgI0DFR+avNNbRdHsy4GxWudV0YyprDQa2tY2LilMGXNnuA 7V/K9YuCXzfEBykcT1zNyGJV/m59g3B6ct7XlJnI5Z80RFJxnmZVxWNt3DpayhCxbkCs NBv35n/I0jZ3+CzglW4uOkAjQWuf2a305fqT2S0iIcLA82DMy6Tn2ArjSRWkJguDY+4/ 7FNUtdFhckKkhw3g6E7bLp6pJJx3bA51PfBDv/OJzuWcG4szOxBHA5MK5m/0bfzeHDD7 czVw== X-Gm-Message-State: ACrzQf3O6w0vcR9FYQQNLfjPj3H8C6d4MtCJPAZOJx27oWEfZEkbu/yi nDJW73nIXy2BrG8od7zrpUPFki+XLxgoobFZ X-Received: by 2002:a17:902:c946:b0:183:4bdf:9478 with SMTP id i6-20020a170902c94600b001834bdf9478mr13138450pla.139.1666266801916; Thu, 20 Oct 2022 04:53:21 -0700 (PDT) Received: from localhost.localdomain ([149.135.10.35]) by smtp.gmail.com with ESMTPSA id w206-20020a627bd7000000b0056109e15638sm13065464pfc.54.2022.10.20.04.53.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 04:53:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/31] tcg: Tidy tcg_reg_alloc_op Date: Thu, 20 Oct 2022 21:52:12 +1000 Message-Id: <20221020115242.2301066-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020115242.2301066-1-richard.henderson@linaro.org> References: <20221020115242.2301066-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace goto allocate_in_reg with a boolean. Remove o_preferred_regs which isn't used, except to copy. Signed-off-by: Richard Henderson --- tcg/tcg.c | 45 +++++++++++++++++++++------------------------ 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index c9e664ee31..660d5eb098 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3606,7 +3606,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* satisfy input constraints */ for (k = 0; k < nb_iargs; k++) { - TCGRegSet i_preferred_regs, o_preferred_regs; + TCGRegSet i_preferred_regs; + bool allocate_new_reg; i = def->args_ct[nb_oargs + k].sort_index; arg = op->args[i]; @@ -3621,9 +3622,12 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) continue; } - i_preferred_regs = o_preferred_regs = 0; + reg = ts->reg; + i_preferred_regs = 0; + allocate_new_reg = false; + if (arg_ct->ialias) { - o_preferred_regs = op->output_pref[arg_ct->alias_index]; + i_preferred_regs = op->output_pref[arg_ct->alias_index]; /* * If the input is readonly, then it cannot also be an @@ -3632,30 +3636,23 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) * register and move it. */ if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { - goto allocate_in_reg; + allocate_new_reg = true; + } else if (ts->val_type == TEMP_VAL_REG) { + /* + * Check if the current register has already been + * allocated for another input. + */ + allocate_new_reg = tcg_regset_test_reg(i_allocated_regs, reg); } - - /* - * Check if the current register has already been allocated - * for another input aliased to an output. - */ - if (ts->val_type == TEMP_VAL_REG) { - reg = ts->reg; - for (int k2 = 0; k2 < k; k2++) { - int i2 = def->args_ct[nb_oargs + k2].sort_index; - if (def->args_ct[i2].ialias && reg == new_args[i2]) { - goto allocate_in_reg; - } - } - } - i_preferred_regs = o_preferred_regs; } - temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); - reg = ts->reg; + if (!allocate_new_reg) { + temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); + reg = ts->reg; + allocate_new_reg = !tcg_regset_test_reg(arg_ct->regs, reg); + } - if (!tcg_regset_test_reg(arg_ct->regs, reg)) { - allocate_in_reg: + if (allocate_new_reg) { /* * Allocate a new register matching the constraint * and move the temporary register into it. @@ -3663,7 +3660,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) temp_load(s, ts, tcg_target_available_regs[ts->type], i_allocated_regs, 0); reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, - o_preferred_regs, ts->indirect_base); + i_preferred_regs, ts->indirect_base); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { /* * Cross register class move not supported. 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Add 'p' and 'm' register constraints for this, in order to be able to allocate the even/odd register first or second. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 + tcg/tcg.c | 469 ++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 393 insertions(+), 78 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d84bae6e3f..5c2254ce9f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -951,6 +951,8 @@ typedef struct TCGArgConstraint { unsigned ct : 16; unsigned alias_index : 4; unsigned sort_index : 4; + unsigned pair_index : 4; + unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ bool oalias : 1; bool ialias : 1; bool newreg : 1; diff --git a/tcg/tcg.c b/tcg/tcg.c index 660d5eb098..e9ff3c92e5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1985,15 +1985,32 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) static int get_constraint_priority(const TCGOpDef *def, int k) { const TCGArgConstraint *arg_ct = &def->args_ct[k]; - int n; + int n = ctpop64(arg_ct->regs); - if (arg_ct->oalias) { - /* an alias is equivalent to a single register */ - n = 1; - } else { - n = ctpop64(arg_ct->regs); + /* + * Sort constraints of a single register first, which includes output + * aliases (which must exactly match the input already allocated). + */ + if (n == 1 || arg_ct->oalias) { + return INT_MAX; } - return TCG_TARGET_NB_REGS - n + 1; + + /* + * Sort register pairs next, first then second immediately after. + * Arbitrarily sort multiple pairs by the index of the first reg; + * there shouldn't be many pairs. + */ + switch (arg_ct->pair) { + case 1: + case 3: + return (k + 1) * 2; + case 2: + return (arg_ct->pair_index + 1) * 2 - 1; + } + + /* Finally, sort by decreasing register count. */ + assert(n > 1); + return -n; } /* sort from highest priority to lowest */ @@ -2028,7 +2045,8 @@ static void process_op_defs(TCGContext *s) for (op = 0; op < NB_OPS; op++) { TCGOpDef *def = &tcg_op_defs[op]; const TCGTargetOpDef *tdefs; - int i, nb_args; + bool saw_alias_pair = false; + int i, o, i2, o2, nb_args; if (def->flags & TCG_OPF_NOT_PRESENT) { continue; @@ -2050,58 +2068,175 @@ static void process_op_defs(TCGContext *s) for (i = 0; i < nb_args; i++) { const char *ct_str = tdefs->args_ct_str[i]; + bool input_p = i >= def->nb_oargs; + /* Incomplete TCGTargetOpDef entry. */ tcg_debug_assert(ct_str != NULL); - while (*ct_str != '\0') { - switch(*ct_str) { - case '0' ... '9': - { - int oarg = *ct_str - '0'; - tcg_debug_assert(ct_str == tdefs->args_ct_str[i]); - tcg_debug_assert(oarg < def->nb_oargs); - tcg_debug_assert(def->args_ct[oarg].regs != 0); - def->args_ct[i] = def->args_ct[oarg]; - /* The output sets oalias. */ - def->args_ct[oarg].oalias = true; - def->args_ct[oarg].alias_index = i; - /* The input sets ialias. */ - def->args_ct[i].ialias = true; - def->args_ct[i].alias_index = oarg; - } - ct_str++; - break; - case '&': - def->args_ct[i].newreg = true; - ct_str++; - break; + switch (*ct_str) { + case '0' ... '9': + o = *ct_str - '0'; + tcg_debug_assert(input_p); + tcg_debug_assert(o < def->nb_oargs); + tcg_debug_assert(def->args_ct[o].regs != 0); + tcg_debug_assert(!def->args_ct[o].oalias); + def->args_ct[i] = def->args_ct[o]; + /* The output sets oalias. */ + def->args_ct[o].oalias = 1; + def->args_ct[o].alias_index = i; + /* The input sets ialias. */ + def->args_ct[i].ialias = 1; + def->args_ct[i].alias_index = o; + if (def->args_ct[i].pair) { + saw_alias_pair = true; + } + tcg_debug_assert(ct_str[1] == '\0'); + continue; + + case '&': + tcg_debug_assert(!input_p); + def->args_ct[i].newreg = true; + ct_str++; + break; + + case 'p': /* plus */ + /* Allocate to the register after the previous. */ + tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); + o = i - 1; + tcg_debug_assert(!def->args_ct[o].pair); + tcg_debug_assert(!def->args_ct[o].ct); + def->args_ct[i] = (TCGArgConstraint){ + .pair = 2, + .pair_index = o, + .regs = def->args_ct[o].regs << 1, + }; + def->args_ct[o].pair = 1; + def->args_ct[o].pair_index = i; + tcg_debug_assert(ct_str[1] == '\0'); + continue; + + case 'm': /* minus */ + /* Allocate to the register before the previous. */ + tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); + o = i - 1; + tcg_debug_assert(!def->args_ct[o].pair); + tcg_debug_assert(!def->args_ct[o].ct); + def->args_ct[i] = (TCGArgConstraint){ + .pair = 1, + .pair_index = o, + .regs = def->args_ct[o].regs >> 1, + }; + def->args_ct[o].pair = 2; + def->args_ct[o].pair_index = i; + tcg_debug_assert(ct_str[1] == '\0'); + continue; + } + + do { + switch (*ct_str) { case 'i': def->args_ct[i].ct |= TCG_CT_CONST; - ct_str++; break; /* Include all of the target-specific constraints. */ #undef CONST #define CONST(CASE, MASK) \ - case CASE: def->args_ct[i].ct |= MASK; ct_str++; break; + case CASE: def->args_ct[i].ct |= MASK; break; #define REGS(CASE, MASK) \ - case CASE: def->args_ct[i].regs |= MASK; ct_str++; break; + case CASE: def->args_ct[i].regs |= MASK; break; #include "tcg-target-con-str.h" #undef REGS #undef CONST default: + case '0' ... '9': + case '&': + case 'p': + case 'm': /* Typo in TCGTargetOpDef constraint. */ g_assert_not_reached(); } - } + } while (*++ct_str != '\0'); } /* TCGTargetOpDef entry with too much information? */ tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL); + /* + * Fix up output pairs that are aliased with inputs. + * When we created the alias, we copied pair from the output. + * There are three cases: + * (1a) Pairs of inputs alias pairs of outputs. + * (1b) One input aliases the first of a pair of outputs. + * (2) One input aliases the second of a pair of outputs. + * + * Case 1a is handled by making sure that the pair_index'es are + * properly updated so that they appear the same as a pair of inputs. + * + * Case 1b is handled by setting the pair_index of the input to + * itself, simply so it doesn't point to an unrelated argument. + * Since we don't encounter the "second" during the input allocation + * phase, nothing happens with the second half of the input pair. + * + * Case 2 is handled by setting the second input to pair=3, the + * first output to pair=3, and the pair_index'es to match. + */ + if (saw_alias_pair) { + for (i = def->nb_oargs; i < nb_args; i++) { + /* + * Since [0-9pm] must be alone in the constraint string, + * the only way they can both be set is if the pair comes + * from the output alias. + */ + if (!def->args_ct[i].ialias) { + continue; + } + switch (def->args_ct[i].pair) { + case 0: + break; + case 1: + o = def->args_ct[i].alias_index; + o2 = def->args_ct[o].pair_index; + tcg_debug_assert(def->args_ct[o].pair == 1); + tcg_debug_assert(def->args_ct[o2].pair == 2); + if (def->args_ct[o2].oalias) { + /* Case 1a */ + i2 = def->args_ct[o2].alias_index; + tcg_debug_assert(def->args_ct[i2].pair == 2); + def->args_ct[i2].pair_index = i; + def->args_ct[i].pair_index = i2; + } else { + /* Case 1b */ + def->args_ct[i].pair_index = i; + } + break; + case 2: + o = def->args_ct[i].alias_index; + o2 = def->args_ct[o].pair_index; + tcg_debug_assert(def->args_ct[o].pair == 2); + tcg_debug_assert(def->args_ct[o2].pair == 1); + if (def->args_ct[o2].oalias) { + /* Case 1a */ + i2 = def->args_ct[o2].alias_index; + tcg_debug_assert(def->args_ct[i2].pair == 1); + def->args_ct[i2].pair_index = i; + def->args_ct[i].pair_index = i2; + } else { + /* Case 2 */ + def->args_ct[i].pair = 3; + def->args_ct[o2].pair = 3; + def->args_ct[i].pair_index = o2; + def->args_ct[o2].pair_index = i; + } + break; + default: + g_assert_not_reached(); + } + } + } + /* sort the constraints (XXX: this is just an heuristic) */ sort_constraints(def, 0, def->nb_oargs); sort_constraints(def, def->nb_oargs, def->nb_iargs); @@ -3197,6 +3332,52 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, tcg_abort(); } +static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, + TCGRegSet allocated_regs, + TCGRegSet preferred_regs, bool rev) +{ + int i, j, k, fmin, n = ARRAY_SIZE(tcg_target_reg_alloc_order); + TCGRegSet reg_ct[2]; + const int *order; + + /* Ensure that if I is not in allocated_regs, I+1 is not either. */ + reg_ct[1] = required_regs & ~(allocated_regs | (allocated_regs >> 1)); + tcg_debug_assert(reg_ct[1] != 0); + reg_ct[0] = reg_ct[1] & preferred_regs; + + order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; + + /* + * Skip the preferred_regs option if it cannot be satisfied, + * or if the preference made no difference. + */ + k = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; + + /* + * Minimize the number of flushes by looking for 2 free registers first, + * then a single flush, then two flushes. + */ + for (fmin = 2; fmin >= 0; fmin--) { + for (j = k; j < 2; j++) { + TCGRegSet set = reg_ct[j]; + + for (i = 0; i < n; i++) { + TCGReg reg = order[i]; + + if (tcg_regset_test_reg(set, reg)) { + int f = !s->reg_to_temp[reg] + !s->reg_to_temp[reg + 1]; + if (f >= fmin) { + tcg_reg_free(s, reg, allocated_regs); + tcg_reg_free(s, reg + 1, allocated_regs); + return reg; + } + } + } + } + } + tcg_abort(); +} + /* Make sure the temporary is in a register. If needed, allocate the register from DESIRED while avoiding ALLOCATED. */ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, @@ -3606,8 +3787,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* satisfy input constraints */ for (k = 0; k < nb_iargs; k++) { - TCGRegSet i_preferred_regs; - bool allocate_new_reg; + TCGRegSet i_preferred_regs, i_required_regs; + bool allocate_new_reg, copyto_new_reg; + TCGTemp *ts2; + int i1, i2; i = def->args_ct[nb_oargs + k].sort_index; arg = op->args[i]; @@ -3624,43 +3807,142 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) reg = ts->reg; i_preferred_regs = 0; + i_required_regs = arg_ct->regs; allocate_new_reg = false; + copyto_new_reg = false; - if (arg_ct->ialias) { + switch (arg_ct->pair) { + case 0: /* not paired */ + if (arg_ct->ialias) { + i_preferred_regs = op->output_pref[arg_ct->alias_index]; + + /* + * If the input is readonly, then it cannot also be an + * output and aliased to itself. If the input is not + * dead after the instruction, we must allocate a new + * register and move it. + */ + if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { + allocate_new_reg = true; + } else if (ts->val_type == TEMP_VAL_REG) { + /* + * Check if the current register has already been + * allocated for another input. + */ + allocate_new_reg = + tcg_regset_test_reg(i_allocated_regs, reg); + } + } + if (!allocate_new_reg) { + temp_load(s, ts, i_required_regs, i_allocated_regs, + i_preferred_regs); + reg = ts->reg; + allocate_new_reg = !tcg_regset_test_reg(i_required_regs, reg); + } + if (allocate_new_reg) { + /* + * Allocate a new register matching the constraint + * and move the temporary register into it. + */ + temp_load(s, ts, tcg_target_available_regs[ts->type], + i_allocated_regs, 0); + reg = tcg_reg_alloc(s, i_required_regs, i_allocated_regs, + i_preferred_regs, ts->indirect_base); + copyto_new_reg = true; + } + break; + + case 1: + /* First of an input pair; if i1 == i2, the second is an output. */ + i1 = i; + i2 = arg_ct->pair_index; + + /* + * It is easier to default to allocating a new pair + * and to identify a few cases where it's not required. + */ + allocate_new_reg = true; + ts2 = i1 != i2 ? arg_temp(op->args[i2]) : NULL; + + if (arg_ct->ialias) { + i_preferred_regs = op->output_pref[arg_ct->alias_index]; + if (IS_DEAD_ARG(i1) && + IS_DEAD_ARG(i2) && + !temp_readonly(ts) && + ts->val_type == TEMP_VAL_REG && + ts->reg < TCG_TARGET_NB_REGS - 1 && + tcg_regset_test_reg(i_required_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg + 1) && + (ts2 + ? !temp_readonly(ts2) && + ts2->val_type == TEMP_VAL_REG && + ts2->reg == reg + 1 + : s->reg_to_temp[reg + 1] == NULL)) { + allocate_new_reg = false; + } + } else { + /* Without aliasing, the pair must also be an input. */ + tcg_debug_assert(ts2); + if (ts->val_type == TEMP_VAL_REG && + ts2->val_type == TEMP_VAL_REG && + ts2->reg == reg + 1 && + tcg_regset_test_reg(i_required_regs, reg)) { + allocate_new_reg = false; + } + } + if (allocate_new_reg) { + reg = tcg_reg_alloc_pair(s, i_required_regs, i_allocated_regs, + 0, ts->indirect_base); + if (ts->val_type != TEMP_VAL_REG) { + temp_load(s, ts, (TCGRegSet)1 << reg, i_allocated_regs, 0); + } else { + copyto_new_reg = true; + } + } + break; + + case 2: /* pair second */ + reg = new_args[arg_ct->pair_index] + 1; + i_required_regs = (TCGRegSet)1 << reg; + temp_load(s, ts, i_required_regs, i_allocated_regs, 0); + allocate_new_reg = ts->reg != reg; + break; + + case 3: /* ialias with second output, no first input */ + tcg_debug_assert(arg_ct->ialias); i_preferred_regs = op->output_pref[arg_ct->alias_index]; - /* - * If the input is readonly, then it cannot also be an - * output and aliased to itself. If the input is not - * dead after the instruction, we must allocate a new - * register and move it. - */ - if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { - allocate_new_reg = true; - } else if (ts->val_type == TEMP_VAL_REG) { - /* - * Check if the current register has already been - * allocated for another input. - */ - allocate_new_reg = tcg_regset_test_reg(i_allocated_regs, reg); + allocate_new_reg = true; + if (IS_DEAD_ARG(i) && + ts->val_type == TEMP_VAL_REG && + reg > 0 && + !s->reg_to_temp[reg - 1] && + tcg_regset_test_reg(i_required_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg - 1)) { + tcg_regset_set_reg(i_allocated_regs, reg - 1); + allocate_new_reg = false; } + if (allocate_new_reg) { + reg = tcg_reg_alloc_pair(s, i_required_regs >> 1, + i_allocated_regs, 0, + ts->indirect_base); + tcg_regset_set_reg(i_allocated_regs, reg); + reg += 1; + if (ts->val_type != TEMP_VAL_REG) { + temp_load(s, ts, (TCGRegSet)1 << reg, i_allocated_regs, 0); + } else { + copyto_new_reg = true; + } + } + break; + + default: + g_assert_not_reached(); } - if (!allocate_new_reg) { - temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs); - reg = ts->reg; - allocate_new_reg = !tcg_regset_test_reg(arg_ct->regs, reg); - } - - if (allocate_new_reg) { - /* - * Allocate a new register matching the constraint - * and move the temporary register into it. - */ - temp_load(s, ts, tcg_target_available_regs[ts->type], - i_allocated_regs, 0); - reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, - i_preferred_regs, ts->indirect_base); + if (copyto_new_reg) { if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { /* * Cross register class move not supported. Sync the @@ -3675,7 +3957,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) const_args[i] = 0; tcg_regset_set_reg(i_allocated_regs, reg); } - + /* mark dead temporaries and free the associated registers */ for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { if (IS_DEAD_ARG(i)) { @@ -3703,7 +3985,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } /* satisfy the output constraints */ - for(k = 0; k < nb_oargs; k++) { + for (k = 0; k < nb_oargs; k++) { i = def->args_ct[k].sort_index; arg = op->args[i]; arg_ct = &def->args_ct[i]; @@ -3712,15 +3994,46 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); - if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { - reg = new_args[arg_ct->alias_index]; - } else if (arg_ct->newreg) { - reg = tcg_reg_alloc(s, arg_ct->regs, - i_allocated_regs | o_allocated_regs, - op->output_pref[k], ts->indirect_base); - } else { - reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, - op->output_pref[k], ts->indirect_base); + switch (arg_ct->pair) { + case 0: /* not paired */ + if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { + reg = new_args[arg_ct->alias_index]; + } else if (arg_ct->newreg) { + reg = tcg_reg_alloc(s, arg_ct->regs, + i_allocated_regs | o_allocated_regs, + op->output_pref[k], ts->indirect_base); + } else { + reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, + op->output_pref[k], ts->indirect_base); + } + break; + + case 1: /* first of pair */ + tcg_debug_assert(!arg_ct->newreg); + if (arg_ct->oalias) { + reg = new_args[arg_ct->alias_index]; + break; + } + reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs, + op->output_pref[k], ts->indirect_base); + break; + + case 2: /* second of pair */ + tcg_debug_assert(!arg_ct->newreg); + if (arg_ct->oalias) { + reg = new_args[arg_ct->alias_index]; + } else { + reg = new_args[arg_ct->pair_index] + 1; + } + break; + + case 3: /* first of pair, aliasing with a second input */ + tcg_debug_assert(!arg_ct->newreg); + reg = new_args[arg_ct->pair_index] - 1; + break; + + default: + g_assert_not_reached(); } tcg_regset_set_reg(o_allocated_regs, reg); if (ts->val_type == TEMP_VAL_REG) { @@ -3728,12 +4041,12 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } ts->val_type = TEMP_VAL_REG; ts->reg = reg; + s->reg_to_temp[reg] = ts; /* * Temp value is modified, so the value kept in memory is * potentially not the same. */ ts->mem_coherent = 0; - s->reg_to_temp[reg] = ts; new_args[i] = reg; } } From patchwork Thu Oct 20 11:52:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616756 Delivered-To: patch@linaro.org Received: by 2002:a17:906:1c0f:b0:78b:b85f:9498 with SMTP id k15csp350638ejg; Thu, 20 Oct 2022 06:53:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4UhW1/gHSV/wffMIrqKSKdpySE3IsHqqw/Nnx74TZIboBELcXf/njHS7nWxhVDsNX3v9hA X-Received: by 2002:a05:620a:2984:b0:6ee:cd87:26ae with SMTP id r4-20020a05620a298400b006eecd8726aemr9405443qkp.753.1666274032392; Thu, 20 Oct 2022 06:53:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666274032; cv=none; d=google.com; s=arc-20160816; b=r2c4wjK9S3V+kEDd7Xm8hG4PRHO7j+BeHwhaQtgOa7+f/yqlF0P4l3qOwC5CykYEek d3mZYQ7aqviVyxwLRNdt7c1TQFVUg4fCEuZanfwjXIv9v2CAYQByc9KDF1/GPMYyE52O QRMEl1eYdC5KJbF9Q7GMQvbzzD+zjvdKqvdRYxYievwHxpzDGf/X8JJFpwBpliFY7q3L ZMLg3CWxlZlV6KzcIJGDSTf+xgvLZBfzqhI7A84jALpuMelAuCwzB+ZEVzdtbYEFCYHo 2Hxd13AtxNFNOhhGVFr+CrDdiQTdWR4AV0Ivvl2LO4gbjx0pQN4a5v0aHuJmXDRNtntk mdaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+XZZb+kD5PLDfiZzYREY/FqgovJZfyA/XfR3p9NEW64=; b=X0eKstUV6M2yL9Qp0kEMO4XWI2/6lQ8ZxivWVnDAUuabnWIiOV8ZyPbgld7l+UYmFF rEQBcBLf3mN/EkIEc/rGBc21hyMLGYHgv7fEKHEmaJNdjmuVBG4FFS/u6xm6PrTvIlId i7alveiRkpp8nRY0nQDUqFo0KhdO5cruPrZ/H6JPjLVs1SH3zulj0SULr8coz+I63di4 g/VB3n/luZtGhEG/wCVBFlfv0CtvhoPpSmh+hCJ78CZ+p8TQTlUVyhSlv0YsMW1mAIBg RnVqRUzrMJPgHz02zElHg2qNdYuKy87tBP6ELNDdX5EkX42pm5DtsJz7GmjilPB7QW1q j+wQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XXplLCy0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 4 ++-- tcg/s390x/tcg-target-con-str.h | 8 +------ tcg/s390x/tcg-target.c.inc | 43 +++++++++++++++++++++++++--------- 3 files changed, 35 insertions(+), 20 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 426dd92e51..00ba727b70 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -29,8 +29,8 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) -C_O2_I2(b, a, 0, r) -C_O2_I3(b, a, 0, 1, r) +C_O2_I2(o, m, 0, r) +C_O2_I3(o, m, 0, 1, r) C_O2_I4(r, r, 0, 1, rA, r) C_O2_I4(r, r, 0, 1, ri, r) C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 8bb0358ae5..76446aecae 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -11,13 +11,7 @@ REGS('r', ALL_GENERAL_REGS) REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) REGS('v', ALL_VECTOR_REGS) -/* - * A (single) even/odd pair for division. - * TODO: Add something to the register allocator to allow - * this kind of regno+1 pairing to be done more generally. - */ -REGS('a', 1u << TCG_REG_R2) -REGS('b', 1u << TCG_REG_R3) +REGS('o', 0xaaaa) /* odd numbered general regs */ /* * Define constraint letters for constants: diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 33becd7694..47aaba7667 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2258,10 +2258,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_div2_i32: - tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]); + tcg_debug_assert(args[0] == args[2]); + tcg_debug_assert(args[1] == args[3]); + tcg_debug_assert((args[1] & 1) == 0); + tcg_debug_assert(args[0] == args[1] + 1); + tcg_out_insn(s, RR, DR, args[1], args[4]); break; case INDEX_op_divu2_i32: - tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]); + tcg_debug_assert(args[0] == args[2]); + tcg_debug_assert(args[1] == args[3]); + tcg_debug_assert((args[1] & 1) == 0); + tcg_debug_assert(args[0] == args[1] + 1); + tcg_out_insn(s, RRE, DLR, args[1], args[4]); break; case INDEX_op_shl_i32: @@ -2515,17 +2523,30 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_div2_i64: - /* ??? We get an unnecessary sign-extension of the dividend - into R3 with this definition, but as we do in fact always - produce both quotient and remainder using INDEX_op_div_i64 - instead requires jumping through even more hoops. */ - tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]); + /* + * ??? We get an unnecessary sign-extension of the dividend + * into op0 with this definition, but as we do in fact always + * produce both quotient and remainder using INDEX_op_div_i64 + * instead requires jumping through even more hoops. + */ + tcg_debug_assert(args[0] == args[2]); + tcg_debug_assert(args[1] == args[3]); + tcg_debug_assert((args[1] & 1) == 0); + tcg_debug_assert(args[0] == args[1] + 1); + tcg_out_insn(s, RRE, DSGR, args[1], args[4]); break; case INDEX_op_divu2_i64: - tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); + tcg_debug_assert(args[0] == args[2]); + tcg_debug_assert(args[1] == args[3]); + tcg_debug_assert((args[1] & 1) == 0); + tcg_debug_assert(args[0] == args[1] + 1); + tcg_out_insn(s, RRE, DLGR, args[1], args[4]); break; case INDEX_op_mulu2_i64: - tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]); + tcg_debug_assert(args[0] == args[2]); + tcg_debug_assert((args[1] & 1) == 0); + tcg_debug_assert(args[0] == args[1] + 1); + tcg_out_insn(s, RRE, MLGR, args[1], args[3]); break; case INDEX_op_shl_i64: @@ -3220,10 +3241,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - return C_O2_I3(b, a, 0, 1, r); + return C_O2_I3(o, m, 0, 1, r); case INDEX_op_mulu2_i64: - return C_O2_I2(b, a, 0, r); + return C_O2_I2(o, m, 0, r); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: From patchwork Thu Oct 20 11:52:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616747 Delivered-To: patch@linaro.org Received: by 2002:a17:906:1c0f:b0:78b:b85f:9498 with SMTP id k15csp344341ejg; Thu, 20 Oct 2022 06:46:36 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7LUMShBuIUfLOezgDJUr1ia8bupiY7zhTajQh36vs5ZNEr4GQDyuMPqDpPz5iqoy2JNZTh X-Received: by 2002:a05:622a:394:b0:39c:dcd7:ae69 with SMTP id j20-20020a05622a039400b0039cdcd7ae69mr10841968qtx.546.1666273596679; Thu, 20 Oct 2022 06:46:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666273596; cv=none; d=google.com; s=arc-20160816; b=tDFMnqXPUJ+jn/xDn++m+IykuwFMcYpRqKx5kfqtrhJwQ/FPEclVqkoIa86mpdaxrC bQ6OxNmJVYL6VyLAUjrwdN7yn3mI7XtYUmAcGAJ57ELgJyaGkr9KfL7Kd2OgKyOJb1D8 J+7vXaHCBzVss+SucfMG7D8tBoABPJ4K6JT0ywAUWUp6H0DriLKDqMhnx2n9iIdyrdCI 86LSrlc/Z1Ywvs//c89By8zaiy3K3uZeiFP8aKMEdRwULRsB3Uv+u1J7OuK6sklsDTm7 Qf58u9nScKLIRmdJYafwa9L1mkTUUsYakLmfX4+1pGLSqa4AzqiY+av+BZxQOBJ06gjT OOBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pcFc6BCiy8AgtsELn4bI9AGbxpo/4pmRIjtL3WupDdQ=; b=sXn6J0+tOzWQr1jIqe5MFuT1DkXkJ8+MRwsyR/8m6n2TKX0ePG/m32OFFuxb09B3Vd Uqka0aKLkAz61oxqzOnqeM+NMYKSqWhPR+xBO3JQZsv2GMayFuM6LHbt/HIxKV4r6C7U FE1H2Czk65lShwRqfgJGPxn++xBLwBRWt9sx9NNq3IdBVBGPsEIjJQ7GhRqEOV1fAXM3 MLMxnDBS0xNSBJnNOXQWpi/4PTMNQ5Sd0xa/arNY3fdyfWOhHJ8VUsOBHtvCmcsZdnLR TkQOqf19/R/5llOJis/qE7KBiTUI6akpLF/asXa/5fln8kgkIbG4VAcjrAtOaZwUJUTT 18kg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jiyaZZuz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 7 ++++--- tcg/arm/tcg-target-con-str.h | 2 ++ tcg/arm/tcg-target.c.inc | 28 ++++++++++++++++++---------- 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index 3685e1786a..b8849b2478 100644 --- a/tcg/arm/tcg-target-con-set.h +++ b/tcg/arm/tcg-target-con-set.h @@ -15,8 +15,9 @@ C_O0_I2(r, rIN) C_O0_I2(s, s) C_O0_I2(w, r) C_O0_I3(s, s, s) +C_O0_I3(S, p, s) C_O0_I4(r, r, rI, rI) -C_O0_I4(s, s, s, s) +C_O0_I4(S, p, s, s) C_O1_I1(r, l) C_O1_I1(r, r) C_O1_I1(w, r) @@ -38,8 +39,8 @@ C_O1_I2(w, w, wZ) C_O1_I3(w, w, w, w) C_O1_I4(r, r, r, rI, rI) C_O1_I4(r, r, rIN, rIK, 0) -C_O2_I1(r, r, l) -C_O2_I2(r, r, l, l) +C_O2_I1(e, p, l) +C_O2_I2(e, p, l, l) C_O2_I2(r, r, r, r) C_O2_I4(r, r, r, r, rIN, rIK) C_O2_I4(r, r, rI, rI, rIN, rIK) diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h index 8f501149e1..24b4b59feb 100644 --- a/tcg/arm/tcg-target-con-str.h +++ b/tcg/arm/tcg-target-con-str.h @@ -8,9 +8,11 @@ * Define constraint letters for register sets: * REGS(letter, register_mask) */ +REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */ REGS('r', ALL_GENERAL_REGS) REGS('l', ALL_QLOAD_REGS) REGS('s', ALL_QSTORE_REGS) +REGS('S', ALL_QSTORE_REGS & 0x5555) /* even qstore */ REGS('w', ALL_VECTOR_REGS) /* diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2c6c353eea..aa3a888fed 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1686,9 +1686,11 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); break; case MO_UQ: + /* We used pair allocation for datalo, so already should be aligned. */ + tcg_debug_assert((datalo & 1) == 0); + tcg_debug_assert(datahi == datalo + 1); /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64 - && (datalo & 1) == 0 && datahi == datalo + 1) { + if (get_alignment_bits(opc) >= MO_64) { /* * Rm (the second address op) must not overlap Rt or Rt + 1. * Since datalo is aligned, we can simplify the test via alignment. @@ -1742,9 +1744,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_UQ: + /* We used pair allocation for datalo, so already should be aligned. */ + tcg_debug_assert((datalo & 1) == 0); + tcg_debug_assert(datahi == datalo + 1); /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64 - && (datalo & 1) == 0 && datahi == datalo + 1) { + if (get_alignment_bits(opc) >= MO_64) { tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); } else if (datalo == addrlo) { tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); @@ -1826,9 +1830,11 @@ static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, tcg_out_st32_r(s, cond, datalo, addrlo, addend); break; case MO_64: + /* We used pair allocation for datalo, so already should be aligned. */ + tcg_debug_assert((datalo & 1) == 0); + tcg_debug_assert(datahi == datalo + 1); /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64 - && (datalo & 1) == 0 && datahi == datalo + 1) { + if (get_alignment_bits(opc) >= MO_64) { tcg_out_strd_r(s, cond, datalo, addrlo, addend); } else if (scratch_addend) { tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); @@ -1863,9 +1869,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); break; case MO_64: + /* We used pair allocation for datalo, so already should be aligned. */ + tcg_debug_assert((datalo & 1) == 0); + tcg_debug_assert(datahi == datalo + 1); /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >= MO_64 - && (datalo & 1) == 0 && datahi == datalo + 1) { + if (get_alignment_bits(opc) >= MO_64) { tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); } else { tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); @@ -2333,11 +2341,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_qemu_ld_i32: return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l); case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l); + return TARGET_LONG_BITS == 32 ? C_O2_I1(e, p, l) : C_O2_I2(e, p, l, l); case INDEX_op_qemu_st_i32: return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s); case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s); + return TARGET_LONG_BITS == 32 ? C_O0_I3(S, p, s) : C_O0_I4(S, p, s, s); case INDEX_op_st_vec: return C_O0_I2(w, r); From patchwork Thu Oct 20 11:52:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616764 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp298461pvb; Thu, 20 Oct 2022 07:26:33 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5k/eAihLgPiDwxRTMjDbcXhwmN9W9DHyxwOX4dDRbIEExUyxjGp26sqg/tZgzLwnT2E665 X-Received: by 2002:a05:6214:29e3:b0:4b3:f368:de31 with SMTP id jv3-20020a05621429e300b004b3f368de31mr11572660qvb.127.1666275993450; Thu, 20 Oct 2022 07:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666275993; cv=none; d=google.com; s=arc-20160816; b=oLaV+LmaMtgjVw6MgLTzJeLukQO0wUb4eeACucXk+k9Tdb4l1LTFpvguQr1flprPAR d5XeRni/QI1PrmbbS1U38LkuysFQTYVCJ9+udnANqFG/XTGQ77l4Dpho56GbWCsQa2fE H4+n8jPYmq3+4t+H4+fjWhUWJrRiq4IguiBAcWG8Uevt/2uChnJFuuGKvPz/s2eu0qBQ MeFD36qkzSbWXQviMNjTRusMER7I+vGZNKs8i4dD3cRMwei4E8+xbNXKe8gSk2YBEenb JkXYpInba3Nhh1ijJU1bpdi/lUewC8Tt43DHpxqKgb+JlKb0XVG4Eg3NNE/zOgJytpqe X0hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IOaxiECMeAtcEEimlb1VbYj3g1IJJKw/XxWwWkisLhM=; b=vTua4eVBZzLpVxfnYGzUP0veNYB6pM73NvxXs9gniwk9CHalozCuxHTFLVrMGJCOml dhFpAsv5o1bQuXcKvb8r+OlEFXLdySGpfCQ5oa2MpPm13oI6kPtF7+fzeqFhYj/qOclX nQWYWh1VoQkhpSjM+kvtnxiDZ0musc8M70npMl7QBtA1zSF7ckFOjPKY2djyGK7S7/t2 waZVYFiU+CI/wWcx6g5Ly/xRr41pPzuHIQHqKat3HXsnvgc2/ZqsmZJugdfunbWjcOVQ vnT+TDCQulUf04HxYZhji/yJGeebyEeMxUEWiD+4bicY/RO03uFQYuzJfq9CZ5uTVpm2 SnJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZSv1w3SB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This exposes the define to compile-once files. Signed-off-by: Richard Henderson --- meson.build | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 1ec3f72edc..64c87d45a5 100644 --- a/meson.build +++ b/meson.build @@ -469,6 +469,7 @@ if get_option('tcg').allowed() endif if get_option('tcg_interpreter') tcg_arch = 'tci' + config_host += { 'CONFIG_TCG_INTERPRETER': 'y' } elif host_arch == 'x86_64' tcg_arch = 'i386' elif host_arch == 'ppc64' @@ -2507,9 +2508,6 @@ foreach target : target_dirs if sym == 'CONFIG_TCG' or target in accelerator_targets.get(sym, []) config_target += { sym: 'y' } config_all += { sym: 'y' } - if sym == 'CONFIG_TCG' and tcg_arch == 'tci' - config_target += { 'CONFIG_TCG_INTERPRETER': 'y' } - endif if target in modular_tcg config_target += { 'CONFIG_TCG_MODULAR': 'y' } else From patchwork Thu Oct 20 11:52:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616769 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp304125pvb; Thu, 20 Oct 2022 07:34:35 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6pqYlvsYNUoCfMig4UKbDfGE2HISWhrgQoZ7JfM6M8GXxioAnabsrzBHDlUqNdJx+po6nH X-Received: by 2002:a37:44e:0:b0:6ee:80b6:2eec with SMTP id 75-20020a37044e000000b006ee80b62eecmr9405312qke.712.1666276475631; Thu, 20 Oct 2022 07:34:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666276475; cv=none; d=google.com; s=arc-20160816; b=nElLVwMajL6zKDtxphjhUj32XJ8EJustPB/fpUla2TNGx7aoJwmp8nTgK3Sz/0sJK2 /ZYeKOPQxwPy4DyrEaJpS5ELsxWf82rErUOvsZP/wjkq9yOpq4ofT7A8IdmHD6MrifmB ZJB589XxjkQK+wV1KUKfalEhleadN1yPZ9AaWbuGXkrBJMWXDEOB0fQp/KI/nO19aApj Gn89vqngg900HLdZn8aMMEd9LIpyTuDbNVj25k79aP/mzioJwybiBJukTWDAtldjf6ly X5UPbVWCkqs8uRjDdXmvUvNsLuBdo9G7PqOUQN4lTGwxl9hfgYhpcU4BA8vKQPxHWo7j j8DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aV7leB8My78EqE2WvpaW/QUa1BwI9gtdQsk3y5nTaWs=; b=NqEkrE3A1257sVH6B0Rqhg4npw884Z6re+EPVNnU3l7Q+zCxe8G+cLPywfa4Ti56DH VGUvvovrML8hZZWInx/5mB6kIpQ0NTfyrJZ60JOyH/QXCwnLlmlamR07G3WHayQMgAWu M4cX+1h1ECDFaxv/Z/HpjQhix2I7JGbCmztDZrf+p9DS095s+rfXbG988RDCEQgmjL0A rHGFtSmvZUa4UQYN2LNKHmjuQnVps3QQPWoXHkhLfQyabCaZZLiNNddKtBMCTkHdPdZr 2PF7oeRS+2//MkvWhOZanmwmVlp5ubC3E4J/961YHQj3t2X8TgGTY1qYCE6kbHuXAdpG rMzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mfw19+ON; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/tcg.c | 32 ++------------------------------ 3 files changed, 2 insertions(+), 32 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 485f685bd2..e145d50fef 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -16,7 +16,6 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 #define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) -#undef TCG_TARGET_STACK_GROWSUP typedef enum { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 7e96495392..56c1ac4586 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -30,7 +30,6 @@ extern int arm_arch; #define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7) -#undef TCG_TARGET_STACK_GROWSUP #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX diff --git a/tcg/tcg.c b/tcg/tcg.c index e9ff3c92e5..6c4f949c85 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1551,25 +1551,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) } if (TCG_TARGET_REG_BITS < 64 && is_64bit) { - /* - * If stack grows up, then we will be placing successive - * arguments at lower addresses, which means we need to - * reverse the order compared to how we would normally - * treat either big or little-endian. For those arguments - * that will wind up in registers, this still works for - * HPPA (the only current STACK_GROWSUP target) since the - * argument registers are *also* allocated in decreasing - * order. If another such target is added, this logic may - * have to get more complicated to differentiate between - * stack arguments and register arguments. - */ -#if HOST_BIG_ENDIAN != defined(TCG_TARGET_STACK_GROWSUP) - op->args[pi++] = temp_arg(args[i] + 1); - op->args[pi++] = temp_arg(args[i]); -#else - op->args[pi++] = temp_arg(args[i]); - op->args[pi++] = temp_arg(args[i] + 1); -#endif + op->args[pi++] = temp_arg(args[i] + HOST_BIG_ENDIAN); + op->args[pi++] = temp_arg(args[i] + !HOST_BIG_ENDIAN); real_args += 2; continue; } @@ -4166,12 +4149,6 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) return true; } -#ifdef TCG_TARGET_STACK_GROWSUP -#define STACK_DIR(x) (-(x)) -#else -#define STACK_DIR(x) (x) -#endif - static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs = TCGOP_CALLO(op); @@ -4211,18 +4188,13 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) stack_offset = TCG_TARGET_CALL_STACK_OFFSET; for (i = nb_regs; i < nb_iargs; i++) { arg = op->args[nb_oargs + i]; -#ifdef TCG_TARGET_STACK_GROWSUP - stack_offset -= sizeof(tcg_target_long); -#endif if (arg != TCG_CALL_DUMMY_ARG) { ts = arg_temp(arg); temp_load(s, ts, tcg_target_available_regs[ts->type], s->reserved_regs, 0); tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); } -#ifndef TCG_TARGET_STACK_GROWSUP stack_offset += sizeof(tcg_target_long); -#endif } /* assign input registers */ From patchwork Thu Oct 20 11:52:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616787 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp327734pvb; Thu, 20 Oct 2022 08:08:05 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6numK7+IclZbJni4goFNyNdYrSNU+T4ftVvj2XJsrzvXxGfNebyoK+aqSro21tPngeI25k X-Received: by 2002:a05:620a:4543:b0:6e3:8848:dc34 with SMTP id u3-20020a05620a454300b006e38848dc34mr9909380qkp.24.1666278484887; Thu, 20 Oct 2022 08:08:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666278484; cv=none; d=google.com; s=arc-20160816; b=OJLAi+8lFdpZH4Fv7KqapOXvxMz9NBpEN2K5i9ckc+FTpzOx07KrFzgoTkze9WvJHm iSTayjqAqpNAqKlmi44weHFDqFCrN6rF1SaUeBpBCmikZgxQAlXsaCBDSYplayCTxI2N s0U6a05WZ/c19aLi/LYtDIrT4s70V5n0GwwhoYYdCYhYVjbp3K+ZV9WBXnf9E5I0fz/I umqRUCc3n186QohVZxBsgW354H5bF2S2AOumn5s5U1DtTVEui50BpjK737+IKzDpEqKm 7Zu7DFjEzmU37mLkyuFmAtlx0K/RuiPT7nV4tJfPAuhIm7C2+pSYUQ5LZorV8FRX5BcT UN+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1fcBWbZUmm5Jnpz4Izudl/A6K0HNswQpl9r23JhxDb4=; b=rDoFaxkk0aZEFkeAyA8pIi6Pm9xWoqxD3ciN+X64/uaAtfV8Q9KXP9qpICnv6DRUzR uRbQrmtKTfDAy5OKWbE6/wf98a7NY8AEUeUT6klvPPVPdkZUVtDkfz7up0XiC4aqX/lC NqAFZPE8qSCzHp8ohBiordU43MOBVjr+LJT7KVMDZqvImyhHhJ2OYSO/r414cBgK4oqT KLiBI6jztmUTC6n6wSqyEuG6z4Hj67fdsfxztRbvACYZwENV+NV+S7GrgpvFNG6CoR5z WGz3zrQX81Ri9DGplGHpaOf+6kMs5C1ct87U8sFQV4Fg742i0Jj12GNHo/KAjm7XKEF8 /RDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ytVfOy4F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This fixes -singlestep versus the very first TB. Fixes: 04f5b647ed07 ("accel/tcg: Handle -singlestep in curr_cflags") Signed-off-by: Richard Henderson --- hw/core/cpu-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index f9fdd46b9d..6a4022eb14 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -235,6 +235,7 @@ static void cpu_common_initfn(Object *obj) /* the default value is changed by qemu_init_vcpu() for softmmu */ cpu->nr_cores = 1; cpu->nr_threads = 1; + cpu->cflags_next_tb = -1; qemu_mutex_init(&cpu->work_mutex); QSIMPLEQ_INIT(&cpu->work_list); From patchwork Thu Oct 20 11:52:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616751 Delivered-To: patch@linaro.org Received: by 2002:a17:906:1c0f:b0:78b:b85f:9498 with SMTP id k15csp347779ejg; Thu, 20 Oct 2022 06:50:39 -0700 (PDT) X-Google-Smtp-Source: AMsMyM54D5QCNjHqulJi0fRgeNsFWpyzBBdNq0fvES4LbQ+YgCs7r+CKLqeKfjg/FfpVVbOuEeXk X-Received: by 2002:ac8:7f11:0:b0:39c:e908:6451 with SMTP id f17-20020ac87f11000000b0039ce9086451mr11102152qtk.560.1666273839258; Thu, 20 Oct 2022 06:50:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666273839; cv=none; d=google.com; s=arc-20160816; b=ZM3aIeNwxDSST1wRTFEZlhh2B0c7fhsQEE8ybnWIx6nnZMxTDulEEyqnCF23lX0pdI HQKBTNCeqzeomtqZCsb1Kus2XEenyHSG82fXp9ZNYsEamBagezt9isNSpP4RcNIAY2l/ 2nAWe7YDcwZWzpd0cErpoOWpp92hgD7U1xDqEQzQ+6k2cc6hDNu+PUFQbFELgTDSQMND CUDSD17hWsWApXP1mwYxraf9knUyy3xJxSfaeDf2nqCuUV4eWPSMltGlpxV95roL344u gzocNTBkuQNJNukqNvl/WM0AO9/QYH2ZEzS0BYberQ8fW4D2zOJDiuBHiOzqIkkGOoBJ yMhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ffAk/uKFmYMud8oNMjB2hkT94GX/9Rmm5gafjNWj2X0=; b=DJeFl50YITpBy1J3pnDVM08hmxv9/wPdnQjWeqaQOLhLDac9gefLLdQdVq830kVkQ6 F3H9UaIYp2yBGHAjxj5ceNDmAnDBQbl9cT1JSD+OczkFqwfsJzWCBteyoKaPN1G8Oogo d527+JXPymrH6T5jsSLFWQNhNRkySMivSJwM0eSiH9hFeJb105dmxrCoIpGbg83sRouh 0aUSGP98wxDFT5B/VFxWH5+5o7bqfb7ZlFxYMNSTI4H/IBTl/yPYriPxCGSnz915cOx0 GwZm6zb7Xs2wfnHMK0t5ID8Yq30926SwYFHxnLfWmbRr/GjE14oK0CIaeFJaecUcNahp 1xvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XcTUuWoR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Cc: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2cbbe2396a..7e9631f004 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -163,13 +163,6 @@ static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) /* floating point registers moves */ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) { -#if TCG_TARGET_REG_BITS == 32 - if (src & 1) { - return TCGV_LOW(cpu_fpr[src / 2]); - } else { - return TCGV_HIGH(cpu_fpr[src / 2]); - } -#else TCGv_i32 ret = get_temp_i32(dc); if (src & 1) { tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); @@ -177,22 +170,16 @@ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]); } return ret; -#endif } static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) { -#if TCG_TARGET_REG_BITS == 32 - if (dst & 1) { - tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v); - } else { - tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v); - } -#else - TCGv_i64 t = (TCGv_i64)v; + TCGv_i64 t = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(t, v); tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, (dst & 1 ? 0 : 32), 32); -#endif + tcg_temp_free_i64(t); gen_update_fprs_dirty(dc, dst); } From patchwork Thu Oct 20 11:52:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616749 Delivered-To: patch@linaro.org Received: by 2002:a17:906:1c0f:b0:78b:b85f:9498 with SMTP id k15csp345693ejg; Thu, 20 Oct 2022 06:48:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5RihDILlTvV2uPlWxhICtereF8bN0O8YX7BYSizFaEDSaZ7wcfIR9rOrTA7pP2a/U2Hmvg X-Received: by 2002:a05:622a:1ba2:b0:39c:ed3c:6310 with SMTP id bp34-20020a05622a1ba200b0039ced3c6310mr10982375qtb.516.1666273693696; Thu, 20 Oct 2022 06:48:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666273693; cv=none; d=google.com; s=arc-20160816; b=bNlv1ZHb4ENeBYH3DVXUZOnUiiNatnF8Kc2rrNo0zBuRZLA1efzBoKtt104SmNuqSn ndEI6zoO2ZVCKDlXmHlJjWUfFdlLGWdlscn0fMj1VzDuOBKvBX+Pn6+yo93pcCUyoUeE 1PszCkMm1+n4BIdFWfU5bO8439zsKkp89+z1BfQGS/r8s0Srb1hHIy1pOwLpsZ5aTksO hD7pSmN2w2zaji7zrBwQPSvOLe++OzEgUYbadSbxC7jXIz/fm37uX19hJEzCmwqgiWKF RTj0B78AA97UtOsB16RjjRL/Oif/VyDprqoKVLbeuvzxgphOv09SctqwvsBaC/Cj/quR kvPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zCtMHoOPMsKaLkXmKcpRImXO58gKxjrF6Vf3m+rKoTs=; b=TN4o2doCw42ZKmBP5OcX210om/BXE9v6otWZTunnstehD+ay1WBQ3VmF9K73c0g+M/ EODtO13knFOqa4VUcw7suYTk8okN5EuSZGKYGHkxhgdn29h0gK49cNGLH+dTtvQxYFPV upB7p+gTBmsHg2E4Evu71C2+WLwh0fsztRPs8PVCXjhczezY6rKn2qoHbTcujzf3WQ/0 vHIU9xLB6xcX5/VnLRIL0sLP1nMaii3ld8ACRmCzl2lM8Ne47WSZsyf4MeoMuQSs2Inl xNeEvNiv6VZe9X/mX2EU03mwr0f66URFk0r4FoczpoLBQpybXRr69zYZ1YGGqGHKqMVr 4Vpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QDUK+zjy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/tcg/tcg.h | 12 ------------ tcg/tcg-internal.h | 14 ++++++++++++++ tcg/tcg-op.c | 10 +--------- 3 files changed, 15 insertions(+), 21 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 5c2254ce9f..d207bc47be 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -737,18 +737,6 @@ static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) return (TCGv_vec)temp_tcgv_i32(t); } -#if TCG_TARGET_REG_BITS == 32 -static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) -{ - return temp_tcgv_i32(tcgv_i64_temp(t)); -} - -static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) -{ - return temp_tcgv_i32(tcgv_i64_temp(t) + 1); -} -#endif - static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) { return op->args[arg]; diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index cc82088d52..a9ea27f67a 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -59,4 +59,18 @@ static inline unsigned tcg_call_flags(TCGOp *op) return tcg_call_info(op)->flags; } +#if TCG_TARGET_REG_BITS == 32 +static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) +{ + return temp_tcgv_i32(tcgv_i64_temp(t)); +} +static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) +{ + return temp_tcgv_i32(tcgv_i64_temp(t) + 1); +} +#else +extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); +extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); +#endif + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 019fab00cc..3ed98ffa01 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,16 +28,8 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" #include "exec/plugin-gen.h" +#include "tcg-internal.h" -/* Reduce the number of ifdefs below. This assumes that all uses of - TCGV_HIGH and TCGV_LOW are properly protected by a conditional that - the compiler can eliminate. */ -#if TCG_TARGET_REG_BITS == 64 -extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64); -extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); -#define TCGV_LOW TCGV_LOW_link_error -#define TCGV_HIGH TCGV_HIGH_link_error -#endif void tcg_gen_op1(TCGOpcode opc, TCGArg a1) { From patchwork Thu Oct 20 11:52:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616746 Delivered-To: patch@linaro.org Received: by 2002:a17:906:1c0f:b0:78b:b85f:9498 with SMTP id k15csp342678ejg; Thu, 20 Oct 2022 06:44:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7/DlRbm1V3aVknonzi8NhbX3gKDmVfNHeVBvdzRAj/YMoqEEqxzDWOMQHjI04F3gdXJ6LV X-Received: by 2002:ad4:4eec:0:b0:4b1:9859:b74b with SMTP id dv12-20020ad44eec000000b004b19859b74bmr11087005qvb.102.1666273488471; Thu, 20 Oct 2022 06:44:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666273488; cv=none; d=google.com; s=arc-20160816; b=Lvr+fPs3099OTxnZYVALsXoNaGHfNbNqnO9Ko0WiGv5vHoL2Bd+TMKMY7tT38eJDlp Ze8yUpIhbozWP0QFeY3IUX150wIXswPc08ueL0h+JKjjvC+6vpln9vhOUhaQ+DkHZi0Z tgH+yZdkvA48tI378ASZnQ9Dz32YMxwxn+z7CgtcFodmAhUq2igA0hvEc2VA9vxniYnG NpZH9lw5DZK4MUqLXwBwvjaxLHh9eFHEsBKgovHcbaZsBA+uS+IwYTfeYSBwqB9cg8uk eiJLLe9r+whUEyBvXJmrsSLFRNCNl34vDsuUqDCBWaUamPSdrjPGp9YdZJANuA18Lw0T hyqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ecyLf9UvK3GuacwmNTSkckTuqIdVcU8ZGXDLAydoDBw=; b=SxOOQGoaOQTXuIRNVLtR/TT/1vHV92RARa5i7SmZF9DzXavtNUAfUzN37ZS8pq7NaB /9rxHzz9sTZT086ScoTnmlvlMMEog5eTvfaFH0TOtGfBxHsZRQYcbYOvwfyU5yCWbEOb B92PH9kdnRTuuztuHGywcZ1L3yAFPTro6ZScFVFh6RkUTNNy1Tdc5n7ENtsmN1SqvXEp YVZj9f3sh95bmJ7h0InRGVXprUqn+Zr5znceoq8BBSTQiTHGRJF8ErKro3+YMRFwI4yF WfnLNnNtGi/EekmISJEMVd6UFRSRhQJBCvafy/h/SQzLn+Ln1kEmNAFgBxYRB41L25QZ IolQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o4stW68Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/tcg/tcg.h | 1 + tcg/tcg.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d207bc47be..afa18986b1 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -456,6 +456,7 @@ typedef struct TCGTemp { unsigned int mem_coherent:1; unsigned int mem_allocated:1; unsigned int temp_allocated:1; + unsigned int temp_subindex:1; int64_t val; struct TCGTemp *mem_base; diff --git a/tcg/tcg.c b/tcg/tcg.c index 6c4f949c85..135d9a9a0a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -927,6 +927,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, ts2->mem_allocated = 1; ts2->mem_base = base_ts; ts2->mem_offset = offset + (1 - bigendian) * 4; + ts2->temp_subindex = 1; pstrcpy(buf, sizeof(buf), name); pstrcat(buf, sizeof(buf), "_1"); ts2->name = strdup(buf); @@ -973,6 +974,7 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) ts2->base_type = TCG_TYPE_I64; ts2->type = TCG_TYPE_I32; ts2->temp_allocated = 1; + ts2->temp_subindex = 1; ts2->kind = kind; } else { ts->base_type = type; @@ -1091,6 +1093,7 @@ TCGTemp *tcg_constant_internal(TCGType type, int64_t val) ts2->type = TCG_TYPE_I32; ts2->kind = TEMP_CONST; ts2->temp_allocated = 1; + ts2->temp_subindex = 1; ts2->val = val >> 32; } else { ts->base_type = type; From patchwork Thu Oct 20 11:52:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616740 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp266201pvb; Thu, 20 Oct 2022 06:38:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5QsNEp3anx1Rhh4/e77DZPwdzdzWfjBLEwSOp+OfxR5StAGMs5g4xOvBgLi3/kZ3HxeUOc X-Received: by 2002:ac8:7c55:0:b0:39c:e345:9cc6 with SMTP id o21-20020ac87c55000000b0039ce3459cc6mr10861222qtv.679.1666273088675; Thu, 20 Oct 2022 06:38:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666273088; cv=none; d=google.com; s=arc-20160816; b=uICOjBge6yWhc/LEV3fdwWEkZhtBf84NHbpF5/kxJU4t0DMJ/z8h1lXvGbcyt3UtaS 3g7d0MPCpPQCwXLLG2T9PUnOhViZj4KA1OX+U4fsJwwDOr+mMsFFbNbORJxwhKJ9x+O6 Rwdnu5cWsZNliFfaXFt45DtDAhI7ciZakudr1hUXUCo51u8I2xcP5fshWOUHNHLRncyn 9Fzajhl/BBS3WIcrR8lDa86G3FzjPHplwgC64yoH3bgw7OLqp5iEPYgwdMckl00xXNAc SsFS92mYRdYd8Hcuauu0eYMnr3zW98esMq5+K7MkPWRpGBo97UV66EinTEvvz6ugUOw8 IFrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FvhGnFHzWfI6y4DuUWYRaxVVosi7A5FepLQOww3MqYY=; b=Z21d9IK1GAm4tOL5B0ZYvoSfQFfo/ehs/sKtW7O9t8R6WO4ogfkwVb4Ntwk2qE+1E/ NBZTujl6FWFjWUMggpZ+2dwGogbResrLyi80uaVwjqIZaaJjgncFNl/w3oDCUebK0mMN nYqMNm2Yg49uPnjUMbK18jVZ7Twzw8jfGew2Cb8gEJcS+ggKY1C77bB0xqtyeIaHJGWH aJJeAVjyNJcovG/e0VKIe/VgU6gqXpZa4KxIAKVO9f4x+ZeW6H7JMBkxshlvU70p0Za4 60nELBRHrwkQ7QsV9gYjzbG8bmkp74ZZnmcBJyBs16oaIGck/TiSd8/HUUMOKYVxEgsN +4CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="C/7GIQqn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This will make it easier to find the beginning of the larger memory block. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 ++-- tcg/tcg.c | 60 ++++++++++++++++++++-------------------------- 2 files changed, 28 insertions(+), 36 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index a9ea27f67a..2c06b5116a 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -62,11 +62,11 @@ static inline unsigned tcg_call_flags(TCGOp *op) #if TCG_TARGET_REG_BITS == 32 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) { - return temp_tcgv_i32(tcgv_i64_temp(t)); + return temp_tcgv_i32(tcgv_i64_temp(t) + HOST_BIG_ENDIAN); } static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) { - return temp_tcgv_i32(tcgv_i64_temp(t) + 1); + return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN); } #else extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); diff --git a/tcg/tcg.c b/tcg/tcg.c index 135d9a9a0a..71afa4b749 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -886,10 +886,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, TCGContext *s = tcg_ctx; TCGTemp *base_ts = tcgv_ptr_temp(base); TCGTemp *ts = tcg_global_alloc(s); - int indirect_reg = 0, bigendian = 0; -#if HOST_BIG_ENDIAN - bigendian = 1; -#endif + int indirect_reg = 0; switch (base_ts->kind) { case TEMP_FIXED: @@ -915,7 +912,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, ts->indirect_reg = indirect_reg; ts->mem_allocated = 1; ts->mem_base = base_ts; - ts->mem_offset = offset + bigendian * 4; + ts->mem_offset = offset; pstrcpy(buf, sizeof(buf), name); pstrcat(buf, sizeof(buf), "_0"); ts->name = strdup(buf); @@ -926,7 +923,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, ts2->indirect_reg = indirect_reg; ts2->mem_allocated = 1; ts2->mem_base = base_ts; - ts2->mem_offset = offset + (1 - bigendian) * 4; + ts2->mem_offset = offset + 4; ts2->temp_subindex = 1; pstrcpy(buf, sizeof(buf), name); pstrcat(buf, sizeof(buf), "_1"); @@ -1072,37 +1069,43 @@ TCGTemp *tcg_constant_internal(TCGType type, int64_t val) ts = g_hash_table_lookup(h, &val); if (ts == NULL) { + int64_t *val_ptr; + ts = tcg_temp_alloc(s); if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { TCGTemp *ts2 = tcg_temp_alloc(s); + tcg_debug_assert(ts2 == ts + 1); + ts->base_type = TCG_TYPE_I64; ts->type = TCG_TYPE_I32; ts->kind = TEMP_CONST; ts->temp_allocated = 1; - /* - * Retain the full value of the 64-bit constant in the low - * part, so that the hash table works. Actual uses will - * truncate the value to the low part. - */ - ts->val = val; - tcg_debug_assert(ts2 == ts + 1); ts2->base_type = TCG_TYPE_I64; ts2->type = TCG_TYPE_I32; ts2->kind = TEMP_CONST; ts2->temp_allocated = 1; ts2->temp_subindex = 1; - ts2->val = val >> 32; + + /* + * Retain the full value of the 64-bit constant in the low + * part, so that the hash table works. Actual uses will + * truncate the value to the low part. + */ + ts[HOST_BIG_ENDIAN].val = val; + ts[!HOST_BIG_ENDIAN].val = val >> 32; + val_ptr = &ts[HOST_BIG_ENDIAN].val; } else { ts->base_type = type; ts->type = type; ts->kind = TEMP_CONST; ts->temp_allocated = 1; ts->val = val; + val_ptr = &ts->val; } - g_hash_table_insert(h, &ts->val, ts); + g_hash_table_insert(h, val_ptr, ts); } return ts; @@ -1514,13 +1517,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) pi = 0; if (ret != NULL) { if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) == dh_typecode_i64) { -#if HOST_BIG_ENDIAN - op->args[pi++] = temp_arg(ret + 1); - op->args[pi++] = temp_arg(ret); -#else op->args[pi++] = temp_arg(ret); op->args[pi++] = temp_arg(ret + 1); -#endif nb_rets = 2; } else { op->args[pi++] = temp_arg(ret); @@ -1554,8 +1552,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) } if (TCG_TARGET_REG_BITS < 64 && is_64bit) { - op->args[pi++] = temp_arg(args[i] + HOST_BIG_ENDIAN); - op->args[pi++] = temp_arg(args[i] + !HOST_BIG_ENDIAN); + op->args[pi++] = temp_arg(args[i]); + op->args[pi++] = temp_arg(args[i] + 1); real_args += 2; continue; } @@ -4116,18 +4114,12 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) } /* If the two inputs form one 64-bit value, try dupm_vec. */ - if (itsl + 1 == itsh && itsl->base_type == TCG_TYPE_I64) { - if (!itsl->mem_coherent) { - temp_sync(s, itsl, s->reserved_regs, 0, 0); - } - if (!itsh->mem_coherent) { - temp_sync(s, itsh, s->reserved_regs, 0, 0); - } -#if HOST_BIG_ENDIAN - TCGTemp *its = itsh; -#else - TCGTemp *its = itsl; -#endif + if (itsl - itsl->temp_subindex == itsh - itsh->temp_subindex) { + TCGTemp *its = itsl - itsl->temp_subindex; + + temp_sync(s, its + 0, s->reserved_regs, 0, 0); + temp_sync(s, its + 1, s->reserved_regs, 0, 0); + if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, its->mem_base->reg, its->mem_offset)) { goto done; From patchwork Thu Oct 20 11:52:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616758 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp282948pvb; Thu, 20 Oct 2022 07:04:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6W/Y8ox+llr2tijVHdOOGzWh/CqXVPLWq88gYY8ogTh+PgE7U7dZYe/3vEzx+gYMevaaW+ X-Received: by 2002:a05:6214:d8b:b0:4b3:ed11:eb59 with SMTP id e11-20020a0562140d8b00b004b3ed11eb59mr11639376qve.80.1666274698716; Thu, 20 Oct 2022 07:04:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666274698; cv=none; d=google.com; s=arc-20160816; b=XDX2CBgLKdiUL/SNkRn+/B4RtpfHXa0oQTskCnMl3g+OZ+KGizySdg9jUmnXp9UcDN qgmVAflYpIc6wB6AVysZkiETxg4vjjEtCuQKrkERFW+BQ57qaaUagOHcGwoT3nAvK8/Z O7Qqo5y4coOLSLWuSFTcbws6f8zztYQ/y7wp2880zFwJIPcW2M4fRZdAmajrqywm/oXr /1ZwSdYzEhDQYtXE7uOTOs88qaa/QmoJV+FiAJrVM2qQ2ABKTitfEJO6qpyBpFguUNZ1 Vk1mELAYQrB9uQLgxuVpK3ThOjEH2mEUpZJdVUGR8qgtBYjsCe+Fj/pbb3qKSZ4AXIKY k0Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=D1apVJcxnpic/nI7vbdbPH7dVAQUtKqpSfoNGvBLQCc=; b=f0O8ZGy4wq+pvcdOGdpU1BlybnIDpDEz8z8s1CKZFLiZ1AgEuiZTq11iSY0UwJN0JE VvbhbEU+1323q+APlZksSGPq9AnkFYWyGnJTjIGDXoFxqnSCo0R3dU7R6nn7F8101UEc 7HrHXAkYcahI+lcjy2MAhIrmChRPsglh3E7UG5xm7h0a1JqjtFlTWiQhDZUx1gxU8sgc +0vBSCtEjW0Hh/eOF6Wubzaz3ealAQAg0sD36Uv+PCxhZz788ggPVFZsLnrXCKNPH/ys QU1xtwUVaIFR6Dp7dTdDBP2iJJIFnpe3R7DQleN5BhhBxt8sSujGud/4hpeJdj0Bhcwe Lz2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zpft5ngG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Move it outside to prevent the compiler from considering it with -Wswitch-enum. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/tcg/tcg.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index afa18986b1..a631e0bc80 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -294,8 +294,6 @@ typedef enum TCGType { TCG_TYPE_V128, TCG_TYPE_V256, - TCG_TYPE_COUNT, /* number of different types */ - /* An alias for the size of the host register. */ #if TCG_TARGET_REG_BITS == 32 TCG_TYPE_REG = TCG_TYPE_I32, @@ -318,6 +316,9 @@ typedef enum TCGType { #endif } TCGType; +/* Number of different types */ +#define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) + /** * get_alignment_bits * @memop: MemOp value From patchwork Thu Oct 20 11:52:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616757 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp282802pvb; Thu, 20 Oct 2022 07:04:47 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5+2xLYHIJX/NghZVGHXeyoZEg82zK4Lr24CKX0IpGqZ0UDXn6Ckd+R72XLBXJrLUpdeH/m X-Received: by 2002:a05:622a:180b:b0:39c:e932:8926 with SMTP id t11-20020a05622a180b00b0039ce9328926mr11320435qtc.386.1666274687560; Thu, 20 Oct 2022 07:04:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666274687; cv=none; d=google.com; s=arc-20160816; b=JwigslzsRXUpQgbymaMJWxgJ6X5ygk0qqbJh7VWIUROVfEP0Z7T5MNAp5Q1fxVOlT7 PbvPea1sF8kEeV/jwlh9LiJQ1DCCOh9kvOnrBKtRYUpjaNVMt6xFoF155FawKfS/floP LhqlexMvEg8fM2WSRmZdprDY7hL+Q09Nm9lH4n/bjLk6XsFz65xKHQrDsKD/BUoIWpld M0cvnOlDUrbHZMjnEbl+0VtUiAWTaFdoevtGkj3+IK1AXXi/W9dSf1R1AmGaQGp6rHLl ZmvhBer/liFSNKMbaQ+snmt4YA9vlgVzdla/wi+l5vr6AoZlH7B4aHY4R31FZvdP9xC9 LyWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YCzzdZnSyQ77Hz0BhaipGA74v3MTG0pAyrseErj1GHU=; b=MoaWKyHZXieKE1+J2+a9jC4ZmXVfcKEVl7a4N6tWHc6VtzfyYWvUjejWURx9yGlupK Z0IzxFikBrCM6pbyf3n5zrYpgr1c6c+bqCfS869GBGtj7lPyru3eLxKvyL4u3BSADLLO 18j411ADamRabW7oIpJ+lclNO4yGCTQGRKDPIpBl1nwyE56vCbBx4LfYxmDz/gazcEcT diz1dhx+RS4GJRhEqCAJCjw316qSFeSLbYIv6oyG7PxkcOpF74eXAdkURkLjDLKIGAk/ CYKIRe4zK4I0y4qj00yfXs8mLEs2wqvzCCwNpblXSht4SAKaieDKlcXFwv2o6uEKuTtl ayuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wo31aJuU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 10 ++++++++++ tcg/tcg.c | 26 ++++++++++++-------------- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index a631e0bc80..08f997cbbc 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -319,6 +319,16 @@ typedef enum TCGType { /* Number of different types */ #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) +static inline int tcg_type_size(TCGType t) +{ + unsigned i = t; + if (i >= TCG_TYPE_V64) { + tcg_debug_assert(i < TCG_TYPE_COUNT); + i -= TCG_TYPE_V64 - 1; + } + return 4 << i; +} + /** * get_alignment_bits * @memop: MemOp value diff --git a/tcg/tcg.c b/tcg/tcg.c index 71afa4b749..c1b9010b55 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3110,22 +3110,22 @@ static void check_regs(TCGContext *s) static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - intptr_t off, size, align; + int size = tcg_type_size(ts->type); + int align; + intptr_t off; switch (ts->type) { case TCG_TYPE_I32: - size = align = 4; + align = 4; break; case TCG_TYPE_I64: case TCG_TYPE_V64: - size = align = 8; + align = 8; break; case TCG_TYPE_V128: - size = align = 16; - break; case TCG_TYPE_V256: /* Note that we do not require aligned storage for V256. */ - size = 32, align = 16; + align = 16; break; default: g_assert_not_reached(); @@ -3641,8 +3641,8 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) TCGRegSet dup_out_regs, dup_in_regs; TCGTemp *its, *ots; TCGType itype, vtype; - intptr_t endian_fixup; unsigned vece; + int lowpart_ofs; bool ok; ots = arg_temp(op->args[0]); @@ -3711,14 +3711,12 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) /* fall through */ case TEMP_VAL_MEM: -#if HOST_BIG_ENDIAN - endian_fixup = itype == TCG_TYPE_I32 ? 4 : 8; - endian_fixup -= 1 << vece; -#else - endian_fixup = 0; -#endif + lowpart_ofs = 0; + if (HOST_BIG_ENDIAN) { + lowpart_ofs = tcg_type_size(itype) - (1 << vece); + } if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, - its->mem_offset + endian_fixup)) { + its->mem_offset + lowpart_ofs)) { goto done; } tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset); From patchwork Thu Oct 20 11:52:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616768 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp304106pvb; Thu, 20 Oct 2022 07:34:34 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6rI9QurmVJccUk/UQRHCKz2TlzyuKATRKueAU+qqAKYBq9pie/aMXiWdp0igQORNxrJqZX X-Received: by 2002:ac8:7f54:0:b0:39c:bb57:a1aa with SMTP id g20-20020ac87f54000000b0039cbb57a1aamr11332034qtk.382.1666276474133; Thu, 20 Oct 2022 07:34:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666276474; cv=none; d=google.com; s=arc-20160816; b=L/68cVEPVL/i+lXwOj+o4lXUVGB9uCexf0k6z608Uk7tgL4QYjxgNbLREWOC+Wa1kR f3zqyypmlUfiD0FVTfs9GPj23kJmQAseM2EbHtkZr6qfFm0TRdUResld/PaghurRnp3I +XifQUiJR175fWjYe3ipSbtqgc49Ad3oWabHn7rx0cjW2/xTfFX4BjDP7FFCkr2l1Qxi khga8GH7skwj0HMY1vlz81RIADU/ObsSeH29Diq2iyB7HlJlG6YcX4wUbpEyz88XNrls Y9TBLdj8413iaONjBN1HNF9NZb6wNDE2yQQrKYQb3PmsuPTLDRNWUrrqeT9tgTJy8m0/ iLtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5vQArXkcT1RDMZRTO1vvTA3LiXCIJpRLbh9UK0Nx/ps=; b=slGuN2mP57C9B40lUuilqmWdFPZks7zOIkWRqDNm+Rlple006/7ClUD4scgWYHYqM9 +Q6xyzO+vmWPP/oy3ZsabkJGUYCJBxAP9L4UUrSJnDqAV0eN4Ipt13PY/fiWuZCe36w8 xuY4kcOyOSlr4H625Dhdmm8MFm4Zzeq4HGd06O8WuJIURnTsvCsFBsAn3YMT1NKbhGgw fvCJDS7KwC3EFMWu2Tp8UeF+OveNI+6YVSqs2aJnme8SeiryLcWO819+fJJNqvpME7ja TZySIkimS4lteXMCQYXqAxs5AuhwV4UDB0sGwXLvxstgsWOlvlmZM0mD6xgNvOPlJCWu STKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PwzN2oEj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2c06b5116a..f574743ff8 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -27,6 +27,21 @@ #define TCG_HIGHWATER 1024 +/* + * Describe the calling convention of a given argument type. + */ +typedef enum { + TCG_CALL_RET_NORMAL, /* by registers */ +} TCGCallReturnKind; + +typedef enum { + TCG_CALL_ARG_NORMAL, /* by registers (continuing onto stack) */ + TCG_CALL_ARG_EVEN, /* like normal, but skipping odd slots */ + TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ + TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ + TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ +} TCGCallArgumentKind; + typedef struct TCGHelperInfo { void *func; const char *name; From patchwork Thu Oct 20 11:52:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616722 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp229374pvb; Thu, 20 Oct 2022 05:40:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7SCynbmbozrTsZStrFy2/Sel9fGCIUMqbW7ryx/Fntqpug81FwuapgbCY8qR8UPZTrDsiK X-Received: by 2002:ae9:e00f:0:b0:6ee:909e:ed48 with SMTP id m15-20020ae9e00f000000b006ee909eed48mr9045928qkk.46.1666269637427; Thu, 20 Oct 2022 05:40:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666269637; cv=none; d=google.com; s=arc-20160816; b=fcYaPydITDCp4n65g3suTyK/0dIrPnt/CMYMdAcPgrQQvrn3Ccr3W/nKh05HvELJDh 1Y71iaH3bPYHKTKTmZn0Ow4GUNBam0v+BEwoj+ZbncUkF2CQFLGlpLvWXXhuYOpO+nXL 8eQ9WphLFkjCgd/Lqkiwawfd7NXGJYdEnM9K91UoRUNkbLDIFmnLPV50RceR/naC43ZH 4X/LdZYXh5XX8EXzjwRVUhokFpnRFksF9D93M7oA3wFhgQYkFLXNpxzfV/5Za6NFF2hQ vX5AzZjfC3BLTa/jEDXWP5oJoReZ7YjOzLp40oy3d4mIUDlT+qCOan706ovWvCqlyQnF M7Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bfJ9mjaoh/bzZ7mExDxQS6i2vQ2bw3ZLVkF8JJ2Slok=; b=a074+STCHyXVV3mxkYCwGjY2GX9E63WcA0wT347nS+BN3bHbjZ5eY4svqHfRnoY61j vtH7eCy+3c7SapzWfOA0T4rELb7RvRj1W1SNyCbf3TVZCcgVuF6Anb3P9d5unug285D7 cXD3AGbwSV6zyRmmCPWUks01OOuVKL2V2QZNovxMspJ/rzM3ksHmZ/KKIfF8Vl36HdcQ bpQXmB1el/3kKA5zXWLYQ/YGqGFqruxliC3WOhLZAo/BjH2Gs/tQ13Q9Ltn4/q4vQR96 n7gy74gIDi9pr627UservXuxUpsvKY4lerOfOQmDafCVJi/LYTLYioqsTXDxO0XSABye Xgnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SgJO9CiM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t3-20020ac85883000000b0039a2f191254si11465257qta.8.2022.10.20.05.40.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 20 Oct 2022 05:40:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SgJO9CiM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47532 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olUqh-0007sa-2f for patch@linaro.org; Thu, 20 Oct 2022 08:40:36 -0400 Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olUef-0005g9-KH for patch@linaro.org; Thu, 20 Oct 2022 08:28:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olU7k-000538-10 for qemu-devel@nongnu.org; Thu, 20 Oct 2022 07:54:13 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:36515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1olU7c-00012q-DQ for qemu-devel@nongnu.org; Thu, 20 Oct 2022 07:54:04 -0400 Received: by mail-pl1-x636.google.com with SMTP id c24so20097561plo.3 for ; Thu, 20 Oct 2022 04:53:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bfJ9mjaoh/bzZ7mExDxQS6i2vQ2bw3ZLVkF8JJ2Slok=; b=SgJO9CiMq1GWSZbc3Ujiy96VIqYvQaJ/PC4ENpez4/G/7QFvXfI1ZHhuxN/AhsBOI3 2qV3a2OjG0HZD6gtpYnwIAWfkQqv70wZDNrrfdZDBMcdWanKkjrQtYiDQqO+ERVODCzv JxeXOFi7leDNyo5xfq0lgOB5Ddyc/GypScxz7MSZnb205zPz6Ngolmfwp1mBCc8OeYNB vofbVr2hSDghtF1t6yyj1CeHsycS2rxY32J0vnW6LYl7FzE77NYW6+f6iLWNFyX4bKpL jZPG1gLeatGRhyGMotUknF0UE2xD4Xz/WoAWZaTpfSCPSiJNwAVB5vIeS8L/YpWiVH9X TouQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bfJ9mjaoh/bzZ7mExDxQS6i2vQ2bw3ZLVkF8JJ2Slok=; b=7zub8U9MO2dKGlepnJtkFMFJsGK17btXUxtQbQNJJXZEqhlm/0g90x1hB9P2RsvY3W QpX0O71M7c89uymo0uNryQYR7eF6zH7VjK4I96Dsa2jSeMJuEsO0sez7ehJuJZAahfmX hnoXhj11MtmOkNnIQiWrizBDm6rB3305U4TcUzT2zRNACdvpSyex248GK8SehkMUDhA7 LvRBU5xtZmxkKSgDFsJLuDhV5LXHfUEzb19p2KrVXPoy4SElfuHL3t+hIUOt4k/T6qlA 6LccE2l8qUNUwt+hcZ7OznRBt2AYcFKbCEhfkaIB9QNgAqgDs6dEqrUHhZ7p39tOfWfz 0t8Q== X-Gm-Message-State: ACrzQf0JPxUEheQuqjwMgXwxij0nFJuwGajgmbtd4A5QGvAG2R4s8X9C JXSa1Ix/scxadpfHFJ1yg6DbShmysYR9SiAZ X-Received: by 2002:a17:90b:2248:b0:210:10dc:a314 with SMTP id hk8-20020a17090b224800b0021010dca314mr7858139pjb.15.1666266838790; Thu, 20 Oct 2022 04:53:58 -0700 (PDT) Received: from localhost.localdomain ([149.135.10.35]) by smtp.gmail.com with ESMTPSA id w206-20020a627bd7000000b0056109e15638sm13065464pfc.54.2022.10.20.04.53.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 04:53:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/31] tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 Date: Thu, 20 Oct 2022 21:52:26 +1000 Message-Id: <20221020115242.2301066-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020115242.2301066-1-richard.henderson@linaro.org> References: <20221020115242.2301066-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For 32-bit hosts when TCG_TARGET_CALL_ALIGN_ARGS was set, use TCG_CALL_ARG_EVEN. For 64-bit hosts, TCG_TARGET_CALL_ALIGN_ARGS was silently ignored, so always use TCG_CALL_ARG_NORMAL. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/arm/tcg-target.h | 2 +- tcg/i386/tcg-target.h | 1 + tcg/loongarch64/tcg-target.h | 2 +- tcg/mips/tcg-target.h | 3 ++- tcg/riscv/tcg-target.h | 2 +- tcg/s390x/tcg-target.h | 1 + tcg/sparc64/tcg-target.h | 1 + tcg/tci/tcg-target.h | 5 +++++ tcg/tcg.c | 6 ++++-- tcg/ppc/tcg-target.c.inc | 21 ++++++++------------- 11 files changed, 26 insertions(+), 20 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index e145d50fef..d9dd777caa 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -51,8 +51,8 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_CALL_ALIGN_ARGS 1 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 56c1ac4586..09dd0550aa 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -88,8 +88,8 @@ extern bool use_neon_instructions; /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_ALIGN_ARGS 1 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN /* optional instructions */ #define TCG_TARGET_HAS_ext8s_i32 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 00fcbe297d..42628a2791 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -98,6 +98,7 @@ typedef enum { #else #define TCG_TARGET_CALL_STACK_OFFSET 0 #endif +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL extern bool have_bmi1; extern bool have_popcnt; diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index d58a6162f2..584cac3dc2 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -88,8 +88,8 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_CALL_ALIGN_ARGS 1 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 7669213175..bb7312aed4 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -83,10 +83,11 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 16 #if _MIPS_SIM == _ABIO32 # define TCG_TARGET_CALL_STACK_OFFSET 16 +# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #else # define TCG_TARGET_CALL_STACK_OFFSET 0 +# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif -#define TCG_TARGET_CALL_ALIGN_ARGS 1 /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 11c9b3e4f4..0b2171ebf0 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -81,8 +81,8 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_CALL_ALIGN_ARGS 1 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 23e2063667..7e86791ff6 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -166,6 +166,7 @@ extern uint64_t s390_facilities[3]; /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_RET_NORMAL #define TCG_TARGET_EXTEND_ARGS 1 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 8655acdbe5..44ac164b31 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -72,6 +72,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #if defined(__VIS__) && __VIS__ >= 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index ceb36c4f7a..e11c293906 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -158,6 +158,11 @@ typedef enum { /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 8 +#if TCG_TARGET_REG_BITS == 32 +# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#else +# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#endif #define HAVE_TCG_QEMU_TB_EXEC #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index c1b9010b55..41052869cb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1541,9 +1541,11 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) * for passing off to ffi_call. */ want_align = true; -#elif defined(TCG_TARGET_CALL_ALIGN_ARGS) +#else /* Some targets want aligned 64 bit args */ - want_align = is_64bit; + if (is_64bit) { + want_align = TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN; + } #endif if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e3dba47697..d1d6a40c6c 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -45,7 +45,9 @@ #endif #ifdef _CALL_SYSV -# define TCG_TARGET_CALL_ALIGN_ARGS 1 +# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#else +# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif /* For some memory operations, we need a scratch that isn't R0. For the AIX @@ -2202,9 +2204,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) lo = lb->addrlo_reg; hi = lb->addrhi_reg; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif + arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); } else { @@ -2250,9 +2250,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) lo = lb->addrlo_reg; hi = lb->addrhi_reg; if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif + arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); } else { @@ -2266,9 +2264,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) if (TCG_TARGET_REG_BITS == 32) { switch (s_bits) { case MO_64: -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif + arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); /* FALLTHRU */ case MO_32: @@ -2324,9 +2320,8 @@ static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { TCGReg arg = TCG_REG_R4; -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - arg |= 1; -#endif + + arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); if (l->addrlo_reg != arg) { tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); From patchwork Thu Oct 20 11:52:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616735 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp256132pvb; Thu, 20 Oct 2022 06:22:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM42qRHCJjxTg5AK59BHAxqC0GUatAcVtM1JwzXshl45ub94OPE+woCr6QKiGeiv2lxIYt24 X-Received: by 2002:a05:620a:1b8c:b0:6ee:cffb:2222 with SMTP id dv12-20020a05620a1b8c00b006eecffb2222mr9332811qkb.674.1666272123931; Thu, 20 Oct 2022 06:22:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666272123; cv=none; d=google.com; s=arc-20160816; b=BZSAOxXiUdDbTgT/7MKTUZrYm4C6YG8SJtdArusFtvc2p2Ki95kzhMclAI3l2Jb5a6 4zbJ7vBEaf0PjtqlXDgoqZAuEA33/001DNmbTfy9VEPUUGiJyVoGZXfHJH4ju0ROHWuy P9ghq8v/YE5OkTwyt9oJ21gidTpmC7ZCB6T0n/ywUvAqE+spQoTKwBhQB6bR5quibfYi x05+0atopn4eYxPSZ5rabkwXbLsWKYXgAxApqbTqNPrlxFRQlGhBBuLVt04V1kUjY3/X P1ifq1ozcDLhOwqVsBj+B1yfsyacldUzhSzY9gk3YkzM9ei6PZ9YXj5T3XFV0SDxmkWJ ciCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Rc5eKaPoq15S3q+CyuaJRWW7YVkSg/Gi4+WBpExbrwE=; b=inZgB4x0eyiVruNfXDxS55nmy0fa1A4FDV/8CGehitXxqs9/vJLJ22HjGAEjTlG9el 8P/1f60ensQu4r3ZX+ljIm5YY3U/k9xM6TfrUb8KOHT/xzdVAH17mIKIZ9t4VpO3sgSo i2TjfCqfx1Ir4kSuPhXXz8MY5xPI9YvkxZ1mky0whultM+jl+bMAWOxVht6Vw6a3gJU4 GZGv9zzGBgVe36XYvOGfFmfxlb0Xhdj42Zi3BejWzZNcimZVqDwgR/CIXxYzS+YgcZor ItTyi+CaQRJPgF/v1TFI1wm2crEH1F0qZD2kTqo1AGJBPpHsUxzrhV6SDPTZTV6Ugor/ J+zQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xyw7pEW2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Otherwise, use TCG_CALL_ARG_NORMAL. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/loongarch64/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/riscv/tcg-target.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/sparc64/tcg-target.h | 2 +- tcg/tci/tcg-target.h | 1 + tcg/tcg.c | 42 ++++++++++++++++++------------------ tcg/ppc/tcg-target.c.inc | 6 +++++- 11 files changed, 35 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d9dd777caa..413a5410c5 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -52,6 +52,7 @@ typedef enum { #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL /* optional instructions */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 09dd0550aa..b7843d2d54 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -89,6 +89,7 @@ extern bool use_neon_instructions; /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN /* optional instructions */ diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 42628a2791..7edb7f1d9a 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -98,6 +98,7 @@ typedef enum { #else #define TCG_TARGET_CALL_STACK_OFFSET 0 #endif +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL extern bool have_bmi1; diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 584cac3dc2..74fbb22dfd 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -89,6 +89,7 @@ typedef enum { #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL /* optional instructions */ diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index bb7312aed4..15721c3e42 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -88,6 +88,7 @@ typedef enum { # define TCG_TARGET_CALL_STACK_OFFSET 0 # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 0b2171ebf0..6f3b142317 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -82,6 +82,7 @@ typedef enum { #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL /* optional instructions */ diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 7e86791ff6..db5665c375 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -166,9 +166,9 @@ extern uint64_t s390_facilities[3]; /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_RET_NORMAL -#define TCG_TARGET_EXTEND_ARGS 1 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 44ac164b31..0044ac8d78 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -71,7 +71,7 @@ typedef enum { #define TCG_TARGET_STACK_BIAS 2047 #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) -#define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #if defined(__VIS__) && __VIS__ >= 0x300 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index e11c293906..d6e0450ed8 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -158,6 +158,7 @@ typedef enum { /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 8 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS == 32 # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #else diff --git a/tcg/tcg.c b/tcg/tcg.c index 41052869cb..b83bb23281 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1493,24 +1493,24 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) } #endif -#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 - for (i = 0; i < nargs; ++i) { - int argtype = extract32(typemask, (i + 1) * 3, 3); - bool is_32bit = (argtype & ~1) == dh_typecode_i32; - bool is_signed = argtype & 1; + if (TCG_TARGET_CALL_ARG_I32 == TCG_CALL_ARG_EXTEND) { + for (i = 0; i < nargs; ++i) { + int argtype = extract32(typemask, (i + 1) * 3, 3); + bool is_32bit = (argtype & ~1) == dh_typecode_i32; + bool is_signed = argtype & 1; - if (is_32bit) { - TCGv_i64 temp = tcg_temp_new_i64(); - TCGv_i32 orig = temp_tcgv_i32(args[i]); - if (is_signed) { - tcg_gen_ext_i32_i64(temp, orig); - } else { - tcg_gen_extu_i32_i64(temp, orig); + if (is_32bit) { + TCGv_i64 temp = tcg_temp_new_i64(); + TCGv_i32 orig = temp_tcgv_i32(args[i]); + if (is_signed) { + tcg_gen_ext_i32_i64(temp, orig); + } else { + tcg_gen_extu_i32_i64(temp, orig); + } + args[i] = tcgv_i64_temp(temp); } - args[i] = tcgv_i64_temp(temp); } } -#endif /* TCG_TARGET_EXTEND_ARGS */ op = tcg_emit_op(INDEX_op_call); @@ -1571,16 +1571,16 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) tcg_debug_assert(TCGOP_CALLI(op) == real_args); tcg_debug_assert(pi <= ARRAY_SIZE(op->args)); -#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64 - for (i = 0; i < nargs; ++i) { - int argtype = extract32(typemask, (i + 1) * 3, 3); - bool is_32bit = (argtype & ~1) == dh_typecode_i32; + if (TCG_TARGET_CALL_ARG_I32 == TCG_CALL_ARG_EXTEND) { + for (i = 0; i < nargs; ++i) { + int argtype = extract32(typemask, (i + 1) * 3, 3); + bool is_32bit = (argtype & ~1) == dh_typecode_i32; - if (is_32bit) { - tcg_temp_free_internal(args[i]); + if (is_32bit) { + tcg_temp_free_internal(args[i]); + } } } -#endif /* TCG_TARGET_EXTEND_ARGS */ } static void tcg_reg_alloc_start(TCGContext *s) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d1d6a40c6c..500b75a03a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -44,6 +44,11 @@ # endif #endif +#if TCG_TARGET_REG_BITS == 64 +# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND +#else +# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#endif #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #else @@ -2520,7 +2525,6 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count) /* Parameters for function call generation, used in tcg.c. */ #define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_EXTEND_ARGS 1 #ifdef _CALL_AIX # define LINK_AREA_SIZE (6 * SZR) From patchwork Thu Oct 20 11:52:28 2022 Content-Type: text/plain; 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With a small reorg to the argument processing loop, this neatly replaces an ifdef for CONFIG_TCG_INTERPRETER. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 3 ++- tcg/tcg.c | 62 ++++++++++++++++++++++++++------------------ 2 files changed, 39 insertions(+), 26 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index d6e0450ed8..94ec541b4e 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -158,10 +158,11 @@ typedef enum { /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS == 32 +# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #else +# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif diff --git a/tcg/tcg.c b/tcg/tcg.c index b83bb23281..5704373d57 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1532,36 +1532,48 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) real_args = 0; for (i = 0; i < nargs; i++) { int argtype = extract32(typemask, (i + 1) * 3, 3); - bool is_64bit = (argtype & ~1) == dh_typecode_i64; - bool want_align = false; + TCGCallArgumentKind kind; + TCGType type; -#if defined(CONFIG_TCG_INTERPRETER) - /* - * Align all arguments, so that they land in predictable places - * for passing off to ffi_call. - */ - want_align = true; -#else - /* Some targets want aligned 64 bit args */ - if (is_64bit) { - want_align = TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN; - } -#endif - - if (TCG_TARGET_REG_BITS < 64 && want_align && (real_args & 1)) { - op->args[pi++] = TCG_CALL_DUMMY_ARG; - real_args++; + switch (argtype) { + case dh_typecode_i32: + case dh_typecode_s32: + type = TCG_TYPE_I32; + kind = TCG_TARGET_CALL_ARG_I32; + break; + case dh_typecode_i64: + case dh_typecode_s64: + type = TCG_TYPE_I64; + kind = TCG_TARGET_CALL_ARG_I64; + break; + case dh_typecode_ptr: + type = TCG_TYPE_PTR; + kind = TCG_CALL_ARG_NORMAL; + break; + default: + g_assert_not_reached(); } - if (TCG_TARGET_REG_BITS < 64 && is_64bit) { + switch (kind) { + case TCG_CALL_ARG_EVEN: + if (real_args & 1) { + op->args[pi++] = TCG_CALL_DUMMY_ARG; + real_args++; + } + /* fall through */ + case TCG_CALL_ARG_NORMAL: + if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { + op->args[pi++] = temp_arg(args[i]); + op->args[pi++] = temp_arg(args[i] + 1); + real_args += 2; + break; + } op->args[pi++] = temp_arg(args[i]); - op->args[pi++] = temp_arg(args[i] + 1); - real_args += 2; - continue; + real_args++; + break; + default: + g_assert_not_reached(); } - - op->args[pi++] = temp_arg(args[i]); - real_args++; } op->args[pi++] = (uintptr_t)func; op->args[pi++] = (uintptr_t)info; From patchwork Thu Oct 20 11:52:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616745 Delivered-To: patch@linaro.org Received: by 2002:a17:906:1c0f:b0:78b:b85f:9498 with SMTP id k15csp341873ejg; Thu, 20 Oct 2022 06:43:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4z+RDwybMDhGsHqbFR4Py3EqTgdi9KZFZr5wBEZtBVCc4KxEE/OFn2YThK9dYhAdZrKT52 X-Received: by 2002:ad4:5dc6:0:b0:4b3:5d60:f41c with SMTP id m6-20020ad45dc6000000b004b35d60f41cmr11375118qvh.100.1666273431998; Thu, 20 Oct 2022 06:43:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666273431; cv=none; d=google.com; s=arc-20160816; b=skSTjqgP0cS415+7JeXRSfn3jOfClFhVwPpDGXzCjOaqUg7HC1tVzXZ7XC4qHQGxM1 qhTTrWLPj+WtFr68fdDf7LFApC/roEK1ZXAmOFfMfbEODPaSJr/UmjEUJHfRd/iBpnJe b6Hw7g7kLkEjryAwZB4gv4G7aypAMyb9nV04AphWIvyzdsCfE3K2blBqdmdFTb9xxo7D oUgmY/3OaP6lwBpVv9p+Lv7oUDyCXvCHJ1xPtKVxbCyQDqqYVztA6fTjSKxQVv1BWJx6 e7cPT8RFsq1ZOQIpXtAvqIUAA+zWyPxtJZqfMtf3bDYTnUI8mJDqits6UrE1KDRsmyMj 7bxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pJkoywglMDTgQlSNmZJ4+L7Y+TVoCeDYFcp1hOFi9dc=; b=F2n5zxu9Qe0DZmvka/eKndp/eetJcR67QwL+Mlo2u+6gQI1Ziei1qCyRPrKXzluAHn eSMWbnFa0Kmkhutg57hjzU0EFC8BwZplnxlag36W0Rcgglxx1AJg4KDl8djeG+CkBvoY Gx8pKxnk9Lenco/ItYa3ZHgcBrOSj1GaoFVLpA3QrTq9p9rplTx4bFJFkJBjFktAC9kW kw7aVhDhexKuqhM4OrW5OegGbRlcJtXd6GJ29lmc12b9EX74hfrDLMHC7lxE4GDIKLEJ UXWGZG/CHWtcuDf/zkGF5Z/AJUQghT1/27ZeEkBbUsn3G44LSzpJ4h4WgQCzoDK9FqlR OF2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="XS/uZWck"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Drop TCG_CALL_DUMMY_ARG, as we no longer need to leave gaps in the op->args[] array. For tcg_gen_callN, loop over the arguments once. Allocate the TCGOp for the call early but delay emitting it, collecting arguments first. This allows the argument processing loop to emit code for extensions and have them sequenced before the call. Free the temporaries for extensions immediately. For tcg_reg_alloc_call, loop over the arguments in reverse order, which allows stack slots to be filled first naturally. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 3 - tcg/tcg-internal.h | 17 +- tcg/tcg.c | 591 +++++++++++++++++++++++++++------------------ 3 files changed, 377 insertions(+), 234 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 08f997cbbc..c342396260 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -419,9 +419,6 @@ typedef TCGv_ptr TCGv_env; #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) -/* Used to align parameters. See the comment before tcgv_i32_temp. */ -#define TCG_CALL_DUMMY_ARG ((TCGArg)0) - /* * Flags for the bswap opcodes. * If IZ, the input is zero-extended, otherwise unknown. diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index f574743ff8..097fef2325 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -42,11 +42,24 @@ typedef enum { TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ } TCGCallArgumentKind; +typedef struct TCGCallArgumentLoc { + TCGCallArgumentKind kind : 8; + unsigned reg_slot : 8; + unsigned stk_slot : 8; + unsigned reg_n : 2; + unsigned arg_idx : 4; + unsigned tmp_subindex : 1; +} TCGCallArgumentLoc; + typedef struct TCGHelperInfo { void *func; const char *name; - unsigned flags; - unsigned typemask; + unsigned typemask : 32; + unsigned flags : 8; + unsigned nr_in : 8; + unsigned nr_out : 8; + TCGCallReturnKind out_kind : 8; + TCGCallArgumentLoc in[MAX_OPC_PARAM_IARGS * MAX_OPC_PARAM_PER_ARG]; } TCGHelperInfo; extern TCGContext tcg_init_ctx; diff --git a/tcg/tcg.c b/tcg/tcg.c index 5704373d57..31ddace5e5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -546,7 +546,7 @@ void tcg_pool_reset(TCGContext *s) #include "exec/helper-proto.h" -static const TCGHelperInfo all_helpers[] = { +static TCGHelperInfo all_helpers[] = { #include "exec/helper-tcg.h" }; static GHashTable *helper_table; @@ -564,6 +564,162 @@ static ffi_type * const typecode_to_ffi[8] = { }; #endif +typedef struct TCGCumulativeArgs { + int arg_idx; /* tcg_gen_callN args[] */ + int op_arg_idx; /* TCGOp op->args[] */ + int info_in_idx; /* TCGHelperInfo in[] */ + int reg_slot; /* tcg_target_call_iarg_regs[] */ + int stk_slot; /* TCG_TARGET_CALL_STACK_OFFSET + i*word */ + int max_reg_slot; + int max_stk_slot; +} TCGCumulativeArgs; + +static void layout_arg_1(TCGCumulativeArgs *cum, TCGHelperInfo *info, + TCGCallArgumentKind kind) +{ + TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; + + *loc = (TCGCallArgumentLoc){ + .kind = kind, + .arg_idx = cum->arg_idx, + }; + + if (cum->reg_slot < cum->max_reg_slot) { + loc->reg_slot = cum->reg_slot++; + loc->reg_n = 1; + } else { + loc->stk_slot = cum->stk_slot++; + } + + cum->info_in_idx++; + cum->op_arg_idx++; +} + +static void layout_arg_normal_2(TCGCumulativeArgs *cum, TCGHelperInfo *info) +{ + TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; + + /* Layout the pair using the same arg_idx... */ + layout_arg_1(cum, info, TCG_CALL_ARG_NORMAL); + layout_arg_1(cum, info, TCG_CALL_ARG_NORMAL); + + /* ... then adjust the second loc to the second subindex. */ + loc[1].tmp_subindex = 1; +} + +static void init_call_layout(TCGHelperInfo *info) +{ + unsigned typemask = info->typemask; + unsigned typecode; + TCGCumulativeArgs cum = { + .max_reg_slot = ARRAY_SIZE(tcg_target_call_iarg_regs), + .max_stk_slot = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long), + }; + + /* + * Parse and place any function return value. + */ + typecode = typemask & 7; + switch (typecode) { + case dh_typecode_void: + info->nr_out = 0; + break; + case dh_typecode_i32: + case dh_typecode_s32: + case dh_typecode_ptr: + info->nr_out = 1; + info->out_kind = TCG_CALL_RET_NORMAL; + break; + case dh_typecode_i64: + case dh_typecode_s64: + info->nr_out = 64 / TCG_TARGET_REG_BITS; + info->out_kind = TCG_CALL_RET_NORMAL; + break; + default: + g_assert_not_reached(); + } + assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); + + /* + * The final two op->arg[] indexes are used for func & info. + * Account for that now to simplify the test below. + */ + cum.op_arg_idx = info->nr_out + 2; + + /* + * Parse and place function arguments. + */ + for (typemask >>= 3; typemask; typemask >>= 3, cum.arg_idx++) { + TCGCallArgumentKind kind; + TCGType type; + + typecode = typemask & 7; + switch (typecode) { + case dh_typecode_i32: + case dh_typecode_s32: + type = TCG_TYPE_I32; + kind = TCG_TARGET_CALL_ARG_I32; + break; + case dh_typecode_i64: + case dh_typecode_s64: + type = TCG_TYPE_I64; + kind = TCG_TARGET_CALL_ARG_I64; + break; + case dh_typecode_ptr: + type = TCG_TYPE_PTR; + kind = TCG_CALL_ARG_NORMAL; + break; + default: + g_assert_not_reached(); + } + + switch (kind) { + case TCG_CALL_ARG_EVEN: + tcg_debug_assert(cum.max_reg_slot % 2 == 0); + if (cum.reg_slot < cum.max_reg_slot) { + cum.reg_slot += cum.reg_slot & 1; + } else { + cum.stk_slot += cum.stk_slot & 1; + } + /* fall through */ + case TCG_CALL_ARG_NORMAL: + switch (type) { + case TCG_TYPE_I32: + layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); + break; + case TCG_TYPE_I64: + if (TCG_TARGET_REG_BITS == 32) { + layout_arg_normal_2(&cum, info); + } else { + layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); + } + break; + default: + g_assert_not_reached(); + } + break; + case TCG_CALL_ARG_EXTEND: + kind = TCG_CALL_ARG_EXTEND_U + (typecode & 1); + /* fall through */ + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + assert(type == TCG_TYPE_I32); + layout_arg_1(&cum, info, kind); + break; + default: + g_assert_not_reached(); + } + } + info->nr_in = cum.info_in_idx; + + /* Validate that we didn't overrun the input array. */ + assert(cum.info_in_idx <= ARRAY_SIZE(info->in)); + /* Validate that we didn't overrun the output array. */ + assert(cum.op_arg_idx <= MAX_OPC_PARAM); + /* Validate the backend has preallocated enough space on stack. */ + assert(cum.stk_slot <= cum.max_stk_slot); +} + static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; static void process_op_defs(TCGContext *s); static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, @@ -603,6 +759,7 @@ static void tcg_context_init(unsigned max_cpus) helper_table = g_hash_table_new(NULL, NULL); for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { + init_call_layout(&all_helpers[i]); g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, (gpointer)&all_helpers[i]); } @@ -1473,18 +1630,15 @@ bool tcg_op_supported(TCGOpcode op) } } -/* Note: we convert the 64 bit args to 32 bit and do some alignment - and endian swap. Maybe it would be better to do the alignment - and endian swap in tcg_reg_alloc_call(). */ +static TCGOp *tcg_op_alloc(TCGOpcode opc); + void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) { - int i, real_args, nb_rets, pi; - unsigned typemask; + TCGOp *op = tcg_op_alloc(INDEX_op_call); const TCGHelperInfo *info; - TCGOp *op; + int i, n, pi = 0; info = g_hash_table_lookup(helper_table, (gpointer)func); - typemask = info->typemask; #ifdef CONFIG_PLUGIN /* detect non-plugin helpers */ @@ -1493,106 +1647,59 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) } #endif - if (TCG_TARGET_CALL_ARG_I32 == TCG_CALL_ARG_EXTEND) { - for (i = 0; i < nargs; ++i) { - int argtype = extract32(typemask, (i + 1) * 3, 3); - bool is_32bit = (argtype & ~1) == dh_typecode_i32; - bool is_signed = argtype & 1; + TCGOP_CALLO(op) = n = info->nr_out; + switch (n) { + case 0: + tcg_debug_assert(ret == NULL); + break; + case 1: + tcg_debug_assert(ret != NULL); + op->args[pi++] = temp_arg(ret); + break; + case 2: + tcg_debug_assert(ret != NULL); + tcg_debug_assert(ret->temp_subindex == 0); + op->args[pi++] = temp_arg(ret); + op->args[pi++] = temp_arg(ret + 1); + break; + default: + g_assert_not_reached(); + } - if (is_32bit) { + TCGOP_CALLI(op) = n = info->nr_in; + for (i = 0; i < n; i++) { + const TCGCallArgumentLoc *loc = &info->in[i]; + TCGTemp *ts = args[loc->arg_idx] + loc->tmp_subindex; + + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + op->args[pi++] = temp_arg(ts); + break; + + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + { TCGv_i64 temp = tcg_temp_new_i64(); - TCGv_i32 orig = temp_tcgv_i32(args[i]); - if (is_signed) { + TCGv_i32 orig = temp_tcgv_i32(ts); + + if (loc->kind == TCG_CALL_ARG_EXTEND_S) { tcg_gen_ext_i32_i64(temp, orig); } else { tcg_gen_extu_i32_i64(temp, orig); } - args[i] = tcgv_i64_temp(temp); + op->args[pi++] = tcgv_i64_arg(temp); + tcg_temp_free_i64(temp); } - } - } - - op = tcg_emit_op(INDEX_op_call); - - pi = 0; - if (ret != NULL) { - if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) == dh_typecode_i64) { - op->args[pi++] = temp_arg(ret); - op->args[pi++] = temp_arg(ret + 1); - nb_rets = 2; - } else { - op->args[pi++] = temp_arg(ret); - nb_rets = 1; - } - } else { - nb_rets = 0; - } - TCGOP_CALLO(op) = nb_rets; - - real_args = 0; - for (i = 0; i < nargs; i++) { - int argtype = extract32(typemask, (i + 1) * 3, 3); - TCGCallArgumentKind kind; - TCGType type; - - switch (argtype) { - case dh_typecode_i32: - case dh_typecode_s32: - type = TCG_TYPE_I32; - kind = TCG_TARGET_CALL_ARG_I32; break; - case dh_typecode_i64: - case dh_typecode_s64: - type = TCG_TYPE_I64; - kind = TCG_TARGET_CALL_ARG_I64; - break; - case dh_typecode_ptr: - type = TCG_TYPE_PTR; - kind = TCG_CALL_ARG_NORMAL; - break; - default: - g_assert_not_reached(); - } - switch (kind) { - case TCG_CALL_ARG_EVEN: - if (real_args & 1) { - op->args[pi++] = TCG_CALL_DUMMY_ARG; - real_args++; - } - /* fall through */ - case TCG_CALL_ARG_NORMAL: - if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { - op->args[pi++] = temp_arg(args[i]); - op->args[pi++] = temp_arg(args[i] + 1); - real_args += 2; - break; - } - op->args[pi++] = temp_arg(args[i]); - real_args++; - break; default: g_assert_not_reached(); } } op->args[pi++] = (uintptr_t)func; op->args[pi++] = (uintptr_t)info; - TCGOP_CALLI(op) = real_args; - /* Make sure the fields didn't overflow. */ - tcg_debug_assert(TCGOP_CALLI(op) == real_args); - tcg_debug_assert(pi <= ARRAY_SIZE(op->args)); - - if (TCG_TARGET_CALL_ARG_I32 == TCG_CALL_ARG_EXTEND) { - for (i = 0; i < nargs; ++i) { - int argtype = extract32(typemask, (i + 1) * 3, 3); - bool is_32bit = (argtype & ~1) == dh_typecode_i32; - - if (is_32bit) { - tcg_temp_free_internal(args[i]); - } - } - } + QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); } static void tcg_reg_alloc_start(TCGContext *s) @@ -1807,10 +1914,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) } for (i = 0; i < nb_iargs; i++) { TCGArg arg = op->args[nb_oargs + i]; - const char *t = ""; - if (arg != TCG_CALL_DUMMY_ARG) { - t = tcg_get_arg_str(s, buf, sizeof(buf), arg); - } + const char *t = tcg_get_arg_str(s, buf, sizeof(buf), arg); col += ne_fprintf(f, ",%s", t); } } else { @@ -2576,12 +2680,11 @@ static void liveness_pass_1(TCGContext *s) switch (opc) { case INDEX_op_call: { - int call_flags; - int nb_call_regs; + const TCGHelperInfo *info = tcg_call_info(op); + int call_flags = tcg_call_flags(op); nb_oargs = TCGOP_CALLO(op); nb_iargs = TCGOP_CALLI(op); - call_flags = tcg_call_flags(op); /* pure functions can be removed if their result is unused */ if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { @@ -2621,7 +2724,7 @@ static void liveness_pass_1(TCGContext *s) /* Record arguments that die in this helper. */ for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { ts = arg_temp(op->args[i]); - if (ts && ts->state & TS_DEAD) { + if (ts->state & TS_DEAD) { arg_life |= DEAD_ARG << i; } } @@ -2629,31 +2732,59 @@ static void liveness_pass_1(TCGContext *s) /* For all live registers, remove call-clobbered prefs. */ la_cross_call(s, nb_temps); - nb_call_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); + /* + * Input arguments are live for preceding opcodes. + * + * For those arguments that die, and will be allocated in + * registers, clear the register set for that arg, to be + * filled in below. For args that will be on the stack, + * reset to any available reg. Process arguments in reverse + * order so that if a temp is used more than once, the stack + * reset to max happens before the register reset to 0. + */ + for (i = nb_iargs - 1; i >= 0; i--) { + const TCGCallArgumentLoc *loc = &info->in[i]; + ts = arg_temp(op->args[nb_oargs + i]); - /* Input arguments are live for preceding opcodes. */ - for (i = 0; i < nb_iargs; i++) { - ts = arg_temp(op->args[i + nb_oargs]); - if (ts && ts->state & TS_DEAD) { - /* For those arguments that die, and will be allocated - * in registers, clear the register set for that arg, - * to be filled in below. For args that will be on - * the stack, reset to any available reg. - */ - *la_temp_pref(ts) - = (i < nb_call_regs ? 0 : - tcg_target_available_regs[ts->type]); + if (ts->state & TS_DEAD) { + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + if (loc->reg_n) { + *la_temp_pref(ts) = 0; + break; + } + /* fall through */ + default: + *la_temp_pref(ts) = + tcg_target_available_regs[ts->type]; + break; + } ts->state &= ~TS_DEAD; } } - /* For each input argument, add its input register to prefs. - If a temp is used once, this produces a single set bit. */ - for (i = 0; i < MIN(nb_call_regs, nb_iargs); i++) { - ts = arg_temp(op->args[i + nb_oargs]); - if (ts) { - tcg_regset_set_reg(*la_temp_pref(ts), - tcg_target_call_iarg_regs[i]); + /* + * For each input argument, add its input register to prefs. + * If a temp is used once, this produces a single set bit; + * if a temp is used multiple times, this produces a set. + */ + for (i = 0; i < nb_iargs; i++) { + const TCGCallArgumentLoc *loc = &info->in[i]; + ts = arg_temp(op->args[nb_oargs + i]); + + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + if (loc->reg_n) { + tcg_regset_set_reg(*la_temp_pref(ts), + tcg_target_call_iarg_regs[loc->reg_slot]); + } + break; + default: + break; } } } @@ -2922,21 +3053,19 @@ static bool liveness_pass_2(TCGContext *s) /* Make sure that input arguments are available. */ for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { arg_ts = arg_temp(op->args[i]); - if (arg_ts) { - dir_ts = arg_ts->state_ptr; - if (dir_ts && arg_ts->state == TS_DEAD) { - TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 - ? INDEX_op_ld_i32 - : INDEX_op_ld_i64); - TCGOp *lop = tcg_op_insert_before(s, op, lopc); + dir_ts = arg_ts->state_ptr; + if (dir_ts && arg_ts->state == TS_DEAD) { + TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 + ? INDEX_op_ld_i32 + : INDEX_op_ld_i64); + TCGOp *lop = tcg_op_insert_before(s, op, lopc); - lop->args[0] = temp_arg(dir_ts); - lop->args[1] = temp_arg(arg_ts->mem_base); - lop->args[2] = arg_ts->mem_offset; + lop->args[0] = temp_arg(dir_ts); + lop->args[1] = temp_arg(arg_ts->mem_base); + lop->args[2] = arg_ts->mem_offset; - /* Loaded, but synced with memory. */ - arg_ts->state = TS_MEM; - } + /* Loaded, but synced with memory. */ + arg_ts->state = TS_MEM; } } @@ -4156,106 +4285,100 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) return true; } +static void load_arg_normal_1(TCGContext *s, const TCGCallArgumentLoc *loc, + TCGTemp *ts, TCGRegSet *allocated_regs) +{ + TCGReg reg; + + /* + * If the destination is on the stack, load up the temp and store. + * If there are many call-saved registers, the temp might live to + * see another use; otherwise it'll be discarded. + */ + if (!loc->reg_n) { + temp_load(s, ts, tcg_target_available_regs[ts->type], + *allocated_regs, 0); + tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + loc->stk_slot * sizeof(tcg_target_long)); + return; + } + + reg = tcg_target_call_iarg_regs[loc->reg_slot]; + + if (ts->val_type == TEMP_VAL_REG) { + if (ts->reg != reg) { + tcg_reg_free(s, reg, *allocated_regs); + if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { + /* + * Cross register class move not supported. Sync the + * temp back to its slot and load from there. + */ + temp_sync(s, ts, *allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); + } + } + } else { + TCGRegSet arg_set = 0; + + tcg_reg_free(s, reg, *allocated_regs); + tcg_regset_set_reg(arg_set, reg); + temp_load(s, ts, arg_set, *allocated_regs, 0); + } + + tcg_regset_set_reg(*allocated_regs, reg); +} + static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs = TCGOP_CALLO(op); const int nb_iargs = TCGOP_CALLI(op); const TCGLifeData arg_life = op->life; - const TCGHelperInfo *info; - int flags, nb_regs, i; - TCGReg reg; - TCGArg arg; - TCGTemp *ts; - intptr_t stack_offset; - size_t call_stack_size; - tcg_insn_unit *func_addr; - int allocate_args; - TCGRegSet allocated_regs; + const TCGHelperInfo *info = tcg_call_info(op); + TCGRegSet allocated_regs = s->reserved_regs; + int i; - func_addr = tcg_call_func(op); - info = tcg_call_info(op); - flags = info->flags; + /* + * Move inputs into place in reverse order, + * so that we place stacked arguments first. + */ + for (i = nb_iargs - 1; i >= 0; --i) { + const TCGCallArgumentLoc *loc = &info->in[i]; + TCGTemp *ts = arg_temp(op->args[nb_oargs + i]); - nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); - if (nb_regs > nb_iargs) { - nb_regs = nb_iargs; - } - - /* assign stack slots first */ - call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long); - call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) & - ~(TCG_TARGET_STACK_ALIGN - 1); - allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE); - if (allocate_args) { - /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed, - preallocate call stack */ - tcg_abort(); - } - - stack_offset = TCG_TARGET_CALL_STACK_OFFSET; - for (i = nb_regs; i < nb_iargs; i++) { - arg = op->args[nb_oargs + i]; - if (arg != TCG_CALL_DUMMY_ARG) { - ts = arg_temp(arg); - temp_load(s, ts, tcg_target_available_regs[ts->type], - s->reserved_regs, 0); - tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); - } - stack_offset += sizeof(tcg_target_long); - } - - /* assign input registers */ - allocated_regs = s->reserved_regs; - for (i = 0; i < nb_regs; i++) { - arg = op->args[nb_oargs + i]; - if (arg != TCG_CALL_DUMMY_ARG) { - ts = arg_temp(arg); - reg = tcg_target_call_iarg_regs[i]; - - if (ts->val_type == TEMP_VAL_REG) { - if (ts->reg != reg) { - tcg_reg_free(s, reg, allocated_regs); - if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - /* - * Cross register class move not supported. Sync the - * temp back to its slot and load from there. - */ - temp_sync(s, ts, allocated_regs, 0, 0); - tcg_out_ld(s, ts->type, reg, - ts->mem_base->reg, ts->mem_offset); - } - } - } else { - TCGRegSet arg_set = 0; - - tcg_reg_free(s, reg, allocated_regs); - tcg_regset_set_reg(arg_set, reg); - temp_load(s, ts, arg_set, allocated_regs, 0); - } - - tcg_regset_set_reg(allocated_regs, reg); + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + load_arg_normal_1(s, loc, ts, &allocated_regs); + break; + default: + g_assert_not_reached(); } } - - /* mark dead temporaries and free the associated registers */ + + /* Mark dead temporaries and free the associated registers. */ for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { if (IS_DEAD_ARG(i)) { temp_dead(s, arg_temp(op->args[i])); } } - - /* clobber call registers */ + + /* Clobber call registers. */ for (i = 0; i < TCG_TARGET_NB_REGS; i++) { if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { tcg_reg_free(s, i, allocated_regs); } } - /* Save globals if they might be written by the helper, sync them if - they might be read. */ - if (flags & TCG_CALL_NO_READ_GLOBALS) { + /* + * Save globals if they might be written by the helper, + * sync them if they might be read. + */ + if (info->flags & TCG_CALL_NO_READ_GLOBALS) { /* Nothing to do */ - } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) { + } else if (info->flags & TCG_CALL_NO_WRITE_GLOBALS) { sync_globals(s, allocated_regs); } else { save_globals(s, allocated_regs); @@ -4266,31 +4389,41 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) gpointer hash = (gpointer)(uintptr_t)info->typemask; ffi_cif *cif = g_hash_table_lookup(ffi_table, hash); assert(cif != NULL); - tcg_out_call(s, func_addr, cif); + tcg_out_call(s, tcg_call_func(op), cif); } #else - tcg_out_call(s, func_addr); + tcg_out_call(s, tcg_call_func(op)); #endif - /* assign output registers and emit moves if needed */ - for(i = 0; i < nb_oargs; i++) { - arg = op->args[i]; - ts = arg_temp(arg); + /* Assign output registers and emit moves if needed. */ + switch (info->out_kind) { + case TCG_CALL_RET_NORMAL: + for (i = 0; i < nb_oargs; i++) { + TCGTemp *ts = arg_temp(op->args[i]); + TCGReg reg = tcg_target_call_oarg_regs[i]; - /* ENV should not be modified. */ - tcg_debug_assert(!temp_readonly(ts)); + /* ENV should not be modified. */ + tcg_debug_assert(!temp_readonly(ts)); - reg = tcg_target_call_oarg_regs[i]; - tcg_debug_assert(s->reg_to_temp[reg] == NULL); - if (ts->val_type == TEMP_VAL_REG) { - s->reg_to_temp[ts->reg] = NULL; + tcg_debug_assert(s->reg_to_temp[reg] == NULL); + if (ts->val_type == TEMP_VAL_REG) { + s->reg_to_temp[ts->reg] = NULL; + } + ts->val_type = TEMP_VAL_REG; + ts->reg = reg; + ts->mem_coherent = 0; + s->reg_to_temp[reg] = ts; } - ts->val_type = TEMP_VAL_REG; - ts->reg = reg; - ts->mem_coherent = 0; - s->reg_to_temp[reg] = ts; + break; + default: + g_assert_not_reached(); + } + + /* Flush or discard output registers as needed. */ + for (i = 0; i < nb_oargs; i++) { + TCGTemp *ts = arg_temp(op->args[i]); if (NEED_SYNC_ARG(i)) { - temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); 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Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 7 +++ tcg/tcg.c | 129 +++++++++++++++++++++++++-------------------- 2 files changed, 78 insertions(+), 58 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 097fef2325..696dc66ada 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -25,6 +25,10 @@ #ifndef TCG_INTERNAL_H #define TCG_INTERNAL_H +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + #define TCG_HIGHWATER 1024 /* @@ -54,6 +58,9 @@ typedef struct TCGCallArgumentLoc { typedef struct TCGHelperInfo { void *func; const char *name; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif unsigned typemask : 32; unsigned flags : 8; unsigned nr_in : 8; diff --git a/tcg/tcg.c b/tcg/tcg.c index 31ddace5e5..1602ee78d3 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -62,10 +62,6 @@ #include "tcg/tcg-ldst.h" #include "tcg-internal.h" -#ifdef CONFIG_TCG_INTERPRETER -#include -#endif - /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ static void tcg_target_init(TCGContext *s); @@ -552,17 +548,76 @@ static TCGHelperInfo all_helpers[] = { static GHashTable *helper_table; #ifdef CONFIG_TCG_INTERPRETER -static GHashTable *ffi_table; +static ffi_type *typecode_to_ffi(int argmask) +{ + switch (argmask) { + case dh_typecode_void: + return &ffi_type_void; + case dh_typecode_i32: + return &ffi_type_uint32; + case dh_typecode_s32: + return &ffi_type_sint32; + case dh_typecode_i64: + return &ffi_type_uint64; + case dh_typecode_s64: + return &ffi_type_sint64; + case dh_typecode_ptr: + return &ffi_type_pointer; + } + g_assert_not_reached(); +} -static ffi_type * const typecode_to_ffi[8] = { - [dh_typecode_void] = &ffi_type_void, - [dh_typecode_i32] = &ffi_type_uint32, - [dh_typecode_s32] = &ffi_type_sint32, - [dh_typecode_i64] = &ffi_type_uint64, - [dh_typecode_s64] = &ffi_type_sint64, - [dh_typecode_ptr] = &ffi_type_pointer, -}; -#endif +static void init_ffi_layouts(void) +{ + /* g_direct_hash/equal for direct comparisons on uint32_t. */ + GHashTable *ffi_table = g_hash_table_new(NULL, NULL); + + for (int i = 0; i < ARRAY_SIZE(all_helpers); ++i) { + TCGHelperInfo *info = &all_helpers[i]; + unsigned typemask = info->typemask; + gpointer hash = (gpointer)(uintptr_t)typemask; + struct { + ffi_cif cif; + ffi_type *args[]; + } *ca; + ffi_status status; + int nargs; + ffi_cif *cif; + + cif = g_hash_table_lookup(ffi_table, hash); + if (cif) { + info->cif = cif; + continue; + } + + /* Ignoring the return type, find the last non-zero field. */ + nargs = 32 - clz32(typemask >> 3); + nargs = DIV_ROUND_UP(nargs, 3); + + ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); + ca->cif.rtype = typecode_to_ffi(typemask & 7); + ca->cif.nargs = nargs; + + if (nargs != 0) { + ca->cif.arg_types = ca->args; + for (i = 0; i < nargs; ++i) { + int typecode = extract32(typemask, (i + 1) * 3, 3); + ca->args[i] = typecode_to_ffi(typecode); + } + } + + status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, + ca->cif.rtype, ca->cif.arg_types); + assert(status == FFI_OK); + + cif = &ca->cif; + info->cif = cif; + g_hash_table_insert(ffi_table, hash, (gpointer)cif); + } + + g_hash_table_destroy(ffi_table); +} +#endif /* CONFIG_TCG_INTERPRETER */ typedef struct TCGCumulativeArgs { int arg_idx; /* tcg_gen_callN args[] */ @@ -765,44 +820,7 @@ static void tcg_context_init(unsigned max_cpus) } #ifdef CONFIG_TCG_INTERPRETER - /* g_direct_hash/equal for direct comparisons on uint32_t. */ - ffi_table = g_hash_table_new(NULL, NULL); - for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { - struct { - ffi_cif cif; - ffi_type *args[]; - } *ca; - uint32_t typemask = all_helpers[i].typemask; - gpointer hash = (gpointer)(uintptr_t)typemask; - ffi_status status; - int nargs; - - if (g_hash_table_lookup(ffi_table, hash)) { - continue; - } - - /* Ignoring the return type, find the last non-zero field. */ - nargs = 32 - clz32(typemask >> 3); - nargs = DIV_ROUND_UP(nargs, 3); - - ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); - ca->cif.rtype = typecode_to_ffi[typemask & 7]; - ca->cif.nargs = nargs; - - if (nargs != 0) { - ca->cif.arg_types = ca->args; - for (i = 0; i < nargs; ++i) { - int typecode = extract32(typemask, (i + 1) * 3, 3); - ca->args[i] = typecode_to_ffi[typecode]; - } - } - - status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, - ca->cif.rtype, ca->cif.arg_types); - assert(status == FFI_OK); - - g_hash_table_insert(ffi_table, hash, (gpointer)&ca->cif); - } + init_ffi_layouts(); #endif tcg_target_init(s); @@ -4385,12 +4403,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) } #ifdef CONFIG_TCG_INTERPRETER - { - gpointer hash = (gpointer)(uintptr_t)info->typemask; - ffi_cif *cif = g_hash_table_lookup(ffi_table, hash); - assert(cif != NULL); - tcg_out_call(s, tcg_call_func(op), cif); - } + tcg_out_call(s, tcg_call_func(op), info->cif); #else tcg_out_call(s, tcg_call_func(op)); #endif From patchwork Thu Oct 20 11:52:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616789 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp341015pvb; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/tcg.c | 12 ++---------- tcg/aarch64/tcg-target.c.inc | 19 ++++++++++--------- tcg/arm/tcg-target.c.inc | 10 ++++++++-- tcg/i386/tcg-target.c.inc | 5 +++-- tcg/loongarch64/tcg-target.c.inc | 7 ++++--- tcg/mips/tcg-target.c.inc | 3 ++- tcg/ppc/tcg-target.c.inc | 7 ++++--- tcg/riscv/tcg-target.c.inc | 7 ++++--- tcg/s390x/tcg-target.c.inc | 12 +++++++++--- tcg/sparc64/tcg-target.c.inc | 3 ++- tcg/tci/tcg-target.c.inc | 3 ++- 11 files changed, 50 insertions(+), 38 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 1602ee78d3..b0f5eb0505 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -145,12 +145,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2); static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); -#ifdef CONFIG_TCG_INTERPRETER static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, - ffi_cif *cif); -#else -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target); -#endif + const TCGHelperInfo *info); static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -4402,11 +4398,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) save_globals(s, allocated_regs); } -#ifdef CONFIG_TCG_INTERPRETER - tcg_out_call(s, tcg_call_func(op), info->cif); -#else - tcg_out_call(s, tcg_call_func(op)); -#endif + tcg_out_call(s, tcg_call_func(op), info); /* Assign output registers and emit moves if needed. */ switch (info->out_kind) { diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d997f7922a..e8184fe001 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1336,22 +1336,23 @@ static void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target) } } -static inline void tcg_out_callr(TCGContext *s, TCGReg reg) -{ - tcg_out_insn(s, 3207, BLR, reg); -} - -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *target) { ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2; if (offset == sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, BL, offset); } else { tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_callr(s, TCG_REG_TMP); + tcg_out_insn(s, 3207, BLR, reg); } } +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, + const TCGHelperInfo *info) +{ + tcg_out_call_int(s, target); +} + void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) { @@ -1599,7 +1600,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); tcg_out_adr(s, TCG_REG_X3, lb->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & MO_SIZE]); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); if (opc & MO_SIGN) { tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0); } else { @@ -1625,7 +1626,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); tcg_out_adr(s, TCG_REG_X4, lb->raddr); - tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); tcg_out_goto(s, lb->raddr); return true; } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index aa3a888fed..e82749a602 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1131,7 +1131,7 @@ static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr) * The call case is mostly used for helpers - so it's not unreasonable * for them to be beyond branch range. */ -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr) { intptr_t addri = (intptr_t)addr; ptrdiff_t disp = tcg_pcrel_diff(s, addr); @@ -1150,6 +1150,12 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr) tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP); } +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr, + const TCGHelperInfo *info) +{ + tcg_out_call_int(s, addr); +} + static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) { if (l->has_value) { @@ -1515,7 +1521,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14); /* Use the canonical unsigned helpers and minimize icache usage. */ - tcg_out_call(s, qemu_ld_helpers[opc & MO_SIZE]); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); datalo = lb->datalo_reg; datahi = lb->datahi_reg; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index cb04e4b3ad..58bd5873f5 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1661,7 +1661,8 @@ static void tcg_out_branch(TCGContext *s, int call, const tcg_insn_unit *dest) } } -static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, + const TCGHelperInfo *info) { tcg_out_branch(s, 1, dest); } @@ -1885,7 +1886,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) (uintptr_t)l->raddr); } - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); data_reg = l->datalo_reg; switch (opc & MO_SSIZE) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index a3debf6da7..98da264f16 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -567,7 +567,8 @@ static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, + const TCGHelperInfo *info) { tcg_out_call_int(s, arg, false); } @@ -760,7 +761,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); - tcg_out_call(s, qemu_ld_helpers[size]); + tcg_out_call_int(s, qemu_ld_helpers[size], false); switch (opc & MO_SSIZE) { case MO_SB: @@ -821,7 +822,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); - tcg_out_call(s, qemu_st_helpers[size]); + tcg_out_call_int(s, qemu_st_helpers[size], false); return tcg_out_goto(s, l->raddr); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bd76f0c97f..292e490b5c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1020,7 +1020,8 @@ static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, + const TCGHelperInfo *info) { tcg_out_call_int(s, arg, false); tcg_out_nop(s); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 500b75a03a..f561a3492f 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2002,7 +2002,8 @@ static void tcg_out_call_int(TCGContext *s, int lk, #endif } -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, + const TCGHelperInfo *info) { tcg_out_call_int(s, LK, target); } @@ -2221,7 +2222,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); tcg_out32(s, MFSPR | RT(arg) | LR); - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); lo = lb->datalo_reg; hi = lb->datahi_reg; @@ -2290,7 +2291,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); tcg_out32(s, MFSPR | RT(arg) | LR); - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); tcg_out_b(s, 0, lb->raddr); return true; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 81a83e45b1..aa017d665a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -819,7 +819,8 @@ static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, + const TCGHelperInfo *info) { tcg_out_call_int(s, arg, false); } @@ -1002,7 +1003,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & MO_SSIZE]); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0); tcg_out_goto(s, l->raddr); @@ -1047,7 +1048,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); - tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); tcg_out_goto(s, l->raddr); return true; diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 47aaba7667..c3c0bcc3eb 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1691,7 +1691,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, tgen_branch(s, cc, l); } -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) +static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *dest) { ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1; if (off == (int32_t)off) { @@ -1702,6 +1702,12 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) } } +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, + const TCGHelperInfo *info) +{ + tcg_out_call_int(s, dest); +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, TCGReg base, TCGReg index, int disp) { @@ -1897,7 +1903,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) } tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr); - tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); @@ -1938,7 +1944,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) } tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); - tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); return true; diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index cb9453efdd..eb913f33c8 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -859,7 +859,8 @@ static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest, } } -static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest) +static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, + const TCGHelperInfo *info) { tcg_out_call_nodelay(s, dest, false); tcg_out_nop(s); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f3d7441e06..b07b30b9fc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -562,8 +562,9 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, - ffi_cif *cif) + const TCGHelperInfo *info) { + ffi_cif *cif = info->cif; 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Define the type enumerator, the typedef, and the helper-head.h macros. This cannot yet be used, because you can't allocate temporaries of this new type. Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 7 +++++++ include/tcg/tcg.h | 28 ++++++++++++++-------------- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index e242fed46e..9753df8e80 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -26,6 +26,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_i128 i128 #define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 @@ -40,6 +41,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_i128 Int128 #define dh_ctype_f16 uint32_t #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 @@ -71,6 +73,7 @@ #define dh_retvar_decl0_noreturn void #define dh_retvar_decl0_i32 TCGv_i32 retval #define dh_retvar_decl0_i64 TCGv_i64 retval +#define dh_retval_decl0_i128 TCGv_i128 retval #define dh_retvar_decl0_ptr TCGv_ptr retval #define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t)) @@ -78,6 +81,7 @@ #define dh_retvar_decl_noreturn #define dh_retvar_decl_i32 TCGv_i32 retval, #define dh_retvar_decl_i64 TCGv_i64 retval, +#define dh_retvar_decl_i128 TCGv_i128 retval, #define dh_retvar_decl_ptr TCGv_ptr retval, #define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t)) @@ -85,6 +89,7 @@ #define dh_retvar_noreturn NULL #define dh_retvar_i32 tcgv_i32_temp(retval) #define dh_retvar_i64 tcgv_i64_temp(retval) +#define dh_retvar_i128 tcgv_i128_temp(retval) #define dh_retvar_ptr tcgv_ptr_temp(retval) #define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) @@ -95,6 +100,7 @@ #define dh_typecode_i64 4 #define dh_typecode_s64 5 #define dh_typecode_ptr 6 +#define dh_typecode_i128 7 #define dh_typecode_int dh_typecode_s32 #define dh_typecode_f16 dh_typecode_i32 #define dh_typecode_f32 dh_typecode_i32 @@ -104,6 +110,7 @@ #define dh_callflag_i32 0 #define dh_callflag_i64 0 +#define dh_callflag_i128 0 #define dh_callflag_ptr 0 #define dh_callflag_void 0 #define dh_callflag_noreturn TCG_CALL_NO_RETURN diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index c342396260..e80c78b2e8 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -38,18 +38,15 @@ /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 266 -#if HOST_LONG_BITS == 32 #define MAX_OPC_PARAM_PER_ARG 2 -#else -#define MAX_OPC_PARAM_PER_ARG 1 -#endif #define MAX_OPC_PARAM_IARGS 7 #define MAX_OPC_PARAM_OARGS 1 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) -/* A Call op needs up to 4 + 2N parameters on 32-bit archs, - * and up to 4 + N parameters on 64-bit archs - * (N = number of input arguments + output arguments). */ +/* + * A Call op needs up to 4 + 2N parameters. + * (N = number of input arguments + output arguments). + */ #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) #define CPU_TEMP_BUF_NLONGS 128 @@ -289,6 +286,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_I128, TCG_TYPE_V64, TCG_TYPE_V128, @@ -364,13 +362,14 @@ typedef tcg_target_ulong TCGArg; in tcg/README. Target CPU front-end code uses these types to deal with TCG variables as it emits TCG code via the tcg_gen_* functions. They come in several flavours: - * TCGv_i32 : 32 bit integer type - * TCGv_i64 : 64 bit integer type - * TCGv_ptr : a host pointer type - * TCGv_vec : a host vector type; the exact size is not exposed - to the CPU front-end code. - * TCGv : an integer type the same size as target_ulong - (an alias for either TCGv_i32 or TCGv_i64) + * TCGv_i32 : 32 bit integer type + * TCGv_i64 : 64 bit integer type + * TCGv_i128 : 128 bit integer type + * TCGv_ptr : a host pointer type + * TCGv_vec : a host vector type; the exact size is not exposed + to the CPU front-end code. + * TCGv : an integer type the same size as target_ulong + (an alias for either TCGv_i32 or TCGv_i64) The compiler's type checking will complain if you mix them up and pass the wrong sized TCGv to a function. @@ -390,6 +389,7 @@ typedef tcg_target_ulong TCGArg; typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; +typedef struct TCGv_i128_d *TCGv_i128; typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; From patchwork Thu Oct 20 11:52:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616734 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp248807pvb; Thu, 20 Oct 2022 06:11:06 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7cj2L8v4lt1aL7Mu1h2781GQCiOkziJ5xw0XS9BdR1A4coug/3yIeK/0Dpj5KxmCvoiDzV X-Received: by 2002:a05:622a:1353:b0:39a:7309:137c with SMTP id w19-20020a05622a135300b0039a7309137cmr10972173qtk.557.1666271466055; Thu, 20 Oct 2022 06:11:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666271466; cv=none; d=google.com; s=arc-20160816; b=I3jGqFGScCv5zWGo2ZCaR1vJojQFWSUX19ItHLxVl3ar3cofGWZSO16w2sAImJbclO PpWeXGaRebA6UuVtHaEZ+wfqFAwXgkP+WElyUcM7pQDTyjur6X7Liygieh5+yNysjgKU Sid5R6TmTeB3g5D7m43xYWhCDLJPd1Z2YOF2ZaXWrcOHlXM61CQ4ND0P8Ybkjh8CVI1W vQhyauFpt8/9y0Xj8YwYTqe4pl2RfbkX94Om0vXasNkrVhDwgKYcfW2ItMoompiAaUKJ fY6dPX+7aTfd6pKqIuQIvhE2aIuzGp7bQJgroERj7gNJ5Nt6D4h8QaNVzzJkR3pUuCyH cjgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fhmdF+MnCCSp2UKUALsQ6VhhmPNIo+wxdpEVDIQzUk0=; b=pvXF9xXaxNlCbgW3mO5elro7j2gZw0hRUYQ6Vdo/qYQmm8CCu6SPrybNB1IcBe6EYb WptLKIjdesld/sD3LJ24f+30Am6ed25t5AL8XsCetGfUi1czr15Cy/UeZjen6bRQTmUq RbZkQom51KtYhBsiK9V7yLmppdCdyVvA7uj/M0BBlOWyDczf4jkuU0mfJT2A9qFQeNyB e/aKFyWzrTeFqdzGl8nGXaIFM7fN39RzCEx53Usfl2rKVPTf8+YPbw3SVQwRVpr5J4D7 H2eFYSVQ4JgW8VqrRiSDSvHY26Vx4pR5cnKEprybQL9Xj5KCDyB2Uy9GTzknQj+tkaYH Iaog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TA16wkv3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 2 + tcg/tcg.c | 127 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 128 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 696dc66ada..7d4f7049be 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -36,6 +36,7 @@ */ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ + TCG_CALL_RET_NORMAL_4, /* for i128, by 4 registers */ } TCGCallReturnKind; typedef enum { @@ -44,6 +45,7 @@ typedef enum { TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ + TCG_CALL_ARG_NORMAL_4, /* for i128, like normal with 4 slots */ } TCGCallArgumentKind; typedef struct TCGCallArgumentLoc { diff --git a/tcg/tcg.c b/tcg/tcg.c index b0f5eb0505..5b17892058 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -658,6 +658,30 @@ static void layout_arg_normal_2(TCGCumulativeArgs *cum, TCGHelperInfo *info) loc[1].tmp_subindex = 1; } +static void layout_arg_normal_4(TCGCumulativeArgs *cum, TCGHelperInfo *info) +{ + TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; + int reg_n = MIN(4, cum->max_reg_slot - cum->reg_slot); + + *loc = (TCGCallArgumentLoc){ + .kind = TCG_CALL_ARG_NORMAL_4, + .arg_idx = cum->arg_idx, + }; + + if (reg_n > 0) { + loc->reg_slot = cum->reg_slot; + loc->reg_n = reg_n; + cum->reg_slot += reg_n; + } + if (reg_n < 4) { + loc->stk_slot = cum->stk_slot; + cum->stk_slot += 4 - reg_n; + } + + cum->info_in_idx++; + cum->op_arg_idx++; +} + static void init_call_layout(TCGHelperInfo *info) { unsigned typemask = info->typemask; @@ -686,10 +710,29 @@ static void init_call_layout(TCGHelperInfo *info) info->nr_out = 64 / TCG_TARGET_REG_BITS; info->out_kind = TCG_CALL_RET_NORMAL; break; + case dh_typecode_i128: + /* + * No matter the call return method, we must have all of + * the temp subindexes in the call for liveness. + */ + info->nr_out = TCG_TARGET_REG_BITS == 32 ? 1 : 2; + info->out_kind = TCG_CALL_RET_NORMAL; /* TODO */ + switch (/* TODO */ TCG_CALL_RET_NORMAL) { + case TCG_CALL_RET_NORMAL: + if (TCG_TARGET_REG_BITS == 32) { + assert(ARRAY_SIZE(tcg_target_call_oarg_regs) >= 4); + info->out_kind = TCG_CALL_RET_NORMAL_4; + } else { + assert(ARRAY_SIZE(tcg_target_call_oarg_regs) >= 2); + } + break; + default: + g_assert_not_reached(); + } + break; default: g_assert_not_reached(); } - assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); /* * The final two op->arg[] indexes are used for func & info. @@ -745,6 +788,13 @@ static void init_call_layout(TCGHelperInfo *info) layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); } break; + case TCG_TYPE_I128: + if (TCG_TARGET_REG_BITS == 32) { + layout_arg_normal_4(&cum, info); + } else { + layout_arg_normal_2(&cum, info); + } + break; default: g_assert_not_reached(); } @@ -1687,6 +1737,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) switch (loc->kind) { case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_NORMAL_4: op->args[pi++] = temp_arg(ts); break; @@ -4299,6 +4350,41 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) return true; } +static void copy_to_stk_i128(TCGContext *s, int stk_slot, TCGTemp *ts, + int slot, TCGRegSet allocated_regs) +{ + int stk_off = TCG_TARGET_CALL_STACK_OFFSET + + stk_slot * sizeof(tcg_target_long); + + if (TCG_TARGET_REG_BITS == 32) { + TCGReg scratch; + + tcg_debug_assert(ts->type == TCG_TYPE_I128); + tcg_debug_assert(ts->val_type == TEMP_VAL_MEM); + tcg_debug_assert(ts->mem_allocated); + + scratch = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_I32], + allocated_regs, 0, false); + + for (; slot < 4; slot++) { + tcg_out_ld(s, TCG_TYPE_I32, scratch, + ts->mem_base->reg, ts->mem_offset + slot * 4); + tcg_out_st(s, TCG_TYPE_I32, scratch, + TCG_REG_CALL_STACK, stk_off + slot * 4); + } + } else { + tcg_debug_assert(ts->base_type == TCG_TYPE_I128); + tcg_debug_assert(ts->temp_subindex == 0); + + for (; slot < 2; slot++) { + temp_load(s, &ts[slot], tcg_target_available_regs[TCG_TYPE_I64], + allocated_regs, 0); + tcg_out_st(s, TCG_TYPE_I64, ts[slot].reg, + TCG_REG_CALL_STACK, stk_off + slot * 8); + } + } +} + static void load_arg_normal_1(TCGContext *s, const TCGCallArgumentLoc *loc, TCGTemp *ts, TCGRegSet *allocated_regs) { @@ -4344,6 +4430,24 @@ static void load_arg_normal_1(TCGContext *s, const TCGCallArgumentLoc *loc, tcg_regset_set_reg(*allocated_regs, reg); } +static void load_arg_normal_4(TCGContext *s, const TCGCallArgumentLoc *loc, + TCGTemp *ts, TCGRegSet *allocated_regs) +{ + int reg_n = loc->reg_n; + + if (reg_n != 4) { + copy_to_stk_i128(s, loc->stk_slot, ts, reg_n, *allocated_regs); + } + + for (reg_n--; reg_n >= 0; reg_n--) { + TCGReg reg = tcg_target_call_iarg_regs[loc->reg_slot + reg_n]; + + tcg_out_ld(s, TCG_TYPE_I32, reg, + ts->mem_base->reg, ts->mem_offset + reg_n * 4); + tcg_regset_set_reg(*allocated_regs, reg); + } +} + static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs = TCGOP_CALLO(op); @@ -4367,6 +4471,9 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) case TCG_CALL_ARG_EXTEND_S: load_arg_normal_1(s, loc, ts, &allocated_regs); break; + case TCG_CALL_ARG_NORMAL_4: + load_arg_normal_4(s, loc, ts, &allocated_regs); + break; default: g_assert_not_reached(); } @@ -4420,6 +4527,24 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) s->reg_to_temp[reg] = ts; } break; + + case TCG_CALL_RET_NORMAL_4: + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + { + TCGTemp *ts = arg_temp(op->args[0]); + + tcg_debug_assert(ts->type == TCG_TYPE_I128); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + for (i = 0; i < 4; i++) { + tcg_out_st(s, TCG_TYPE_I32, tcg_target_call_oarg_regs[i], + ts->mem_base->reg, ts->mem_offset + i * 4); + } + ts->val_type = TEMP_VAL_MEM; + } + break; + default: g_assert_not_reached(); } From patchwork Thu Oct 20 11:52:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616773 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp306424pvb; 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Signed-off-by: Richard Henderson --- tcg/tcg.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 5b17892058..3a0cbe8ac6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3318,11 +3318,12 @@ static void check_regs(TCGContext *s) static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - int size = tcg_type_size(ts->type); - int align; intptr_t off; + int size, align; - switch (ts->type) { + /* When allocating an object, look at the full type. */ + size = tcg_type_size(ts->base_type); + switch (ts->base_type) { case TCG_TYPE_I32: align = 4; break; @@ -3353,13 +3354,26 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) tcg_raise_tb_overflow(s); } s->current_frame_offset = off + size; - - ts->mem_offset = off; #if defined(__sparc__) - ts->mem_offset += TCG_TARGET_STACK_BIAS; + off += TCG_TARGET_STACK_BIAS; #endif - ts->mem_base = s->frame_temp; - ts->mem_allocated = 1; + + /* If the object was subdivided, assign memory to all the parts. */ + if (ts->base_type != ts->type) { + int part_size = tcg_type_size(ts->type); + int part_count = size / part_size; + + ts -= ts->temp_subindex; + for (int i = 0; i < part_count; ++i) { + ts[i].mem_offset = off + i * part_size; + ts[i].mem_base = s->frame_temp; + ts[i].mem_allocated = 1; + } + } else { + ts->mem_offset = off; + ts->mem_base = s->frame_temp; + ts->mem_allocated = 1; + } } static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); From patchwork Thu Oct 20 11:52:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616793 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp351857pvb; Thu, 20 Oct 2022 08:43:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM50DWxxClRZ/cN2rwXpIrXaFMkrypSWQLMYknpCdE6qlYSTFVnhabEqbUelZrXeKSyY9pt4 X-Received: by 2002:ac8:5741:0:b0:39b:ddca:545 with SMTP id 1-20020ac85741000000b0039bddca0545mr11491281qtx.630.1666280621832; Thu, 20 Oct 2022 08:43:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666280621; cv=none; d=google.com; s=arc-20160816; b=UE0cCYGR3i9sKQn5RP+UQi8JGiH/GBGeYPlSoxdyMyDHtTVCUengf28uhSB6PGVC3w VVSqHNcnuS+owEHShlURwXghtRK7WYtuPzRRuWAguxVQNKinRug3DvQsalUK+gabhrcP Ph0W5AbRS0sex46GGMO9ZW1c6j7CjWomyDwVD/fIk1lt7707R6EYUoGt4imgRmURDQnA 3tkq9832yXBrPxic1IbDdnegZa0OWLvCf33wgUVcoBKG+UnsHQgKHNYcNkX2YWHe/Ar2 54u+E/ClMQwZETAaP9O/cWQ7vlEw2z817rnKxKjOPNzIldK3RL2ToaphgSu1tB77lHNB E4Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iiMIRNpw5P5q7kktS94n7Y1tZR/QEi54aO2/hTFLLN8=; b=rNUwaIkea5Zp418whRqTsU/bxiw+1tqAyDgsHuetJT1Skhp2qnTekpZ1UMq9jW1CuU t2gOYgTjDVSDLKt1MXFhuHflOwUJ0isI3qleeSl9l21kG/OiZx9FMwFhnDqYx8/GWA0g 47vCYVVm+OhTV+mKoHkdm4Jb3GMauY1KkKucAm+O33BpNr3hEocHSIxSR/EKH4eiLzYU c8onO7HMujRXr+SsimQTThGQ27BaVp0wyiR2OYuVx7izex83WciISoWunvZrUL1XmnzJ awIXuAPWI/kbqP8FZUHG0cMzRsTql/lcBFQ+Kw1RkwAYFJa0AKBSsfuquRd8j4DQBcMx QaMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GFy0kIZ9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Add stubs for all other backends. Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 ++ tcg/aarch64/tcg-target.c.inc | 7 +++++++ tcg/arm/tcg-target.c.inc | 20 ++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 8 ++++++++ tcg/loongarch64/tcg-target.c.inc | 7 +++++++ tcg/mips/tcg-target.c.inc | 7 +++++++ tcg/ppc/tcg-target.c.inc | 7 +++++++ tcg/riscv/tcg-target.c.inc | 7 +++++++ tcg/s390x/tcg-target.c.inc | 7 +++++++ tcg/sparc64/tcg-target.c.inc | 7 +++++++ tcg/tci/tcg-target.c.inc | 7 +++++++ 11 files changed, 86 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 3a0cbe8ac6..390724e652 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,6 +103,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long) + __attribute__((unused)); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index e8184fe001..f089a74f0e 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1102,6 +1102,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_out_insn(s, 3305, LDR, 0, rd); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + /* Define something more legible for general use. */ #define tcg_out_ldst_r tcg_out_insn_3310 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index e82749a602..2950a29d49 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2548,6 +2548,26 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + int enc, opc = ARITH_ADD; + + /* All of the easiest immediates to encode are positive. */ + if (imm < 0) { + imm = -imm; + opc = ARITH_SUB; + } + enc = encode_imm(imm); + if (enc >= 0) { + tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); + tcg_out_dat_reg(s, COND_AL, opc, rd, rs, + TCG_REG_TMP, SHIFT_IMM_LSL(0)); + } +} + /* Type is always V128, with I64 elements. */ static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 58bd5873f5..6a021dda8b 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1069,6 +1069,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); +} + static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { if (val == (int8_t)val) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 98da264f16..967bf307b8 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -389,6 +389,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_andi(s, ret, arg, 0xff); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 292e490b5c..22b5463f0f 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -550,6 +550,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) { /* ret and arg can't be register tmp0 */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index f561a3492f..d9e4ba8883 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1125,6 +1125,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static bool mask_operand(uint32_t c, int *mb, int *me) { uint32_t lsb, test; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index aa017d665a..6072945ccb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -545,6 +545,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c3c0bcc3eb..8663a963a6 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1020,6 +1020,13 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, return false; } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); +} + /* load data from an absolute host address */ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, const void *abs) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index eb913f33c8..f6a8a8e605 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -497,6 +497,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, TCGReg a2, int op) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b07b30b9fc..8bf02a96e9 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -561,6 +561,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); 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Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 10 ++-- tcg/tcg.c | 124 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 129 insertions(+), 5 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 7d4f7049be..1fe7bd7d5d 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -37,6 +37,7 @@ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ TCG_CALL_RET_NORMAL_4, /* for i128, by 4 registers */ + TCG_CALL_RET_BY_REF, /* for i128, by reference as first arg */ } TCGCallReturnKind; typedef enum { @@ -46,12 +47,15 @@ typedef enum { TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ TCG_CALL_ARG_NORMAL_4, /* for i128, like normal with 4 slots */ + TCG_CALL_ARG_BY_REF, /* ... by reference, first */ + TCG_CALL_ARG_BY_REF_2, /* ... by reference, second */ } TCGCallArgumentKind; typedef struct TCGCallArgumentLoc { - TCGCallArgumentKind kind : 8; - unsigned reg_slot : 8; - unsigned stk_slot : 8; + TCGCallArgumentKind kind : 4; + unsigned reg_slot : 6; + unsigned stk_slot : 6; + unsigned ref_slot : 6; unsigned reg_n : 2; unsigned arg_idx : 4; unsigned tmp_subindex : 1; diff --git a/tcg/tcg.c b/tcg/tcg.c index 390724e652..c664e3b18d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,8 +103,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long) - __attribute__((unused)); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); @@ -684,6 +683,34 @@ static void layout_arg_normal_4(TCGCumulativeArgs *cum, TCGHelperInfo *info) cum->op_arg_idx++; } +static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) +{ + TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; + int n = 128 / TCG_TARGET_REG_BITS; + + /* The first subindex carries the pointer. */ + layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); + + /* + * The callee is allowed to clobber memory associated with + * structure pass by-reference. Therefore we must make copies. + * Allocate space from the top of TCG_STATIC_CALL_ARGS_SIZE. + */ + cum->max_stk_slot -= n; + loc[0].ref_slot = cum->max_stk_slot; + + /* Any other subindex is present for liveness. */ + if (TCG_TARGET_REG_BITS == 64) { + loc[1] = (TCGCallArgumentLoc){ + .kind = TCG_CALL_ARG_BY_REF_2, + .arg_idx = cum->arg_idx, + .tmp_subindex = 1, + }; + cum->info_in_idx++; + cum->op_arg_idx++; + } +} + static void init_call_layout(TCGHelperInfo *info) { unsigned typemask = info->typemask; @@ -728,6 +755,18 @@ static void init_call_layout(TCGHelperInfo *info) assert(ARRAY_SIZE(tcg_target_call_oarg_regs) >= 2); } break; + case TCG_CALL_RET_BY_REF: + /* + * Allocate the first argument to the output. + * We don't need to store this anywhere, just make it + * unavailable for use in the input loop below. + */ + if (cum.max_reg_slot == 0) { + cum.stk_slot = 1; + } else { + cum.reg_slot = 1; + } + break; default: g_assert_not_reached(); } @@ -765,6 +804,10 @@ static void init_call_layout(TCGHelperInfo *info) type = TCG_TYPE_PTR; kind = TCG_CALL_ARG_NORMAL; break; + case dh_typecode_i128: + type = TCG_TYPE_I128; + kind = TCG_CALL_ARG_NORMAL; /* TODO */ + break; default: g_assert_not_reached(); } @@ -809,6 +852,10 @@ static void init_call_layout(TCGHelperInfo *info) assert(type == TCG_TYPE_I32); layout_arg_1(&cum, info, kind); break; + case TCG_CALL_ARG_BY_REF: + assert(type == TCG_TYPE_I128); + layout_arg_by_ref(&cum, info); + break; default: g_assert_not_reached(); } @@ -1740,6 +1787,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) switch (loc->kind) { case TCG_CALL_ARG_NORMAL: case TCG_CALL_ARG_NORMAL_4: + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_2: op->args[pi++] = temp_arg(ts); break; @@ -4464,6 +4513,27 @@ static void load_arg_normal_4(TCGContext *s, const TCGCallArgumentLoc *loc, } } +static void load_arg_by_ref(TCGContext *s, const TCGCallArgumentLoc *loc, + TCGReg ref_base, int ref_off, + TCGRegSet *allocated_regs) +{ + TCGReg reg; + + if (loc->reg_n) { + reg = tcg_target_call_iarg_regs[loc->reg_slot]; + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_regset_set_reg(*allocated_regs, reg); + } else { + int stk_off = TCG_TARGET_CALL_STACK_OFFSET + + loc->stk_slot * sizeof(tcg_target_long); + + reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], + *allocated_regs, 0, false); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, stk_off); + } +} + static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs = TCGOP_CALLO(op); @@ -4473,6 +4543,19 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) TCGRegSet allocated_regs = s->reserved_regs; int i; + /* + * The callee is allowed to clobber memory associated with + * structure pass by-reference. Therefore we must make copies. + * Do this first, before we start allocating argument regs. + */ + for (i = 0; i < nb_iargs; ++i) { + const TCGCallArgumentLoc *loc = &info->in[i]; + if (loc->kind == TCG_CALL_ARG_BY_REF) { + TCGTemp *ts = arg_temp(op->args[nb_oargs + i]); + copy_to_stk_i128(s, loc->ref_slot, ts, 0, allocated_regs); + } + } + /* * Move inputs into place in reverse order, * so that we place stacked arguments first. @@ -4490,6 +4573,15 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) case TCG_CALL_ARG_NORMAL_4: load_arg_normal_4(s, loc, ts, &allocated_regs); break; + case TCG_CALL_ARG_BY_REF: + load_arg_by_ref(s, loc, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + loc->ref_slot * sizeof(tcg_target_long), + &allocated_regs); + break; + case TCG_CALL_ARG_BY_REF_2: + /* nothing to do */ + break; default: g_assert_not_reached(); } @@ -4521,6 +4613,26 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) save_globals(s, allocated_regs); } + /* + * If the ABI passes a pointer to the returned struct as the first + * argument, load that now. Pass a pointer to the output home slot. + */ + if (info->out_kind == TCG_CALL_RET_BY_REF) { + static const TCGCallArgumentLoc ret_loc = { + .reg_n = ARRAY_SIZE(tcg_target_call_iarg_regs) != 0 + }; + TCGTemp *ts = arg_temp(op->args[0]); + + tcg_debug_assert(ts->base_type == TCG_TYPE_I128); + tcg_debug_assert(ts->temp_subindex == 0); + + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + load_arg_by_ref(s, &ret_loc, ts->mem_base->reg, ts->mem_offset, + &allocated_regs); + } + tcg_out_call(s, tcg_call_func(op), info); /* Assign output registers and emit moves if needed. */ @@ -4561,6 +4673,14 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) } break; + case TCG_CALL_RET_BY_REF: + /* The callee has performed a write through the reference. */ + for (i = 0; i < nb_oargs; i++) { + TCGTemp *ts = arg_temp(op->args[i]); + ts->val_type = TEMP_VAL_MEM; + } + break; + default: g_assert_not_reached(); } From patchwork Thu Oct 20 11:52:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616766 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp300486pvb; Thu, 20 Oct 2022 07:29:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5scGNuvoitFl4UL9dRGi9NcBoCcNkSFABxFgv5STevDAezGVgBHmEz/7MWT2DRBeBqMHN9 X-Received: by 2002:a05:6214:240a:b0:4b1:cb3e:d49c with SMTP id fv10-20020a056214240a00b004b1cb3ed49cmr11702388qvb.39.1666276170202; Thu, 20 Oct 2022 07:29:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666276170; cv=none; d=google.com; s=arc-20160816; b=ZGphuDimALbK+PDyOxvslymxxNnfXHkyIW9Dh6WjvpgMB0EADhGV35KfLd33uOJYDm 7Y42ZBpVwmoYf5HFzEwLxtY+o/52vWtAUyhNI1W0antOvBvZHvCMjIQV0ZUvfQjg45+u CGCI0qRHHsGz5Edw8zkcBa3sbdx0X18ETxLpCZ9uugQmNT+pLF1Z3zD6MRBLLp0wO3eR 9Hn1C2z45Vtwdu5l3bvobS5l7bSUWZK4fwbFSflMZxz3rJpo29XJeO4oR1T01JxOzJdf NXafkqTso+t7/EfNJmjiGFjl0WyS45qg/zNfknqU88yLhpwh8mG812uV0VSCwBVbRGGW xajw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VOKmoswrOKS7Hg0NdJ/RYFv+IzYKkD11gmIxifqiy40=; b=B/bY4uO+D9mcdYPljswtYDm4Enk0rVS67wigcQOeOBVk1WV736UqdU3jX5n86JsPfR ynWfXaLs2xXfRdqvJrdthmm6Z2L2GLk8HXyQN67s6O2RngdBzHwyH281hhneyMKFC2dL YfEgX17x4BenwztJxlW13GAeQ4GRHDKDOLGX5KoGz8BfqgN4nyNBcTR8bF2g6nKep7uI FiPNswY/7YmsrmJZL4NAnaNoTPTGY8cjv6mAijiyeMQHLeEk1gijtgwri0zOO70dZCeb CPpjeORtI5O6P+LhjVyq4q+QHH3mdAi5etkf0uDMTSXmOCX1inGKv9fqBhqlQpnujrF1 LUGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ztJMQVWS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/tcg.c | 14 ++++++++------ tcg/aarch64/tcg-target.c.inc | 10 +++++++--- tcg/arm/tcg-target.c.inc | 9 ++++++--- tcg/i386/tcg-target.c.inc | 22 ++++++++++++++++------ tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 10 ++++++---- tcg/ppc/tcg-target.c.inc | 10 ++++++---- tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 9 ++++++--- tcg/sparc64/tcg-target.c.inc | 12 ++++++------ tcg/tci/tcg-target.c.inc | 11 +++++------ 11 files changed, 78 insertions(+), 49 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index c664e3b18d..47f1f906fd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -148,6 +148,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, const TCGHelperInfo *info); +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -749,11 +750,11 @@ static void init_call_layout(TCGHelperInfo *info) switch (/* TODO */ TCG_CALL_RET_NORMAL) { case TCG_CALL_RET_NORMAL: if (TCG_TARGET_REG_BITS == 32) { - assert(ARRAY_SIZE(tcg_target_call_oarg_regs) >= 4); info->out_kind = TCG_CALL_RET_NORMAL_4; - } else { - assert(ARRAY_SIZE(tcg_target_call_oarg_regs) >= 2); } + /* Query the register now to trigger any assert early. */ + (void)tcg_target_call_oarg_reg(info->out_kind, + 127 / TCG_TARGET_REG_BITS); break; case TCG_CALL_RET_BY_REF: /* @@ -2826,7 +2827,7 @@ static void liveness_pass_1(TCGContext *s) ts->state = TS_DEAD; la_reset_pref(ts); - /* Not used -- it will be tcg_target_call_oarg_regs[i]. */ + /* Not used -- it will be tcg_target_call_oarg_reg(). */ op->output_pref[i] = 0; } @@ -4640,7 +4641,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) case TCG_CALL_RET_NORMAL: for (i = 0; i < nb_oargs; i++) { TCGTemp *ts = arg_temp(op->args[i]); - TCGReg reg = tcg_target_call_oarg_regs[i]; + TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i); /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); @@ -4666,7 +4667,8 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) temp_allocate_frame(s, ts); } for (i = 0; i < 4; i++) { - tcg_out_st(s, TCG_TYPE_I32, tcg_target_call_oarg_regs[i], + tcg_out_st(s, TCG_TYPE_I32, + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL_4, i), ts->mem_base->reg, ts->mem_offset + i * 4); } ts->val_type = TEMP_VAL_MEM; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index f089a74f0e..dc99fa3257 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] = { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 }; -static const int tcg_target_call_oarg_regs[1] = { - TCG_REG_X0 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_X0 + slot; +} #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2950a29d49..41d3af517d 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -79,9 +79,12 @@ static const int tcg_target_reg_alloc_order[] = { static const int tcg_target_call_iarg_regs[4] = { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 }; -static const int tcg_target_call_oarg_regs[2] = { - TCG_REG_R0, TCG_REG_R1 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(slot >= 0 && slot <= 3); + return TCG_REG_R0 + slot; +} #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6a021dda8b..82c8491152 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -109,12 +109,22 @@ static const int tcg_target_call_iarg_regs[] = { #endif }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_EAX, -#if TCG_TARGET_REG_BITS == 32 - TCG_REG_EDX -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + switch (kind) { + case TCG_CALL_RET_NORMAL: + switch (slot) { + case 0: + return TCG_REG_EAX; + case 1: + return TCG_REG_EDX; + } + break; + default: + break; + } + g_assert_not_reached(); +} /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 967bf307b8..2efefe863e 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_A7, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_A0 + slot; +} #ifndef CONFIG_SOFTMMU #define USE_GUEST_BASE (guest_base != 0) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 22b5463f0f..92883176c6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] = { #endif }; -static const TCGReg tcg_target_call_oarg_regs[2] = { - TCG_REG_V0, - TCG_REG_V1 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_V0 + slot; +} static const tcg_insn_unit *tb_ret_addr; static const tcg_insn_unit *bswap32_addr; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d9e4ba8883..781ecfe161 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R10 }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R3, - TCG_REG_R4 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_R3 + slot; +} static const int tcg_target_callee_save_regs[] = { #ifdef _CALL_DARWIN diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6072945ccb..417736cae7 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_A7, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_A0 + slot; +} #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 8663a963a6..50655e9d1d 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -390,9 +390,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R6, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R2, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot == 0); + return TCG_REG_R2; +} #define S390_CC_EQ 8 #define S390_CC_LT 4 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index f6a8a8e605..9b5afb8248 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -133,12 +133,12 @@ static const int tcg_target_call_iarg_regs[6] = { TCG_REG_O5, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 3); + return TCG_REG_O0 + slot; +} #define INSN_OP(x) ((x) << 30) #define INSN_OP2(x) ((x) << 22) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8bf02a96e9..914806c216 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -204,12 +204,11 @@ static const int tcg_target_reg_alloc_order[] = { /* No call arguments via registers. All will be stored on the "stack". */ static const int tcg_target_call_iarg_regs[] = { }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R0, -#if TCG_TARGET_REG_BITS == 32 - TCG_REG_R1 -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(slot >= 0 && slot <= 3); + return TCG_REG_R0 + slot; +} #ifdef CONFIG_DEBUG_TCG static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { From patchwork Thu Oct 20 11:52:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616748 Delivered-To: patch@linaro.org Received: by 2002:a17:906:1c0f:b0:78b:b85f:9498 with SMTP id k15csp344668ejg; Thu, 20 Oct 2022 06:46:59 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5SHCXWaN8aYTSPlOjlvLZ6VWzok+xqMH4465JgBZQ5iA2V33f8EPoqnHHLU+HtWxiH2+id X-Received: by 2002:ac8:5ace:0:b0:39a:9939:8d9 with SMTP id d14-20020ac85ace000000b0039a993908d9mr11306459qtd.625.1666273619673; Thu, 20 Oct 2022 06:46:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666273619; cv=none; d=google.com; s=arc-20160816; b=Qud5QMwwbfGT8c7dT17jiTfWoMFo+Ppo5893SOCKkOj1UK+Xd2gVT8q/MAdJu5jKs2 Gu/4rJSi5E2F6FvEKGikPVznMTsfgJg8I6HfRYU+QBLoOaiAE081b2Pix+HIBSbREcDY D4rmMp7dHXlw8+j5DuEHLAxa1vznEXgmTOcAkicK1Xnl23M/ObSjebm9D6yMdkyS5aJ/ rTjW4RTcUH8JOg344VnX7DlYAtpgUVWh2dALAIR+STywqF1+nZA/vcsNh+9hUGcxIUYE GRW7Y/3QjoH4ESLtWY6eDHpeGH9qpYwAQi9OvAzobSBlbeCsOxzmhQrkQSR+4pTFW2Ys M6Nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LMGG6u36Dw67iE/Juteia6nMKD7kG1VCYlvUM0ALFns=; b=NXHmfLRo37I7Q61Jw+OG3yCqMvimP9vqZPKaV7S2O6vwRj3rWuPjbkMkWFoVPXg7WU btWnMbFjIJBBgCCjX/Q/ZD+mfYkYGn2waFPyQDn9OTuFPZDKXHUFO1RPal/fWrjiAwcp +v05JQ6lT2QV5m8FwM8aEQfn8i9eTaoO+7eEarEEEfp6AHY/iyDtM+x71V9a5dXW0bTC GPwifP3sSjtRS/2lTpultV6XYUFzxNYi0kGgsHGWCVF+KNEX9zaGZB0dGh//BRN0+zJi WW6ZkeeIwhuoPToC48UzEGtl8oVAM6Cyu9XikygGGHNeF01tYkGBT2o9oS2CPHep0xdb i3sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eBRICGFW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Not yet used, because allocation is not yet enabled. Since this is for exactly one backend, go ahead and make the few changes needed. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 1 + tcg/tcg.c | 17 +++++++++++++++++ tcg/i386/tcg-target.c.inc | 16 +++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 1fe7bd7d5d..44ef51ca30 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -38,6 +38,7 @@ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ TCG_CALL_RET_NORMAL_4, /* for i128, by 4 registers */ TCG_CALL_RET_BY_REF, /* for i128, by reference as first arg */ + TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ } TCGCallReturnKind; typedef enum { diff --git a/tcg/tcg.c b/tcg/tcg.c index 47f1f906fd..2c7eece27f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -768,6 +768,8 @@ static void init_call_layout(TCGHelperInfo *info) cum.reg_slot = 1; } break; + case TCG_CALL_RET_BY_VEC: + break; default: g_assert_not_reached(); } @@ -4683,6 +4685,21 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) } break; + case TCG_CALL_RET_BY_VEC: + { + TCGTemp *ts = arg_temp(op->args[0]); + + tcg_debug_assert(ts->type == TCG_TYPE_I128); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + tcg_out_st(s, TCG_TYPE_V128, + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), + ts->mem_base->reg, ts->mem_offset + i * 4); + ts->val_type = TEMP_VAL_MEM; + } + break; + default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 82c8491152..3b4b66c224 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -120,6 +120,13 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) return TCG_REG_EDX; } break; +#ifdef _WIN64 + case TCG_CALL_RET_BY_VEC: + if (slot == 0) { + return TCG_REG_XMM0; + } + break; +#endif default: break; } @@ -1194,9 +1201,16 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, * The gvec infrastructure is asserts that v128 vector loads * and stores use a 16-byte aligned offset. Validate that the * final pointer is aligned by using an insn that will SIGSEGV. + * + * This specific instance is also used by TCG_CALL_RET_BY_VEC, + * for _WIN64, which must have SSE2 but may not have AVX. */ tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + if (have_avx1) { + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + } else { + tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); + } break; case TCG_TYPE_V256: /* From patchwork Thu Oct 20 11:52:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616765 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp299294pvb; Thu, 20 Oct 2022 07:27:45 -0700 (PDT) X-Google-Smtp-Source: AMsMyM518tmiThvBvN3fGMBI3NwgNHmxsVv0nSzoDFHYn5uFYUcVPrVnBenD494C4IdMOXAwW5eY X-Received: by 2002:a05:620a:450d:b0:6ee:5242:9f50 with SMTP id t13-20020a05620a450d00b006ee52429f50mr9518993qkp.82.1666276065223; Thu, 20 Oct 2022 07:27:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666276065; cv=none; d=google.com; s=arc-20160816; b=JRb903nkQcR+8oXzbcpdl2RWoIXRpqBdwXXuCtMWlQ2y8emlVcSVTRi4NRlDh7g/Ny D/61QP7DfI0o290sU8hFPHCBzYvSulWdqEzzUeyzszzlitmUF0JlyE18OPvGZLcitg7O ilxoHb9BUsLci5KsCrcA0XWEpgI/X7VV+fgVpMeTOsTXf16c8Wjj+e1eKOxiXSnsDaQv mXZsli49SRoffDMLXfj6HfM4CMA+5MBmtwDaJ0Z6cnwoEcEFkfvCVn8jl9DtPZ/2NX4l 1i3uOoB5+kDnzF8oiU9SeUe5aZJAtqCNp9fUtey8jBleNQQFhHJMDtTsvz5hxzGg88s6 mlgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=otax3boOrkJbpvJnQWAvehNepZr14GD0jCowiyMr4Ww=; b=K+o7DBP13bcrILPqrkxgSFFNv31Degz1Zg2afNtJcod0JdeJPvuPaXWGfopgQ19fhh ijlMIpmW8a9bWjUxD5zvIWFp+V2GOF3DSBBFnYWgz0k//KMN6Z06plbYlP+RZ7H8xr5V rq7ATsNbaxvvZ8Vi67PUbOlcHxVWSNv+gsO2anYOIr3QGyJdp5AqBYT4VW3IWlGflIIp s+Fw4c/8nin6Z2k90aBI2HeU7EKMjt7fkRl/xEnCTtSul6MAW3flw+MONJ3pFOB7U6Kq mEmzrBMih5Qp0WuP3iHUgFcxoKi+t/MS5WK25zKNGlGreda+8xriem013SN8LrB2jjJP Q8SQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dUAlh0zH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this. We cannot modify Int128 itself, as any changed alignment would also break libffi. Signed-off-by: Richard Henderson --- include/qemu/atomic128.h | 34 ++++++++++++++++++++++++-------- include/qemu/int128.h | 18 ++++++++++++++--- util/int128.c | 42 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 11 deletions(-) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index d179c05ede..5ba53f2f10 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -44,13 +44,23 @@ #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return qatomic_cmpxchg__nocheck(ptr, cmp, new); + Int128Alias r, c, n; + + c.s = cmp; + n.s = new; + r.i = qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(CONFIG_CMPXCHG128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return __sync_val_compare_and_swap_16(ptr, cmp, new); + Int128Alias r, c, n; + + c.s = cmp; + n.s = new; + r.i = __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(__aarch64__) @@ -89,12 +99,18 @@ Int128 QEMU_ERROR("unsupported atomic") #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_read(Int128 *ptr) { - return qatomic_read__nocheck(ptr); + Int128Alias r; + + r.i = qatomic_read__nocheck((__int128_t *)ptr); + return r.s; } static inline void atomic16_set(Int128 *ptr, Int128 val) { - qatomic_set__nocheck(ptr, val); + Int128Alias v; + + v.s = val; + qatomic_set__nocheck((__int128_t *)ptr, v.i); } # define HAVE_ATOMIC128 1 @@ -153,7 +169,8 @@ static inline Int128 atomic16_read(Int128 *ptr) if (have_atomic128) { asm("vmovdqa %1, %0" : "=x" (ret) : "m" (*ptr)); } else { - ret = atomic16_cmpxchg(ptr, 0, 0); + Int128 z = int128_make64(0); + ret = atomic16_cmpxchg(ptr, z, z); } return ret; } @@ -167,7 +184,7 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) do { cmp = old; old = atomic16_cmpxchg(ptr, cmp, val); - } while (old != cmp); + } while (int128_ne(old, cmp)); } } @@ -176,7 +193,8 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) static inline Int128 atomic16_read(Int128 *ptr) { /* Maybe replace 0 with 0, returning the old value. */ - return atomic16_cmpxchg(ptr, 0, 0); + Int128 z = int128_make64(0); + return atomic16_cmpxchg(ptr, z, z); } static inline void atomic16_set(Int128 *ptr, Int128 val) @@ -185,7 +203,7 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) do { cmp = old; old = atomic16_cmpxchg(ptr, cmp, val); - } while (old != cmp); + } while (int128_ne(old, cmp)); } # define HAVE_ATOMIC128 1 diff --git a/include/qemu/int128.h b/include/qemu/int128.h index d2b76ca6ac..a062284025 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -3,7 +3,12 @@ #include "qemu/bswap.h" -#ifdef CONFIG_INT128 +/* + * With TCI, we need to use libffi for interfacing with TCG helpers. + * But libffi does not support __int128_t, and therefore cannot pass + * or return values of this type, force use of the Int128 struct. + */ +#if defined(CONFIG_INT128) && !defined(CONFIG_TCG_INTERPRETER) typedef __int128_t Int128; static inline Int128 int128_make64(uint64_t a) @@ -460,8 +465,7 @@ Int128 int128_divu(Int128, Int128); Int128 int128_remu(Int128, Int128); Int128 int128_divs(Int128, Int128); Int128 int128_rems(Int128, Int128); - -#endif /* CONFIG_INT128 */ +#endif /* CONFIG_INT128 && !CONFIG_TCG_INTERPRETER */ static inline void bswap128s(Int128 *s) { @@ -472,4 +476,12 @@ static inline void bswap128s(Int128 *s) #define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX) #define INT128_MIN int128_make128(0, INT64_MIN) +#ifdef CONFIG_INT128 +typedef union { + Int128 s; + __int128_t i; + __uint128_t u; +} Int128Alias; +#endif /* CONFIG_INT128 */ + #endif /* INT128_H */ diff --git a/util/int128.c b/util/int128.c index ed8f25fef1..df6c6331bd 100644 --- a/util/int128.c +++ b/util/int128.c @@ -144,4 +144,46 @@ Int128 int128_rems(Int128 a, Int128 b) return r; } +#elif defined(CONFIG_TCG_INTERPRETER) + +Int128 int128_divu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.u = a.u / b.u; + return r.s; +} + +Int128 int128_remu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.u = a.u % b.u; + return r.s; +} + +Int128 int128_divs(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.i = a.i / b.i; + return r.s; +} + +Int128 int128_rems(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.i = a.i % b.i; + return r.s; +} + #endif From patchwork Thu Oct 20 11:52:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616736 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp256182pvb; Thu, 20 Oct 2022 06:22:09 -0700 (PDT) X-Google-Smtp-Source: AMsMyM71E7eonLjnP1L2TLfk9ju1/78lg386EF30mcSCgFt38HEn92IM35xjNnhcW1qn+vQsnwsg X-Received: by 2002:a05:620a:f15:b0:6cf:1efa:3705 with SMTP id v21-20020a05620a0f1500b006cf1efa3705mr9205335qkl.439.1666272129051; Thu, 20 Oct 2022 06:22:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666272129; cv=none; d=google.com; s=arc-20160816; b=kqrgAzKCqvnVLWOXhv5cYXS3/TZR2ZSPthL53If6U/bh+K9e/c/yp+qh8MdhgvSMPA hc5+YzZH/HJTj6eebMVbFWF5KNpQ2ix2dOw3NfN59/2LIOjy88ccNYMXxBJOvos7Nexs iWKkKuxwsB7OD2HaBGVo3zMR+92FIuEFIszNO8tKdLL1TKSKEikSaSTK0c2fbpHCvVA+ ojsdcxdhZuNZomqPTYhu1LW3F0iLXVzd9Dfy/I9oFHMPUL0nNz5Nd5//qAnsj10eiYP9 8KbwA+mexgjxFQ05HnQht8Nyfm3rASumpJ8oe5qXurD1XM7KWkbrMYcKihMVknIYCG67 F4eA== ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h | 10 ++++++++++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 2 ++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tcg.c | 29 ++++++++++++++++++++++++----- tcg/i386/tcg-target.c.inc | 25 +++++++++++++++++++++++++ tcg/ppc/tcg-target.c.inc | 3 +++ 11 files changed, 76 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 413a5410c5..0dff5807f6 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -54,6 +54,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b7843d2d54..6613d3d791 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -91,6 +91,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF /* optional instructions */ #define TCG_TARGET_HAS_ext8s_i32 1 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7edb7f1d9a..9e0e82d80a 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -100,6 +100,16 @@ typedef enum { #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#if defined(_WIN64) +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC +#elif TCG_TARGET_REG_BITS == 64 +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL +#else +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF +#endif extern bool have_bmi1; extern bool have_popcnt; diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 74fbb22dfd..54e3478355 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -91,6 +91,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 15721c3e42..b235cba8ba 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -89,6 +89,8 @@ typedef enum { # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 6f3b142317..5a514cfe89 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -84,6 +84,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index db5665c375..9a3856f0b3 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -168,6 +168,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_CALL_STACK_OFFSET 160 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_RET_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 0044ac8d78..53cfa843da 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -73,6 +73,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #if defined(__VIS__) && __VIS__ >= 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 2c7eece27f..352175afcd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -548,6 +548,22 @@ static GHashTable *helper_table; #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { + /* + * libffi does not support __int128_t, so we have forced Int128 + * to use the structure definition instead of the builtin type. + */ + static ffi_type *ffi_type_i128_elements[3] = { + &ffi_type_uint64, + &ffi_type_uint64, + NULL + }; + static ffi_type ffi_type_i128 = { + .size = 16, + .alignment = __alignof__(Int128), + .type = FFI_TYPE_STRUCT, + .elements = ffi_type_i128_elements, + }; + switch (argmask) { case dh_typecode_void: return &ffi_type_void; @@ -561,6 +577,8 @@ static ffi_type *typecode_to_ffi(int argmask) return &ffi_type_sint64; case dh_typecode_ptr: return &ffi_type_pointer; + case dh_typecode_i128: + return &ffi_type_i128; } g_assert_not_reached(); } @@ -742,12 +760,13 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: /* - * No matter the call return method, we must have all of - * the temp subindexes in the call for liveness. + * For 32-bit hosts, do not split out individual temps. + * For 64-bit hosts, we need to add both temps for liveness + * no matter the backend calling convention. */ info->nr_out = TCG_TARGET_REG_BITS == 32 ? 1 : 2; - info->out_kind = TCG_CALL_RET_NORMAL; /* TODO */ - switch (/* TODO */ TCG_CALL_RET_NORMAL) { + info->out_kind = TCG_TARGET_CALL_RET_I128; + switch (TCG_TARGET_CALL_RET_I128) { case TCG_CALL_RET_NORMAL: if (TCG_TARGET_REG_BITS == 32) { info->out_kind = TCG_CALL_RET_NORMAL_4; @@ -809,7 +828,7 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: type = TCG_TYPE_I128; - kind = TCG_CALL_ARG_NORMAL; /* TODO */ + kind = TCG_TARGET_CALL_ARG_I128; break; default: g_assert_not_reached(); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 3b4b66c224..fd55089ac9 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1697,6 +1697,31 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, const TCGHelperInfo *info) { tcg_out_branch(s, 1, dest); + + switch (info->out_kind) { + case TCG_CALL_RET_NORMAL: +#ifdef _WIN64 + case TCG_CALL_RET_BY_VEC: +#endif + break; +#if TCG_TARGET_REG_BITS == 32 && !defined(_WIN32) + case TCG_CALL_RET_BY_REF: + /* + * The sysv i386 abi for struct return places a reference as the + * first argument of the stack, and pops that argument with + * the return statement. Since we want to retain the aligned + * stack pointer for the callee, we do not want to actually + * push that argument before the call but rely on the normal + * store to the stack slot. But we do need to compensate + * for the pop to return to steady state. + * Pushing a garbage value back onto the stack is quickest. + */ + tcg_out_push(s, TCG_REG_EAX); + break; +#endif + default: + g_assert_not_reached(); + } } static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 781ecfe161..e86d4a5e78 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -54,6 +54,9 @@ #else # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +/* Note sysv arg alignment applies only to 2-word types, not more. */ +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* For some memory operations, we need a scratch that isn't R0. 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The type is not yet usable, as we have not yet added data movement ops. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 32 ++++++++++++++++++++++++++++++++ tcg/tci/tcg-target.h | 3 +++ tcg/tcg.c | 32 +++++++++++++++++++++++++++----- 3 files changed, 62 insertions(+), 5 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e80c78b2e8..185408935b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -695,6 +695,11 @@ static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) return tcgv_i32_temp((TCGv_i32)v); } +static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) +{ + return tcgv_i32_temp((TCGv_i32)v); +} + static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) { return tcgv_i32_temp((TCGv_i32)v); @@ -715,6 +720,11 @@ static inline TCGArg tcgv_i64_arg(TCGv_i64 v) return temp_arg(tcgv_i64_temp(v)); } +static inline TCGArg tcgv_i128_arg(TCGv_i128 v) +{ + return temp_arg(tcgv_i128_temp(v)); +} + static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) { return temp_arg(tcgv_ptr_temp(v)); @@ -736,6 +746,11 @@ static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) return (TCGv_i64)temp_tcgv_i32(t); } +static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) +{ + return (TCGv_i128)temp_tcgv_i32(t); +} + static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) { return (TCGv_ptr)temp_tcgv_i32(t); @@ -858,6 +873,11 @@ static inline void tcg_temp_free_i64(TCGv_i64 arg) tcg_temp_free_internal(tcgv_i64_temp(arg)); } +static inline void tcg_temp_free_i128(TCGv_i128 arg) +{ + tcg_temp_free_internal(tcgv_i128_temp(arg)); +} + static inline void tcg_temp_free_ptr(TCGv_ptr arg) { tcg_temp_free_internal(tcgv_ptr_temp(arg)); @@ -906,6 +926,18 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return temp_tcgv_i64(t); } +static inline TCGv_i128 tcg_temp_new_i128(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, false); + return temp_tcgv_i128(t); +} + +static inline TCGv_i128 tcg_temp_local_new_i128(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, true); + return temp_tcgv_i128(t); +} + static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, const char *name) { diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 94ec541b4e..9d569c9e04 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -161,10 +161,13 @@ typedef enum { #if TCG_TARGET_REG_BITS == 32 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #define HAVE_TCG_QEMU_TB_EXEC #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index 352175afcd..c6e856a2cc 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1250,18 +1250,39 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) tcg_debug_assert(ts->base_type == type); tcg_debug_assert(ts->kind == kind); } else { + bool want_pair = false; + TCGType half = type; + + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + break; + case TCG_TYPE_I64: + half = TCG_TYPE_I32; + want_pair = TCG_TARGET_REG_BITS == 32; + break; + case TCG_TYPE_I128: + half = TCG_TYPE_I64; + want_pair = TCG_TARGET_REG_BITS == 64; + break; + default: + g_assert_not_reached(); + } + ts = tcg_temp_alloc(s); - if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { + if (want_pair) { TCGTemp *ts2 = tcg_temp_alloc(s); ts->base_type = type; - ts->type = TCG_TYPE_I32; + ts->type = half; ts->temp_allocated = 1; ts->kind = kind; tcg_debug_assert(ts2 == ts + 1); - ts2->base_type = TCG_TYPE_I64; - ts2->type = TCG_TYPE_I32; + ts2->base_type = type; + ts2->type = half; ts2->temp_allocated = 1; ts2->temp_subindex = 1; ts2->kind = kind; @@ -2773,7 +2794,7 @@ static void la_cross_call(TCGContext *s, int nt) for (i = 0; i < nt; i++) { TCGTemp *ts = &s->temps[i]; - if (!(ts->state & TS_DEAD)) { + if (ts->type != TCG_TYPE_I128 && !(ts->state & TS_DEAD)) { TCGRegSet *pset = la_temp_pref(ts); TCGRegSet set = *pset; @@ -3404,6 +3425,7 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) case TCG_TYPE_V64: align = 8; break; + case TCG_TYPE_I128: case TCG_TYPE_V128: case TCG_TYPE_V256: /* Note that we do not require aligned storage for V256. */ From patchwork Thu Oct 20 11:52:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 616741 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp266249pvb; Thu, 20 Oct 2022 06:38:11 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4iPbE7jCthmSMLLvFmkN5DUv3ALZpV4atktKhIFw+LbQGtYRXYP3K7oNOVaoMGF8sBSDHe X-Received: by 2002:a0c:aacd:0:b0:4ad:fe0:4e84 with SMTP id g13-20020a0caacd000000b004ad0fe04e84mr11293483qvb.8.1666273091295; Thu, 20 Oct 2022 06:38:11 -0700 (PDT) ARC-Seal: i=1; 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Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 3 ++ include/tcg/tcg-opc.h | 4 ++ tcg/tcg-internal.h | 12 ++++++ tcg/tcg-op.c | 35 ++++++++++++++++++ tcg/tcg.c | 85 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 139 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 209e168305..2ce2ff28c9 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -735,6 +735,9 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); + static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) { tcg_gen_deposit_i64(ret, lo, hi, 32, 32); diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index dd444734d9..6211fb3242 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -158,6 +158,10 @@ DEF(extrh_i64_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_extrh_i64_i32) | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) +/* For 32-bit host only, implemented generically using ld/st/mov. */ +DEF(extr_i128_i32, 1, 1, 1, TCG_OPF_NOT_PRESENT) +DEF(concat4_i32_i128, 1, 4, 0, TCG_OPF_NOT_PRESENT) + DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64) DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64)) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 44ef51ca30..8112a0a491 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -110,9 +110,21 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) { return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN); } +extern TCGv_i64 TCGV128_LOW(TCGv_i128) + QEMU_ERROR("64-bit code path is reachable"); +extern TCGv_i64 TCGV128_HIGH(TCGv_i128) + QEMU_ERROR("64-bit code path is reachable"); #else extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); +static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) +{ + return temp_tcgv_i64(tcgv_i128_temp(t) + HOST_BIG_ENDIAN); +} +static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) +{ + return temp_tcgv_i64(tcgv_i128_temp(t) + !HOST_BIG_ENDIAN); +} #endif #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3ed98ffa01..6031fa89c2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2718,6 +2718,41 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) tcg_gen_shri_i64(hi, arg, 32); } +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg) +{ + if (TCG_TARGET_REG_BITS == 32) { + TCGArg a_arg = tcgv_i128_arg(arg); + int be = HOST_BIG_ENDIAN ? 0xc : 0; + + tcg_gen_op3(INDEX_op_extr_i128_i32, tcgv_i32_arg(TCGV_LOW(lo)), + a_arg, 0x0 ^ be); + tcg_gen_op3(INDEX_op_extr_i128_i32, tcgv_i32_arg(TCGV_HIGH(lo)), + a_arg, 0x4 ^ be); + tcg_gen_op3(INDEX_op_extr_i128_i32, tcgv_i32_arg(TCGV_LOW(hi)), + a_arg, 0x8 ^ be); + tcg_gen_op3(INDEX_op_extr_i128_i32, tcgv_i32_arg(TCGV_HIGH(hi)), + a_arg, 0xc ^ be); + } else { + tcg_gen_mov_i64(lo, TCGV128_LOW(arg)); + tcg_gen_mov_i64(hi, TCGV128_HIGH(arg)); + } +} + +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi) +{ + if (TCG_TARGET_REG_BITS == 32) { + tcg_gen_op5(INDEX_op_concat4_i32_i128, + tcgv_i128_arg(ret), + tcgv_i32_arg(TCGV_LOW(lo)), + tcgv_i32_arg(TCGV_HIGH(lo)), + tcgv_i32_arg(TCGV_LOW(hi)), + tcgv_i32_arg(TCGV_HIGH(hi))); + } else { + tcg_gen_mov_i64(TCGV128_LOW(ret), lo); + tcg_gen_mov_i64(TCGV128_HIGH(ret), hi); + } +} + /* QEMU specific operations. */ void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) diff --git a/tcg/tcg.c b/tcg/tcg.c index c6e856a2cc..04e52c42d8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3949,6 +3949,85 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) } } +/* + * Specialized code generation for TCG_TYPE_I128 on 32-bit host. + * Here, 128-bit values are *always* in memory, never regs or constants. + * Move 32-bit pieces into and out of the 128-bit memory slot. + */ +static void tcg_reg_alloc_exrl_i128_i32(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life = op->life; + TCGTemp *ots = arg_temp(op->args[0]); + TCGTemp *its = arg_temp(op->args[1]); + TCGArg ofs = op->args[2]; + TCGReg reg; + + assert(TCG_TARGET_REG_BITS == 32); + tcg_debug_assert(ots->type == TCG_TYPE_I32); + tcg_debug_assert(!temp_readonly(ots)); + tcg_debug_assert(its->type == TCG_TYPE_I128); + tcg_debug_assert(its->val_type == TEMP_VAL_MEM); + tcg_debug_assert(ofs < 16); + tcg_debug_assert((ofs & 3) == 0); + + if (ots->val_type == TEMP_VAL_REG) { + reg = ots->reg; + } else { + reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_I32], + s->reserved_regs, op->output_pref[0], + ots->indirect_base); + ots->val_type = TEMP_VAL_REG; + ots->reg = reg; + s->reg_to_temp[reg] = ots; + } + + tcg_out_ld(s, TCG_TYPE_I32, reg, + its->mem_base->reg, its->mem_offset + ofs); + ots->mem_coherent = 0; + + if (IS_DEAD_ARG(1)) { + temp_dead(s, its); + } +} + +static void tcg_reg_alloc_concat4_i32_i128(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life = op->life; + TCGTemp *ots = arg_temp(op->args[0]); + int be = HOST_BIG_ENDIAN ? 0xc : 0; + + assert(TCG_TARGET_REG_BITS == 32); + tcg_debug_assert(ots->type == TCG_TYPE_I128); + tcg_debug_assert(!temp_readonly(ots)); + tcg_debug_assert(NEED_SYNC_ARG(0)); + + if (!ots->mem_allocated) { + temp_allocate_frame(s, ots); + } + + for (int i = 0; i < 4; ++i) { + TCGTemp *its = arg_temp(op->args[i + 1]); + int ofs = ots->mem_offset + ((i * 4) ^ be); + + if (its->val_type == TEMP_VAL_CONST && + IS_DEAD_ARG(i + 1) && + tcg_out_sti(s, TCG_TYPE_I32, its->val, ots->mem_base->reg, ofs)) { + continue; + } + + temp_load(s, its, tcg_target_available_regs[TCG_TYPE_I32], + s->reserved_regs, 0); + tcg_out_st(s, TCG_TYPE_I32, its->reg, ots->mem_base->reg, ofs); + + if (IS_DEAD_ARG(i + 1)) { + temp_dead(s, its); + } + } + + ots->val_type = TEMP_VAL_MEM; + ots->mem_coherent = 1; +} + /* * Specialized code generation for INDEX_op_dup_vec. */ @@ -5007,6 +5086,12 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start) case INDEX_op_mov_vec: tcg_reg_alloc_mov(s, op); break; + case INDEX_op_extr_i128_i32: + tcg_reg_alloc_exrl_i128_i32(s, op); + break; + case INDEX_op_concat4_i32_i128: + tcg_reg_alloc_concat4_i32_i128(s, op); + break; case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break;