From patchwork Tue Oct 25 06:52:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 618428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31460C04A95 for ; Tue, 25 Oct 2022 06:53:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229515AbiJYGxO (ORCPT ); Tue, 25 Oct 2022 02:53:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231377AbiJYGxL (ORCPT ); Tue, 25 Oct 2022 02:53:11 -0400 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2052.outbound.protection.outlook.com [40.107.212.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 063BD43323; Mon, 24 Oct 2022 23:53:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IqHrqWupdgZ/TnxflcZdQMc0WxIaoeO21TwG/ejd6NzxxUYMipx/8AagLhYCdGhRyBdIJoPsKdz+661NhX7YCED9dr0P79j2MgBJOAzfsNgpNdBUXwzhNWgbkfXWF7nD6dScw4dULGE9swmUiDtuGXBstYRMfPOVWLbJZfT2EJkv51YKY+4l90fLHBDeRLITM2Bem75Q/WSu27gRyRPgiCVBSasVpBB+h5sfq5dhdALHnoFWxIMaZr5OcC1d86NxCeIjelY2jtHvXGXaGKETdzpiv5d4vuZfWLVCgWuRrZr30B9bqVJ09cW1/xWSzz6BY64bcyMnnfJqXOH5+WlYEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3W+4MPc5n6RdCbQDePmn1uWM4TgWoEY5+Ukz/RNbSVw=; b=jqSM2naIAskIXlBhAmRDeyYrW0a2EtHbwmNUcFBulliFlz+RdrZq9y5qCdwu0N0/dUNu/UytHZk0KjcQ643Fw5lOStyl0HoE96ZIrODt+UaS24XvJv5qxiGY2ha34etHCD2Z15r86KGOAF9gMMcD4lSX33rxRztYGl43sDhiENz54jiItuKF2qzkd8g3MzAQEMUASzzPTVy0e3wzx968L3wymNxAkYaQrlrAaNx99AkcD7QH5rNJJBYxNzQBIpMHBN8M9Ue/4R9TsQA3kee1Zh24bSecJCWAcsN7Dro4HroVW+orrXItrsKyTgax3y7k9mqlH3M3YgRCo4dKUQtxFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3W+4MPc5n6RdCbQDePmn1uWM4TgWoEY5+Ukz/RNbSVw=; b=ek7ZOX48pcddHFrnWOpGzlVA04ylKn+LGMyDzxzXs7j850FswBSTasfDogj3MiUwNHcQuvIyBeUEvUMeOKsaf31CFaFJrRKYkqioDK9iYOrJd9ZHCv2vwdEH26jRK8JjuxcyKb2LrQW9FQt4V/nHkRPfjPcWEw1b23UQ79cR88k= Received: from DS7PR05CA0075.namprd05.prod.outlook.com (2603:10b6:8:57::16) by PH0PR12MB5606.namprd12.prod.outlook.com (2603:10b6:510:141::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.23; Tue, 25 Oct 2022 06:53:05 +0000 Received: from DM6NAM11FT025.eop-nam11.prod.protection.outlook.com (2603:10b6:8:57:cafe::1e) by DS7PR05CA0075.outlook.office365.com (2603:10b6:8:57::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.8 via Frontend Transport; Tue, 25 Oct 2022 06:53:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT025.mail.protection.outlook.com (10.13.172.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Tue, 25 Oct 2022 06:53:05 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:53:04 -0500 Received: from xhdbharatku40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Tue, 25 Oct 2022 01:53:01 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , "Thippeswamy Havalige" Subject: [PATCH 02/13] microblaze/PCI: Remove Null PCI config access unused functions Date: Tue, 25 Oct 2022 12:22:03 +0530 Message-ID: <20221025065214.4663-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221025065214.4663-1-thippeswamy.havalige@amd.com> References: <20221025065214.4663-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT025:EE_|PH0PR12MB5606:EE_ X-MS-Office365-Filtering-Correlation-Id: a064805e-01b9-43d6-1794-08dab6559152 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rHgOq6UuPUvFF5qX6dnpHgZimNvhE7easo+B+o9DPIa7nel4RfMpcnYI4Eo291LT3IVcek3os30rAYFLpd7ZdaBi6IhBUCp1OwVx6YbT69NmYNI6daNPKSslqaJu7OFv420teKmm39selypYJzkugsJdph/0nOdXkhUxgeQxWaIT82VfOJWPxMpHYewassnkwDu4Q5b7819WTyBx1QSF/ychFQeqd8QBARJiIUGO+CbybuXh7m7AC95apOW5+tOcjs3Lipe5lBhAWbAEbi9kd9toFFklMlXT3CSltkTBfPrDllt6J8diDHYM+sacpPrQTgQRuocH7WA12v1ouAZXFidyzkLcWN+0sR9z39G3hyXhp8hdNrIUMIJabpZ2Yx3uLWt9mhuQsPxrAYR0b/iFOdLivJ9DOBEA4p4DLKzhz3Wsrki4WCmzswIDzz4MjN5LxVrcmgbJkKHwZsZWd2co4lJhl0XT7LsjFZWPf2G9S0qUeKsGYFL0wIqwuCtkqBtWUeEdR3c4LQEX/hBdwxBTVQLx9Cxxd4O6WW9wM46KcSfvnG+Ql/5/AduAEYkSA8LgPKCtBMMDnI5Sl24z9HjI8RWz1/7yLUm3sqqeawp/nLISseiTQRYOj9uM++umLbDgoyzzYfD5q8aaKvO429gseFzm4QFUYZH9bikoWTEKthCaxwXLN/2Q36FfZuVx1tvCcVXhIt73lYQh2E9Ws5QUJH2i1Lk6igYG1bf1qf59hmUgWmUNX7kpgiwxe4PaQGeDSm4QLCCahZOOfW3BW4WpH7hfN+FD9mCWpJy9mHR7Y7XcUcy0B9HZOHuoST/E0mYC X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199015)(46966006)(40470700004)(36840700001)(86362001)(70586007)(110136005)(8676002)(70206006)(4326008)(316002)(40460700003)(54906003)(44832011)(36756003)(5660300002)(8936002)(41300700001)(47076005)(81166007)(82740400003)(40480700001)(36860700001)(26005)(356005)(82310400005)(478600001)(426003)(336012)(83380400001)(186003)(2616005)(1076003)(2906002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 06:53:05.2116 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a064805e-01b9-43d6-1794-08dab6559152 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5606 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove unused NULL_PCI_OP config access functions, for the case when we can't find a hose. Remove unused EARLY_PCI_OP and other declarations. Signed-off-by: Thippeswamy Havalige --- arch/microblaze/pci/pci-common.c | 64 ---------------------------------------- 1 file changed, 64 deletions(-) diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 69ce51c..58397cf 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -996,67 +996,3 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) return result; } - -/* - * Null PCI config access functions, for the case when we can't - * find a hose. - */ -#define NULL_PCI_OP(rw, size, type) \ -static int \ -null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ -{ \ - return PCIBIOS_DEVICE_NOT_FOUND; \ -} - -static int -null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static int -null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; -} - -static struct pci_ops null_pci_ops = { - .read = null_read_config, - .write = null_write_config, -}; - -/* - * These functions are used early on before PCI scanning is done - * and all of the pci_dev and pci_bus structures have been created. - */ -static struct pci_bus * -fake_pci_bus(struct pci_controller *hose, int busnr) -{ - static struct pci_bus bus; - - if (!hose) - pr_err("Can't find hose for PCI bus %d!\n", busnr); - - bus.number = busnr; - bus.sysdata = hose; - bus.ops = hose ? hose->ops : &null_pci_ops; - return &bus; -} - -#define EARLY_PCI_OP(rw, size, type) \ -int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ - int devfn, int offset, type value) \ -{ \ - return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ - devfn, offset, value); \ -} - -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, word, u16 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, word, u16) -EARLY_PCI_OP(write, dword, u32) - From patchwork Tue Oct 25 06:52:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 618427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6764C38A2D for ; Tue, 25 Oct 2022 06:53:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229777AbiJYGx4 (ORCPT ); Tue, 25 Oct 2022 02:53:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231391AbiJYGxv (ORCPT ); Tue, 25 Oct 2022 02:53:51 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2081.outbound.protection.outlook.com [40.107.244.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85DAB57225; Mon, 24 Oct 2022 23:53:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=a7nmNeANpyECj6UHhLNT5RgfUI3ksdmkQNz6eqJH4ZdOKaLgI2tYfR/c6zW1JxiQi440PCRqgpwB464eer/dlZLWFRwPsXdmiNu3PO5rVrvV2Dqv36EDURwzYdStp2gwl3ODaH2Fvj9lyRH+7PSPGLG5xLWlZVwI2kdhjI07bCGwr1C2p3QrzeeNrf+YscrIp8zps+FdtELyjyN4wjJpy/FPA86TgHVJwghEj3myYCAKKhm7hkUFvib6lgouWkhjI1aBbC8KxvJ+F31l/NKJ4N/7Ngm7DccJpuASLe/TQA42fKpOZhupiFTnMupCQEW7UEMVngCzx+JpGmVT/mEjbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=g7Ch1D7H4JfsRTBSbPRLM8rYC0XAUY7OwecvH+SsaXQ=; b=goVIIVk1MWrHoeChqLSygC0b+35FE7IujF03wyA/jr1tSrAnpj50yn3wdcwokf3lcOGROPaj+ZjloNh+IfKppM8nWTUwsMT3pWd/vngaPRcvB41a/H4AbUq1zKObi1Kzj2Wlm7q4br1on8iKxCpRLcsCXjGALdLzhMKW7LbB8E0j/7H6IMg0BZoUHq2f0dPTDL+vwQAVtx0C36UVlSbW4ZaFVB2gg6YxVnBIyH6wv8yqDD1RyCmaqbAPQdOv9pz/EGMzY2nzRGwcX2bmrvfSo7MFpe1wsI0/eiaL0JHxYZwx7CDQDTQye5A/RkgulB0kIFtC3x1tfkXgTSujg0Ku3g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=g7Ch1D7H4JfsRTBSbPRLM8rYC0XAUY7OwecvH+SsaXQ=; b=eDJLoSnJUSU8bNc3NwwcnJsPJUfse7/YHLjEShZn8Ic1Akk9GxGHVqOXYzOZmttBDPPlfUDzGl3OCdqngYObRy4Y56+tBN0x2mERm1t6P+YQwbuTs6rV27pQ0DaQsUHs55Qu0MCBnShyviicl64vKf043PqHuutHCTZXxLphR5U= Received: from DM6PR02CA0064.namprd02.prod.outlook.com (2603:10b6:5:177::41) by PH7PR12MB6419.namprd12.prod.outlook.com (2603:10b6:510:1fd::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.34; Tue, 25 Oct 2022 06:53:47 +0000 Received: from DM6NAM11FT071.eop-nam11.prod.protection.outlook.com (2603:10b6:5:177:cafe::d9) by DM6PR02CA0064.outlook.office365.com (2603:10b6:5:177::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.27 via Frontend Transport; Tue, 25 Oct 2022 06:53:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT071.mail.protection.outlook.com (10.13.173.48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Tue, 25 Oct 2022 06:53:47 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:53:46 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:53:46 -0500 Received: from xhdbharatku40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Tue, 25 Oct 2022 01:53:43 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , "Thippeswamy Havalige" Subject: [PATCH 05/13] microblaze/PCI: Remove unused device tree parsing for a host bridge resources Date: Tue, 25 Oct 2022 12:22:06 +0530 Message-ID: <20221025065214.4663-6-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221025065214.4663-1-thippeswamy.havalige@amd.com> References: <20221025065214.4663-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT071:EE_|PH7PR12MB6419:EE_ X-MS-Office365-Filtering-Correlation-Id: 86879a29-65a0-462e-8025-08dab655aa78 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Z/auqdwrSr9w9UNOfKucILuWp51mCqRP0xyw8wj8qz0S6musgX+BhEJyQZz8AswZXWjoUaya0bQLEWiEvlX/XxRjW6NqGE+VFyhb9iN+CGbKhijsVvPaZvtypzv934aHQfk9bQihu7rqgUZH8+ND8n4XhvJaRx43W+QUlJXxIIrixc35ff396tyTseAJ/WYDOWjHZRyJBn/G9BMs+h02AsGm95lm4tef2Iw0mgucYJfru7y73EzlCV4nsMwWpteLsTzvCFEEhi+9rIji9VfSEXxC0senDioPmFf862H3tIGMFAZ7zsI5geBo5moUJtUEaKGzVu6UaaJSlatv5bE6NyhCU54WIWmUBnHR/t97pMEmLQvqV6lxwkKvM1TNO6nXXpIOqxsKVSbgaOvaHN2tEK293H/lcfvlV7QXS26cmRkdlpZFxg0auadFtNOEaeYhyjV3V6a50+P3l+s6qR5LKKrkD8BnCG4fKndw18WYd+LasgB/zlTMd63840ISKE4xzEIT6niMBkIUi1cPVQ1AtihnlbV7lAjU/mnhaEBsqGdj5rKpDozbVGIEOhotAhK3n/xPcdMmmq7MQ9dorHx//1vDJo96aaCq4eweVyTD2dxsZAp+56jRhImMguEg9dp33zx6tyXIH/TikKag8HxYK2HMTTk7BR6BdwNL4EgDXUBDj7Q/XmcrB2hPybrM1PNsaE3Rnh2XBaP+TWWXKQY43LmwtKZ5QQuFeGXgpcxQpfD/KL5IwUdYTlPQTzm1dYuKty7+HmNqwWubO0oyX9jC/hDbEM+ITJ0az6KsAZx1aRa9AMhQMQ8L/W8VQVUYWeAG X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(39860400002)(346002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(82310400005)(6666004)(4326008)(86362001)(70206006)(8676002)(70586007)(36860700001)(336012)(82740400003)(186003)(83380400001)(1076003)(2906002)(40460700003)(41300700001)(426003)(47076005)(26005)(356005)(81166007)(8936002)(2616005)(5660300002)(40480700001)(44832011)(36756003)(478600001)(66899015)(54906003)(316002)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 06:53:47.4064 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86879a29-65a0-462e-8025-08dab655aa78 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT071.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6419 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove unused pci_process_bridge_OF_ranges function, used to parse the "ranges" property of a PCI host device. Signed-off-by: Thippeswamy Havalige --- arch/microblaze/include/asm/pci-bridge.h | 13 --- arch/microblaze/pci/pci-common.c | 163 ------------------------------- arch/microblaze/pci/xilinx_pci.c | 5 - 3 files changed, 181 deletions(-) diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index ce74b0c..252bcc1 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -38,20 +38,11 @@ struct pci_controller { void __iomem *io_base_virt; resource_size_t io_base_phys; - resource_size_t pci_io_size; - /* Some machines (PReP) have a non 1:1 mapping of * the PCI memory space in the CPU bus space */ resource_size_t pci_mem_offset; - /* Some machines have a special region to forward the ISA - * "memory" cycles such as VGA memory regions. Left to 0 - * if unsupported - */ - resource_size_t isa_mem_phys; - resource_size_t isa_mem_size; - struct pci_ops *ops; unsigned int __iomem *cfg_addr; void __iomem *cfg_data; @@ -107,10 +98,6 @@ extern void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); -/* Fill up host controller resources from the OF node */ -extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, - struct device_node *dev, int primary); - /* Allocate & free a PCI host bridge structure */ extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); extern void pcibios_free_controller(struct pci_controller *phb); diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index ef4a9fc..12764df0 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -171,169 +171,6 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar, *end = rsrc->end; } -/** - * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree - * @hose: newly allocated pci_controller to be setup - * @dev: device node of the host bridge - * @primary: set if primary bus (32 bits only, soon to be deprecated) - * - * This function will parse the "ranges" property of a PCI host bridge device - * node and setup the resource mapping of a pci controller based on its - * content. - * - * Life would be boring if it wasn't for a few issues that we have to deal - * with here: - * - * - We can only cope with one IO space range and up to 3 Memory space - * ranges. However, some machines (thanks Apple !) tend to split their - * space into lots of small contiguous ranges. So we have to coalesce. - * - * - We can only cope with all memory ranges having the same offset - * between CPU addresses and PCI addresses. Unfortunately, some bridges - * are setup for a large 1:1 mapping along with a small "window" which - * maps PCI address 0 to some arbitrary high address of the CPU space in - * order to give access to the ISA memory hole. - * The way out of here that I've chosen for now is to always set the - * offset based on the first resource found, then override it if we - * have a different offset and the previous was set by an ISA hole. - * - * - Some busses have IO space not starting at 0, which causes trouble with - * the way we do our IO resource renumbering. The code somewhat deals with - * it for 64 bits but I would expect problems on 32 bits. - * - * - Some 32 bits platforms such as 4xx can have physical space larger than - * 32 bits so we need to use 64 bits values for the parsing - */ -void pci_process_bridge_OF_ranges(struct pci_controller *hose, - struct device_node *dev, int primary) -{ - int memno = 0, isa_hole = -1; - unsigned long long isa_mb = 0; - struct resource *res; - struct of_pci_range range; - struct of_pci_range_parser parser; - - pr_info("PCI host bridge %pOF %s ranges:\n", - dev, primary ? "(primary)" : ""); - - /* Check for ranges property */ - if (of_pci_range_parser_init(&parser, dev)) - return; - - pr_debug("Parsing ranges property...\n"); - for_each_of_pci_range(&parser, &range) { - /* Read next ranges element */ - - /* If we failed translation or got a zero-sized region - * (some FW try to feed us with non sensical zero sized regions - * such as power3 which look like some kind of attempt - * at exposing the VGA memory hole) - */ - if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) - continue; - - /* Act based on address space type */ - res = NULL; - switch (range.flags & IORESOURCE_TYPE_BITS) { - case IORESOURCE_IO: - pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n", - range.cpu_addr, range.cpu_addr + range.size - 1, - range.pci_addr); - - /* We support only one IO range */ - if (hose->pci_io_size) { - pr_info(" \\--> Skipped (too many) !\n"); - continue; - } - /* On 32 bits, limit I/O space to 16MB */ - if (range.size > 0x01000000) - range.size = 0x01000000; - - /* 32 bits needs to map IOs here */ - hose->io_base_virt = ioremap(range.cpu_addr, - range.size); - - /* Expect trouble if pci_addr is not 0 */ - if (primary) - isa_io_base = - (unsigned long)hose->io_base_virt; - /* pci_io_size and io_base_phys always represent IO - * space starting at 0 so we factor in pci_addr - */ - hose->pci_io_size = range.pci_addr + range.size; - hose->io_base_phys = range.cpu_addr - range.pci_addr; - - /* Build resource */ - res = &hose->io_resource; - range.cpu_addr = range.pci_addr; - - break; - case IORESOURCE_MEM: - pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", - range.cpu_addr, range.cpu_addr + range.size - 1, - range.pci_addr, - (range.flags & IORESOURCE_PREFETCH) ? - "Prefetch" : ""); - - /* We support only 3 memory ranges */ - if (memno >= 3) { - pr_info(" \\--> Skipped (too many) !\n"); - continue; - } - /* Handles ISA memory hole space here */ - if (range.pci_addr == 0) { - isa_mb = range.cpu_addr; - isa_hole = memno; - if (primary || isa_mem_base == 0) - isa_mem_base = range.cpu_addr; - hose->isa_mem_phys = range.cpu_addr; - hose->isa_mem_size = range.size; - } - - /* We get the PCI/Mem offset from the first range or - * the, current one if the offset came from an ISA - * hole. If they don't match, bugger. - */ - if (memno == 0 || - (isa_hole >= 0 && range.pci_addr != 0 && - hose->pci_mem_offset == isa_mb)) - hose->pci_mem_offset = range.cpu_addr - - range.pci_addr; - else if (range.pci_addr != 0 && - hose->pci_mem_offset != range.cpu_addr - - range.pci_addr) { - pr_info(" \\--> Skipped (offset mismatch) !\n"); - continue; - } - - /* Build resource */ - res = &hose->mem_resources[memno++]; - break; - } - if (res != NULL) { - res->name = dev->full_name; - res->flags = range.flags; - res->start = range.cpu_addr; - res->end = range.cpu_addr + range.size - 1; - res->parent = res->child = res->sibling = NULL; - } - } - - /* If there's an ISA hole and the pci_mem_offset is -not- matching - * the ISA hole offset, then we need to remove the ISA hole from - * the resource list for that brige - */ - if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { - unsigned int next = isa_hole + 1; - pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb); - if (next < memno) - memmove(&hose->mem_resources[isa_hole], - &hose->mem_resources[next], - sizeof(struct resource) * (memno - next)); - hose->mem_resources[--memno].flags = 0; - } -} - /* Display the domain number in /proc */ int pci_proc_domain(struct pci_bus *bus) { diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c index 7ed6647..f1a5112 100644 --- a/arch/microblaze/pci/xilinx_pci.c +++ b/arch/microblaze/pci/xilinx_pci.c @@ -114,9 +114,4 @@ void __init xilinx_pci_init(void) out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff); iounmap(pci_reg); - /* Register the host bridge with the linux kernel! */ - pci_process_bridge_OF_ranges(hose, pci_node, - INDIRECT_TYPE_SET_CFG_TYPE); - - pr_info("xilinx-pci: Registered PCI host bridge\n"); } From patchwork Tue Oct 25 06:52:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 618426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A496C04A95 for ; Tue, 25 Oct 2022 06:53:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231381AbiJYGx5 (ORCPT ); Tue, 25 Oct 2022 02:53:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231367AbiJYGxy (ORCPT ); Tue, 25 Oct 2022 02:53:54 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2066.outbound.protection.outlook.com [40.107.94.66]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE61C4332A; Mon, 24 Oct 2022 23:53:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fb74m58qKYf33zF2Is5CSesvCtN5VkQ8gAOOtCi1zZ1wESv8YS5ZHYnZ4XbU/6CtPVvmzlhP2Mp0h+sXcD32qVJ8YTdG0DqpjKjIdfOFifaBK/oF8ey4PcUy++WCi2tOxWHrnNYcsJzjNN8zMzGr8bNUWDykJoz8nfHw4RFbYZySJC1PFXj8MBFDYiPZ/CbARe7Bk58yGBfTH6CpJ1F5J7w/KqmYLMUyA9vITQXtHFQ8WVO53SLYz90UxvN4Bt2YfEDEp3TAp+t8MKxs5K3uIQHqicRdr+t+znCZ+0PW+vhDa5Nuy22bSdm6+ZS2pAHLvn5QLyPWwpH/jt4YZwJyaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UH/cfqf9ieuKLueHLHhaOcJB6Bv30CVf3bh3wwEhjIA=; b=N2IBSDXvaweFkbKW6GR2LlV2HzZnaTBtFqf4z/pX3gj4BJZCvTBla6ePo3qzTuIVdXftRt15El+ERgCP6IPP4rWL9x8wDp/toQ9G5FGuL0zFg17YRf4zGVFodDHm4dzA+lLtl7RpBfEVCx3tMdjYukDhVLbDP1toak+Bk4UTf1Q4gsu+mAUE6qKmHbB56cZc2V/eNVtN85/uKghvsvv7ju+wbeBn5s6v8kJyjXFRSm13LJjoNn1JyojGIZt5ZkF1UeialRJQ+G+YWwRbsnrnG9tWPLiLvzZ/gp3ejXMDoxDysECHH0xoo2DbJd6DcyZN+iJRUEpVU3wAKsC7pri+rg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UH/cfqf9ieuKLueHLHhaOcJB6Bv30CVf3bh3wwEhjIA=; b=miZDp6/SVgateYEdAUper6stg5CKenVfiw/Pt1lfqR/GOvaYLdzP63ePofIBBWq8s8aZnDDxHt5BSdcjM6u0RYCqLIZ6fxUFQMCxr70og4w8M4eBjGsGPZ2YAlvAG38EQW91Lo93kctX8MTQCzI+IYPml57oyIuSFna8Tc24Q7c= Received: from DS7PR05CA0079.namprd05.prod.outlook.com (2603:10b6:8:57::9) by BL1PR12MB5239.namprd12.prod.outlook.com (2603:10b6:208:315::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.28; Tue, 25 Oct 2022 06:53:50 +0000 Received: from DM6NAM11FT026.eop-nam11.prod.protection.outlook.com (2603:10b6:8:57:cafe::b6) by DS7PR05CA0079.outlook.office365.com (2603:10b6:8:57::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.8 via Frontend Transport; Tue, 25 Oct 2022 06:53:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT026.mail.protection.outlook.com (10.13.172.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Tue, 25 Oct 2022 06:53:50 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:53:49 -0500 Received: from xhdbharatku40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Tue, 25 Oct 2022 01:53:46 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , "Thippeswamy Havalige" Subject: [PATCH 06/13] microblaze/PCI: Remove unused allocation & free of PCI host bridge structure Date: Tue, 25 Oct 2022 12:22:07 +0530 Message-ID: <20221025065214.4663-7-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221025065214.4663-1-thippeswamy.havalige@amd.com> References: <20221025065214.4663-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT026:EE_|BL1PR12MB5239:EE_ X-MS-Office365-Filtering-Correlation-Id: 304f5851-1a0e-4d50-9752-08dab655ac3e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8Gw17mJxEDPptZf/ce2yGk1qGPeBaZXmAsJ4etBikbIeN0NYwhHgg6aeyiTLd279vlbba8E+GTbPI+mgPepX7hOI05yVAwUSvq6IJTt4pgz4JR02OGzBpMMDMWOjEHfCJXnVG8hUWBpNZOM7dq6zaJxh16FvEr3RZejDhOryPmoZagZcPkLAc4aEY7avSzHLEqhIuwYir4SkXMR+Jxzc/7Rv9y4eOKVzLWYq6jp0D2M7gvEXQySngm1Rvz/OxLiuODZzzQWo6duUHD+BoIj5ftjT6m4Jkec7M1lNf454/QRrg/WAcuYlSTKR3QBN18nYtRAZQLug+E3mW9KgqFCA2pueFUV3y8lO/UJZa8c8I3mQLmpH6Kq6nVz9cmkxhLHc391f7N6fo6Nd/Aq7iwV8Z722jMteKZ05dIpW6LrI5pLvDEsfYDlLEO0WlApjd4Ra0i41PO41kfHhxZJIKydci5gvGbzqNMs3CRGtlIteoImJl1nnXIn4oyxchmMcjxdMdfaugO736L1sh0/jBW4RWFcV9dOnQmI2czLBSi20Yeubzs6GVzpWDp5DoNw2fE+LGKIrT4ZGjiOrGWoov686SJ15gTST0A2N6me9zSLG9pEtzVPwD13iyKFrhIty2U0Bzl4yqRFFW0WN1AImcgxDj8NPWqwL2a+YOtZFHXAWKsQhby2S36Ls87MfzQ+J1utVU4rSU2nl9CMwxulITPZQkmdniOs3zTb5YD9Kj5XpHCHONx81fipnwQZPguMlUbTAMgMBsY8imimrvMnz3Y9bdnWALXkzEjZy0LkGJNcZLVS8DhuiCaU35L4jTzL+Nq0LupgHwgpse7THoKNtafGMZw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(396003)(39860400002)(346002)(376002)(451199015)(36840700001)(40470700004)(46966006)(82310400005)(2906002)(36756003)(2616005)(70206006)(70586007)(44832011)(5660300002)(82740400003)(8676002)(36860700001)(8936002)(41300700001)(4326008)(110136005)(54906003)(6666004)(40480700001)(86362001)(47076005)(316002)(478600001)(26005)(186003)(1076003)(336012)(81166007)(356005)(40460700003)(426003)(83380400001)(21314003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 06:53:50.3823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 304f5851-1a0e-4d50-9752-08dab655ac3e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5239 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove unused allocation and freeing of PCI host bridge structure. Signed-off-by: Thippeswamy Havalige --- arch/microblaze/include/asm/pci-bridge.h | 5 ----- arch/microblaze/pci/pci-common.c | 29 ----------------------------- arch/microblaze/pci/xilinx_pci.c | 6 ------ 3 files changed, 40 deletions(-) diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 252bcc1..018c632 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -25,7 +25,6 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address) */ struct pci_controller { struct pci_bus *bus; - char is_dynamic; struct device_node *dn; struct list_head list_node; struct device *parent; @@ -98,9 +97,5 @@ extern void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); -/* Allocate & free a PCI host bridge structure */ -extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); -extern void pcibios_free_controller(struct pci_controller *phb); - #endif /* __KERNEL__ */ #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */ diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 12764df0..2965892 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -38,9 +38,6 @@ static DEFINE_SPINLOCK(hose_spinlock); LIST_HEAD(hose_list); -/* XXX kill that some day ... */ -static int global_phb_number; /* Global phb counter */ - /* ISA Memory physical address */ resource_size_t isa_mem_base; @@ -49,32 +46,6 @@ static int pci_bus_count; -struct pci_controller *pcibios_alloc_controller(struct device_node *dev) -{ - struct pci_controller *phb; - - phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); - if (!phb) - return NULL; - spin_lock(&hose_spinlock); - phb->global_number = global_phb_number++; - list_add_tail(&phb->list_node, &hose_list); - spin_unlock(&hose_spinlock); - phb->dn = dev; - phb->is_dynamic = mem_init_done; - return phb; -} - -void pcibios_free_controller(struct pci_controller *phb) -{ - spin_lock(&hose_spinlock); - list_del(&phb->list_node); - spin_unlock(&hose_spinlock); - - if (phb->is_dynamic) - kfree(phb); -} - static resource_size_t pcibios_io_size(const struct pci_controller *hose) { return resource_size(&hose->io_resource); diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c index f1a5112..3fa16e3 100644 --- a/arch/microblaze/pci/xilinx_pci.c +++ b/arch/microblaze/pci/xilinx_pci.c @@ -97,12 +97,6 @@ void __init xilinx_pci_init(void) return; } - hose = pcibios_alloc_controller(pci_node); - if (!hose) { - pr_err("xilinx-pci: pcibios_alloc_controller() failed\n"); - return; - } - /* Setup config space */ setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR, r.start + XPLB_PCI_DATA, From patchwork Tue Oct 25 06:52:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 618425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D379FA373E for ; Tue, 25 Oct 2022 06:54:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231432AbiJYGyK (ORCPT ); Tue, 25 Oct 2022 02:54:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231441AbiJYGyA (ORCPT ); Tue, 25 Oct 2022 02:54:00 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2086.outbound.protection.outlook.com [40.107.223.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB5DA43301; Mon, 24 Oct 2022 23:53:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aKFvQBEZfEDR63gRjhomQ3lidc7TFn6I1+IVDu0J9sBaPJK5hFQU+5lZbH4NxXZIZ2IvZq8EZ6uNluf6Wx/4xIOahgvigGO6h9zaa6x0qKQvrbnDI+6hrXY3FGVezVtYqnB6+6GjFpAN8fUcotIEvnWovgfwKdGOxGFPew0ffYQSeiKLFNeLzBMIThmxVXjxyEw+O326dto7hoQm/iw7IAY03zNeUSz4nOYtAcsJm3MwRGt1e+1CKYU8fr2QofZncIJMiyhKXppGVXpZsIVOzlLAPRjgM2f74y0al/0VaHIHnHWcBG2TPURpRPzcobKD/zaENPsiWcrQNoGf2P4d8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5OlJneRi2U1pLc3VrOTJl+hE6sjfNt4he202WZf6aDQ=; b=LQrPSsl0vEMmw9Q8iUnHMF02J8l4opiYEwkKtQTPxSOSWrQsfHDasIukY4QnrSpPKEUMiAGMupYHrgHM8t6IrZ0cQc+8CvFYzn14LdhRv6G8OcK5HT7EyLn6tERgsfP7RTU/7TyY3qArwF+rnKJw2GZTgqG12eM+LUvJyf3rNj+eiwQ467W4rQ/2ToABdhSjA66ZWvh52qeBWs4+I773Lezvgvu1WKnFzd0FIpKVrEQLMHzfqj7jIy9oaryoncl8criSINCpATU2e4z7lFTuRFwX4Qcw0ANGBa44dMrznmlGRBdvPlp0erlQGV7WJXI2XygenfWDzpkx5GtCA7WY6g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5OlJneRi2U1pLc3VrOTJl+hE6sjfNt4he202WZf6aDQ=; b=O3ojNyFSMX6HBr8p6MiMvOK7uv4K9J9v98wXfPpiScnE9r6LrnhLwwOjeIjCX+Pa6CSmlvNEN2fx8wwYibteFsdbVfLDbZQ71Pitof4ua8SCpVTHvCakhw1PnF7DTtv3NgArusKnVhpko+k4xF5mdT/gv4iBSZm6VdmuOhQ4p5U= Received: from DM6PR07CA0083.namprd07.prod.outlook.com (2603:10b6:5:337::16) by PH0PR12MB5605.namprd12.prod.outlook.com (2603:10b6:510:129::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.21; Tue, 25 Oct 2022 06:53:56 +0000 Received: from DM6NAM11FT107.eop-nam11.prod.protection.outlook.com (2603:10b6:5:337:cafe::79) by DM6PR07CA0083.outlook.office365.com (2603:10b6:5:337::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.28 via Frontend Transport; Tue, 25 Oct 2022 06:53:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT107.mail.protection.outlook.com (10.13.172.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Tue, 25 Oct 2022 06:53:56 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:53:55 -0500 Received: from xhdbharatku40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Tue, 25 Oct 2022 01:53:53 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , "Thippeswamy Havalige" Subject: [PATCH 08/13] microblaze/PCI: Remove unused PCI Indirect ops Date: Tue, 25 Oct 2022 12:22:09 +0530 Message-ID: <20221025065214.4663-9-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221025065214.4663-1-thippeswamy.havalige@amd.com> References: <20221025065214.4663-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT107:EE_|PH0PR12MB5605:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ddbd582-d17a-40f8-e37c-08dab655affb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +5EnBRXirMoK9BpifcIfrVz6YsbyTABVfEvLFLNpQiBRGEJ/5s2nY5jMboUpmQgAN8e89VqwoNYF7hGb+Os0mwp0PBm5fT0RcfI9M/xz5f9JLwbJW7b6mq4VWKwyfiQwZ45kah403MNBjPsHA2Xl5hZSYWhpn84hFPhehtjU+ax9YpVibtCnDjJgtf+38ACz1zSnTdSFp6S+TxD6bAEy6DQyRRJymT2fPjSakm+GPheo3/IV513xmK2/rMHEKi34X4Zo0MKgbolixA7G7lPwzBkWC+7XATPDDeX6o1fmWCsoJ9DzZGhbYkPOlYCkG1YZYItS+GTwqPzrOgnHvgpzXlEkprw5LOrN/Y2M5brjlSEPFA5dKG7FwtV4yxlGeTLTWec5/7Sf/yQC2SWSv4TegQNaclHuFcfIHKpIz8sj/ye30PLfc+Ab40XO2XgWdmGMR667bGUasvjN+iGMBNgHDFGzIr29XMFrwCyr+pqHExBM6MwVcnvfImlh3owK6QoWeAmajJCXY/PwgRgd2TnNYFckLo8GDhS5Yr0i1Ct83HhB70q7GJg7u9XBBYT3LYSWUwVMxizhwi4Y37KN5qOhX4Sx2MxdpmkFnre8RnvaJny/7iOtdjNznk/Zb0agHYVoCzH9DZFhfgQYBFPI9B0OcPO8ug+Pfdu0/dxZTTbJNzBh3UEKG/cYWLnj+/68MWu4v0fArEVgNogaNeTeoxCwHaZJD+dMmmpJXkSkzF2xyLmGF5qS8hpSZ3lOiKe+rlEjNbbDiBA0zP+12nOM71i6fegs4rg+Qy4Cz7xQ631PC8WRbEwhX2UsyX061p5qyX3i X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199015)(46966006)(36840700001)(40470700004)(36860700001)(8676002)(44832011)(316002)(41300700001)(54906003)(110136005)(4326008)(40480700001)(8936002)(70206006)(70586007)(5660300002)(82740400003)(6666004)(478600001)(2616005)(1076003)(186003)(26005)(426003)(83380400001)(356005)(81166007)(40460700003)(47076005)(86362001)(336012)(82310400005)(36756003)(2906002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 06:53:56.6717 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ddbd582-d17a-40f8-e37c-08dab655affb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5605 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove unused variants of PCI indirect handling. Signed-off-by: Thippeswamy Havalige --- arch/microblaze/include/asm/pci-bridge.h | 34 ------- arch/microblaze/pci/Makefile | 2 +- arch/microblaze/pci/indirect_pci.c | 158 ------------------------------- arch/microblaze/pci/xilinx_pci.c | 6 -- 4 files changed, 1 insertion(+), 199 deletions(-) delete mode 100644 arch/microblaze/pci/indirect_pci.c diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 170369d..cd9ae71 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -32,8 +32,6 @@ struct pci_controller { int first_busno; int last_busno; - int self_busno; - void __iomem *io_base_virt; resource_size_t io_base_phys; @@ -42,34 +40,6 @@ struct pci_controller { */ resource_size_t pci_mem_offset; - struct pci_ops *ops; - unsigned int __iomem *cfg_addr; - void __iomem *cfg_data; - - /* - * Used for variants of PCI indirect handling and possible quirks: - * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 - * EXT_REG - provides access to PCI-e extended registers - * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS - * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS - * to determine which bus number to match on when generating type0 - * config cycles - * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with - * hanging if we don't have link and try to do config cycles to - * anything but the PHB. Only allow talking to the PHB if this is - * set. - * BIG_ENDIAN - cfg_addr is a big endian register - * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs - * on the PLB4. Effectively disable MRM commands by setting this. - */ -#define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 -#define INDIRECT_TYPE_EXT_REG 0x00000002 -#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 -#define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 -#define INDIRECT_TYPE_BIG_ENDIAN 0x00000010 -#define INDIRECT_TYPE_BROKEN_MRM 0x00000020 - u32 indirect_type; - /* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more */ @@ -91,9 +61,5 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) } #endif /* CONFIG_PCI */ -extern void setup_indirect_pci(struct pci_controller *hose, - resource_size_t cfg_addr, - resource_size_t cfg_data, u32 flags); - #endif /* __KERNEL__ */ #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */ diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile index 0251c20..3cbdf25 100644 --- a/arch/microblaze/pci/Makefile +++ b/arch/microblaze/pci/Makefile @@ -3,5 +3,5 @@ # Makefile # -obj-$(CONFIG_PCI) += pci-common.o indirect_pci.o iomap.o +obj-$(CONFIG_PCI) += pci-common.o iomap.o obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o diff --git a/arch/microblaze/pci/indirect_pci.c b/arch/microblaze/pci/indirect_pci.c deleted file mode 100644 index 1caf7d3..0000000 --- a/arch/microblaze/pci/indirect_pci.c +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Support for indirect PCI bridges. - * - * Copyright (C) 1998 Gabriel Paubert. - */ - -#include -#include -#include -#include -#include - -#include -#include - -static int -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) -{ - struct pci_controller *hose = pci_bus_to_host(bus); - volatile void __iomem *cfg_data; - u8 cfg_type = 0; - u32 bus_no, reg; - - if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) { - if (bus->number != hose->first_busno) - return PCIBIOS_DEVICE_NOT_FOUND; - if (devfn != 0) - return PCIBIOS_DEVICE_NOT_FOUND; - } - - if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE) - if (bus->number != hose->first_busno) - cfg_type = 1; - - bus_no = (bus->number == hose->first_busno) ? - hose->self_busno : bus->number; - - if (hose->indirect_type & INDIRECT_TYPE_EXT_REG) - reg = ((offset & 0xf00) << 16) | (offset & 0xfc); - else - reg = offset & 0xfc; /* Only 3 bits for function */ - - if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN) - out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | - (devfn << 8) | reg | cfg_type)); - else - out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | - (devfn << 8) | reg | cfg_type)); - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */ - switch (len) { - case 1: - *val = in_8(cfg_data); - break; - case 2: - *val = in_le16(cfg_data); - break; - default: - *val = in_le32(cfg_data); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) -{ - struct pci_controller *hose = pci_bus_to_host(bus); - volatile void __iomem *cfg_data; - u8 cfg_type = 0; - u32 bus_no, reg; - - if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) { - if (bus->number != hose->first_busno) - return PCIBIOS_DEVICE_NOT_FOUND; - if (devfn != 0) - return PCIBIOS_DEVICE_NOT_FOUND; - } - - if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE) - if (bus->number != hose->first_busno) - cfg_type = 1; - - bus_no = (bus->number == hose->first_busno) ? - hose->self_busno : bus->number; - - if (hose->indirect_type & INDIRECT_TYPE_EXT_REG) - reg = ((offset & 0xf00) << 16) | (offset & 0xfc); - else - reg = offset & 0xfc; - - if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN) - out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | - (devfn << 8) | reg | cfg_type)); - else - out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | - (devfn << 8) | reg | cfg_type)); - - /* suppress setting of PCI_PRIMARY_BUS */ - if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) - if ((offset == PCI_PRIMARY_BUS) && - (bus->number == hose->first_busno)) - val &= 0xffffff00; - - /* Workaround for PCI_28 Errata in 440EPx/GRx */ - if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) && - offset == PCI_CACHE_LINE_SIZE) { - val = 0; - } - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - cfg_data = hose->cfg_data + (offset & 3); - switch (len) { - case 1: - out_8(cfg_data, val); - break; - case 2: - out_le16(cfg_data, val); - break; - default: - out_le32(cfg_data, val); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops indirect_pci_ops = { - .read = indirect_read_config, - .write = indirect_write_config, -}; - -void __init -setup_indirect_pci(struct pci_controller *hose, - resource_size_t cfg_addr, - resource_size_t cfg_data, u32 flags) -{ - resource_size_t base = cfg_addr & PAGE_MASK; - void __iomem *mbase; - - mbase = ioremap(base, PAGE_SIZE); - hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK); - if ((cfg_data & PAGE_MASK) != base) - mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); - hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK); - hose->ops = &indirect_pci_ops; - hose->indirect_type = flags; -} diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c index 3fa16e3..5dc4182 100644 --- a/arch/microblaze/pci/xilinx_pci.c +++ b/arch/microblaze/pci/xilinx_pci.c @@ -83,7 +83,6 @@ static void xilinx_pci_fixup_bridge(struct pci_dev *dev) */ void __init xilinx_pci_init(void) { - struct pci_controller *hose; struct resource r; void __iomem *pci_reg; struct device_node *pci_node; @@ -97,11 +96,6 @@ void __init xilinx_pci_init(void) return; } - /* Setup config space */ - setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR, - r.start + XPLB_PCI_DATA, - INDIRECT_TYPE_SET_CFG_TYPE); - /* Set the max bus number to 255, and bus/subbus no's to 0 */ pci_reg = of_iomap(pci_node, 0); WARN_ON(!pci_reg); From patchwork Tue Oct 25 06:52:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 618424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DA30FA373E for ; Tue, 25 Oct 2022 06:54:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231483AbiJYGyM (ORCPT ); Tue, 25 Oct 2022 02:54:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231492AbiJYGyG (ORCPT ); Tue, 25 Oct 2022 02:54:06 -0400 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on20610.outbound.protection.outlook.com [IPv6:2a01:111:f400:7e8b::610]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04E2013A5AE; Mon, 24 Oct 2022 23:54:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=K9ecFPbqgjnaUNp9wKoqPtFxFQIzREskmZXT/+2T0iTZ4nI1BBaXPome5g6lgUKkem501NJ+R9k9wgejXfYKVdt9H/zwL5H6FyuPkoPYLhqEZwm6/oovB4EAZLt2gEaxGHeg8cI4Y7PtRYaCcQH8X/elCI+p9RmnAXytMcVAevvKNFwTK0X+Fa0Sk2VtxiF2Z8mdP8n8En9XIqlozSEEsCaDYYU91c4TXVIK9Ho1elEMOsjWM0paD9afyTEG/ZQVB/YDvSCIn3fQLC99baxMPZD6KKS2/2oWaFpMTYxtUuqoWyesvPDCjUwPNvLouLEGR3RFmol7fDfN5YU45Ze3jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lUctBlJERuwrSI3gA8HvJQePg/GtTmxRoBwMQwLiI54=; b=PeK3aYdzePizLWz8uq0n0K3e19O/W8RGmRVE2g6iS38QqyyzYew6QDqunDtT7ri8BpbKjwyDWGu0aGDfUhg99IavICP5pMn91HuuyH3xCUofZGuMupb6fVWJclkvHwp8A9vMihBxEaJhqLOQ1yIaoDtrMJsQNSguNrNsrz6xHd8RpcO7PM6WgG18P9QyxdVLSceTF67W5uEurmJfl2E9ENuLnAc8qItK3upJr/lDR9sh6Bw0vV1z1T3LoEriavZ463DmXSDydNKrNhAYkdptjSHB+OERnVKyqiklQX7Ozpc3kUpwjJgckq3aOj5rNLCO3BGhGcATlQiyQalT6N35+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lUctBlJERuwrSI3gA8HvJQePg/GtTmxRoBwMQwLiI54=; b=Q/xmM9QqU2fIQN2SqOmqP2L5I6/LBweqnTRZP93JgSnNSMa8Ha4Oc4Sorg4TWCLKYNXI47WtedN30fog8exyBvjJWFNtCRSGdwOT7Xs0QV3fX0ixlnmpgJNPgc8xXq0XQJlLhT4sDNeREKdgZPmkv7aWvCx2ewizZu9T7w0/zYs= Received: from DM6PR17CA0013.namprd17.prod.outlook.com (2603:10b6:5:1b3::26) by PH7PR12MB7283.namprd12.prod.outlook.com (2603:10b6:510:20a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.26; Tue, 25 Oct 2022 06:54:00 +0000 Received: from DM6NAM11FT031.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1b3:cafe::1a) by DM6PR17CA0013.outlook.office365.com (2603:10b6:5:1b3::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.23 via Frontend Transport; Tue, 25 Oct 2022 06:54:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT031.mail.protection.outlook.com (10.13.172.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Tue, 25 Oct 2022 06:53:59 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:53:59 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:53:59 -0500 Received: from xhdbharatku40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Tue, 25 Oct 2022 01:53:56 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , "Thippeswamy Havalige" Subject: [PATCH 09/13] microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU address to I/O port Date: Tue, 25 Oct 2022 12:22:10 +0530 Message-ID: <20221025065214.4663-10-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221025065214.4663-1-thippeswamy.havalige@amd.com> References: <20221025065214.4663-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT031:EE_|PH7PR12MB7283:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ffda11d-ee2c-4756-9a18-08dab655b1f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k12s6wiOd5e28g1YzE0D6Mtex7tkfrAvlbSc7oqwO6TyTGUZygOv7VcAfzw4x1B4TEnHusCmGJ3B0If6RU6jOdtopErfzbJGUl1rOdNG+yWfSVs23OC++g0cs+rLg8akZsH3CrqP51IawJDwNbC7Su1uFEEJ9fHxBM5RfEEMPQOnJkvPyEq7EojgrILzq4V9r0aaTtV4Jc7s7EigV7aTT2bSwoy2FnXedt62hz38FNKJ/oXIs0GKKIyuq/DYEBdSXjqbsK0BbKNVvsjkZm/i7ofNEufJXt5wR9qiiceLp83dMCj4Z+gmLeWRolW9fSM3UOXYAVI1EYdbRunChKl+G7hnQEDcGyMZeWsjGXIB1eynNPam0PBbmMfRXiVE2ZgzVF1dpXKBcX+onc4WqQMqBq8ttjNNgPU8m0rD5NsJXVAh0gXi/dztUadtloCp36awqCC7YX8ywQcOPNeqpM9i2HeJERu0HqvjPvVs3Fh/pth2uwOwq6P1MeDkJN0MQ0qhL3HZyzGCr19MMceWNPUSdCrsRV3NJh4A4K5LkitOaFYaNx2dp4RR32OgE0OfuuLJR9B6+HPEXK1uG6CPIEZJPVE7jHtT6LFgmlfUQkkAv85m0+2L9CPbey0FQv3LKN4LkuRyXntQhYieYLUWFVz6n6wEDMkcJwbC68U3RRRT/nPL+KHgrtyT3/xFuiyM9yGT+rr1LKR7fSYZgbuUPDg1Uf6yusSkIDLIkGScGslqForMeuc5oPhIreGJHe2V6nBfm3WOgh16cQMGuXLD1R7w38LJKERwdCbD0uS1imBtKiWD+ds3XDTy26WhH4dl8LMC X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(396003)(39860400002)(346002)(376002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(356005)(82740400003)(81166007)(5660300002)(70586007)(70206006)(8936002)(47076005)(426003)(83380400001)(36860700001)(86362001)(54906003)(110136005)(2616005)(26005)(40480700001)(186003)(336012)(40460700003)(1076003)(316002)(478600001)(82310400005)(44832011)(41300700001)(8676002)(4326008)(2906002)(6666004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 06:53:59.9900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ffda11d-ee2c-4756-9a18-08dab655b1f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7283 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove unused pci_address_to_pio() conversion of CPU address to I/O port function. Signed-off-by: Thippeswamy Havalige --- arch/microblaze/pci/pci-common.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 085e673..555281c 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -68,29 +68,6 @@ int pcibios_vaddr_is_ioport(void __iomem *address) return ret; } -unsigned long pci_address_to_pio(phys_addr_t address) -{ - struct pci_controller *hose; - resource_size_t size; - unsigned long ret = ~0; - - spin_lock(&hose_spinlock); - list_for_each_entry(hose, &hose_list, list_node) { - size = pcibios_io_size(hose); - if (address >= hose->io_base_phys && - address < (hose->io_base_phys + size)) { - unsigned long base = - (unsigned long)hose->io_base_virt - _IO_BASE; - ret = base + (address - hose->io_base_phys); - break; - } - } - spin_unlock(&hose_spinlock); - - return ret; -} -EXPORT_SYMBOL_GPL(pci_address_to_pio); - /* * Platform support for /proc/bus/pci/X/Y mmap()s. */ From patchwork Tue Oct 25 06:52:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 618423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ECFCC04A95 for ; Tue, 25 Oct 2022 06:54:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231496AbiJYGyp (ORCPT ); Tue, 25 Oct 2022 02:54:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231520AbiJYGyP (ORCPT ); Tue, 25 Oct 2022 02:54:15 -0400 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2078.outbound.protection.outlook.com [40.107.96.78]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57ED9F5CDD; Mon, 24 Oct 2022 23:54:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=R5mF3Lgar9S5JjJ6yChDrncPaFLvpbFk0Wfb+5WKcp33gMN5r8VMdtUE5ac0hnEmu8u1WnP+JU17KXBL2vCtQJRSA7ZRgdM7tEgkcjVqhi4fX7cH7yUHI0sla5ZxXCjOzngKB+rK+ZEbkvEK22AXaetzi/PmtCf3czBmfpJ7wbVM0In9QLYLEJMTjJBB1CldmJ0ODsQoPiisyE8gyInXom0xRtqeDEPG7qlAP4d915qWbgnbiBL+7A4RQZQLzMoMnvJw7wBsUv0wUYK6oTRYz2Vax1v+G5QcWNkKjlAkigmJvq1lqYFc2P91IJCZHUKgIl5t1SwAFep4vEBjg6PS9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uNmc0ViRQ0BiI9dEUPMNkAPWKmquEQOo/ZcNAn88p18=; b=YScW3la8+xSGKmZS491lWYDklUBdSMlImineQnIA6LFLGZWQL8FwjvkzZkSRKnyFkCzNhHo0VTbJKBIJcJ8J4FNU93+NeRB5JdI1Ic2Q0dyrGQ3ZRWVH50IVm9QV25rAZiHXp0r8q/6neOQnDsWhrjJictCyLqECkMMXymyOwfpcxnHjJoDpgyzb5fOQU2GNn8GWSf6SEcGFO5e7vd1PLL6ts5e03pCAxcN9P7n9/WGUuTrkncE7nwckoO7Z7PykAJ+u/FnyxTH07tdQP++GJTO0Uc9XujH7Oc5YeebIfycPS9+Z7T/OHDtFyhPGA6zh3w0T16e4kjEnVmwmiJKsVQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uNmc0ViRQ0BiI9dEUPMNkAPWKmquEQOo/ZcNAn88p18=; b=x4niXnQUxNmm44Wp255fB1L7EOEdPkVJk2lbhIV9c8RLO80m9LCRBxZ2pSXL8oZrtDohl6mrznlcU+yuNoXFE85DJ8SaTBe13EgN4cu0gWpEjWKXpMenoIOx6z4MX6qOJ8avTNbJH22zjUpM4UXCmZ3I8adttY6xuCh9GV3NL7E= Received: from DM6PR11CA0027.namprd11.prod.outlook.com (2603:10b6:5:190::40) by IA0PR12MB7776.namprd12.prod.outlook.com (2603:10b6:208:430::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.28; Tue, 25 Oct 2022 06:54:09 +0000 Received: from DM6NAM11FT040.eop-nam11.prod.protection.outlook.com (2603:10b6:5:190:cafe::31) by DM6PR11CA0027.outlook.office365.com (2603:10b6:5:190::40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.28 via Frontend Transport; Tue, 25 Oct 2022 06:54:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT040.mail.protection.outlook.com (10.13.173.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Tue, 25 Oct 2022 06:54:09 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 01:54:08 -0500 Received: from xhdbharatku40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Tue, 25 Oct 2022 01:54:05 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , "Thippeswamy Havalige" Subject: [PATCH 12/13] microblaze/PCI: Remove support for Xilinx PCI host bridge Date: Tue, 25 Oct 2022 12:22:13 +0530 Message-ID: <20221025065214.4663-13-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221025065214.4663-1-thippeswamy.havalige@amd.com> References: <20221025065214.4663-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT040:EE_|IA0PR12MB7776:EE_ X-MS-Office365-Filtering-Correlation-Id: a47f1b61-5d91-40df-a81d-08dab655b76a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kqHu0DFl6j+xHnqgMfMgaBnNspr7fy2AspCxllqB97t/aTO7+n7cH2yAoqOJ+vDc2GmXinUtbg0udpsTuz7S5ob41bPAOXNyQeY1b1EEoaMu3dKvkyNLxCmX2IgxgoygrXyI86cRaqyN/zPbo6PrcOhDabaQV8udOwuZr5vq7YYO2TGcRxyTxwOoGT8qlmI/3N3xgkMNkw6ujEcaHXl3ey62Hci251ciyeV5CIYZxbgreBq3jS0zCCPxRxiXWp08NL9/VvX3q1xsNLPYwJ4r03vHKLRZ3EqaExgRQrje72x8V9aGYcKYFWIusZUx159qtSc+CaImQ4ObYbB4YPHlnIvHU2UdXubqJFQDfcV0F8A2Tyz6GhjEvFy6rBMgwflf4kLGauaHhv5nYxJcfMeFNtbEjJ0zmlE1HV6/FHxJpq6XKgsK6ONp0RB/sZVUqWFsepWGzWOZIk5mrKD/m6N7wpiLJb2NqetQRbdM3KizyTXWavzm2YIHJWeJhlBRyz/I9FjRIDI2t6we8mSUYz3aHHqmaCaryvevY/qahB/XzR4VC3tnyCk2qw7zVUCqdATiv0j44xVsYEGpKkR7uPrRfAR1KStekiUEBxlao5sOMtk/WtSoAkGZnOv3sBpGBG8orOdxPZplijwX7hrW/HeKJZsECYtsn4Bl14haF9SkWh08TPvX0DJcu/QDS2jfHj3atybsMuOv4svyQ28xXh68aaRANNJYjASueP6TGSaY/4HTT5gDBp3AJmmWKj7fU9ZpQef54bsfPS67Ubfowcpxmo/j7Juo4H9GVzrtGUSmm0pTYv66gm6p6CD7mSlZEMCC X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199015)(46966006)(36840700001)(40470700004)(316002)(81166007)(40480700001)(54906003)(110136005)(36860700001)(356005)(5660300002)(82740400003)(4326008)(70586007)(70206006)(8676002)(8936002)(41300700001)(426003)(26005)(86362001)(336012)(6666004)(478600001)(1076003)(186003)(40460700003)(83380400001)(2616005)(47076005)(82310400005)(2906002)(36756003)(44832011)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 06:54:09.1261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a47f1b61-5d91-40df-a81d-08dab655b76a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7776 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch removes support for the Xilinx PCI host bridge IPcore. Signed-off-by: Thippeswamy Havalige --- arch/microblaze/Kconfig | 8 --- arch/microblaze/include/asm/pci-bridge.h | 6 -- arch/microblaze/include/asm/pci.h | 5 -- arch/microblaze/pci/Makefile | 1 - arch/microblaze/pci/xilinx_pci.c | 105 ------------------------------- 5 files changed, 125 deletions(-) delete mode 100644 arch/microblaze/pci/xilinx_pci.c diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 996132a..9bacdab 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -205,11 +205,3 @@ config TASK_SIZE default "0x80000000" endmenu - -menu "Bus Options" - -config PCI_XILINX - bool "Xilinx PCI host bridge support" - depends on PCI - -endmenu diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 5db2c66..be5f504 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -25,7 +25,6 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address) */ struct pci_controller { struct pci_bus *bus; - struct device_node *dn; struct list_head list_node; void __iomem *io_base_virt; @@ -37,11 +36,6 @@ struct pci_controller { }; #ifdef CONFIG_PCI -static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) -{ - return bus->sysdata; -} - static inline int isa_vaddr_is_ioport(void __iomem *address) { /* No specific ISA handling on ppc32 at this stage, it diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index a75bf3b..91f1f71 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h @@ -38,12 +38,7 @@ struct file; -/* This part of code was originally in xilinx-pci.h */ -#ifdef CONFIG_PCI_XILINX -extern void __init xilinx_pci_init(void); -#else static inline void __init xilinx_pci_init(void) { return; } -#endif #endif /* __KERNEL__ */ #endif /* __ASM_MICROBLAZE_PCI_H */ diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile index 3cbdf25..293b416 100644 --- a/arch/microblaze/pci/Makefile +++ b/arch/microblaze/pci/Makefile @@ -4,4 +4,3 @@ # obj-$(CONFIG_PCI) += pci-common.o iomap.o -obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c deleted file mode 100644 index 5dc4182..0000000 --- a/arch/microblaze/pci/xilinx_pci.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * PCI support for Xilinx plbv46_pci soft-core which can be used on - * Xilinx Virtex ML410 / ML510 boards. - * - * Copyright 2009 Roderick Colenbrander - * Copyright 2009 Secret Lab Technologies Ltd. - * - * The pci bridge fixup code was copied from ppc4xx_pci.c and was written - * by Benjamin Herrenschmidt. - * Copyright 2007 Ben. Herrenschmidt , IBM Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include - -#define XPLB_PCI_ADDR 0x10c -#define XPLB_PCI_DATA 0x110 -#define XPLB_PCI_BUS 0x114 - -#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \ - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY) - -static const struct of_device_id xilinx_pci_match[] = { - { .compatible = "xlnx,plbv46-pci-1.03.a", }, - {} -}; - -/** - * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration. - */ -static void xilinx_pci_fixup_bridge(struct pci_dev *dev) -{ - struct pci_controller *hose; - int i; - - if (dev->devfn || dev->bus->self) - return; - - hose = pci_bus_to_host(dev->bus); - if (!hose) - return; - - if (!of_match_node(xilinx_pci_match, hose->dn)) - return; - - /* Hide the PCI host BARs from the kernel as their content doesn't - * fit well in the resource management - */ - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - - dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", - pci_name(dev)); -} -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge); - -#ifdef DEBUG -/** - * xilinx_pci_exclude_device - Don't do config access for non-root bus - * - * This is a hack. Config access to any bus other than bus 0 does not - * currently work on the ML510 so we prevent it here. - */ -static int -xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) -{ - return (bus != 0); -} -#endif - -/** - * xilinx_pci_init - Find and register a Xilinx PCI host bridge - */ -void __init xilinx_pci_init(void) -{ - struct resource r; - void __iomem *pci_reg; - struct device_node *pci_node; - - pci_node = of_find_matching_node(NULL, xilinx_pci_match); - if (!pci_node) - return; - - if (of_address_to_resource(pci_node, 0, &r)) { - pr_err("xilinx-pci: cannot resolve base address\n"); - return; - } - - /* Set the max bus number to 255, and bus/subbus no's to 0 */ - pci_reg = of_iomap(pci_node, 0); - WARN_ON(!pci_reg); - out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff); - iounmap(pci_reg); - -}