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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Peter Xu , Jason Wang , Peter Maydell , qemu-arm@nongnu.org (open list:ARM PrimeCell and...) Subject: [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs Date: Fri, 11 Nov 2022 18:25:16 +0000 Message-Id: <20221111182535.64844-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We currently have hacks across the hw/ to reference current_cpu to work out what the current accessing CPU is. This breaks in some cases including using gdbstub to access HW state. As we have MemTxAttrs to describe details about the access lets extend it so CPU accesses can be explicitly marked. To achieve this we create a new requester_type which indicates to consumers how requester_id it to be consumed. We absorb the existing unspecified:1 bitfield into this type and also document a potential machine specific encoding which will be useful to (currently) out-of-tree extensions. Places that checked to see if things where unspecified now instead check the source if what they expected. There are a number of places we need to fix up including: CPU helpers directly calling address_space_*() fns models in hw/ fishing the data out of current_cpu hypervisors offloading device emulation to QEMU I'll start addressing some of these in following patches. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - use separate field cpu_index - bool for requester_is_cpu v3 - switch to enum MemTxRequesterType - move helper #define to patch - revert to overloading requester_id - mention hypervisors in commit message - drop cputlb tweaks, they will move to target specific code v4 - merge unspecified:1 into MTRT_UNSPECIFIED - document a MTRT_MACHINE for more complex encoding - ensure existing users of requester_id set MTRT_PCI - ensure existing consumers of requester_id check type is MTRT_PCI - have MEMTXATTRS_CPU take CPUState * directly v5 - re-order so MTRT_UNSPECIFIED is zero - fix up comments referring to the difference between empty and unspecified:1 - kernel-doc annotations for typedefs - don't impose source type tz-msc during transformation - re-order bitfields so requester_type/id at top - add helper for MEMTXATTRS_PCI --- include/exec/memattrs.h | 68 ++++++++++++++++++++++++++++++++--------- hw/i386/amd_iommu.c | 6 ++-- hw/i386/intel_iommu.c | 2 +- hw/misc/tz-mpc.c | 2 +- hw/misc/tz-msc.c | 6 ++-- hw/pci/pci.c | 4 +-- 6 files changed, 60 insertions(+), 28 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..8359fc448b 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -14,7 +14,32 @@ #ifndef MEMATTRS_H #define MEMATTRS_H -/* Every memory transaction has associated with it a set of +/** + * typedef MemTxRequesterType - source of memory transaction + * + * Every memory transaction comes from a specific place which defines + * how requester_id should be handled if at all. + * + * UNSPECIFIED: the default for otherwise undefined MemTxAttrs + * CPU: requester_id is the global cpu_index + * This needs further processing if you need to work out which + * socket or complex it comes from + * PCI: indicates the requester_id is a PCI id + * MACHINE: indicates a machine specific encoding + * This will require further processing to decode into its + * constituent parts. + */ +typedef enum MemTxRequesterType { + MTRT_UNSPECIFIED = 0, + MTRT_CPU, + MTRT_PCI, + MTRT_MACHINE +} MemTxRequesterType; + +/** + * typedef MemTxAttrs - attributes of a memory transaction + * + * Every memory transaction has associated with it a set of * attributes. Some of these are generic (such as the ID of * the bus master); some are specific to a particular kind of * bus (such as the ARM Secure/NonSecure bit). We define them @@ -23,13 +48,12 @@ * different semantics. */ typedef struct MemTxAttrs { - /* Bus masters which don't specify any attributes will get this - * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can - * distinguish "all attributes deliberately clear" from - * "didn't specify" if necessary. - */ - unsigned int unspecified:1; - /* ARM/AMBA: TrustZone Secure access + /* Requester type (e.g. CPU or PCI MSI) */ + MemTxRequesterType requester_type:2; + /* Requester ID */ + unsigned int requester_id:16; + /* + * ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ unsigned int secure:1; @@ -43,8 +67,6 @@ typedef struct MemTxAttrs { * (see MEMTX_ACCESS_ERROR). */ unsigned int memory:1; - /* Requester ID (for MSI for example) */ - unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; /* @@ -59,12 +81,28 @@ typedef struct MemTxAttrs { unsigned int target_tlb_bit2 : 1; } MemTxAttrs; -/* Bus masters which don't specify any attributes will get this, - * which has all attribute bits clear except the topmost one - * (so that we can distinguish "all attributes deliberately clear" - * from "didn't specify" if necessary). +/* + * Bus masters which don't specify any attributes will get this which + * indicates none of the attributes can be used. + */ +#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) \ + { .requester_type = MTRT_UNSPECIFIED }) + +/* + * Helper for setting a basic CPU sourced transaction, it expects a + * CPUState * + */ +#define MEMTXATTRS_CPU(cs) ((MemTxAttrs) \ + {.requester_type = MTRT_CPU, \ + .requester_id = cs->cpu_index}) + +/* + * Helper for setting a basic PCI sourced transaction, it expects a + * PCIDevice * */ -#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) +#define MEMTXATTRS_PCI(dev) ((MemTxAttrs) \ + {.requester_type = MTRT_PCI, \ + .requester_id = pci_requester_id(dev)}) /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 725f69095b..284359c16e 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -153,9 +153,7 @@ static void amdvi_assign_andq(AMDVIState *s, hwaddr addr, uint64_t val) static void amdvi_generate_msi_interrupt(AMDVIState *s) { MSIMessage msg = {}; - MemTxAttrs attrs = { - .requester_id = pci_requester_id(&s->pci.dev) - }; + MemTxAttrs attrs = MEMTXATTRS_PCI(&s->pci.dev); if (msi_enabled(&s->pci.dev)) { msg = msi_get_message(&s->pci.dev, 0); @@ -1356,7 +1354,7 @@ static MemTxResult amdvi_mem_ir_write(void *opaque, hwaddr addr, trace_amdvi_mem_ir_write_req(addr, value, size); - if (!attrs.unspecified) { + if (attrs.requester_type == MTRT_PCI) { /* We have explicit Source ID */ sid = attrs.requester_id; } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a08ee85edf..12752413eb 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3517,7 +3517,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr, from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; from.data = (uint32_t) value; - if (!attrs.unspecified) { + if (attrs.requester_type == MTRT_PCI) { /* We have explicit Source ID */ sid = attrs.requester_id; } diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index 30481e1c90..4beb5daa1a 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -461,7 +461,7 @@ static int tz_mpc_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs) * All the real during-emulation transactions from the CPU will * specify attributes. */ - return (attrs.unspecified || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_NS; + return ((attrs.requester_type == MTRT_UNSPECIFIED) || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_NS; } static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu) diff --git a/hw/misc/tz-msc.c b/hw/misc/tz-msc.c index acbe94400b..e93bfc7083 100644 --- a/hw/misc/tz-msc.c +++ b/hw/misc/tz-msc.c @@ -137,11 +137,9 @@ static MemTxResult tz_msc_read(void *opaque, hwaddr addr, uint64_t *pdata, return MEMTX_OK; case MSCAllowSecure: attrs.secure = 1; - attrs.unspecified = 0; break; case MSCAllowNonSecure: attrs.secure = 0; - attrs.unspecified = 0; break; } @@ -179,11 +177,11 @@ static MemTxResult tz_msc_write(void *opaque, hwaddr addr, uint64_t val, return MEMTX_OK; case MSCAllowSecure: attrs.secure = 1; - attrs.unspecified = 0; + attrs.requester_type = MTRT_CPU; break; case MSCAllowNonSecure: attrs.secure = 0; - attrs.unspecified = 0; + attrs.requester_type = MTRT_CPU; break; } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..1d0d8d866f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -319,9 +319,7 @@ void pci_device_deassert_intx(PCIDevice *dev) static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg) { - MemTxAttrs attrs = {}; - - attrs.requester_id = pci_requester_id(dev); + MemTxAttrs attrs = MEMTXATTRS_PCI(dev); address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, attrs, NULL); } From patchwork Fri Nov 11 18:25:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623755 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp956983pvb; Fri, 11 Nov 2022 10:27:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf5n49Yt/Bg171MTJa/0grKV1SG/kWarNbakIKtPg6me2qTDKzETrDctTx8mdDUwOlMils9e X-Received: by 2002:a05:620a:2588:b0:6fa:2081:cbef with SMTP id x8-20020a05620a258800b006fa2081cbefmr2187582qko.66.1668191274947; Fri, 11 Nov 2022 10:27:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191274; cv=none; d=google.com; s=arc-20160816; b=DBMfY7AxvdqFvu3Cz82aTnXrc5OCSWTwQlVTNKzV1Vc7Nw1R01C4KYaS2hU6F951Js nDSejDqDXAgSa0lsFxEDp2I+42VqRkS1+4dLmWnAyUM1olqmpd0n3/zJgWWIib3EbTP5 xvuvAyLtxX7GBdgm324b7dlHnt9F7ric/0jJQB8wQPgl7yPS5dcLGVk1+nz9k8LmSxpl gJVTQcRCQlHN4FhneOXefqaTorUL9SIcwCSOeuGb+WeO+B7+2CXXx9d8J3SqnIWX19Pp /RLhFIWWipqZ9h97dVnI0BbxgSIwaWnNtyzvUzcuGGHYleYaGEyeqDyZnyM0wJCj7agO oMAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yY8gyIcqdeUzmVMf2hGXZI0D0ZNZAMDajQW2IAWcs9k=; b=uYDmVOGsdwAnXltFzTIKq4xaX9EQ0IfXdz9a2HH8pqZvkkv86agn6b0npzkjjjdQ1W FQdH6ioi3KkXOoSV+G77ZZ2pWX6RyDTEx86PJkXyQR/CdfckN6rr2PjTcjoOQiJ/mMBu 6FY45Fd2RhnkfEfQfW1TheMfN+9HDdx14ySHCN2YS6m5AQHjTW1DIc7Uk7KgGjXDkCKT 74of2rMMjhXaIQo9jNQfFteQnkQj/UA9gjupSzQmKn6W3v6RAuk/4riGSNPfrJ6njPLh JXypanxDu6CzCSp8xlAMH2bNr5NML1xuNbZyZ5tymQ4C7G9oeiaVpZsLgfX0wRPSIK+k hZyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GcI1a7EI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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As these are all by definition CPU accesses we can also set the requested_type/index as appropriate. We also have to handle where the attributes are totally reset if we call into get_phys_addr_twostage. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v3 - reword commit summary v5 - fix for new *result ABI - use MEMTXATTRS_CPU to fill in the initial values - also reset attrs in get_phys_addr_twostage --- target/arm/ptw.c | 3 ++- target/arm/tlb_helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3745ac9723..4b6683f90d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2634,6 +2634,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, s1_lgpgsz = result->f.lg_page_size; cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); + result->f.attrs = MEMTXATTRS_CPU(env_cpu(env)); ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi); fi->s2addr = ipa; @@ -2872,7 +2873,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, .in_secure = arm_is_secure(env), .in_debug = true, }; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; bool ret; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 0f4f4fc809..5960269421 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -208,7 +208,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo local_fi, *fi; int ret; From patchwork Fri Nov 11 18:25:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623749 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp956528pvb; Fri, 11 Nov 2022 10:26:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf5m9WPp1o6rk9JG17SRZ/lrjNXoZgwlW6PgpuvtjNXlZDMfGru7lCMmjjbyOnQabbakYCHc X-Received: by 2002:ad4:518e:0:b0:4bb:9feb:9204 with SMTP id b14-20020ad4518e000000b004bb9feb9204mr2958115qvp.74.1668191215725; Fri, 11 Nov 2022 10:26:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191215; cv=none; d=google.com; s=arc-20160816; b=04afScZ0IQ6DV4CEarrRw8mO/DklTGnGwUkmZep2JV9aNhgzEP9c7WSJQ2GsJh3INI jTpY6Si7vobwthAfFroEFoW8UICkZmu2wm3zmTc1R2Xs3P1Z5i60p6UQcZZoKJfJ5xXy R/EX5qQYDMAXg1fVg4uS9sW7fDDayz4yUVJfknqcHfx2jw6iluUMDZvSP/6fJgc/Q3+f b7Lxg0npCGfGfWCpPalA2vq48dIDGcZqbX9JijivVknp4AWt9H1D52MTieHnkgO3/s05 k7xFdLCMD9k72JKSDnOlq0jK4zFKV5hBGg3zJ4qer9AFkEunzqzLUNHJ6eqonpWhMh1q SxEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yRiOg7bg8oS8kaYUc50xaOLL3jm/f2eXWCl+zuHDC2s=; b=gg+l8btBvM35bQoQdLFwHBNIepOBQXhe5doXxrL4N4NxQMaM/OMUq/hrop9V4y89wr e6d5PbvC+mRglaXTQVtNW5IQVi+WfLgPvb2y89hT4sB5XIHSU5BySovT4m4K0LKJV/2g F6Wi6puG1jMo5tHUHR0ktREnZg33B5/TDijIrOFwdJ3F0APQjFdorz42ZoR6s1E48Y3I NS8taLD28r9HJSfZhMeu/40/bNXuJeqt7u9NvY8dtL6qnG87mhfwyCHAnq/8n+7MoeJ9 hjQmnLUAtcU9XPC0mGWZKiBXywOoh066zc6zZk6EUgVyCB5dxZd47qKkzlTCOIerd0+w NDhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=id7utgly; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q6-20020a05620a0d8600b006ee83d2fe45si1503968qkl.158.2022.11.11.10.26.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Nov 2022 10:26:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=id7utgly; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otYio-00082C-94; Fri, 11 Nov 2022 13:25:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otYil-00080Q-Vc for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:44 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otYij-0005Ev-83 for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:43 -0500 Received: by mail-wr1-x430.google.com with SMTP id v1so7471953wrt.11 for ; Fri, 11 Nov 2022 10:25:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yRiOg7bg8oS8kaYUc50xaOLL3jm/f2eXWCl+zuHDC2s=; b=id7utgly0WQbUninVCOnLgxd/TcwkyrRfiZ/OerQyzTwXl38i82MjTJ/qm79pPpKxK EW+z/Ibvx6TzEL9DAzcf0Nk8nf5RywE1k/07J6T3uLIdnLvZIM59ODi4TyyLcAIWiK52 HmJMpv01Agsw9xTs4sOBOPzQQujEoy6gJJAz5dnds2H76GA/tlodRanJFUgeRwVuIBLC CHZMym90Cft7RqHDHSVBTqZCfij4O2MdLqzmFhTfQdYC/b1EJ+p7Ww/gQurP80VI1C8u k6uNrBQ7A/sG+fYbrEiBZIHBA4wD8Fw03l7hNy3QJdcsEq1D9aIXEYmcXcslwbv9Dmyr YUAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yRiOg7bg8oS8kaYUc50xaOLL3jm/f2eXWCl+zuHDC2s=; b=EbMjHuXHAG/VkkMqx5pSgdi5v8is1vBXGZSj4tLT7r5H0JLLGBBljDeQ5lMd1WkwzO PZdiHiQ6Nk4WSFNmz7IEKl9crkkWlVvaPImHi0yBRw7Y0dERI1Hl6VMo+cVYWXe4itZh KHCC3hoWE3Y90zfRwsqFXpvu4XB6vXjP+ulUC2763L9uUJtgvbDyAy26XK86yi3nMrN9 WFhcm5MhzI9Z0GOuF7D0Js4bRBQN13oOte9rpFUfRXN04bDrTV1EbCFFrSQvzt+rmpaY +Zim0VG+9t7IAwV+ICkw68bUbAjNexsxWNuGnDRk2lWo97nP0NKyamiLLpc05sY8XxIN T/BQ== X-Gm-Message-State: ANoB5plv0fspbDOTpbcFbcuG3cE1ut4D3nNH5uqFg/IMwJ5NzXoQtNhX yHLEHrafEV5lT7w9uynu6Z2qJA== X-Received: by 2002:a5d:45d0:0:b0:238:3d2a:cd12 with SMTP id b16-20020a5d45d0000000b002383d2acd12mr2016487wrs.172.1668191137779; Fri, 11 Nov 2022 10:25:37 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id t67-20020a1c4646000000b003cfa622a18asm9443469wma.3.2022.11.11.10.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 10:25:36 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E4CFE1FFBB; Fri, 11 Nov 2022 18:25:35 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Mads Ynddal , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v5 03/20] target/arm: ensure HVF traps set appropriate MemTxAttrs Date: Fri, 11 Nov 2022 18:25:18 +0000 Message-Id: <20221111182535.64844-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As most HVF devices are done purely in software we need to make sure we properly encode the source CPU in MemTxAttrs. This will allow the device emulations to use those attributes rather than relying on current_cpu (although current_cpu will still be correct in this case). Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Mads Ynddal Acked-by: Alexander Graf --- v2 - update MEMTXATTRS macro v5 - more tags --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 060aa0ccf4..d81fbbb2df 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1233,11 +1233,11 @@ int hvf_vcpu_exec(CPUState *cpu) val = hvf_get_reg(cpu, srt); address_space_write(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu), &val, len); } else { address_space_read(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu), &val, len); hvf_set_reg(cpu, srt, val); } From patchwork Fri Nov 11 18:25:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623750 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp956529pvb; Fri, 11 Nov 2022 10:26:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf7v90m5C2dRr1SQeDVEG1BIHUVuto+l8K9BvTcW/94Rxv97GTZVoHVx67AAxymUPIB69Lb0 X-Received: by 2002:ac8:4e03:0:b0:3a5:d46:507f with SMTP id c3-20020ac84e03000000b003a50d46507fmr2468662qtw.538.1668191215732; Fri, 11 Nov 2022 10:26:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191215; cv=none; d=google.com; s=arc-20160816; b=jcqZkluaUIh/iW3JtpxSvRWcmv/o81x3iU9veF7uDMpgjlnL0bkXouUfE1s7osNV0X DzshTMotPGn8HEPtLBGIehb51F/3qt4AkE+kLT1ti+MPbxqMYCdHeIsSB+geIPxwUsvA 0YWDww8xLjghk9faEoJazURRCbM+GygVOOGLFhbNbJTJk6ZsWWoADYrMca4U+Mu8sqcO 7chrGamoex2NCtrIWywGqSXEU2E+GLna/Q4N/P8edpYofoxDWMVpGj+48vQ6ILYIdnXu LMmCZAxcmfHQ4sLXzo+QhNx3M3jjJ5LDt3XVtmxRPj8fmKcVtkmT81wYp5WslIKjGlwZ Rxbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=G49Mn+39h2vPHN4AzQaatrKwexURVZpgkUVTRaS+5Pc=; b=xXeMCAeOFlRT21dXvYuwjSalAyCPb2TIg4jGzRAz68syXzEKM55UTEOWPe9LZi5EdW ejU8UHKRoIqWsF9V6TsrCUvhvQokRWW2h5NcQtGL8jbzYoe90A7eAunjk3Jg6n7DeDnO vvrWRjXrBsDqJTW8UnuFta+WbRqScvyAFqvOOc2/qz4Urs5eejsPmZDwXBKT7YorsMBZ XCtoXxJQ1mrWaIx0Y3T+GjuS3TUAFMkInWhRces1nE3mf2jYHrvmmBvnVM8pEpR5s5CP lAbgtvnMNHt4UkonpniJL0WtvJ46jqyyWJupdNywmj2hhJlUpaiKF/y4xEehAviPY71P AbXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WB/wwEOI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u3-20020a05622a17c300b003a5214d70d2si1439659qtk.423.2022.11.11.10.26.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Nov 2022 10:26:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WB/wwEOI"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otYip-00083X-Mn; Fri, 11 Nov 2022 13:25:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otYin-00081D-Hy for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:45 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otYij-0005FH-9e for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:45 -0500 Received: by mail-wr1-x429.google.com with SMTP id h9so7561652wrt.0 for ; Fri, 11 Nov 2022 10:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G49Mn+39h2vPHN4AzQaatrKwexURVZpgkUVTRaS+5Pc=; b=WB/wwEOIACBjbBhKnyfseiSz3pDcL9oZTsaYCULkUqK3NEvW0UQwVPMxFjZ6EBZLBa epcz/PYPc+SWbDx2qfiyXulkJo0Tmc6G0c4IEY52tTo7MF7SL/hTwoQn1pyR3J7pHu6K 12gNv78rx8nYNn6Xhlnm0u+lsZ9P4GNJ8g2ohlNkDb1Z553J2IqQOLizgZmzkYCx5b9v OPg7jOUuOgzbd4GyUJ0DDJ4Y9M7+lQoYivaRYQAtt9MPVrl7pXdoMAHvBe77mMwzsRaB b11UK9xHiz8WTKIxB4ZaapVY7+7CYkn2rLnQ6fQ5a5wwXeTYDEVi45qMMACsMWYMbE58 X1QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G49Mn+39h2vPHN4AzQaatrKwexURVZpgkUVTRaS+5Pc=; b=CjFFFM+gp9+D4SOkg+lCOe57TASp2AG6gOWRGYDpghbsAsaoqsBfwIOUaxtJbglOWz lWCGXtVApgiNjSiYoVqUnSAoKEPNCfiEyAxdWklCi2QR/UDxn+xsgooUq6CP4dG303YW lVvpVsg8YRGkDMHMJSnupjybBN3BhTE14GdeF5kPbAP5ANEUVShwID0V5NL7KCyXIq2O 9G7dnsha/9KfJulezPD8ZxcbNdb7InVjxIIq5b2ems4l40QwQo3NVzcp7Ik4odkqoeK2 naaMjGSWICeV+Do5TbedYPyd+7dZVQiy6smluiP7/lJRlfVqzrsHkTrlzeP3ejPj3vnm Fnag== X-Gm-Message-State: ANoB5pk4MDbcenvrUd5xmDp8gQOrTt+jCPOqtqhsJpgrcBSMeDIm3lzq jCaE6gmXrb8SyQ9erWyuOp3SWd0ijVoFLg== X-Received: by 2002:adf:ea4d:0:b0:236:8fa1:47cf with SMTP id j13-20020adfea4d000000b002368fa147cfmr2101859wrn.50.1668191139036; Fri, 11 Nov 2022 10:25:39 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id n7-20020adffe07000000b002366f9bd717sm2921843wrr.45.2022.11.11.10.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 10:25:37 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0B9BF1FFBC; Fri, 11 Nov 2022 18:25:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Peter Maydell , Paolo Bonzini , qemu-arm@nongnu.org (open list:ARM KVM CPUs), kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v5 04/20] target/arm: ensure KVM traps set appropriate MemTxAttrs Date: Fri, 11 Nov 2022 18:25:19 +0000 Message-Id: <20221111182535.64844-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Although most KVM users will use the in-kernel GIC emulation it is perfectly possible not to. In this case we need to ensure the MemTxAttrs are correctly populated so the GIC can divine the source CPU of the operation. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v3 - new for v3 v5 - tags - use MEMTXATTRS_PCI --- target/arm/kvm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f022c644d2..bb4cdbfbd5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -803,13 +803,14 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) { ARMCPU *cpu; uint32_t switched_level; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); if (kvm_irqchip_in_kernel()) { /* * We only need to sync timer states with user-space interrupt * controllers, so return early and save cycles if we don't. */ - return MEMTXATTRS_UNSPECIFIED; + return attrs; } cpu = ARM_CPU(cs); @@ -850,7 +851,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) qemu_mutex_unlock_iothread(); } - return MEMTXATTRS_UNSPECIFIED; + return attrs; } void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) @@ -1005,6 +1006,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, hwaddr xlat, len, doorbell_gpa; MemoryRegionSection mrs; MemoryRegion *mr; + MemTxAttrs attrs = MEMTXATTRS_PCI(dev); if (as == &address_space_memory) { return 0; @@ -1014,8 +1016,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, RCU_READ_LOCK_GUARD(); - mr = address_space_translate(as, address, &xlat, &len, true, - MEMTXATTRS_UNSPECIFIED); + mr = address_space_translate(as, address, &xlat, &len, true, attrs); if (!mr) { return 1; From patchwork Fri Nov 11 18:25:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623752 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp956775pvb; Fri, 11 Nov 2022 10:27:24 -0800 (PST) X-Google-Smtp-Source: AA0mqf514ZIphwtkyZZF1CqqlJALTV9Qp21au3JUHYjx2Qc3+KhH7+nKH7LFRSlHd8cw1pTkUX/f X-Received: by 2002:ac8:5796:0:b0:3a5:2a53:bba2 with SMTP id v22-20020ac85796000000b003a52a53bba2mr2498090qta.406.1668191244735; Fri, 11 Nov 2022 10:27:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191244; cv=none; d=google.com; s=arc-20160816; b=T2ExZm8byu5XQ0wBCgJ1+gAFNh8A+R46PzB6n4ewvTwR3AiGCQoSoG50P4koND1fSi okNreypSR1nExitqXn4pzdxNoyMk2Jil0KhxKqaBTswBYUbg9fj3Fd8hn8jGlcGge/7C YLLdqZ9ZDftd1NHUmGu+hULt7Elbej7qAUvgT/8otUeM6neuKXQngeCDZ0gvgopTBYRk yUqFjYGbCnRWjxRFSOMhiTNHp7d1aQDBj71qu4KqoeonW8ifl87n1jKs0owopRq+7bRl s3T8ZX4AxtGYGcWDw5JHqfoT+4DlyrrtZ/FWcr5nYrZLzaBjZOgDdxQzkfF+6SYpN8mt aJYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dnKrKEY1uLyQf2qXKEQwvTPUiYfi6aVs4dXdbcR/wWc=; b=Lh3gdOazP0shhTgQJLLE7H9shO9eS4uE2BrxpzlvMk1L8IKg6Vtva3AjN4N4cx2PJo Dl6RselvpR7oTsGoT+sQuzh4EvG+IK8kHMksVFWUfH839xmKzryucVpyt19QBwSwe0Vi gJF+8BeuKtxT9DCbqcpN6hnBBfkNakgiYoKHTW9fLrokkwPhL3cDeeuj/sATc/xgZAAr /UZzkIsj3eWPGWfZUe7qIX5wjseAoWOrfnKHVMVgdHe0M/Wx0IPmrGVG5teI4R2GsMH8 oHZnIeXVuM/KfCzWNtMuGZrsUh3tGMlkSA0Yv76gVUZzQYU6J2mCzP/3e0bIhpNkwRC7 rsSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FYLJBbYR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id fe4-20020a05622a4d4400b003a4f0c53ab1si1433071qtb.727.2022.11.11.10.27.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Nov 2022 10:27:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FYLJBbYR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otYip-00083o-Sl; Fri, 11 Nov 2022 13:25:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otYin-00081M-I8 for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:45 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otYij-0005FO-9f for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:45 -0500 Received: by mail-wr1-x42a.google.com with SMTP id w14so7487410wru.8 for ; Fri, 11 Nov 2022 10:25:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dnKrKEY1uLyQf2qXKEQwvTPUiYfi6aVs4dXdbcR/wWc=; b=FYLJBbYRqzKlFJ87eihxA+mx9Vk2O8F0L5bkxpfEMsqJvTWGMpjzXAAOTWk8xxq9cA d6blwBV8UwlwjDkLmxaQpUqUjCM4g2pCvCnxHAMb06V+CuTikEFTgHLsYrjzQ+KXr69d P/h3Re9m6SObv02o8PsgAYuD5capryBOAMOM7ERTI0Bhnj4vKSzRFo3hdfHjJ4HpvKbG Gdhr1nF1MYhMpI9DGp3mnqNFMpgPNKyuGkG3T1zPRbcO2YZC+KcjmYWk2HLSUDFSbU9z ptd2QQ3sOhIq4Mm+2XGkaGf09YwbZfr3CZNKgV33j2/B6s6TAg3kf9OApEt78rMaHBFF RBkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dnKrKEY1uLyQf2qXKEQwvTPUiYfi6aVs4dXdbcR/wWc=; b=K/gplTKMME6SrcRgLJe7YsLT0h/5+bSH2XgBLEdQBOMlGI82I9dwgiBu7pqoQrsZrp QTMR6zWXca4YrqKQrJ7OrQp+mxymqN9gNR/R8QsDfrrAWCKV0knmtXm9+XqFXsR/6zXx FHAvds4HT8GTyk+ibcY7K+djUHhF2KJw4hDoiW3lAksMq9U2yOvwgk/zyOWtWJ2JQ8Ub SMhDvisdEfJABrI2eGY+hubZ4ju0ZcA1aWPj2BqALtz4bCVLUx9s3h3kpcviQaHr9aKJ p4Oa9N7gLvLZXh5oLDHPcCnfujEkKKs3XvBdpj6Vg72dTOAZFtvHcAwF9sDeL3k3NHcc 5ghQ== X-Gm-Message-State: ANoB5plShgixPIfrHxQygmXDCvkUou0DUZpCFvoEvckNa6L3kFL7FYCd nk4ibb6lCzYBMU77iZk8kjedLg== X-Received: by 2002:adf:ff85:0:b0:235:c5de:75c3 with SMTP id j5-20020adfff85000000b00235c5de75c3mr1967895wrr.285.1668191139613; Fri, 11 Nov 2022 10:25:39 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id p25-20020a05600c1d9900b003c64c186206sm3651008wms.16.2022.11.11.10.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 10:25:38 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 233261FFBD; Fri, 11 Nov 2022 18:25:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v5 05/20] target/arm: ensure m-profile helpers set appropriate MemTxAttrs Date: Fri, 11 Nov 2022 18:25:20 +0000 Message-Id: <20221111182535.64844-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There are a number of helpers for M-profile that deal with CPU initiated access to the vector and stack areas. While it is unlikely these coincided with memory mapped IO devices it is not inconceivable. Embedded targets tend to attract all sorts of interesting code and for completeness we should tag the transaction appropriately. Signed-off-by: Alex Bennée --- v5 - rebase fixes for refactoring --- target/arm/m_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 355cd4d60a..2fb1ef95cd 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -184,7 +184,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult txres; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; bool secure = mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -272,7 +272,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult txres; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; bool secure = mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -665,7 +665,7 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, MemTxResult result; uint32_t addr = env->v7m.vecbase[targets_secure] + exc * 4; uint32_t vector_entry; - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); ARMMMUIdx mmu_idx; bool exc_secure; @@ -1999,7 +1999,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; V8M_SAttributes sattrs = {}; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; MemTxResult txres; @@ -2047,7 +2047,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; MemTxResult txres; - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi = {}; uint32_t value; @@ -2805,7 +2805,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) != 0 || alt) { - GetPhysAddrResult res = {}; + GetPhysAddrResult res = { .f.attrs = MEMTXATTRS_CPU(env_cpu(env)) }; ARMMMUFaultInfo fi = {}; /* We can ignore the return value as prot is always set */ From patchwork Fri Nov 11 18:25:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623754 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp956912pvb; Fri, 11 Nov 2022 10:27:47 -0800 (PST) X-Google-Smtp-Source: AA0mqf54LD29SZJ6va40SM6YvBCoVwWkAhA1DFM+8jMU5Tx+o/xVC5++4O8CKu6xkk9MDlEERK3R X-Received: by 2002:a37:6c04:0:b0:6fa:65dd:814b with SMTP id h4-20020a376c04000000b006fa65dd814bmr2144128qkc.757.1668191267739; Fri, 11 Nov 2022 10:27:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191267; cv=none; d=google.com; s=arc-20160816; b=q3ubZHimKWrgn6cDEF1CA+Zz1IjxWiRi9vw3lDZrxxaAHFug14UnjhEnxzT0qKwapM 6SR4oJsA2A477+ud/NFwRWS+c1W9a9lqS+NvyQN4IK2uPxqSrOapkK1JiPsbQ/Otrpw6 N6t0Ru1VMd4WqrqOBAFPq4eVaEh+SV75+ObIOsLL/ZZJ59dNRz8EBI9mfUbNmRQuCBIH MySHsF+vO5QpRcj/UbIZ93Fa2uWb0ZybvarFHkCFIospOmMJVgZggHjAqiEnJktK4OSb UIHlhx0cc5uXGvApHsbmCo5q3TpE9Lr8jdF20IKIb4v+YzkL2uhymaV3/2DtE4M/jkk9 aubA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sZTswvbms0KUj8W6VozmeTx2aCc51iOLIgIJjYfUOE0=; b=hSo8r3z1iZNOhANxSV44/xBM3S4f8eId4JZtQtA/6GAbTtDhL8pr52KBJ2zLwloCEU s25pHO5IQYfYwmM39YpL8MswIk75k4waWF5nlXXbO0YcvjO9k2pW5UkRNO1ldhUfTN6n q3Bg/amYYI/6HffV6CljDd5APrlpRp6ix5u8opziOT1+gQn18YflGk7+8R66DEHMYY00 7BlZawzpcsLtcEeQmFsXkc5D98TRQ5S87SF5rAn8VQ/7yhwsa7HWv3pIHj2e3mE1E6wt O/qszs6IJo3/Nrnk4jI+VQifzUqknJhztSM9F2N5Wg38fU43uYjt+9WGBnRLTqbgDaH1 iubg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cp+zbzcB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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However because it's not a real system we have places in the code which especially handle check qtest_enabled() before referencing current_cpu. Now we can encode these details in the MemTxAttrs lets do that so we can start removing them. Reviewed-by: Richard Henderson Acked-by: Thomas Huth Signed-off-by: Alex Bennée --- v2 - use a common macro instead of specific MEMTXATTRS_QTEST v3 - macro moved to earlier patch --- softmmu/qtest.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index d3e0ab4eda..5e9ac234ce 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][5] == 'b') { uint8_t data = value; - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 1); } else if (words[0][5] == 'w') { uint16_t data = value; tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 2); } else if (words[0][5] == 'l') { uint32_t data = value; tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 4); } else if (words[0][5] == 'q') { uint64_t data = value; tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 8); } qtest_send_prefix(chr); @@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][4] == 'b') { uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 1); value = data; } else if (words[0][4] == 'w') { uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 2); value = tswap16(data); } else if (words[0][4] == 'l') { uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &data, 4); value = tswap32(data); } else if (words[0][4] == 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), &value, 8); tswap64s(&value); } @@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(len); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); enc = g_malloc(2 * len + 1); @@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(ret == 0); data = g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); b64_data = g_base64_encode(data, len); qtest_send_prefix(chr); @@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) data[i] = 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); g_free(data); @@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (len) { data = g_malloc(len); memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); g_free(data); } @@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words) out_len = MIN(out_len, len); } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu), data, len); qtest_send_prefix(chr); From patchwork Fri Nov 11 18:25:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623762 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp959528pvb; Fri, 11 Nov 2022 10:32:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf54DvlVp/Y9P3zmofvecIIDWNnibmusz34UeU0fowYBhr5qDxtQfppm9FtHFDxlW5bY9Tcw X-Received: by 2002:a05:620a:cec:b0:6fa:9a8b:1 with SMTP id c12-20020a05620a0cec00b006fa9a8b0001mr2118030qkj.207.1668191566474; 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This solves edge cases like accessing via gdbstub or qtest. As we should only be processing accesses from CPU cores we can push the CPU extraction logic out to the main access functions. If the access does not come from a CPU we log it and fail the transaction with MEMTX_ACCESS_ERROR. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 --- v2 - update for new field - bool asserts v3 - fail non-CPU transactions v5 - split gic_valid_cpu from gic_get_current_cpu and use this - fix dud return false from gic_valid_cpu() --- hw/intc/arm_gic.c | 159 +++++++++++++++++++++++++++++----------------- 1 file changed, 102 insertions(+), 57 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 65b1ef7151..62f36b247f 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,38 @@ static const uint8_t gic_id_gicv2[] = { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -static inline int gic_get_current_cpu(GICState *s) + +/* + * The GIC should only be accessed by the CPU so if it is not we + * should fail the transaction (it would either be a bug in how we've + * wired stuff up, a limitation of the translator or the guest doing + * something weird like programming a DMA master to write to the MMIO + * region). + * + * Note the cpu_index is global and we currently don't have any models + * with multiple SoC's with different CPUs. However if we did we would + * need to transform the cpu_index into the socket core. + */ + +static bool gic_valid_cpu(MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; + if (attrs.requester_type != MTRT_CPU) { + qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR, + "%s: saw non-CPU transaction", __func__); + return false; } - return 0; + return true; +} + +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) +{ + g_assert(attrs.requester_id < s->num_cpu); + return attrs.requester_id; } -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } /* Return true if this GIC config has interrupt groups, which is @@ -945,17 +966,14 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) * Although this is named a byte read we don't always return bytes and * rely on the calling function oring bits together. */ -static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) +static uint32_t gic_dist_readb(GICState *s, int cpu, hwaddr offset, MemTxAttrs attrs) { - GICState *s = (GICState *)opaque; uint32_t res; int irq; int i; - int cpu; int cm; int mask; - cpu = gic_get_current_cpu(s); cm = 1 << cpu; if (offset < 0x100) { if (offset < 0xc) { @@ -1168,19 +1186,27 @@ bad_reg: static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, unsigned size, MemTxAttrs attrs) { + GICState *s = (GICState *)opaque; + int cpu; + + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + cpu = gic_get_current_cpu(s, attrs); + switch (size) { case 1: - *data = gic_dist_readb(opaque, offset, attrs); + *data = gic_dist_readb(s, cpu, offset, attrs); break; case 2: - *data = gic_dist_readb(opaque, offset, attrs); - *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; + *data = gic_dist_readb(s, cpu, offset, attrs); + *data |= gic_dist_readb(s, cpu, offset + 1, attrs) << 8; break; case 4: - *data = gic_dist_readb(opaque, offset, attrs); - *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8; - *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16; - *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24; + *data = gic_dist_readb(s, cpu, offset, attrs); + *data |= gic_dist_readb(s, cpu, offset + 1, attrs) << 8; + *data |= gic_dist_readb(s, cpu, offset + 2, attrs) << 16; + *data |= gic_dist_readb(s, cpu, offset + 3, attrs) << 24; break; default: return MEMTX_ERROR; @@ -1190,15 +1216,12 @@ static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data, return MEMTX_OK; } -static void gic_dist_writeb(void *opaque, hwaddr offset, +static void gic_dist_writeb(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - GICState *s = (GICState *)opaque; int irq; int i; - int cpu; - cpu = gic_get_current_cpu(s); if (offset < 0x100) { if (offset == 0) { if (s->security_extn && !attrs.secure) { @@ -1475,24 +1498,21 @@ bad_reg: "gic_dist_writeb: Bad offset %x\n", (int)offset); } -static void gic_dist_writew(void *opaque, hwaddr offset, +static void gic_dist_writew(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - gic_dist_writeb(opaque, offset, value & 0xff, attrs); - gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); + gic_dist_writeb(s, cpu, offset, value & 0xff, attrs); + gic_dist_writeb(s, cpu, offset + 1, value >> 8, attrs); } -static void gic_dist_writel(void *opaque, hwaddr offset, +static void gic_dist_writel(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - GICState *s = (GICState *)opaque; if (offset == 0xf00) { - int cpu; int irq; int mask; int target_cpu; - cpu = gic_get_current_cpu(s); irq = value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1519,24 +1539,32 @@ static void gic_dist_writel(void *opaque, hwaddr offset, gic_update(s); return; } - gic_dist_writew(opaque, offset, value & 0xffff, attrs); - gic_dist_writew(opaque, offset + 2, value >> 16, attrs); + gic_dist_writew(s, cpu, offset, value & 0xffff, attrs); + gic_dist_writew(s, cpu, offset + 2, value >> 16, attrs); } static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs) { + GICState *s = (GICState *)opaque; + int cpu; + + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + cpu = gic_get_current_cpu(s, attrs); + trace_gic_dist_write(offset, size, data); switch (size) { case 1: - gic_dist_writeb(opaque, offset, data, attrs); + gic_dist_writeb(s, cpu, offset, data, attrs); return MEMTX_OK; case 2: - gic_dist_writew(opaque, offset, data, attrs); + gic_dist_writew(s, cpu, offset, data, attrs); return MEMTX_OK; case 4: - gic_dist_writel(opaque, offset, data, attrs); + gic_dist_writel(s, cpu, offset, data, attrs); return MEMTX_OK; default: return MEMTX_ERROR; @@ -1796,7 +1824,10 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1804,7 +1835,10 @@ static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1833,8 +1867,10 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1842,8 +1878,10 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, attrs); } static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1874,9 +1912,8 @@ static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) return ret; } -static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) +static void gic_vmcr_write(GICState *s, int vcpu, uint32_t value, MemTxAttrs attrs) { - int vcpu = gic_get_current_vcpu(s); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1893,11 +1930,10 @@ static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) gic_set_priority_mask(s, vcpu, prio_mask, attrs); } -static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, +static MemTxResult gic_hyp_read(GICState *s, int cpu, hwaddr addr, uint64_t *data, MemTxAttrs attrs) { - GICState *s = ARM_GIC(opaque); - int vcpu = cpu + GIC_NCPU; + int vcpu = gic_get_current_vcpu(s, attrs); switch (addr) { case A_GICH_HCR: /* Hypervisor Control */ @@ -1961,11 +1997,10 @@ static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, return MEMTX_OK; } -static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, +static MemTxResult gic_hyp_write(GICState *s, int cpu, hwaddr addr, uint64_t value, MemTxAttrs attrs) { - GICState *s = ARM_GIC(opaque); - int vcpu = cpu + GIC_NCPU; + int vcpu = gic_get_current_vcpu(s, attrs); trace_gic_hyp_write(addr, value); @@ -1975,12 +2010,13 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, break; case A_GICH_VMCR: /* Virtual Machine Control */ - gic_vmcr_write(s, value, attrs); + gic_vmcr_write(s, vcpu, value, attrs); break; case A_GICH_APR: /* Active Priorities */ s->h_apr[cpu] = value; - s->running_priority[vcpu] = gic_get_prio_from_apr_bits(s, vcpu); + s->running_priority[vcpu] = + gic_get_prio_from_apr_bits(s, vcpu); break; case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ @@ -2007,20 +2043,24 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, } static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *data, - unsigned size, MemTxAttrs attrs) + unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) + uint64_t value, unsigned size, + MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, @@ -2029,6 +2069,9 @@ static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data, GICState **backref = (GICState **)opaque; GICState *s = *backref; int id = (backref - s->backref); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } return gic_hyp_read(s, id, addr, data, attrs); } @@ -2040,9 +2083,11 @@ static MemTxResult gic_do_hyp_write(void *opaque, hwaddr addr, GICState **backref = (GICState **)opaque; GICState *s = *backref; int id = (backref - s->backref); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } return gic_hyp_write(s, id + GIC_NCPU, addr, value, attrs); - } static const MemoryRegionOps gic_ops[2] = { From patchwork Fri Nov 11 18:25:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623753 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp956793pvb; Fri, 11 Nov 2022 10:27:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf7gtKDdnPajS1SjTcFED29FhPxphdDC2xnhbSQujhHlCOA2zVtHjLftecPBw1mS5lgWMl2J X-Received: by 2002:a37:a4e:0:b0:6fa:16f2:7f58 with SMTP id 75-20020a370a4e000000b006fa16f27f58mr2105525qkk.204.1668191247775; Fri, 11 Nov 2022 10:27:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191247; cv=none; d=google.com; s=arc-20160816; b=M5j8XYP/4BhxFUd8iX5kLlu5BwtZsQ3sSoa/VZjs85hZLz6rp2C/E/CdQQL3THyqqO k1WeKbeW+SlJfNmqMxiMDVRBFUxDfS050HKm/OaLun2igBkXUrwvBCQvFcYBkV384L4m WWx9GNHPkgAAQVnocoQrPQRLsZXc3oPgtmZCiw5LKGl8xsDiXpdxnwxz/BsdfNt5RNBV hCJAjBHz6t/1TMtC1oPKFY8Hwj1NQzxVv5G1Ekuq97Pzjcy3PqZNfDPZb5B+yYRxFQN8 2In7X7MhSWFYNYXBQu+YwHUsUyMCHmP1Vi7uZu1yQVw4RPgFsdhGLI0sa1AUIkMbxuRm otYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=y1oPa43v+0HZaP362mwFJPM6SRKSInCeIyiDIAZ7nyM=; b=uPtlfqbUq0QOQ73TSpg/sm/S0tttriWx5CWh0UMQzuhKNGGbd4Q/CN8PLxUDbnF06x c0f4t5Zv6kay0/H/1Nmq/8EchcVQ4mcAoQvSw61UYIftS1QQCriYfsGBA0cEq8I8aSkD g64aNU+tjWQ1mvc6PzqKLQZJUDapSEORLroZqAiph4A77pb3Izoh+7mdCOY92j4UxH+P ISYTrq7kITPX4uM3Ptlv7DiCKXj3HqfjUnbR2vWT/n6X/DLlcRG0A50kL9mvKCPkPDtE dn5r+9HwxYt73NPHc0HmBBXkwiJmKKJocX2BCM1vH2eiz4T9LKUA2R035oVWIsm6/y7E p0kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WHNtgfOd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- v2 - update for new fields - bool asserts v3 - properly fail memory transactions from non-CPU sources --- hw/timer/arm_mptimer.c | 49 +++++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cdfca3000b..4618779ade 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -28,6 +28,7 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/core/cpu.h" #define PTIMER_POLICY \ @@ -41,15 +42,23 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ -static inline int get_current_cpu(ARMMPTimerState *s) +static bool is_from_cpu(MemTxAttrs attrs) { - int cpu_id = current_cpu ? current_cpu->cpu_index : 0; + if (attrs.requester_type != MTRT_CPU) { + qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR, + "%s: saw non-CPU transaction", __func__); + return false; + } + return true; +} +static int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs) +{ + int cpu_id = attrs.requester_id; if (cpu_id >= s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", s->num_cpu, cpu_id); } - return cpu_id; } @@ -178,25 +187,35 @@ static void timerblock_write(void *opaque, hwaddr addr, /* Wrapper functions to implement the "read timer/watchdog for * the current CPU" memory regions. */ -static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, - unsigned size) +static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { - ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); - return timerblock_read(&s->timerblock[id], addr, size); + if (is_from_cpu(attrs)) { + ARMMPTimerState *s = (ARMMPTimerState *)opaque; + int id = get_current_cpu(s, attrs); + *data = timerblock_read(&s->timerblock[id], addr, size); + return MEMTX_OK; + } else { + return MEMTX_ACCESS_ERROR; + } } -static void arm_thistimer_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, MemTxAttrs attrs) { - ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); - timerblock_write(&s->timerblock[id], addr, value, size); + if (is_from_cpu(attrs)) { + ARMMPTimerState *s = (ARMMPTimerState *)opaque; + int id = get_current_cpu(s, attrs); + timerblock_write(&s->timerblock[id], addr, value, size); + return MEMTX_OK; + } else { + return MEMTX_ACCESS_ERROR; + } } static const MemoryRegionOps arm_thistimer_ops = { - .read = arm_thistimer_read, - .write = arm_thistimer_write, + .read_with_attrs = arm_thistimer_read, + .write_with_attrs = arm_thistimer_write, .valid = { .min_access_size = 4, .max_access_size = 4, From patchwork Fri Nov 11 18:25:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623760 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp958981pvb; Fri, 11 Nov 2022 10:31:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf5+MCWNZleNDKCH9YIqId/mLBxF89dYDmm9DqZScIi7YT2ub5xbPG+a3klJVaZnDxrZ/e7r X-Received: by 2002:a37:bd47:0:b0:6df:923d:13ba with SMTP id n68-20020a37bd47000000b006df923d13bamr2174915qkf.751.1668191502665; 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[209.51.188.17]) by mx.google.com with ESMTPS id cj22-20020a05622a259600b0039cca19804asi1504208qtb.18.2022.11.11.10.31.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Nov 2022 10:31:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=saAec4Ah; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otYix-00087k-Lz; Fri, 11 Nov 2022 13:25:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otYiq-000848-H7 for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:48 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otYil-0005G5-6L for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:48 -0500 Received: by mail-wm1-x32f.google.com with SMTP id v7so3399653wmn.0 for ; Fri, 11 Nov 2022 10:25:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t8IRhutszjP7KcNpe3Rgsdhclavr2Z8wlN87Tg35KU0=; b=saAec4AhXJ9Ngi+mzzbh1wkeLpO8irkzPmrllFG+3Qj6akdEDfDOqPQrk+IRyQ6hMp BMPfIikAFR1GZhB7GbTQ8AEHnI9xppOUMHvmj4ybYa4Oa6b/Lks3rlWx/hTt1KjkZihQ km9jttR8Ox7vbOubLm7Bbtd8VUKaoZEByxemZOMAgL5PIz0eKTrbwxiL9w4W1+YnNFKm 4N+XyE1lhk0fDRENjReB4YB0CyhL5M4FC1AKTpNxMRsVZpzlwQrScudDudv2pZ+SRaYA 7m1+21FhKWAaSeMdRZRtZp1UhmcE+k6a6Y0yww4TQDa6LqXQT84zIkWx/om++i2TB+xl TaaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t8IRhutszjP7KcNpe3Rgsdhclavr2Z8wlN87Tg35KU0=; b=CoMGENILQ794F/6Kn0enC9AFPBBP7OLmjxTYU3W81Dsm9YAs4fPBmDcsiqtjJ1nLkD M+uBmWDdGMdNQpqhN8CCln/nHfehlD8FODLHb/77+9IKzEl72slIjNc5yrlOgSPnsFZn ZJJc+MmaPE0vkSG5WhqZizLVYUWn7YTlqGHLMMRgZdxcq71fOiJh8x9RMy2LBiWpyymC UBW9tP5GYY81hHmvV3EuLIuEwAeaPv+jGO5OCbKM7+dFFiVGsHQ1sRWtJJ9TSBHh4Btl oXkwmmkrDToqN3Jk4BYHrM8AIqhZ6JPNPNfypISlc23d62+5R9clt/26q5HjoRqADL0N Cz3Q== X-Gm-Message-State: ANoB5pnIrI0gLrXh3ew37kKfZEqIQh4jaWzxmFkelwJKQFcXnQ9YjSEv TSpphnERGyxs/IVhuPUBharXCg== X-Received: by 2002:a05:600c:3516:b0:3cf:8952:300c with SMTP id h22-20020a05600c351600b003cf8952300cmr2177458wmq.51.1668191141704; Fri, 11 Nov 2022 10:25:41 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id j8-20020a5d5648000000b002416e383e1csm2289017wrw.25.2022.11.11.10.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 10:25:39 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 88DD61FFC0; Fri, 11 Nov 2022 18:25:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:PXA2XX) Subject: [PATCH v5 09/20] hw/arm: remove current_cpu hack from pxa2xx access Date: Fri, 11 Nov 2022 18:25:24 +0000 Message-Id: <20221111182535.64844-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We can derive the correct CPU from CPUARMState so lets not rely on current_cpu. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 93dda83d7a..065392a8bc 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -319,7 +319,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, #endif /* Suspend */ - cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); goto message; From patchwork Fri Nov 11 18:25:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623769 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp961841pvb; Fri, 11 Nov 2022 10:37:10 -0800 (PST) X-Google-Smtp-Source: AA0mqf6OnepqWVuYH+FhlYS1kH0mhFcOrrd2mB6CteBEPN7bhm6CJbCUfueNQw8hJcVrq5GdZnn2 X-Received: by 2002:a05:6214:2dc7:b0:4bb:754f:e974 with SMTP id nc7-20020a0562142dc700b004bb754fe974mr3101299qvb.2.1668191830371; Fri, 11 Nov 2022 10:37:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191830; cv=none; d=google.com; s=arc-20160816; b=xv/WYwhvjidZtnhKNCHR/6urfZh2BJ4nym4I6YSLfbUK/uGwS5H2xQfpGpzS4w6PP+ rUG29zYWE7TCL4lfs4GhX6hVlj613Dnva+YAVeLmjUwp1YGiqN8c4ryjb7/gk+EOZhcY /CL5V3XLjG11PsCsKESEg8IUSZtGVoTx6xmtsSOcC7R8HKPWAnnIG62qJ6ff0YC+JPPe NRG0KzuOIfWAE5yBzmZwi2YG9/v2UcAi4R6XDE6wsHW9SUzk2lJ+z/gxcjhfW013L90u Lvc26ctklEcyLr8LvlHgrYkKTzfH/bXf+gAQ0OGIfnFbykFUcct+rWn/kDa5cnTdxb2Y UhmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cbpO0AZ4Acrg9xoN2SNVugKcaQMd8HDZpSEMLYorBkM=; b=YHi87bJ70NX0HlGJSzfWuHxHdkiV6ZrP8dhniIDLMCRw8CxBrHkBMxbfGRbgr+vMix Zak/VB/2tm4K8zi8KDiNV82TGG2zMOx7WS52liw3UhKiMuqZqLy5PhoD6dRponoDwWsm 5Ks5hBEc5ey6OBzd8sZHQkZz8P94tYVgueYE1yt9S0XohR3yjVIWYYq9CHIN/pgDTf8b Im631YHNRlCWBdR4OGNXNVTkzy7dAOn/l5KFH7WnghPWk/fLAO/LgU9lLqd0TrrwFSlP o7DUyUHzv4QiQJvWnS4DppOYNgy2GGYMjSfxUKNU2gdHxdBflmu6quLWS0NR6HXyFUYQ 99hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="OOGKyx/0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" Subject: [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access Date: Fri, 11 Nov 2022 18:25:25 +0000 Message-Id: <20221111182535.64844-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both of these functions deal with CPU based access (as is evidenced by the secure check straight after). Use the new MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in should it ever be needed by any devices later. Signed-off-by: Alex Bennée Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..655be3b320 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -44,7 +44,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MicroBlazeMMULookup lu; unsigned int hit; int prot; - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); attrs.secure = mb_cpu_access_is_secure(cpu, access_type); @@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, unsigned int hit; /* Caller doesn't initialize */ - *attrs = (MemTxAttrs) {}; + *attrs = MEMTXATTRS_CPU(cs); attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); if (mmu_idx != MMU_NOMMU_IDX) { From patchwork Fri Nov 11 18:25:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623767 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp961425pvb; Fri, 11 Nov 2022 10:36:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf6lnNR6ZqSL27rHeDxbd8gTJ6IBHgrWAM0gpEuWcdKMoqQhKJiBAqrNhnr4tpaHaBDvjMyd X-Received: by 2002:a05:6214:5652:b0:4bb:5669:fb53 with SMTP id mh18-20020a056214565200b004bb5669fb53mr3045428qvb.84.1668191783111; Fri, 11 Nov 2022 10:36:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191783; cv=none; d=google.com; s=arc-20160816; b=bSww9rLBw7HE7ZEYmak8iB/6SEytzuAutFeRbQ3/ripgiN44uWKwVEG9bQ2BomU8pk GUuCzS8I6RWTWeE1nDzrJAS+Ygawb1k5XhQ52x0m37T5f0rYHznuYkuYM0BxnhpvmX4F 4WzDDab/dujkXjXBNEqIFxnXWocOi7jyQ+wOWaf8R9apKlEvgcbHMPxyFXyDFH4LvE9c feZ+sDgeeSrV6x87l5dC5/8RBSq+yWbpRWC0lLhJrfyrxOvhUCASGKbm40HwZFwWCRAU 9PUnKbRjEG7NjJpDzSY6elNm/E3sNvpLjZwMYsVPBJX5KiullBgQY2EeRffJasaakxRQ kiBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=D4e6Eni3qQrLsasdgaGetPChuPB8kPgudPLx+PRHc34=; b=WGpAWPZf7ioyXuWLeMnn8VAGUDpHSGcpybCjyLM0a6PrmpYUbKBgTBapMjc75ziwxN g9MUZKm40SgzonZktKuAeM1LAxkG7QZaEbFiQmLg6YKQjqOBSSIxq0Dyv8jD6qgekzBu 9y+7Z7Qov8ck27Nie7Mq3sfQPLpCgWRI0fa1AnWvCgLxssASERCId6P3PlYp0xI+95Ar fqNGZ5jzAhP6Hp+KJK+ZHlNOCKpxPtxtq9tmMZ6erOW8HfmsSk1/t+GrwfnZVqTF9iSo sf2z6QJoEqNMakXm4L3kTwGpDaEhNi7V1XPi2rC1VsIa3ZWxNKUZ2AMJZNBtIlVDthPK bTkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GXNd1Dgo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v15-20020ae9e30f000000b006f9f9a3a423si1269686qkf.93.2022.11.11.10.36.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Nov 2022 10:36:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GXNd1Dgo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otYrq-0007oe-6E; Fri, 11 Nov 2022 13:35:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otYrg-0007mg-Aj for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:34:56 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otYre-0007Nu-M2 for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:34:56 -0500 Received: by mail-wr1-x436.google.com with SMTP id k8so7556557wrh.1 for ; Fri, 11 Nov 2022 10:34:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D4e6Eni3qQrLsasdgaGetPChuPB8kPgudPLx+PRHc34=; b=GXNd1DgohE14lgLwodrub+y1G5c+qiajvd6NcQKUQC1iP3bvA2j9n7QtNx4aC6Pp2s vPr49Z1UkB+yH5mN9r7kWTPjcADEDqqBgK9NoMhqZPfkfM/bz1OReTJEOHevXgXliPRK n8Pvcl/XRyAO8HD7jGQT7pfMMQMhtwHu38fXiVajMfMgtgAY3BdjYbDw5700bFor15fK mdV67ag1gGLK1ThBdWsekMpkKf+rGo8vKFAgwgv6bUqv75Fb8/4KRPIQiEJY3nmWRbu5 3e57zO7LYRAgWFqcaUglvUf8YMSIRr3LN9xM3NRrBcIr4Bhd+0vtpF5pYTYYuPlAkTRr FyOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D4e6Eni3qQrLsasdgaGetPChuPB8kPgudPLx+PRHc34=; b=RAjhicrGfn4Bem+/PYjIJuQwFD22mNCC3bQwWi0UrrAEpljTZUDmRa87E4YGTCeYFK 1Zk/Pt+cx1d8ztI1QFudNjkqhBFEKBKSGm1pdGdZTwl/ONBF52ZzmPsC6VNGgRs47Cp0 rusdho4XAHGUjfYdLd3XLQWALiYMN0pf66qqQ9t09FRcUeu5lHLiAWvdDIAAsxLwY4fX mpsTZcM58i4H+LBRwGPC/W/5cQ5ghO7RopQVCTvL+ynQeU8xabuzlie2InEK+aIT2ng9 j2PjUUZpffJw0ogcJEdL9BdaWkPGDefhREc0vnQucFvwkB5CSqwh7ocHPLKQJOsrJJNX /csA== X-Gm-Message-State: ANoB5plDRIXo28oJNDQMt25bkzKU2tvkpDfzvaXKDydSuTvwt6FI1xXx eaGERFF+RHrxooBM0YauqhiGjg== X-Received: by 2002:adf:a3cb:0:b0:22e:4b62:7ca6 with SMTP id m11-20020adfa3cb000000b0022e4b627ca6mr1892051wrb.441.1668191691793; Fri, 11 Nov 2022 10:34:51 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id i9-20020adfefc9000000b00228dbf15072sm2543164wrp.62.2022.11.11.10.34.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 10:34:51 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B8E581FFC2; Fri, 11 Nov 2022 18:25:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v5 11/20] target/sparc: initialise MemTxAttrs for CPU access Date: Fri, 11 Nov 2022 18:25:26 +0000 Message-Id: <20221111182535.64844-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both of the TLB fill functions and the cpu_sparc_get_phys_page deal with CPU based access. Use the new MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in should it ever be needed by any devices later. Signed-off-by: Alex Bennée Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/mmu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 919448a494..eeb52b5ee6 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -212,7 +212,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, target_ulong vaddr; target_ulong page_size; int error_code = 0, prot, access_index; - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -771,7 +771,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, target_ulong vaddr; hwaddr paddr; target_ulong page_size; - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); int error_code = 0, prot, access_index; address &= TARGET_PAGE_MASK; @@ -890,7 +890,7 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys, { target_ulong page_size; int prot, access_index; - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(env_cpu(env)); return get_physical_address(env, phys, &prot, &access_index, &attrs, addr, rw, mmu_idx, &page_size); From patchwork Fri Nov 11 18:25:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623756 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp957010pvb; Fri, 11 Nov 2022 10:27:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf7zVSYjrRqlbIpEI08kaPYqQw4nA+A9U0DQFZ3W8mHtbKvX38MJpy7rfFJ3h6vSCMHlqYRs X-Received: by 2002:a05:620a:1525:b0:6ed:6067:fbd8 with SMTP id n5-20020a05620a152500b006ed6067fbd8mr2179244qkk.394.1668191278441; Fri, 11 Nov 2022 10:27:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191278; cv=none; d=google.com; s=arc-20160816; b=ZFmliGFN+WXVI/koikqZ7p8D22DF8LMb1JYoPnzq/B8vie5VYKHVnSUNjzwwkRNxYJ SqbCOoK281Od2jX9z/9hAbQT3A3lQpMpBImLlPZSuibFdAo1WNBmODLo9ETuBzaszbE0 yRJSYOTxkKupWEvQIo/qqA2xY2kCiUAde3OUf7exXIS3fVZo5or/7pYr9TWKUcRe86J8 PkzoeiQIwXwZckI4Gs58lFhq/ndz4HH/Rnj15QEGPl8xgjE0C6ULVmetOq6SR+rY+wkC ZwngEwZ6uHdMHmkb8bJMJR4UZjkTC1QuI0Px2q+qX0+QCebi6QPQoh8w39btH1+oQFnE 86Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kIPHK6op8WfT+LuyUEUjPy9me25/GAi6rKKy/+XKxJ0=; b=YTg5ZHFQGMEFrq4jiLTIF8E/Rjl6+wDx1sm3M0qiQ73MS0bsBmk5ZYH93IG9OU7HDM 1lHBzMFCB+UguIM0k/w/hAl+vAcP/VH87+fDvedJW6Q3WRRxcdK6LRhwBM38l6yrgF/H 8qeviOJd9NLcEb4uZkVZgjQmTPe0v4geUnnh2Nkbe1veHaPal7W2bCobXDyWOYX35xZf RQqDrQLWijKnlmvORWU/LJHZR3PRG0Bf4QLdPim68PMHNetvuxvkqhf/m2R8bPzLrh2m tS4n3DN/uuTFL/leIQbGJcWczFTMxjKOJnKYetyoNGKMNo1T+I63lxhZ9++06jpmL0O3 9Asg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XDQdgaEE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use the new MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in should it ever be needed by any devices later. Currently the tlb_fill function isn't using the set with attributes function so IO accesses from the softmmu slow-path will not be tagged as coming from the CPU. Signed-off-by: Alex Bennée --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 278d163803..e661f9e68a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -761,7 +761,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * correct, but the value visible to the exception handler * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; - MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; + MemTxAttrs attrs = MEMTXATTRS_CPU(env_cpu(env)); int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background = false; hwaddr ppn; From patchwork Fri Nov 11 18:25:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623766 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp961389pvb; Fri, 11 Nov 2022 10:36:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf45L94H8QCSSeaEOOIZNViDK79fC4KEfbR+SvnmhBTVc4lkBTxjm1tlAV1kP35hFZ21Bc9p X-Received: by 2002:a37:d284:0:b0:6ec:5539:52fa with SMTP id f126-20020a37d284000000b006ec553952famr2238626qkj.38.1668191779315; Fri, 11 Nov 2022 10:36:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191779; cv=none; d=google.com; s=arc-20160816; b=tXw8bHi+iB3rKcqMQ8m0XqwyQ7AcKpa13SS3IAtEa9r+23kgfBK95emSidm+QVskrl OqHDSyfV3k51c4hyD9rOhoa5AELeJUPoJqlJj+vJMXwqpCtXhMCL2rVVePlMlk+YM/hl txOXQ00OvF6mq1NFn763d5nHQVshlrYWQyiG6GKlkKfBYzhBDwSZks0LUZquPJ6lRLY6 nR5tmWycVAK9i7pDEw2Ht3aNmbUz2jiPMntd23H5in/5p5NibT4zdf7Gjg88nRvtxNgj 4bt40VDT7+5XHn9fyeKVCst08wdzdR4p/SpJ6/XTDPA/u25vjNA+hhceDxhxd6WvLpJ2 o1Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KjvcD/bUb6v85GBYMsY2wRda3lPUntOnEJ8cQndopVc=; b=ei/LshaXD3LSSnsCX02dPRbqmJkycVRMdJOpHp2Ptkp9+l7lW0WIZTCTnS7J9LNkPH p8YPWfMDUB6/v3acvHiW8d70ftw+bHqSp0xjL+zSEKKOK/beiktThR+0TcxRRGUq0tPw qo+mgQ9KSVtwrUNPEy59euXyN9LRZEBaHQAdLGyoYrVgvyCS1M/J3KKosyXqVBj/jlGL CE81SlsmoI2nGlJK3rpx+GiFarpFrEMDk9Xt4NUyfxr8LhTDQuhpR5gXTqa8k6Fd5w23 IpmQ8/kqHf7ol4YSbp0Vxb7xIAv56dmerPsBxzbI7p17oSIVgZ6PHptcePIgvzpWBH01 H31w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j07ZcctB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m8-20020a05620a290800b006e2c12e0307si1603550qkp.358.2022.11.11.10.36.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Nov 2022 10:36:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j07ZcctB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otYrt-0007sj-Gy; Fri, 11 Nov 2022 13:35:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otYrn-0007rN-6Y for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:35:06 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otYrl-0007Om-4y for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:35:02 -0500 Received: by mail-wr1-x42c.google.com with SMTP id k8so7556705wrh.1 for ; Fri, 11 Nov 2022 10:34:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KjvcD/bUb6v85GBYMsY2wRda3lPUntOnEJ8cQndopVc=; b=j07ZcctBaiVRR4dHoUX9jCUfu4N4o7HNNO6oPYNq/GaPjeAsFFnZJfoBUGtZa7iaVC q7Tk8wIPIr3lqDUZ/U9GgOVskORuQJhX2zf3JXG98i1S58y29kCb7N+62SW+0myhkOtD QVqjnwVU8Hbe6zEOhXf/wVIJW3kZmpxtnHDeFJAvao/pPWbSHgAtY+tHi3oNMubkT0ai nIGN8RERXD+MGSz1CQTDUPYbIngyaiSRAHT0SucBRJNeS6/MCbvLg97iJTEbGPF27foP 3euQevj5rwR32v2a/X8vycNPPui7dx2sG4u5N9cozpWDNekiDzJ4y1b0Ej5lURnLsFq2 hfTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KjvcD/bUb6v85GBYMsY2wRda3lPUntOnEJ8cQndopVc=; b=dYeImgXHZZ5eyitGZVndHrM2Ghub+bXU21kKf20rOU8ZSjyhLgugVHFVQEI4SAaIb6 3EAWcUzu46kNBq+AWT2Gz3mUSIgmK0XXomlCxb+/1RMTY2z+Yf3bdWkM1lf0nKIlh6HG Hq8bdEtoAgoCDL0X/BiM5ddRHe6/2bpjFALL0ROR1ITeBEPLUH1LWvymRym7ofFwvay8 sLngAXHkwaMQ2oGIPQwl5J9lYrb6u+nUKor98HUkzmfWQU4diOMkRD7bdRpRaq5GC6n3 pUY2Fa/m43A0Ly2yGB/XeZaCe1F/Di1g8dSACkKyXYUkkH14pgEUlURQdEKYdL2WIjO/ z5YQ== X-Gm-Message-State: ANoB5pnu+XdVAWvJzshY11fdvMGJZSnC9UeRWawl+jk8giVYynhDTiZu 89r2YuGdZT2agXaZCwJfW02PHg== X-Received: by 2002:a5d:68c1:0:b0:236:84b5:c0d8 with SMTP id p1-20020a5d68c1000000b0023684b5c0d8mr2071393wrw.342.1668191695330; Fri, 11 Nov 2022 10:34:55 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c4d1100b003cfb7c02542sm3505512wmp.11.2022.11.11.10.34.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 10:34:51 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id F38891FFB8; Fri, 11 Nov 2022 18:25:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Wenchao Wang , Kamil Rytarowski , Reinoud Zandijk , Paolo Bonzini , Marcelo Tosatti , Sunil Muthuswamy , haxm-team@intel.com (open list:X86 HAXM CPUs), kvm@vger.kernel.org (open list:X86 KVM CPUs) Subject: [PATCH v5 13/20] target/i386: add explicit initialisation for MexTxAttrs Date: Fri, 11 Nov 2022 18:25:28 +0000 Message-Id: <20221111182535.64844-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Where appropriate initialise with MEMTXATTRS_CPU otherwise use MEMTXATTRS_UNSPECIFIED instead of the null initialiser. Signed-off-by: Alex Bennée --- target/i386/cpu.h | 4 +++- target/i386/hax/hax-all.c | 2 +- target/i386/nvmm/nvmm-all.c | 2 +- target/i386/sev.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a..04ab96b076 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2246,7 +2246,9 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env) static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) { - return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); + MemTxAttrs attrs = MEMTXATTRS_CPU(env_cpu(env)); + attrs.secure = (env->hflags & HF_SMM_MASK) != 0; + return attrs; } static inline int32_t x86_get_a20_mask(CPUX86State *env) diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index b185ee8de4..337090e16f 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -385,7 +385,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df, uint16_t port, { uint8_t *ptr; int i; - MemTxAttrs attrs = { 0 }; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; if (!df) { ptr = (uint8_t *) buffer; diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index b75738ee9c..cb0720a6fa 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -502,7 +502,7 @@ nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) static void nvmm_io_callback(struct nvmm_io *io) { - MemTxAttrs attrs = { 0 }; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; int ret; ret = address_space_rw(&address_space_io, io->port, attrs, io->data, diff --git a/target/i386/sev.c b/target/i386/sev.c index 32f7dbac4e..292cbcdd92 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -1274,7 +1274,7 @@ bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp) uint8_t *hashp; size_t hash_len = HASH_SIZE; hwaddr mapped_len = sizeof(*padded_ht); - MemTxAttrs attrs = { 0 }; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; bool ret = true; /* diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index e738d83e81..42846144dd 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -791,7 +791,7 @@ static HRESULT CALLBACK whpx_emu_ioport_callback( void *ctx, WHV_EMULATOR_IO_ACCESS_INFO *IoAccess) { - MemTxAttrs attrs = { 0 }; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; address_space_rw(&address_space_io, IoAccess->Port, attrs, &IoAccess->Data, IoAccess->AccessSize, IoAccess->Direction); From patchwork Fri Nov 11 18:25:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623764 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp961203pvb; Fri, 11 Nov 2022 10:35:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf66ZxmH22JKQ9IX67butBoIkpUc99ZhnVrSxiSMzoy1k0D/XN04OFZ0Gf1rbfsv9sfrRwcG X-Received: by 2002:a0c:c784:0:b0:4bb:77fe:4bd4 with SMTP id k4-20020a0cc784000000b004bb77fe4bd4mr3075560qvj.59.1668191759030; Fri, 11 Nov 2022 10:35:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191759; cv=none; d=google.com; s=arc-20160816; b=qcPmByGAT+qcR4K3h1Ps2tWcavDfPysgi9gkSVkd5SuCfcnwUk65xgmKtawltz6rwK uEzNO3f1LAXLV5xZD3zWDMO9XfRCIXmTzKuIhgoSxAZkXVnEEZKLfHbHhfXgc6kivMkJ vgmhwF0a/WrTcSPmsdQ5IBwCuwZbTfuMedr9VieIwmkx0ZpvTQazCjN9IZwn0lY4tYf7 +8AoT7ZvD7PouiY6Zke4PmBkGjYrcnwmQ5qZJZMiChkNrEdAyFpy0pUdhGI0WEeMmr2Z KL9uh+tCVCF2Au7/RiH3qA7VDiF9vt5KJKVaaGuAqYfO1bScwc6qr6+zpFf+koJFNmnn 2sFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=K9jGL/FUfAGFTfK5rC1/vlTivx143+0Q3Bji1lhCRr0=; b=wEVD0OAxjhmtA/i+l2r5a8poHj1oU+3Hy6Oeo6zgVgm16f9+uZ7zY6bDLkpSxZC+2q n8PqkV3rruI26hAVYUbgka/JNTgUBmNRhiqeFB/lYkJ4SD11OBdpBPTLV135npEAfoGT FSN1co408ruciYQ8LJ8o6Z0fSSFwMfPlqof1VovSe8nyIswH3Zcc8JUZpq/Jli9u1kUQ Wlqzjbc3pEGGYPH3bJgyCHQR380WFoqfyCRnOfNhDcucpgBynH+8jNJBqRSuMagMfsOo TiMQCpsRaicJIX4RMUHWjBsVgythUOseZJX3BectPL1Q487B0I+uGqMfEo34i5vejxwk kKrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jV89u6Vy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mark it as such. Signed-off-by: Alex Bennée --- hw/audio/intel-hda.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index f38117057b..95c28b315c 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -345,7 +345,7 @@ static void intel_hda_corb_run(IntelHDAState *d) static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) { - const MemTxAttrs attrs = { .memory = true }; + const MemTxAttrs attrs = { .requester_type = MTRT_PCI, .memory = true }; HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); IntelHDAState *d = container_of(bus, IntelHDAState, codecs); hwaddr addr; From patchwork Fri Nov 11 18:25:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623761 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp959136pvb; Fri, 11 Nov 2022 10:31:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf4bt9ZD4cSG7sVnTWWo4XlkCrLq3yHa9Pc3PvQmrg7kGgDn1nL/aNxftDk2A2cEFLuQCxCS X-Received: by 2002:ac8:460c:0:b0:3a5:4942:a7d5 with SMTP id p12-20020ac8460c000000b003a54942a7d5mr2506888qtn.33.1668191518432; Fri, 11 Nov 2022 10:31:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191518; cv=none; d=google.com; s=arc-20160816; b=SG3krLLFtqYIpy16bw8ncgdOJXtz2kDOmZs9v1TL3qHj2zLTfKz1fqk10j+RsCxqZP +7z+uQFVydcYVqTeyBu0SjoRpO9+v61t9JQGlKb1as18KCyLnJ8KZJkJED5mG2kC+ITM cP/0zuUii2XBV7Qj+7XkZOxv8EHPvJy7x1ABMhG/J4EsAzyUzJ7Rgr0zXCNT4VPjRPCq V/6hlblQBoi5+vzos+Kv0JRzODD+OOVE1jOfMyP0mLFPP26PWwD04O4skvDc0fVBWrNy GCo3vyLjTtkPcCPC7IkR/nAnN1sQ64zqMhFpqsmfAXnQn95eLotvm7+doAAIDYMN+W9g pTsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6dm7DBaeF2cZRUQRIT8/o6GsqUIEGkYXBsJF1ojYAj4=; b=r8C2o5pX9TsLDGwbXNBr/cvvgiykGXz9lF+naeRqLoXyhOWMdu0YNtECMMGJFNBY1h Y5zL5Fzavo9HhwjHgXEHD907WQdRaflfGO7WHrLNbLcJPquXtDS4jMipqPE9w4PoDAOv HoMFAZUvG8FPn0qcFfkkX5V33yBFncj89oS0xqQsMQzRjdQhJ3TUEJm0v2qif9j9mtwI ZOPiXr9QMEK4wCRaG6hdaYddH2rtpUBHzkQLLjY3wAoaa/Je80bVnITxYRW77RE9sFZE 9eGHt7L8LdsTEk+7dpvgOtKoZXRdweAMqBwfwtDoFVCAI4+lVoWne0H61L9Y43RHWXXy Y60g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="AT72/gVz"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs Date: Fri, 11 Nov 2022 18:25:30 +0000 Message-Id: <20221111182535.64844-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This allows us to drop the current_cpu hack and properly model an invalid access to the vapic. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/i386/kvmvapic.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 43f8a8f679..a76ed07199 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -635,20 +635,21 @@ static int vapic_prepare(VAPICROMState *s) return 0; } -static void vapic_write(void *opaque, hwaddr addr, uint64_t data, - unsigned int size) +static MemTxResult vapic_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size, MemTxAttrs attrs) { VAPICROMState *s = opaque; + CPUState *cs; X86CPU *cpu; CPUX86State *env; hwaddr rom_paddr; - if (!current_cpu) { - return; + if (attrs.requester_type != MTRT_CPU) { + return MEMTX_ACCESS_ERROR; } - - cpu_synchronize_state(current_cpu); - cpu = X86_CPU(current_cpu); + cs = qemu_get_cpu(attrs.requester_id); + cpu_synchronize_state(cs); + cpu = X86_CPU(cs); env = &cpu->env; /* @@ -708,6 +709,8 @@ static void vapic_write(void *opaque, hwaddr addr, uint64_t data, } break; } + + return MEMTX_OK; } static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size) @@ -716,7 +719,7 @@ static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size) } static const MemoryRegionOps vapic_ops = { - .write = vapic_write, + .write_with_attrs = vapic_write, .read = vapic_read, .endianness = DEVICE_NATIVE_ENDIAN, }; From patchwork Fri Nov 11 18:25:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623759 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp958457pvb; Fri, 11 Nov 2022 10:30:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf6XGfoHyA9l5d98PWMMvj+lNc2Xj4FWS2I+7CUyg6poXAZ5f16Km+xlWIG85ZOzAmP7EG6Y X-Received: by 2002:a05:622a:5a87:b0:3a5:460f:f155 with SMTP id fz7-20020a05622a5a8700b003a5460ff155mr2528497qtb.264.1668191449255; Fri, 11 Nov 2022 10:30:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191449; cv=none; d=google.com; s=arc-20160816; b=XEY+f8JPDB0uNlNmrae3w0bSftXdjd0Qxn6UDT7eJnXKEc3tCxzTMr+B3ddHfK8FtE Sce8+KqGLDlGBkn6/m9oegR9XxRvQN2NAXM39kRX1EDfT40fEZVV4qp9mXX4p69JUYhr WXwOQghJ01C2AIGsGyvji93vcULIHhqk1ELCtLGJ4PSqghJLmM5Igd8GLq9BzvuQ1S54 q0AaLOAmpWiplg+2xSkrWD9R4kh7ZYeu5aHuvE9AfK3KyAePOVIeXSdEwfqjYyTcXLY3 dl6edCh5HdK6RnrST+G8gdQhWMQVWv9KCP4hh3dD71CO1fZ6qhv+Y1c4bu6oYVNysKos qAgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tP1tnCJDD0/845PJkX8UHaIw8B4BsTZ1dk/TTCfeP/A=; b=V/N4oWGrRzcXPNoFe3pGU0wKFtLeER8QeBF2gYj7uridoZGdSxpRnQadrs2H1KQpNH P8fl3cD/+K/JL4l8H8AkFtdDtTJN3Fm9RzuWaZLnI0LTjR6lWhsdGG/6IgqutUE71lXY ROwbbAVWfYbG4Tx0tu9XL8/Mtq18FjAIpURJxkQgpZaoRAqBwDASDzBXjAxxVqnMxyPK CdsnuX3Bb+S6HSHJSkcXiTLnMya/IQFa1mYltWh6lz8R59IpYo09UrmrxCeuNRaCZAMZ cVMhaISYCotxRfqOt6f/MV8bMogdKgHiqZv56NWqJVKKxZOSg5Mj4iuAZYd2FMZ8HFgq 1GLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vJ1rwERz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/exec/memattrs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 8359fc448b..b92f11aaa4 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -104,6 +104,14 @@ typedef struct MemTxAttrs { {.requester_type = MTRT_PCI, \ .requester_id = pci_requester_id(dev)}) +/* + * Helper for setting a machine specific sourced transaction. The + * details of how to decode the requester_id are machine specific. + */ +#define MEMTXATTRS_MACHINE(id) ((MemTxAttrs) \ + {.requester_type = MTRT_MACHINE, \ + .requester_id = id }) + /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure * of some kind. The memory subsystem will bitwise-OR together results From patchwork Fri Nov 11 18:25:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623757 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp957165pvb; Fri, 11 Nov 2022 10:28:21 -0800 (PST) X-Google-Smtp-Source: AA0mqf4pUL4+xdiQG8J4Qk802W6IVMibP2N0TShnb3wJ1+61e7+h7wUcd2mG1VZA2snJVjBK6+ar X-Received: by 2002:a05:620a:2b8a:b0:6fa:4e7a:b13d with SMTP id dz10-20020a05620a2b8a00b006fa4e7ab13dmr2094766qkb.406.1668191301542; Fri, 11 Nov 2022 10:28:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191301; cv=none; d=google.com; s=arc-20160816; b=eLGlgt6oc76CidFAnvp0O9vhkF6zUt1SEQwAHUEOPDapkYRvhZqgH7DnvO62Isgc2X NZDqOnJj5gEicPPCcvH5r5D0/Rs9mbJPRD7PBF7Y0qRVkcrsMMgbJBg0MYRtKZGkWa83 Y8L6Lkg/p5K49Z8dJPLv9+Mqkzdntp75Xt0E48J+FoNwFb8aEkdaVg+l5BSubMeWGZNv gAQbpFcRy/GZpX1Pf7IX6TNvON79+cpwj2CxdELfXPPUHf0ArjyiDF9P9+TMTIMpJna/ iP3nl6G3tSfbpU/5vqS5AzoF9B2IQ5jN4Z6Dm9+nVnJ+hRMIwmy0F6HEQLHOoELbuPfU BwEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PuFr65DHYvQCpbDpxv+MZAfjV8gOeGfjlaJ44Vc426s=; b=PEctMNrsCbeyUx58uA0uBf7HkxfJj1JpnvwmW7n7JyfhFD87RcUq12a4wghiy2W1e0 lRXxDEFPCqZgXMKSjj2epJPPB1Ji1Aja18p9AaZGZqt84rk1lF3kw0w9BW8B+5nOsXLA 4xzH+zW2UNgGrRA+86otjyVh3UGAFJibCXpafCEFfANwJ+e9B8vBccXCxS6ClQTN3Hrp j8LjfhcRCOPiggUjHQPkyyRhe8g2CZzeBL3ZFJ2hokTauphfYiblr+GCGmrIbcUaona4 uBKyVJLTGOAi83YTF3GCoMm/Mh+01jGG7rdXSYsZX4hA/2xwrGLLqzWdSdzNnZW0ntJR PJLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aJshykLP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Marcel Apfelbaum Subject: [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages Date: Fri, 11 Nov 2022 18:25:32 +0000 Message-Id: <20221111182535.64844-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org On the real HW the IOAPIC is wired directly to the APIC and doesn't really generate memory accesses on the main bus of the system. To model this we can use the MTRT_MACHINE requester type and set the id as a magic number to represent the IOAPIC as the source. Signed-off-by: Alex Bennée Cc: Paolo Bonzini Cc: Peter Xu Reviewed-by: Richard Henderson --- include/hw/i386/ioapic_internal.h | 2 ++ hw/intc/ioapic.c | 35 ++++++++++++++++++++++++------- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 9880443cc7..a8c7a1418a 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -82,6 +82,8 @@ #define IOAPIC_VER_ENTRIES_SHIFT 16 +/* Magic number to identify IOAPIC memory transactions */ +#define MEMTX_IOAPIC 0xA71C #define TYPE_IOAPIC_COMMON "ioapic-common" OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 264262959d..8a5418002b 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -21,6 +21,7 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "qapi/error.h" #include "monitor/monitor.h" #include "hw/i386/apic.h" @@ -88,9 +89,33 @@ static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info) (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); } -static void ioapic_service(IOAPICCommonState *s) +/* + * No matter whether IR is enabled, we translate the IOAPIC message + * into a MSI one, and its address space will decide whether we need a + * translation. + * + * As the IOPIC is directly wired to the APIC writes to it are not the + * same as writes coming from the main bus of the machine. To model + * this we set its source as machine specific with the MEMTX_IOPIC + * id. + */ +static void send_ioapic_msi(struct ioapic_entry_info info) { AddressSpace *ioapic_as = X86_MACHINE(qdev_get_machine())->ioapic_as; + MemTxAttrs attrs = MEMTXATTRS_MACHINE(MEMTX_IOAPIC); + MemTxResult res; + + address_space_stl_le(ioapic_as, info.addr, info.data, + attrs, &res); + if (res != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: couldn't write to %"PRIx32"\n", __func__, info.addr); + } +} + + +static void ioapic_service(IOAPICCommonState *s) +{ struct ioapic_entry_info info; uint8_t i; uint32_t mask; @@ -130,12 +155,8 @@ static void ioapic_service(IOAPICCommonState *s) continue; } #endif - - /* No matter whether IR is enabled, we translate - * the IOAPIC message into a MSI one, and its - * address space will decide whether we need a - * translation. */ - stl_le_phys(ioapic_as, info.addr, info.data); + /* If not handled by KVM we now send it ourselves */ + send_ioapic_msi(info); } } } From patchwork Fri Nov 11 18:25:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623765 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp961221pvb; Fri, 11 Nov 2022 10:36:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf5fjMPkVhSRRTISDRaWGyNXk6UkJDf50RNCKoBRe/Rk1GiyMcjmbXq2z8Mw1enYIOuPn/fi X-Received: by 2002:a05:620a:439c:b0:6f9:9833:1e21 with SMTP id a28-20020a05620a439c00b006f998331e21mr2149429qkp.715.1668191760702; Fri, 11 Nov 2022 10:36:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191760; cv=none; d=google.com; s=arc-20160816; b=lyn5y2YbSqpAMMLQ7pL0P17qJrAufndbZueXOqeio9/3O42UcFoO+rPWCs/XTDu8/z YBJsQvodZeAqhqNB6ZxaWApZIznBSnM9drg3q6mD9L11XvTKAtMEJdeL/YAflAjuhgG/ ipc3f8QBGuCl0TSgBecYLwCvDcEmUs4kY1sWoJCN5uvLplsLGWZcoS/OQbIihzsKsmDM on5RZZNTSEk2hoUW1Jj+dg+j04yk0QLJSoteSstPqTW6qBc1DuRGcgkrqfVOry+m7UqJ ziaK664SebNqeBrMNAofI72kUwBfbTDmVO/G1gzeR3bAXTD/JKT7XKmFNtMX4K1578QP AvEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ABoGqsqA9eKSAz+FBs0/NNjZz/xcfytUN16WsWs1Ty0=; b=HZPwboSR2O+GZFNpEehKIPktgu6a05V+7Kf1ULrWlzQVeG+N0TIey6Zy/6uxKP0cdO 6LdTDm8s097fzTXbFKS/tDOhBFWe1nvJ+XJgi3LhbjhTCUFPCt4ork/661iSKpN+KrRM oAHwioIbI6nYvGh+GCthq6vCVFHZzvC2uXHIC49kG1RIE/ESnyAWj7Aqw4RpCnenIknN 83Cg39AQsXul0i/ghQ+FGAedm+TH39JB/KR0hqtfT+Lz4ueah8GW1OEHyAe7iwpDDYnV K+ojr/yGm7LGWd5dIyyTA2A50MWk3IEXpQVTX+jrYF1O1+CleU8+WEeV53TtFdpLLVRO vDjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z8ydcl8p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Subject: [PATCH v5 18/20] hw/i386: convert apic access to use MemTxAttrs Date: Fri, 11 Nov 2022 18:25:33 +0000 Message-Id: <20221111182535.64844-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This allows us to correctly model invalid accesses to the interrupt controller as well as avoiding the use of current_cpu hacks to find the APIC structure. We have to ensure we check for MSI signals first which shouldn't arrive from the CPU but are either triggered by PCI or internal IOAPIC writes. Signed-off-by: Alex Bennée Cc: Paolo Bonzini Cc: Peter Xu Reviewed-by: Richard Henderson --- v1 - don't validate requester_id for MTRT_MACHINE, just assume IOPIC --- include/hw/i386/apic.h | 2 +- hw/i386/x86.c | 11 +++----- hw/intc/apic.c | 62 ++++++++++++++++++++++++++++-------------- 3 files changed, 46 insertions(+), 29 deletions(-) diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index da1d2fe155..064ea5ac1b 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -22,6 +22,6 @@ void apic_designate_bsp(DeviceState *d, bool bsp); int apic_get_highest_priority_irr(DeviceState *dev); /* pc.c */ -DeviceState *cpu_get_current_apic(void); +DeviceState *cpu_get_current_apic(int cpu_index); #endif diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 78cc131926..66645a669c 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -585,14 +585,11 @@ int cpu_get_pic_interrupt(CPUX86State *env) return intno; } -DeviceState *cpu_get_current_apic(void) +DeviceState *cpu_get_current_apic(int cpu_index) { - if (current_cpu) { - X86CPU *cpu = X86_CPU(current_cpu); - return cpu->apic_state; - } else { - return NULL; - } + CPUState *cs = qemu_get_cpu(cpu_index); + X86CPU *cpu = X86_CPU(cs); + return cpu->apic_state; } void gsi_handler(void *opaque, int n, int level) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 3df11c34d6..0a9897e64f 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -18,9 +18,11 @@ */ #include "qemu/osdep.h" #include "qemu/thread.h" +#include "qemu/log.h" #include "hw/i386/apic_internal.h" #include "hw/i386/apic.h" #include "hw/i386/ioapic.h" +#include "hw/i386/ioapic_internal.h" #include "hw/intc/i8259.h" #include "hw/pci/msi.h" #include "qemu/host-utils.h" @@ -634,21 +636,23 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } -static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult apic_mem_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned int size, MemTxAttrs attrs) { DeviceState *dev; APICCommonState *s; uint32_t val; int index; - if (size < 4) { - return 0; + if (attrs.requester_type != MTRT_CPU) { + return MEMTX_ACCESS_ERROR; } + dev = cpu_get_current_apic(attrs.requester_id); - dev = cpu_get_current_apic(); - if (!dev) { - return 0; + if (size < 4) { + return MEMTX_ERROR; } + s = APIC(dev); index = (addr >> 4) & 0xff; @@ -719,7 +723,8 @@ static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) break; } trace_apic_mem_readl(addr, val); - return val; + *data = val; + return MEMTX_OK; } static void apic_send_msi(MSIMessage *msi) @@ -735,32 +740,45 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } -static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, - unsigned size) +static MemTxResult apic_mem_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size, MemTxAttrs attrs) { DeviceState *dev; APICCommonState *s; int index = (addr >> 4) & 0xff; if (size < 4) { - return; + return MEMTX_ERROR; } + /* + * MSI and MMIO APIC are at the same memory location, but actually + * not on the global bus: MSI is on PCI bus APIC is connected + * directly to the CPU. + * + * We can check the MemTxAttrs to check they are coming from where + * we expect. Even though the MSI registers are reserved in APIC + * MMIO and vice versa they shouldn't respond to CPU writes. + */ if (addr > 0xfff || !index) { - /* MSI and MMIO APIC are at the same memory location, - * but actually not on the global bus: MSI is on PCI bus - * APIC is connected directly to the CPU. - * Mapping them on the global bus happens to work because - * MSI registers are reserved in APIC MMIO and vice versa. */ + switch (attrs.requester_type) { + case MTRT_MACHINE: /* MEMTX_IOPIC */ + case MTRT_PCI: /* PCI signalled MSI */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: rejecting write from %d", + __func__, attrs.requester_id); + return MEMTX_ACCESS_ERROR; + } MSIMessage msi = { .address = addr, .data = val }; apic_send_msi(&msi); - return; + return MEMTX_OK; } - dev = cpu_get_current_apic(); - if (!dev) { - return; + if (attrs.requester_type != MTRT_CPU) { + return MEMTX_ACCESS_ERROR; } + dev = cpu_get_current_apic(attrs.requester_id); s = APIC(dev); trace_apic_mem_writel(addr, val); @@ -839,6 +857,8 @@ static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, s->esr |= APIC_ESR_ILLEGAL_ADDRESS; break; } + + return MEMTX_OK; } static void apic_pre_save(APICCommonState *s) @@ -856,8 +876,8 @@ static void apic_post_load(APICCommonState *s) } static const MemoryRegionOps apic_io_ops = { - .read = apic_mem_read, - .write = apic_mem_write, + .read_with_attrs = apic_mem_read, + .write_with_attrs = apic_mem_write, .impl.min_access_size = 1, .impl.max_access_size = 4, .valid.min_access_size = 1, From patchwork Fri Nov 11 18:25:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623763 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp960632pvb; Fri, 11 Nov 2022 10:34:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf4sf2jZZd4HJuTHIM124JbMslAvdMGK4BOySdTQk+U1dQvUclh81tzeO1fRyTkBZPcXt0gN X-Received: by 2002:ac8:568a:0:b0:3a5:1f05:64c5 with SMTP id h10-20020ac8568a000000b003a51f0564c5mr2496388qta.453.1668191694672; Fri, 11 Nov 2022 10:34:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191694; cv=none; d=google.com; s=arc-20160816; b=EGrh62YJnrQvooungTSTtT/lXvZiT4WExE3aAFATuoG0jUTN3ijiOAq2oddu9UfTl6 2A66iU7Bghy16ZnElwQu71SDjzAUeBed2tjGoZX/ztLhWpqnvpxG42lJK1zXgwTLKB1B 4vMWLB8XO9Gb37+wW962jNXMIkPYuPfPV5vGhjIWNwI6jJYCaT+b4iIpn0lOXp13MJOo FZoONPS5AXxT7CbtplGq4rycZ/OAtPjmhQ/l0qvOvLuGobhbEcXCEuqxyyMJi3NKyzGG esrcKToCnhr8QkiwRrOOp7V5yYlETHNRcT2X4SwIJ+UIi9EUoL1xsrpOsuPkQTUSTf5Z 16pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5iH61ih5qpB2sELZhsEsE8puEse88yX4jWDb+Zn9fY4=; b=pjXMdoDXRvCQORL4i449ixQiQV63n81u2BTwo8BA4Dn13geiw+O91LQ4sK5exS/ylu A2C/oD+KbCTWrILHOrR0jueDUSUd69aiZSglDvocE+esnDKcu8YT99d4yKV30+evxLQo 9HazCc2wnYa24nsX9+cxd9wCgCpko0RriLuNLUHoStVwOaX+7W+UUX3L62cn643QSmjz /jGqVjHpwve6sRTxxnki3ANOSmeDHLtwa5FyUKrEC3snU0eT9Y/GWDRlp1mAraUVjBAS 58s2Q5aQBrVb3HXAieMdyKFkkA1cQAOH2/NgDv7+UTNJ63mOC2vF9GFo2tP6OWM0lPa5 vncw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KosjgZvQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Marcel Apfelbaum , Igor Mammedov , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Subject: [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb Date: Fri, 11 Nov 2022 18:25:34 +0000 Message-Id: <20221111182535.64844-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Some of the callbacks need a CPUState so extend the interface so we can pass that down rather than relying on current_cpu hacks. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/isa/apm.h | 2 +- hw/acpi/ich9.c | 1 - hw/acpi/piix4.c | 2 +- hw/isa/apm.c | 21 +++++++++++++++++---- hw/isa/lpc_ich9.c | 5 ++--- 5 files changed, 21 insertions(+), 10 deletions(-) diff --git a/include/hw/isa/apm.h b/include/hw/isa/apm.h index b6e070c00e..eb952e1c1c 100644 --- a/include/hw/isa/apm.h +++ b/include/hw/isa/apm.h @@ -6,7 +6,7 @@ #define APM_CNT_IOPORT 0xb2 #define ACPI_PORT_SMI_CMD APM_CNT_IOPORT -typedef void (*apm_ctrl_changed_t)(uint32_t val, void *arg); +typedef void (*apm_ctrl_changed_t)(CPUState *cs, uint32_t val, void *arg); typedef struct APMState { uint8_t apmc; diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index bd9bbade70..70ad1cd1ff 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -30,7 +30,6 @@ #include "hw/pci/pci.h" #include "migration/vmstate.h" #include "qemu/timer.h" -#include "hw/core/cpu.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "hw/acpi/acpi.h" diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 0a81f1ad93..43b78ef8f9 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -70,7 +70,7 @@ static void pm_tmr_timer(ACPIREGS *ar) acpi_update_sci(&s->ar, s->irq); } -static void apm_ctrl_changed(uint32_t val, void *arg) +static void apm_ctrl_changed(CPUState *cs, uint32_t val, void *arg) { PIIX4PMState *s = arg; PCIDevice *d = PCI_DEVICE(s); diff --git a/hw/isa/apm.c b/hw/isa/apm.c index dfe9020d30..95efbf2457 100644 --- a/hw/isa/apm.c +++ b/hw/isa/apm.c @@ -21,6 +21,8 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/core/cpu.h" #include "hw/isa/apm.h" #include "hw/pci/pci.h" #include "migration/vmstate.h" @@ -30,10 +32,19 @@ /* fixed I/O location */ #define APM_STS_IOPORT 0xb3 -static void apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, - unsigned size) +static MemTxResult apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, + unsigned size, MemTxAttrs attrs) { APMState *apm = opaque; + CPUState *cs; + + if (attrs.requester_type != MTRT_CPU) { + qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR, + "%s: saw non-CPU transaction", __func__); + return MEMTX_ACCESS_ERROR; + } + cs = qemu_get_cpu(attrs.requester_id); + addr &= 1; trace_apm_io_write(addr, val); @@ -41,11 +52,13 @@ static void apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, apm->apmc = val; if (apm->callback) { - (apm->callback)(val, apm->arg); + (apm->callback)(cs, val, apm->arg); } } else { apm->apms = val; } + + return MEMTX_OK; } static uint64_t apm_ioport_readb(void *opaque, hwaddr addr, unsigned size) @@ -77,7 +90,7 @@ const VMStateDescription vmstate_apm = { static const MemoryRegionOps apm_ops = { .read = apm_ioport_readb, - .write = apm_ioport_writeb, + .write_with_attrs = apm_ioport_writeb, .impl = { .min_access_size = 1, .max_access_size = 1, diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 0b0a83e080..2700a18a65 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -443,7 +443,7 @@ void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) /* APM */ -static void ich9_apm_ctrl_changed(uint32_t val, void *arg) +static void ich9_apm_ctrl_changed(CPUState *cs, uint32_t val, void *arg) { ICH9LPCState *lpc = arg; @@ -459,12 +459,11 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *arg) if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { if (lpc->smi_negotiated_features & (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { - CPUState *cs; CPU_FOREACH(cs) { cpu_interrupt(cs, CPU_INTERRUPT_SMI); } } else { - cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + cpu_interrupt(cs, CPU_INTERRUPT_SMI); } } } From patchwork Fri Nov 11 18:25:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 623768 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp961789pvb; Fri, 11 Nov 2022 10:37:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf6JuO7rLT3Oc4sDEjEFwuFTsj0wXYpIYl+0cDdpfAnIHxGTyqKInECm6giCgQcHFUsVQ2oL X-Received: by 2002:a05:6214:5f84:b0:4ba:171b:8978 with SMTP id ls4-20020a0562145f8400b004ba171b8978mr3034599qvb.82.1668191825850; Fri, 11 Nov 2022 10:37:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668191825; cv=none; d=google.com; s=arc-20160816; b=H0sI74J0ZAN2GQgFyFZKEaTS77VGW7wVltEqyhhAxLxvgD5u/2EMcIwzMLxj1dSPTN 75hW8hSatVsUp60E/9hBd0REAcHVkAuS+/S0oENzQYVnoyXBehAImMyLv994v4dfqqBx tKLj/rbWC9Hgx5OQdOVHW8KVY6tRwXKcLyPoYZFcLvwNgdUzYcKY9L1B2lA5/wdNzq3W 2o5sL5PclODgtOUo/g/iITJuYn0rYQhNmi/beomIJ88KilHDiz3fz6p/A+sObiJP5TUs xlQmKFSGBFiyXF+++EFUN4Clr6eqsOVzuvntc/TyRyY1PzsEF8fGmOt50qfgxLtv6unQ yWTg== ARC-Message-Signature: i=1; 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Once we have fully converted the tree we should probably move this extern to another header. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8830546121..209b88e559 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -454,6 +454,20 @@ extern CPUTailQ cpus; #define CPU_FOREACH_SAFE(cpu, next_cpu) \ QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) +/** + * current_cpu - TLS pointing to the current executing CPU + * + * current_cpu is a thread local convenience variable containing that + * threads executing CPUState. It is intended to be used deep in + * accelerator related operations where passing down CPUState is too + * fiddly. + * + * Its use in HW emulation is heavily discouraged in new code as not + * all memory accesses will necessarily be from an executing CPU (e.g. + * from a debugger). HW emulation should be using MemTxAttrs to derive + * the exact source of a memory access. If the access is from a CPU it + * can be derived from qemu_get_cpu(cpu_index). + */ extern __thread CPUState *current_cpu; /**