From patchwork Thu Nov 17 21:03:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 626380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 263CEC43217 for ; Thu, 17 Nov 2022 21:05:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240745AbiKQVFG (ORCPT ); Thu, 17 Nov 2022 16:05:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240076AbiKQVEu (ORCPT ); Thu, 17 Nov 2022 16:04:50 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78BEA8E2A5 for ; Thu, 17 Nov 2022 13:04:07 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id kt23so8212816ejc.7 for ; Thu, 17 Nov 2022 13:04:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X3nU7X0djX9jQ80iI8+t0kZ5Fy4kB3s5F+snjwXKwEE=; b=x0/2+JLtr5Wevfc3DaNs8djNaF+ABrzMQdBLyBvmMIRdvFr6TTAal/W4ymfMF/LlMm UmJRTSm/5ZTxaaFM+jIxzkNZt/gGSeS94TkXx6WN8rWl7SsHcL0P9Dzz+sVnmPvFa5OY zJe1wFSiHOnYcbK5spt/YUA+pX2CpMN2X5HCQxWMCok+28apKKiMYIznTp6dENuNVIbH 5a4KZsa0LSxYYLUSkVZ5hMRsVQ4tnnjBL2eq0rB9hADwj/LotVke1a/rmuiScWKgwFPb 9yHqrhNxV5adPmAm5q/DnxiqoWKxH/nf/e9WDHuxJHHT6hh3r0fpL+BaiJqrcrxrqF5D oPBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X3nU7X0djX9jQ80iI8+t0kZ5Fy4kB3s5F+snjwXKwEE=; b=HBUjr2kgHegrs5orma0LuPb7vkF4vniPQKI+uDN1tW3htML8FiLd7PbgxwoVRJMdka FNumxTrs7fA3nM/yndOEV2EZ9XCPe34dXF3dhbg3l2a4DRGgy6KcuDcZMJip+GLF4UVr gA8B3HKOSbCw0eilKNzZqFudP8+TKWpxrN0SKXD7sXez5GO0t1Uyq/OSPQsLBUhjbizF PMkhCTXMJZzJZ+zNk6XfhO9MBrG85lyc8NO7RxrzlEYOOCKAcRS0MO/k+IDqbandGupj R6kB+hZnoXSe7sqKFBv0IlsrPbIG1UcAL81dv1RD04E/BmfQ594hXRV5SVol6Tk1ecmK I/jg== X-Gm-Message-State: ANoB5pl8Nym+W0rEbbgH2lzkTaUytsD0TTn7JBvP37eadEduuY9QN6gj aRNBgkaEiT5lVNCtwq1fWST9Tw== X-Google-Smtp-Source: AA0mqf4uoNtESHdzhp16/6ko0ItxfiZu0quayLxZD4UoKpS1Y/Tuw9fVd+KNhzvHX8Qelbqbvsb62A== X-Received: by 2002:a17:906:4e46:b0:7ae:129b:2d3a with SMTP id g6-20020a1709064e4600b007ae129b2d3amr3568516ejw.552.1668719045581; Thu, 17 Nov 2022 13:04:05 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:05 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 2/7] dt-bindings: irq: mtk, sysirq: add support for mt8365 Date: Thu, 17 Nov 2022 22:03:51 +0100 Message-Id: <20221117210356.3178578-3-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding documentation of mediatek,sysirq for mt8365 SoC. Signed-off-by: Bernhard Rosenkränzer --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 84ced3f4179b9..3ffc60184e445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. - reg: Physical base address of the intpol registers and length of memory From patchwork Thu Nov 17 21:03:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 626379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C46BC43219 for ; Thu, 17 Nov 2022 21:05:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240571AbiKQVFb (ORCPT ); Thu, 17 Nov 2022 16:05:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240562AbiKQVE4 (ORCPT ); Thu, 17 Nov 2022 16:04:56 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E2CD90587 for ; Thu, 17 Nov 2022 13:04:12 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id ud5so8250809ejc.4 for ; Thu, 17 Nov 2022 13:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cOZMxW37BY8Yd9fEGMThaSEaaYa1HlPqz2FtFLwUuYk=; b=kR8n89044TBqJ54l4lMHOxRV7EqoXki+eLerysd/jNKPYGrAgxT799qR28Qvy/LCJX in49v01xRAuavqdSJSNE+XvSNP9EjMvNp4AM++hjjJD5029gwjysKmNLLwPmk2gbblOt Bcz4U54Rv+ENpz/1P74mPIQ1ZwCj8reBpQwVGykfGJ64rXJ0az+imp5MWD+EukriXf2f xD6ikXLo/tzc+bODI2IFP+DDOXZnuq0i8gR+Pup1MdF3McRAG/9SYACWT3BSzGPsfxuO HohqWTodc3G+LuF6Q0LMJfM8QLl0NCQmXDVFI6YirVVTX0IMKc/KkHe2VvvCyKD/8TWm T3bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cOZMxW37BY8Yd9fEGMThaSEaaYa1HlPqz2FtFLwUuYk=; b=ekKfWyEg8ydO7fUpIaF9QEyBBWS6piYIJmpNG03EF6R+QEGtLdVTkMk1zzwq9k8nc9 UMYgkgxxijSTNMB4pZ1fuLlPXfC60LrD1czSvcum69/H6BfeaRn1VbTkMGOa8t6QkgF8 QKBgOSP37f6hRdYHjHxn/XoaNF2e3UoVV3ySX32pht2CYuaFfukkkv4NBjP1iiGX9wKQ f92tVfP2qEMV7K7KwaKpYHj0ftIveEBhRZg+pvQvUjOEaeW8tdu0JMFuPZWDUAkowzbC GqWV16muLUbM7SCRVuFZCgsnCkPSpBKb5oYPUN0HKKM6fOMp+ScMYUVcKHqNvb+UIX9g QNKg== X-Gm-Message-State: ANoB5plOdl+1gxzPSG4x4lxT7ksz48xJRnyP2BOHtMKbM4TehBUWv9HN Rha4M2vVYMzjGiMQ6ls1XKC6qA== X-Google-Smtp-Source: AA0mqf7GVJmPGe5w3OiV7GSu8z66QxmncDwrO3Radqx3bd+fbpsX4JPWp837tyt8F7gTqW3iiR3Cfg== X-Received: by 2002:a17:906:ef1:b0:78d:260d:a6e4 with SMTP id x17-20020a1709060ef100b0078d260da6e4mr3532130eji.93.1668719047430; Thu, 17 Nov 2022 13:04:07 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:06 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 4/7] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Date: Thu, 17 Nov 2022 22:03:53 +0100 Message-Id: <20221117210356.3178578-5-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkränzer --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 0000000000000..7758644da302a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkränzer + +description: |+ + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + pins-are-numbered: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Specify the subnodes are using numbered pinmux to specify pins. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + 'pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pull up + settings for 2 pull resistors, R0 and R1. User can configure those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + pio-pins { + pins { + pinmux = , ; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + }; + }; From patchwork Thu Nov 17 21:03:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 626378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 600ACC4332F for ; Thu, 17 Nov 2022 21:05:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240574AbiKQVFe (ORCPT ); Thu, 17 Nov 2022 16:05:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240648AbiKQVE5 (ORCPT ); Thu, 17 Nov 2022 16:04:57 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 237E68E2B2 for ; Thu, 17 Nov 2022 13:04:13 -0800 (PST) Received: by mail-ed1-x52d.google.com with SMTP id z20so2913928edc.13 for ; Thu, 17 Nov 2022 13:04:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g6+ABKaCFT5+1C0Y5clbHMJQa6kjF8TIULfr4cCgl3o=; b=u4zUPtRBGTY9L9LHvnW9DqAWYRm0igVQllWoBz7XgHmcYSdMBuVAy58/lGWh4Dilqg 1UGWqw1Tezv5eZIYrQAdS5o5Y1q3ZB5f7z3i9FiJjFpOBmoKbUvRPlKrhKORJiYDLCA5 Pxu4VRIheLOlOvgE8Q7uWtouFjvgiuGkDdNjTP7dtEzfOp32WFKde4Sur0OYVYFhwHig ej/t/AXSZK8srV7eq50+nqPGqdyKShmDbKr5Vy2Pb5n1c1+TBEbgFx4xRQmV7BdicTpY 2McR2oldXKaFyZNjoYkZerusy/kP6ufcoRqtvQa+Fw+QK38iG4Ra7be2auIaioimyX+D xsjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g6+ABKaCFT5+1C0Y5clbHMJQa6kjF8TIULfr4cCgl3o=; b=yP0/19ET0icI0fEQI8ymPlyncXBf/2T3u6LKkVhItLHnGltcp4QYSL1LhKZ8Myms8Y LC8rHk8TpwGaUFh5dt0FrrlOSSww6tEueDnDQOzuaFX55uiWgLcuUQPZR91yNuHYVY5G lWMZzBgzRzg0kCJFt/5IPkdtNFFnkk3P7CZMaBmfRCgj5JxjJRb1hjN2yxikfADYoEVG OAqrhATMfuZHb1NU4y8PI3csE6lxFqfrM+E0T4Upfl6kP9Pu24nXojBKuFs2lJ+TP3UN O567CAb355lU+Xb82goA3RUiTcpMy0yLHFmpnMMeC/UvBcId3I1g7Qn4LFumrmC75pAn yP0A== X-Gm-Message-State: ANoB5pndmv+hMRVpb2+M8kulCHUbupWwWL4GozNIK1VtPoKAr6aZ7dq8 CFLe2sFf8Sl3MGwRaqmnUlwJTQ== X-Google-Smtp-Source: AA0mqf74WUgvaOJMRkg/rYttZ/P7xDEgL2yEBGs7v+osI383w3rkMb4HYPZYzRoe7OA5C12sjAKUGg== X-Received: by 2002:a05:6402:176c:b0:463:c5f7:fae with SMTP id da12-20020a056402176c00b00463c5f70faemr3583579edb.152.1668719049319; Thu, 17 Nov 2022 13:04:09 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b00461c6e8453dsm970807edt.23.2022.11.17.13.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 13:04:08 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogiocchino.delregno@collabora.com Subject: [PATCH v3 6/7] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings Date: Thu, 17 Nov 2022 22:03:55 +0100 Message-Id: <20221117210356.3178578-7-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221117210356.3178578-1-bero@baylibre.com> References: <20221117210356.3178578-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkränzer --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 939623867a646..3b92725bbc99b 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci reg: