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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t1-20020a1c7701000000b003cf4d99fd2asm13296725wmi.6.2022.11.21.05.02.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 05:02:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/5] hw/sd: Fix sun4i allwinner-sdhost for U-Boot Date: Mon, 21 Nov 2022 13:02:35 +0000 Message-Id: <20221121130239.1138631-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121130239.1138631-1-peter.maydell@linaro.org> References: <20221121130239.1138631-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Strahinja Jankovic Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot access SD card. The problem is that FIFO register in current allwinner-sdhost implementation is at the address corresponding to Allwinner H3, but not A10. Linux kernel is not affected since Linux driver uses DMA access and does not use FIFO register for reading/writing. This patch adds new class parameter `is_sun4i` and based on that parameter uses register at offset 0x100 either as FIFO register (if sun4i) or as threshold register (if not sun4i; in this case register at 0x200 is FIFO register). Tested with U-Boot and Linux kernel image built for Cubieboard and OrangePi PC. Signed-off-by: Strahinja Jankovic Reviewed-by: Peter Maydell Message-id: 20221112214900.24152-1-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell --- include/hw/sd/allwinner-sdhost.h | 1 + hw/sd/allwinner-sdhost.c | 67 ++++++++++++++++++++++---------- 2 files changed, 47 insertions(+), 21 deletions(-) diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h index bfe08ff4ef2..30c1e604041 100644 --- a/include/hw/sd/allwinner-sdhost.h +++ b/include/hw/sd/allwinner-sdhost.h @@ -130,6 +130,7 @@ struct AwSdHostClass { /** Maximum buffer size in bytes per DMA descriptor */ size_t max_desc_size; + bool is_sun4i; }; diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index 455d6eabf64..51e5e908307 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -65,7 +65,7 @@ enum { REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ - REG_SD_THLDC = 0x100, /* Card Threshold Control */ + REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ @@ -415,10 +415,29 @@ static void allwinner_sdhost_dma(AwSdHostState *s) } } +static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s) +{ + uint32_t res = 0; + + if (sdbus_data_ready(&s->sdbus)) { + sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t)); + le32_to_cpus(&res); + allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); + allwinner_sdhost_auto_stop(s); + allwinner_sdhost_update_irq(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", + __func__); + } + + return res; +} + static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, unsigned size) { AwSdHostState *s = AW_SDHOST(opaque); + AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s); uint32_t res = 0; switch (offset) { @@ -508,8 +527,12 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ res = s->dmac_irq; break; - case REG_SD_THLDC: /* Card Threshold Control */ - res = s->card_threshold; + case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */ + if (sc->is_sun4i) { + res = allwinner_sdhost_fifo_read(s); + } else { + res = s->card_threshold; + } break; case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ res = s->startbit_detect; @@ -531,16 +554,7 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, res = s->status_crc; break; case REG_SD_FIFO: /* Read/Write FIFO */ - if (sdbus_data_ready(&s->sdbus)) { - sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t)); - le32_to_cpus(&res); - allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t)); - allwinner_sdhost_auto_stop(s); - allwinner_sdhost_update_irq(s); - } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n", - __func__); - } + res = allwinner_sdhost_fifo_read(s); break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" @@ -553,11 +567,20 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, return res; } +static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value) +{ + uint32_t u32 = cpu_to_le32(value); + sdbus_write_data(&s->sdbus, &u32, sizeof(u32)); + allwinner_sdhost_update_transfer_cnt(s, sizeof(u32)); + allwinner_sdhost_auto_stop(s); + allwinner_sdhost_update_irq(s); +} + static void allwinner_sdhost_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { AwSdHostState *s = AW_SDHOST(opaque); - uint32_t u32; + AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s); trace_allwinner_sdhost_write(offset, value, size); @@ -657,18 +680,18 @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset, s->dmac_irq = value; allwinner_sdhost_update_irq(s); break; - case REG_SD_THLDC: /* Card Threshold Control */ - s->card_threshold = value; + case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */ + if (sc->is_sun4i) { + allwinner_sdhost_fifo_write(s, value); + } else { + s->card_threshold = value; + } break; case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ s->startbit_detect = value; break; case REG_SD_FIFO: /* Read/Write FIFO */ - u32 = cpu_to_le32(value); - sdbus_write_data(&s->sdbus, &u32, sizeof(u32)); - allwinner_sdhost_update_transfer_cnt(s, sizeof(u32)); - allwinner_sdhost_auto_stop(s); - allwinner_sdhost_update_irq(s); + allwinner_sdhost_fifo_write(s, value); break; case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ @@ -834,12 +857,14 @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data) { AwSdHostClass *sc = AW_SDHOST_CLASS(klass); sc->max_desc_size = 8 * KiB; + sc->is_sun4i = true; } static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data) { AwSdHostClass *sc = AW_SDHOST_CLASS(klass); sc->max_desc_size = 64 * KiB; + sc->is_sun4i = false; } static const TypeInfo allwinner_sdhost_info = { From patchwork Mon Nov 21 13:02:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 627253 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1737270pvb; Mon, 21 Nov 2022 05:03:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Bib68aQOfrK3mNcPfhZ/dlOZ6Ns3OawmcucK5uD9x0WZisJ368fAE+hl+DRmvRcyI99mq X-Received: by 2002:ad4:4492:0:b0:4c6:a70c:75fe with SMTP id m18-20020ad44492000000b004c6a70c75femr6491403qvt.24.1669035796501; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t1-20020a1c7701000000b003cf4d99fd2asm13296725wmi.6.2022.11.21.05.02.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 05:02:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/5] hw/intc: clean-up access to GIC multi-byte registers Date: Mon, 21 Nov 2022 13:02:36 +0000 Message-Id: <20221121130239.1138631-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121130239.1138631-1-peter.maydell@linaro.org> References: <20221121130239.1138631-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée gic_dist_readb was returning a word value which just happened to work as a result of the way we OR the data together. Lets fix it so only the explicit byte is returned for each part of GICD_TYPER. I've changed the return type to uint8_t although the overflow is only detected with an explicit -Wconversion. Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab4..1a04144c38b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -941,7 +941,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) gic_update(s); } -static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) +static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; uint32_t res; @@ -955,6 +955,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) cm = 1 << cpu; if (offset < 0x100) { if (offset == 0) { /* GICD_CTLR */ + /* We rely here on the only non-zero bits being in byte 0 */ if (s->security_extn && !attrs.secure) { /* The NS bank of this register is just an alias of the * EnableGrp1 bit in the S bank version. @@ -964,11 +965,14 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) return s->ctlr; } } - if (offset == 4) - /* Interrupt Controller Type Register */ - return ((s->num_irq / 32) - 1) - | ((s->num_cpu - 1) << 5) - | (s->security_extn << 10); + if (offset == 4) { + /* GICD_TYPER byte 0 */ + return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5); + } + if (offset == 5) { + /* GICD_TYPER byte 1 */ + return (s->security_extn << 2); + } if (offset < 0x08) return 0; if (offset >= 0x80) { From patchwork Mon Nov 21 13:02:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 627255 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1739202pvb; Mon, 21 Nov 2022 05:05:43 -0800 (PST) X-Google-Smtp-Source: AA0mqf5JHltXGuqgX5MpGQHwwROUxvrnytE2ND3aIK1dyfH363CVun9nVj2vdAZuv/YrllNMcvQ3 X-Received: by 2002:a05:6102:a4c:b0:3aa:2125:2573 with SMTP id i12-20020a0561020a4c00b003aa21252573mr2853220vss.59.1669035943009; Mon, 21 Nov 2022 05:05:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669035943; cv=none; d=google.com; s=arc-20160816; b=KVUXjXChlVkPJ6cMi7jRuwy8hr/oKI5GnQ7zubhAjmgXZfJe07boMezIbR/MkZWYnc EWomY32Zw3b3MlAOguhCB8yWrHqnV/+4LOgA2eTVnrgj3nDA7zFdXR+JCdjBWnz3zRd9 Vq34fiuwv3Kf6QkCjD7ApXHbduEQQ4ugtueAfmn76hQNf10lfX91kBPIh/sFCejxUUBW cmjoPZSm0FeFo/BV+ad2XblDJuEIo4coaCf3jJMRHzVmXslZwrmImZNLJ9/5dh0oMG5s SlU1BatRuZ2YLcM4Ucq0ZjJbP3ct1wB/kwX+RpXUGsj5JCtWVs3zHvL4x1e7f3S7Opxs GqQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dfFlEzHVaLMstRWNXLjvHFrz5cabOw805eWOhqpeeRA=; b=zUjwiqdhW9tolbfoNQVuVBOGyAPW8edl0ZIPVmB9X5M+YMtdVINRI9WDEE7Tlsx7KT fVYGpWG655mQfcPzJrSxxH8p7ly4HVLEJY+rq7CqaqfJ7aEbOfTTMdEEurFn6h6RxxMc WlykfjBfwQyeskZq2ct2t/avpNj4PcSOcJcw955Z1nG/NXxbgjP8w3Ffk/u/rpXL7IV+ NW1EV1FsKmHjkCtmTly226p3DpIDXVi0j0r83L1kBA+nt/jpQ4i4an/x3syO6gYbogIv 3nAIyrB6hqE/A2sry+OBBskYSnq/fhGPjlxCWlBAcWltckHyP+VGabD7+uZZFEleuXwd YGiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oRH6dU8H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t1-20020a1c7701000000b003cf4d99fd2asm13296725wmi.6.2022.11.21.05.02.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 05:02:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/5] hw/intc: add implementation of GICD_IIDR to Arm GIC Date: Mon, 21 Nov 2022 13:02:37 +0000 Message-Id: <20221121130239.1138631-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121130239.1138631-1-peter.maydell@linaro.org> References: <20221121130239.1138631-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented this for the CPU interface register. The fact we don't implement it shows up when running Xen with -d guest_error which is definitely wrong because the guest is perfectly entitled to read it. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1a04144c38b..7a34bc0998a 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -973,8 +973,18 @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) /* GICD_TYPER byte 1 */ return (s->security_extn << 2); } - if (offset < 0x08) + if (offset == 8) { + /* GICD_IIDR byte 0 */ + return 0x3b; /* Arm JEP106 identity */ + } + if (offset == 9) { + /* GICD_IIDR byte 1 */ + return 0x04; /* Arm JEP106 identity */ + } + if (offset < 0x0c) { + /* All other bytes in this range are RAZ */ return 0; + } if (offset >= 0x80) { /* Interrupt Group Registers: these RAZ/WI if this is an NS * access to a GIC with the security extensions, or if the GIC From patchwork Mon Nov 21 13:02:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 627252 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1737247pvb; Mon, 21 Nov 2022 05:03:14 -0800 (PST) X-Google-Smtp-Source: AA0mqf7rc3zpSWzudSPnb2JPcygm7fUcpKsGiZuQnUcx6DioNuH4XhN9mjJspWwT/fNooAR9R3yh X-Received: by 2002:a05:620a:600c:b0:6ee:ca6f:7652 with SMTP id dw12-20020a05620a600c00b006eeca6f7652mr16323400qkb.489.1669035794688; Mon, 21 Nov 2022 05:03:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669035794; cv=none; d=google.com; s=arc-20160816; b=i22TKYYtB7BlAd/RqPblvy11v1W31riZd+oF+g5OOD0GQBR5ZL+25K5Ty7ocFhgZ19 YKFAdRloAkLFl02Kp4489G8Pex/rcUsyvPCPjqtcw2CVs3VXnS/Nhr38ZA6tQ1DGrMaa qdmSMTgBQH/CpqjGMOHW07Ab0ATkl5UF3cnV/i8+vK6fYrwWkZ1/g0O1bT8KpqClKX5o a/YzM81iN+zZgMQHiYjNp21heaKAGyKLgrweK42YtmeNGv2hzIob3Qc3y5jlJ5TSm14B HgFZos8RBmz0hyeptmW4NDVdnfJifyp6oPfg7X8DuWjJERVFT7srgOO06DY61ahH3HRE fzQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fwMWmQZd9sBU28g/akDXkXxjGE4RWYE++luBOirwphw=; b=NIuQDvTtASnUePvFaYC8ruXhCm6w4+bSh5cKfdAn+s3sDS+CqpsZX3mc11UauTyAg8 Y5svBFwMR9ZA4TWvWT4FNDaaOtzpoVykD2LrQRVr4rZmaCiNkdLX66u8XfZHiojEktNy igxuBY+Vq8pT4aB9gSeJ4+SvnP6PksqPS7yIZwWS+4fZ37eMqLDu1OMudO8i7P1mC/GY Ex2p7DGD7agQ+dt9IwJHx2uNRLE3dkiDYoY/6jNbDQGHMHdNtgR2dknvsmsFphopfQfV m0U0yTfF4NMBZBVYJ+xAK8yDjoqyuDkkqMBTapGrl1d3ECD+DKG5UgrJM6uw1oOz3F4i LyPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kAR4MUmo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t1-20020a1c7701000000b003cf4d99fd2asm13296725wmi.6.2022.11.21.05.02.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 05:02:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/5] tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s Date: Mon, 21 Nov 2022 13:02:38 +0000 Message-Id: <20221121130239.1138631-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121130239.1138631-1-peter.maydell@linaro.org> References: <20221121130239.1138631-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The two tests tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2 tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3 take quite a long time to run, and the current timeout of 240s is not enough for the tests to complete on slow machines: we've seen these tests time out in the gitlab CI in the 'avocado-system-alpine' CI job, for instance. The timeout is also insufficient for running the test with a debug build of QEMU: on my machine the tests take over 10 minutes to run in that config. Push the timeout up to 720s so that the test definitely has enough time to complete. Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- tests/avocado/boot_linux.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py index 571d33882ae..32adae6ff6a 100644 --- a/tests/avocado/boot_linux.py +++ b/tests/avocado/boot_linux.py @@ -64,7 +64,7 @@ class BootLinuxAarch64(LinuxTest): :avocado: tags=machine:virt :avocado: tags=machine:gic-version=2 """ - timeout = 240 + timeout = 720 def add_common_args(self): self.vm.add_args('-bios', From patchwork Mon Nov 21 13:02:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 627257 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1740965pvb; Mon, 21 Nov 2022 05:08:20 -0800 (PST) X-Google-Smtp-Source: AA0mqf5LMtjzVTqteWoegrxhBuRbO3S+tIOJHoH/DpB+N3Qx8NHC9hmsb5vmuPRk+pF+weHeJ0gr X-Received: by 2002:a37:de14:0:b0:6fa:189d:733b with SMTP id h20-20020a37de14000000b006fa189d733bmr580117qkj.20.1669036100203; Mon, 21 Nov 2022 05:08:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669036100; cv=none; d=google.com; s=arc-20160816; b=vsv61L1EErQdJ8k2vVSsu3vtADAzSYvrAfYsb+u6MqkRpKBWFLpmOoQEwmPEaWtLjH Xy+WJ4ZMkd/PR5h/NRzMLvJ/6G49twgArvKZBvFAjZWVmOKmTUs8kyeq4LtMy0QRKCKl NyYPHtU7T9Ninel+TA5cMieOpCRnmHYsD6b6EBSZ6plIr/HwIKUHlViJpTw1hdcNrMAi iR7p7eYGfLudUMVYcPc/4JUizBKmHjPBTXKU+5mUTlVc5GijLqnq0cblYgcpgAiw9jU9 I8pA0tiSqLPfChvmuScsYAxK8x9jBxVs7HzOpTdAd16ZDCSOKH7A8m9aE6mAbYDOPtVS xDeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JBNmxcqLBxZag1unF7NOFteCv/IX3kebN57U4uPMAOo=; b=qh9+6Lbry6wDphfnimp1Ea3IqP78KgGtDb8XQGOAuthd2iZH6YxtzCmR+kkr9ZFCeE F+Tmmo5ivKs539KBKw91DxYvNuXhtJX/IFnw2exOArik0FSzAkR079j1MfBGDHTWsa0L /5yr631tfYh8IH4OTZgYfnB6hPynBR2LZTpVH1oNk0Y9G7qN+6CyrDhInIBAxozm/1jB TsN9JzlXzzKEZ3kt0/abfvZOkCh9MhXDEQoc31PCm9SOu0cjs4YjFSY0GwRvoY1rXFAZ wjHW5TPhDzESr8CfYCoo3kiI5CADqnjng3b4WQEDm/vbP5iq65S5Mx4bdM4uasSK/l4V BHKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iQXSb9MM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t1-20020a1c7701000000b003cf4d99fd2asm13296725wmi.6.2022.11.21.05.02.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 05:02:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/5] target/arm: Limit LPA2 effective output address when TCR.DS == 0 Date: Mon, 21 Nov 2022 13:02:39 +0000 Message-Id: <20221121130239.1138631-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221121130239.1138631-1-peter.maydell@linaro.org> References: <20221121130239.1138631-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ard Biesheuvel With LPA2, the effective output address size is at most 48 bits when TCR.DS == 0. This case is currently unhandled in the page table walker, where we happily assume LVA/64k granule when outputsize > 48 and param.ds == 0, resulting in the wrong conversion to be used from a page table descriptor to a physical address. if (outputsize > 48) { if (param.ds) { descaddr |= extract64(descriptor, 8, 2) << 50; } else { descaddr |= extract64(descriptor, 12, 4) << 48; } So cap the outputsize to 48 when TCR.DS is cleared, as per the architecture. Cc: Peter Maydell Cc: Philippe Mathieu-Daudé Cc: Richard Henderson Signed-off-by: Ard Biesheuvel Reviewed-by: Richard Henderson Message-id: 20221116170316.259695-1-ardb@kernel.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3745ac97234..9a6277d862f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1222,6 +1222,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, ps = MIN(ps, param.ps); assert(ps < ARRAY_SIZE(pamax_map)); outputsize = pamax_map[ps]; + + /* + * With LPA2, the effective output address (OA) size is at most 48 bits + * unless TCR.DS == 1 + */ + if (!param.ds && param.gran != Gran64K) { + outputsize = MIN(outputsize, 48); + } } else { param = aa32_va_parameters(env, address, mmu_idx); level = 1;