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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id h127si1137753pfb.213.2019.03.20.01.08.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:08:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=zQZHLP5h; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B726C211E0112; Wed, 20 Mar 2019 01:08:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::443; helo=mail-pf1-x443.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E5E0C211E0105 for ; Wed, 20 Mar 2019 01:08:46 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id v21so1328015pfm.12 for ; Wed, 20 Mar 2019 01:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nStjCkDwSvD7Acz71PF2JEFATBKIYWPp45M7q5OoJsA=; b=zQZHLP5hEL/aJ3fgvSfbZoQyWGxXMwKWTwDBEy3AgTGEMmySMKtEjQR6bXlpi0sEYX 5ieBr7gpR0lrJd2gMRbqinSGVQ83zScHVV1W7Bf+2Fm1SOH88QEMXoyMVtIaLJZffEJI 3dN6g5AsXRKT0pp5CsSBXQHykK4HWX+DSjUf9bpvxl9TVuGATFC5ibatqbFkM6mAEhj2 51ccv4+1QCLwx8MuzYt0KlJE0jFxJ5YBb0NRBKq8lDnnXhmCNnrKGVN8as4l0azKsKVj Ig8BGe+MubiIt/hy5Z94mtXfgfaQu03k5n2vGFGjg4SYU4r+8LgqJdr0Ep0+mQ9O2kPN RUYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nStjCkDwSvD7Acz71PF2JEFATBKIYWPp45M7q5OoJsA=; b=TlWT/hyc8iQfjU/kMtJRauM1nC7Ad644T/FxS5I+aOZMssACMAI022i2Gv5vNYhhFG s91GZ0xQXhFawc757Qf0THqJXRAPZ6JBN05/ji0W1J9wYgwSRU70X2YrHatE21rMn6CP vMWoRf0bfezUZHnxegx8WOhs/IJ7GVCKzDBAD79xPSkMNO/+z8zUrtPLrxjwBdB2J4Pq 6JxqMG7E6j/jCeRE+bDZo2z0/wA2l+CzaYmn3+9yW4GCH/jD3ZfJeyAYWgpz+zNVoso7 xfl56wbrRNt6tmQDb3gkN30A4Amp76Hp65JIy31WUqu0kPLSR8JmAx48AQlpLcYlmLVl KL5A== X-Gm-Message-State: APjAAAXzX2TkprpW2wDQViQCf8Ww2pUdy+H7NRaGnTkugwZkNiFnOAEd Qk9NUHUTHNq6mRbopIev+URbCg== X-Received: by 2002:a17:902:be09:: with SMTP id r9mr7096801pls.189.1553069326283; Wed, 20 Mar 2019 01:08:46 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.08.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:08:45 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:12 +0800 Message-Id: <20190320080829.52003-2-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 01/18] Hisilicon/D0x: Remove and tidy some codes about SerdesLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" As some definitions are about OemMiscLib, so move them from SerdesLib.h to OemMiscLib.h and drop some useless function definitions. After doing this, some unnecessary references can be removed for D03/D05. SerdesLib is useless for SmbiosMiscDxe and D06, so remove it and delete SerdesLib.h for D06. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D06/D06.dsc | 2 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 109 -------------------- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 64 ------------ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h | 85 --------------- Silicon/Hisilicon/Include/Library/OemMiscLib.h | 75 ++++++++++++++ Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 1 - Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c | 1 - Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 1 - Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c | 2 +- 11 files changed, 77 insertions(+), 266 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 396bd03c9d24..cbbd99e4a659 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -64,8 +64,6 @@ [LibraryClasses.common] CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf - SerdesLib|Silicon/Hisilicon/Hi1620/Library/Hi1620Serdes/Hi1620SerdesLib.inf - TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf index 61cead7779b9..669e6a2d52cc 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -69,6 +69,7 @@ [LibraryClasses] BaseMemoryLib BaseLib DebugLib + OemMiscLib UefiBootServicesTableLib UefiRuntimeServicesTableLib UefiDriverEntryPoint @@ -77,7 +78,6 @@ [LibraryClasses] IpmiCmdLib - SerdesLib [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 077dd5edc847..b493dd9ac090 100755 --- a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -16,116 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_ -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Sas0X8 = 2, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - -typedef enum { - Em32coreEvbBoard = 0, - Em16coreEvbBoard = 1, - EmV2R1CO5Borad = 2, - EmOtherBorad -} BOARD_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); - EFI_STATUS EfiSerdesInitWrap (VOID); -void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg); - -//EYE test -UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData); - -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - -//PRBS test -int serdes_prbs_test(UINT8 macro, UINT8 lane, UINT8 prbstype); - -int serdes_prbs_test_cancle(UINT8 macro,UINT8 lane); - -//CTLE/DFE -void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane); - -void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane); - -void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane); -//int serdes_reset(UINT32 macro); -//int serdes_release_reset(UINT32 macro); -void Custom_Wave(UINT32 macro,UINT32 lane,UINT32 mode); -void serdes_ffe_show(UINT32 macro,UINT32 lane); -void serdes_dfe_show(UINT32 macro,UINT32 lane); -int serdes_read_bert(UINT8 macro, UINT8 lane); -void serdes_clean_bert(UINT8 macro, UINT8 lane); -int serdes_get_four_point_eye_diagram(UINT32 macro, UINT32 lane,UINT32 eyemode, UINT32 data_rate); -void serdes_release_mcu(UINT32 macro,UINT32 val); -int hilink_write(UINT32 macro, UINT32 reg, UINT32 value); -int hilink_read(UINT32 macro, UINT32 reg, UINT32 *value); -int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);//TXRXPARLPBKEN -int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val); -int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val); -void serdes_ctle_show(UINT32 macro,UINT32 lane); -int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num); -int serdes_ds_write(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value); -int serdes_ds_read(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num); -int report_serdes_mux(void); -int serdes_key_reg_show(UINT32 macro); -void serdes_state_show(UINT32 macro); -UINT32 Serdes_ReadBert(UINT32 ulMacroId , UINT32 ulDsNum); - #endif diff --git a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h index 7ff924bd8954..b493dd9ac090 100644 --- a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h +++ b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h @@ -16,71 +16,7 @@ #ifndef _SERDES_LIB_H_ #define _SERDES_LIB_H_ -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType(UINT8 EthChannel); -VOID SerdesEnableCtleDfe(UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - EFI_STATUS EfiSerdesInitWrap (VOID); -INT32 SerdesReset(UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro); #endif diff --git a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h deleted file mode 100644 index 05f0f7020e82..000000000000 --- a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h +++ /dev/null @@ -1,85 +0,0 @@ -/** @file -* -* Copyright (c) 2018, Hisilicon Limited. All rights reserved. -* Copyright (c) 2018, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -typedef enum { - EmHilink0Hccs1X8 = 0, - EmHilink0Pcie1X8 = 2, - EmHilink0Pcie1X4Pcie2X4 = 3, - EmHilink0Sas2X8 = 4, - EmHilink0Hccs1X8Width16, - EmHilink0Hccs1X8Width32, - EmHilink0Hccs1X8Speed5G, -} HILINK0_MODE_TYPE; - -typedef enum { - EmHilink1Sas2X1 = 0, - EmHilink1Hccs0X8 = 1, - EmHilink1Pcie0X8 = 2, - EmHilink1Hccs0X8Width16, - EmHilink1Hccs0X8Width32, - EmHilink1Hccs0X8Speed5G, -} HILINK1_MODE_TYPE; - -typedef enum { - EmHilink2Pcie2X8 = 0, - EmHilink2Hccs2X8 = 1, - EmHilink2Sas0X8 = 2, - EmHilink2Hccs2X8Width16, - EmHilink2Hccs2X8Width32, - EmHilink2Hccs2X8Speed5G, -} HILINK2_MODE_TYPE; - -typedef enum { - EmHilink5Pcie3X4 = 0, - EmHilink5Pcie2X2Pcie3X2 = 1, - EmHilink5Sas1X4 = 2, -} HILINK5_MODE_TYPE; - - -typedef struct { - HILINK0_MODE_TYPE Hilink0Mode; - HILINK1_MODE_TYPE Hilink1Mode; - HILINK2_MODE_TYPE Hilink2Mode; - UINT32 Hilink3Mode; - UINT32 Hilink4Mode; - HILINK5_MODE_TYPE Hilink5Mode; - UINT32 Hilink6Mode; - UINT32 UseSsc; -} SERDES_PARAM; - -#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF -#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF -#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF - -typedef struct { - UINT32 MacroId; - UINT32 DsNum; - UINT32 DsCfg; -} SERDES_POLARITY_INVERT; - -EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId); -extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; -extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; -UINT32 GetEthType (UINT8 EthChannel); -VOID SerdesEnableCtleDfe (UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode); - -EFI_STATUS EfiSerdesInitWrap (UINT32 RateMode); -INT32 SerdesReset (UINT32 SiclId, UINT32 Macro); -VOID SerdesLoadFirmware (UINT32 SiclId, UINT32 Macro); -INT32 h30_serdes_run_firmware (UINT32 nimbus_id, UINT32 macro, UINT8 DsMask, UINT8 ctle_mode); -#endif diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h index 86ea6a1b3deb..b5a768856484 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -22,6 +22,67 @@ #include #include +#define HCCS_PLL_VALUE_2600 0x52240681 +#define HCCS_PLL_VALUE_2800 0x52240701 +#define HCCS_PLL_VALUE_3000 0x52240781 + +typedef enum { + EmHilink0Hccs1X8 = 0, + EmHilink0Pcie1X8 = 2, + EmHilink0Pcie1X4Pcie2X4 = 3, + EmHilink0Sas2X8 = 4, + EmHilink0Hccs1X8Width16, + EmHilink0Hccs1X8Width32, + EmHilink0Hccs1X8Speed5G, +} HILINK0_MODE_TYPE; + +typedef enum { + EmHilink1Sas2X1 = 0, + EmHilink1Hccs0X8 = 1, + EmHilink1Pcie0X8 = 2, + EmHilink1Hccs0X8Width16, + EmHilink1Hccs0X8Width32, + EmHilink1Hccs0X8Speed5G, +} HILINK1_MODE_TYPE; + +typedef enum { + EmHilink2Pcie2X8 = 0, + EmHilink2Hccs2X8 = 1, + EmHilink2Sas0X8 = 2, + EmHilink2Hccs2X8Width16, + EmHilink2Hccs2X8Width32, + EmHilink2Hccs2X8Speed5G, +} HILINK2_MODE_TYPE; + +typedef enum { + EmHilink5Pcie3X4 = 0, + EmHilink5Pcie2X2Pcie3X2 = 1, + EmHilink5Sas1X4 = 2, +} HILINK5_MODE_TYPE; + + +typedef struct { + HILINK0_MODE_TYPE Hilink0Mode; + HILINK1_MODE_TYPE Hilink1Mode; + HILINK2_MODE_TYPE Hilink2Mode; + UINT32 Hilink3Mode; + UINT32 Hilink4Mode; + HILINK5_MODE_TYPE Hilink5Mode; + UINT32 Hilink6Mode; + UINT32 UseSsc; +} SERDES_PARAM; + +#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF + +typedef struct { + UINT32 MacroId; + UINT32 DsNum; + UINT32 DsCfg; +} SERDES_POLARITY_INVERT; + + #define PCIEDEVICE_REPORT_MAX 8 #define MAX_PROCESSOR_SOCKETS MAX_SOCKET #define MAX_MEMORY_CHANNELS MAX_CHANNEL @@ -53,4 +114,18 @@ BOOLEAN OemIsNeedDisableExpanderBuffer(VOID); extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); +UINTN OemGetCpuFreq (UINT8 Socket); + +UINTN +OemGetHccsFreq ( + VOID + ); + +EFI_STATUS +OemGetSerdesParam ( + SERDES_PARAM *ParamA, + SERDES_PARAM *ParamB, + UINT32 SocketId + ); + #endif diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 4771cb900c82..218b3540eb7f 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -21,7 +21,6 @@ #include #include -#include #include #include diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c index ae4c194070e8..1a9ed620c80c 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -22,7 +22,6 @@ #include #include #include -#include #include diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c index 7e3f2e2a0e7d..c28ac6266fc6 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index 2a9db46d1ff9..c5cb77696031 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index bc33639ac51d..945fd4c6e3c0 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -17,7 +17,7 @@ #include "SmbiosMisc.h" -#include +#include extern SMBIOS_TABLE_TYPE9 MiscSystemSlotDesignationPcie0Data; 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Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 1 + Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 1 + Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf | 1 + Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf | 1 + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +- Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf | 1 + Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 1 + Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 1 + Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 1 + Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 22 ---- Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h | 22 ---- Silicon/Hisilicon/Include/Library/IpmiCmdLib.h | 110 ------------------- Silicon/Hisilicon/Include/Library/LpcLib.h | 113 -------------------- Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 45 -------- Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 112 ------------------- 20 files changed, 14 insertions(+), 426 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf index c65cf7b6dd9f..90e40ae2b393 100644 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf @@ -30,6 +30,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf index 0fa7fdf80fa8..c0195b2fa9cf 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf @@ -30,7 +30,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec - + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf index 0f6b68d4c88d..e82c9204d5d6 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -29,6 +29,7 @@ [Packages] ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf index 022c3e940a31..7ec577530610 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -30,6 +30,7 @@ [Packages] ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf index 8296ee02de4e..715a4efadde8 100644 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf @@ -29,6 +29,7 @@ [Packages] ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf index 75c5054bbfd1..9bc6eb549c41 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Platform/Hisilicon/D06/D06.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf index 93a2bcac3726..94f6fe404c6d 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf @@ -31,6 +31,7 @@ [Packages] IntelFrameworkPkg/IntelFrameworkPkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf index 2275586ff324..808da65cd429 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf @@ -32,6 +32,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec IntelFrameworkPkg/IntelFrameworkPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf index 669e6a2d52cc..0c37b53af987 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf @@ -58,7 +58,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec IntelFrameworkPkg/IntelFrameworkPkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec - + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf index c07a5b8aa250..5b917fd3fdea 100644 --- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf +++ b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf @@ -30,6 +30,7 @@ [Sources] [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf index 89447cc52d76..aa8e3c9c0b63 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf @@ -35,6 +35,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf index b603523100ae..d6b5248fcdbf 100644 --- a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf +++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf @@ -27,6 +27,7 @@ [Sources.common] [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec [LibraryClasses] diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf index 9bca88fe8702..e9520b39530e 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf index 1bb4f5c703bb..6211373ce7ba 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf @@ -31,6 +31,7 @@ [Packages] MdeModulePkg/MdeModulePkg.dec ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiliconNonOsi.dec Silicon/Hisilicon/HisiPkg.dec diff --git a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h deleted file mode 100755 index b493dd9ac090..000000000000 --- a/Silicon/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -EFI_STATUS -EfiSerdesInitWrap (VOID); - -#endif diff --git a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h deleted file mode 100644 index b493dd9ac090..000000000000 --- a/Silicon/Hisilicon/Hi1616/Include/Library/SerdesLib.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _SERDES_LIB_H_ -#define _SERDES_LIB_H_ - -EFI_STATUS -EfiSerdesInitWrap (VOID); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h deleted file mode 100644 index b956ee6d072a..000000000000 --- a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h +++ /dev/null @@ -1,110 +0,0 @@ -/** @file -* -* Copyright (c) 2017, Hisilicon Limited. All rights reserved. -* Copyright (c) 2017, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _IPMI_CMD_LIB_H_ -#define _IPMI_CMD_LIB_H_ - -#define BOOT_OPTION_BOOT_FLAG_VALID 1 -#define BOOT_OPTION_BOOT_FLAG_INVALID 0 - -typedef enum { - EfiReserved, - EfiBiosFrb2, - EfiBiosPost, - EfiOsLoad, - EfiSmsOs, - EfiOem, - EfiFrbReserved1, - EfiFrbReserved2 -} EFI_WDT_USER_TYPE; - -typedef enum { - NoOverride = 0x0, - ForcePxe, - ForceDefaultHardDisk, - ForceDefaultHardDiskSafeMode, - ForceDefaultDiagnosticPartition, - ForceDefaultCD, - ForceSetupUtility, - ForceRemoteRemovableMedia, - ForceRemoteCD, - ForcePrimaryRemoteMedia, - ForceRemoteHardDisk = 0xB, - ForcePrimaryRemovableMedia = 0xF -} BOOT_DEVICE_SELECTOR; - -// -// Get System Boot Option data structure -// -typedef struct { - UINT8 ParameterVersion :4; - UINT8 Reserved1 :4; - UINT8 ParameterSelector :7; - UINT8 ParameterValid :1; - // - // Boot Flags Data 1 - // - UINT8 Reserved2 :5; - UINT8 BiosBootType :1; - UINT8 Persistent :1; - UINT8 BootFlagsValid :1; - // - // Boot Flags Data 2 - // - UINT8 LockResetBtn :1; - UINT8 ScreenBlank :1; - UINT8 BootDeviceSelector :4; - UINT8 LockKeyboard :1; - UINT8 ClearCmos :1; - // - // Boot Flags Data 3 - // - UINT8 ConsoleRedirectionControl :2; - UINT8 LockSleepBtn :1; - UINT8 UserPasswordByPass :1; - UINT8 Reserved3 :1; - UINT8 FirmwareVerbosity :2; - UINT8 LockPowerBtn :1; - // - // Boot Flags Data 4 - // - UINT8 MuxControlOverride :3; - UINT8 ShareModeOverride :1; - UINT8 Reserved4 :4; - // - // Boot Flags Data 5 - // - UINT8 DeviceInstanceSelector :5; - UINT8 Reserved5 :3; -} IPMI_GET_BOOT_OPTION; - -EFI_STATUS -EFIAPI -IpmiCmdSetSysBootOptions ( - OUT IPMI_GET_BOOT_OPTION *BootOption - ); - -EFI_STATUS -EFIAPI -IpmiCmdGetSysBootOptions ( - IN IPMI_GET_BOOT_OPTION *BootOption - ); - -EFI_STATUS -IpmiCmdStopWatchdogTimer ( - IN EFI_WDT_USER_TYPE UserType - ); - -#endif diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h deleted file mode 100755 index 236a52ba45a7..000000000000 --- a/Silicon/Hisilicon/Include/Library/LpcLib.h +++ /dev/null @@ -1,113 +0,0 @@ -/** @file -* -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _LPC_LIB_H_ -#define _LPC_LIB_H_ - -#include - -#define PCIE_SUBSYS_IO_MUX 0xA0170000 -#define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) -#define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) -#define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90) -#define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4) -#define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8) -#define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC) -#define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0) -#define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4) -#define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8) - -#define IO_WRAP_CTRL_BASE 0xA0100000 -#define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0) -#define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4) -#define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8) -#define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac) -#define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8) -#define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc) -#define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0) -#define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4) -#define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028) - - -#define LPC_BASE 0xA01B0000 -#define LPC_START_REG (LPC_BASE + 0x00) -#define LPC_OP_STATUS_REG (LPC_BASE + 0x04) -#define LPC_IRQ_ST_REG (LPC_BASE + 0x08) -#define LPC_OP_LEN_REG (LPC_BASE + 0x10) -#define LPC_CMD_REG (LPC_BASE + 0x14) -#define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18) -#define LPC_ADDR_REG (LPC_BASE + 0x20) -#define LPC_WDATA_REG (LPC_BASE + 0x24) -#define LPC_RDATA_REG (LPC_BASE + 0x28) -#define LPC_LONG_CNT_REG (LPC_BASE + 0x30) -#define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50) -#define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54) -#define LPC_TIME_OUT_REG (LPC_BASE + 0x58) -#define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80) -#define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84) -#define LPC_SIRQ_INT_REG (LPC_BASE + 0x90) -#define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94) -#define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0) - -#define LPC_FIFO_LEN (16) - -typedef enum{ - LPC_ADDR_MODE_INCREASE, - LPC_ADDR_MODE_SINGLE -}LPC_ADDR_MODE; - -typedef enum{ - LPC_TYPE_IO, - LPC_TYPE_MEM, - LPC_TYPE_FWH -}LPC_TYPE; - - -typedef union { - struct{ - UINT32 lpc_wr:1; - UINT32 lpc_type:2; - UINT32 same_addr:1; - UINT32 resv:28; - }bits; - UINT32 u32; -}LPC_CMD_STRUCT; - -typedef union { - struct{ - UINT32 op_len:5; - UINT32 resv:27; - }bits; - UINT32 u32; -}LPC_OP_LEN_STRUCT; - - -VOID LpcInit(VOID); -BOOLEAN LpcIdle(VOID); -EFI_STATUS LpcByteWrite( - IN UINT32 Addr, - IN UINT8 Data); -EFI_STATUS LpcByteRead( - IN UINT32 Addr, - IN OUT UINT8 *Data); - -EFI_STATUS LpcWrite( - IN UINT32 Addr, - IN UINT8 *Data, - IN UINT8 Len); - -#endif - - diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h deleted file mode 100644 index b5de34f5facb..000000000000 --- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h +++ /dev/null @@ -1,45 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _OEM_ADDRESS_MAP_LIB_H_ -#define _OEM_ADDRESS_MAP_LIB_H_ - -#include - -typedef struct _DDRC_BASE_ID{ - UINTN Base; - UINTN Id; -}DDRC_BASE_ID; - -// Invalid address, will cause exception when accessed by bug code -#define ADDRESS_MAP_INVALID ((UINTN)(-1)) - -UINTN OemGetPoeSubBase (UINT32 NodeId); -UINTN OemGetPeriSubBase (UINT32 NodeId); -UINTN OemGetAlgSubBase (UINT32 NodeId); -UINTN OemGetCfgbusBase (UINT32 NodeId); -UINTN OemGetGicSubBase (UINT32 NodeId); -UINTN OemGetHACSubBase (UINT32 NodeId); -UINTN OemGetIOMGMTSubBase (UINT32 NodeId); -UINTN OemGetNetworkSubBase (UINT32 NodeId); -UINTN OemGetM3SubBase (UINT32 NodeId); -UINTN OemGetPCIeSubBase (UINT32 NodeId); - -VOID OemAddressMapInit(VOID); - -extern DDRC_BASE_ID DdrcBaseId[MAX_SOCKET][MAX_CHANNEL]; - -#endif - diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h deleted file mode 100644 index a232e52ed719..000000000000 --- a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ /dev/null @@ -1,112 +0,0 @@ -/** @file -* -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef _PLATFORM_SYS_CTRL_LIB_H_ -#define _PLATFORM_SYS_CTRL_LIB_H_ - -#define PACKAGE_16CORE 0 -#define PACKAGE_32CORE 1 -#define PACKAGE_RESERVED 2 -#define PACKAGE_TYPE_NUM 3 - -UINT32 PlatformGetPackageType (VOID); - -VOID DisplayCpuInfo (VOID); -UINT32 CheckChipIsEc(VOID); - -UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll); - -#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF -#define DJTAG_CHAIN_ID_AA 1 -#define DJTAG_CHAIN_ID_LLC 4 - - -#define SC_DJTAG_MSTR_EN_OFFSET 0x6800 -#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804 -#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808 -#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C -#define SC_DJTAG_MSTR_WR_OFFSET 0x6810 -#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814 -#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818 -#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C -#define SC_DJTAG_TMOUT_OFFSET 0x6820 -#define SC_TDRE_OP_ADDR_OFFSET 0x6824 -#define SC_TDRE_WDATA_OFFSET 0x6828 -#define SC_TDRE_REPAIR_EN_OFFSET 0x682C -#define SC_DJTAG_RD_DATA0_OFFSET 0xE800 -#define SC_TDRE_RDATA0_OFFSET 0xE830 - - -UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port); - -VOID PlatformAddressMapCleanUp (VOID); -VOID PlatformDisableDdrWindow (VOID); - -VOID PlatformEnableArchTimer (VOID); - -EFI_STATUS -DawFindFreeWindow (UINTN Socket, UINTN *DawIndex); - -VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value); - -VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); - -UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); - -VOID RemoveRoceReset(VOID); - -UINTN PlatformGetDdrChannel (VOID); - -VOID ITSCONFIG (VOID); - -VOID MN_CONFIG (VOID); - -VOID SmmuConfigForOS (VOID); -VOID SmmuConfigForBios (VOID); - -VOID StartupAp (VOID); - -VOID LlcCleanInvalidate (VOID); - -UINTN PlatformGetCpuFreq (UINT8 Socket); -VOID ClearInterruptStatus(VOID); - -UINTN PlatformGetCoreCount (VOID); -VOID DAWConfigEn(UINT32 socket); - -VOID DResetUsb (); -UINT32 PlatformGetEhciBase (); -UINT32 PlatformGetOhciBase (); -VOID PlatformPllInit(); -// PLL initialization for super IO clusters. -VOID SiclPllInit(UINT32 SclId); -VOID PlatformDeviceDReset(); -VOID PlatformGicdInit(); -VOID PlatformLpcInit(); -// Synchronize architecture timer counter between different super computing -// clusters. -VOID PlatformArchTimerSynchronize(VOID); -VOID PlatformEventBroadcastConfig(VOID); -UINTN GetDjtagRegBase(UINT32 NodeId); -VOID LlcCleanInvalidateAsm(VOID); -VOID PlatformMdioInit(VOID); -VOID DisableClusterClock(UINTN CpuClusterBase); -VOID EnableClusterClock(UINTN CpuClusterBase); -VOID DisableSocketClock (UINT8 Skt); - -EFI_STATUS EFIAPI HandleI2CException (UINT32 Socket, UINT32 Port); -EFI_STATUS EFIAPI HandleI2CExceptionBySocket (UINT32 Socket); - -#endif From patchwork Wed Mar 20 08:08:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160635 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp518484jad; Wed, 20 Mar 2019 01:09:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqxCdIPbSl/sim4wNmIlFtF1fPiOUzFMVn7co8ZTC957ylr3H4do7L1XVVvGrxKygfpLNrFr X-Received: by 2002:a62:e910:: with SMTP id j16mr6567733pfh.44.1553069340575; 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[198.145.21.10]) by mx.google.com with ESMTPS id l7si1325680plb.219.2019.03.20.01.09.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:09:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SOvCtzhd; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2F887211E0118; Wed, 20 Mar 2019 01:09:00 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B2020211E0105 for ; Wed, 20 Mar 2019 01:08:58 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id v21so1328392pfm.12 for ; Wed, 20 Mar 2019 01:08:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6LAPom+daNM4z1090uzrUATU4k1jYlf9mrcvdpOnPQs=; b=SOvCtzhds3yKrfmOp4PAN/wPRrtVA8h86yxu7gyo7rnCHEUkCQFNWq1vyPCMfMDWC6 O8lByvggO+Sqob116Gi3Y35+hFXAbBeFQUU9laSPpqS+8fneMf2vi/bmmlwuXHhQNQmq 9kU1igDVC4oGyCxdULB59qplY0wO4qZZOx61NtmPOPgkYYM/9yruqSjLag8FMpUraKt8 ssz7ZQYQ3sOstPh9ciZfnAAFxNP8v9IWcPs4N2TEsGnrjI6wWMATUoELqTkfEFQP01vM Yc6kGjaC0iDVwKnLGQaX1HbTVnNw6OizHZWgwC5RuEOw4TwBzNmaNDGgytEjZUeZ1ZC4 R1rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6LAPom+daNM4z1090uzrUATU4k1jYlf9mrcvdpOnPQs=; b=kpXNzNb3lxSQLSdGYumGU4YRuKoiGcqJrmIp8DHHYpk0heMtraFovrePl+nvkv+v45 5nzZ+2A2FdWpT8ojg1Hs/tSFr3PkTUgsGp7pKC5pJ/41098jI2s2957oZ0d3KK88U0Ch t68Tfjv43qj1iQtxK7nRL0Hld9mpLPr2RWGSXhhSjAfsDkeUFDTlX5XFKezRIsRA4WIN AljeY+7buV/RBj3apjUMoNKyYAlXl+EdO5Df9fxj07OVLp3pzpvFE5YYXfZ71A+vdjFX 0cJ/NHFUsXwAVQUjBUNHMrkmB6IquFW6kNSp9n3iKnA5pEdq8/6R9l/ntLfFZOLfUBPP Xgjg== X-Gm-Message-State: APjAAAWbVvRd3kKzxw+gHmKFJPGNWeUacijJbdf2+4bIbi5n7XKliNEt nfpPciKmmYCscXjqm6/6hR7pnA== X-Received: by 2002:a65:6548:: with SMTP id a8mr6121843pgw.103.1553069338285; Wed, 20 Mar 2019 01:08:58 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.08.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:08:57 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:14 +0800 Message-Id: <20190320080829.52003-4-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 03/18] Hisilicon/D0x: Add DriverHealthManagerDxe X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" DriverHealthManagerDxe Collect driver health form of third party drivers to repair no healthy card. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/D03.dsc | 1 + Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D06/D06.dsc | 1 + Platform/Hisilicon/D03/D03.fdf | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D06/D06.fdf | 1 + 6 files changed, 6 insertions(+) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 3f59be22ec8e..fe443dd929ad 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -492,6 +492,7 @@ [Components.common] MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 25db1c38d287..0c4f21fbe056 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -638,6 +638,7 @@ [Components.common] MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index cbbd99e4a659..6d581337f199 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -435,6 +435,7 @@ [Components.common] Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf { diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index f453f9e46321..3f07b2e57778 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -295,6 +295,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf [FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 85dd791564a4..9632aea4b00e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -314,6 +314,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf [FV.FVMAIN_COMPACT] diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index fda29ab322e9..a937660a09e2 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -319,6 +319,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf [FV.FVMAIN_COMPACT] From patchwork Wed Mar 20 08:08:15 2019 Content-Type: text/plain; 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[198.145.21.10]) by mx.google.com with ESMTPS id h7si1155905pfd.250.2019.03.20.01.09.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:09:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IOHOmU73; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5FC32211E011B; Wed, 20 Mar 2019 01:09:04 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D16BA211E0105 for ; Wed, 20 Mar 2019 01:09:03 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id d25so1338483pfn.8 for ; Wed, 20 Mar 2019 01:09:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5ya02E/Gn6Ahh5Zs25SSjnsdWUtDfMBLswWn/1KrjEw=; b=IOHOmU732usfzXTKkvHDbjg9L4OsuMo7LUT2nwEO/A4Sr7Ro/Rkf26hqnD1F7iTQth NChH5X3t9i45CplqpJxIDoyDQpB+M1S2oVDOU7V4r87jeYoWne31OEc1uwe6s2VnvB3U g467G74vYZmNQTw8CAHLgCe2AXww4BFByHuYbIWSE6+wfTooeqPmuUaOsTl/Ikov6bVx 8ln1DlGTpZZSHtLFMsDNEDl9yCEiJeAIR5xrLT976pUnYurHgKcMfEFclCn7mw84i2dl aWypqNqyvxMtumZjLBvEuK916VxbSvR9+GAHso7c5iob7bVOfo1vvZNn2MZ9aQmp/Hjd MAGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5ya02E/Gn6Ahh5Zs25SSjnsdWUtDfMBLswWn/1KrjEw=; b=KWt8eXoNtHrKCr7E43R5VjIpGEW+RRR2EZ6OHlZK/KGzgFsaUUOR/DpvfKKW8aanxO 0+cAc6f1c91Zj2Rzr+fV4faTePG7RLooFJYn/I8TmoXer5ghQa96aSRUhdtmNE0AJF+B 24WUQA/Uhq0AIpc4KXhmk1TCmc1Viox3dmu4zH/7DEyPFeDlR1e5bF05IpcUt0M0Sc6w sfeRzfshCf+yVplDPl+7A3vg4oZTLSt+ffoLizFOg8T+kH0Alx19Y6K5SqClt0VlMGgS WW4kP4gx4K8dA1L/igu3RejXngvaTaQ6OCNwxfkIQcER9BQVjYaQkDni6YU637sMljTm QgVg== X-Gm-Message-State: APjAAAUCrLNBDkATZkVxPAn6J2+Lr8GYkwP0BHx5FCNF557opwSaz9U7 rM6GQksYzXJBYCZBgbYbmHa9Rg== X-Received: by 2002:a17:902:1621:: with SMTP id g30mr6900165plg.116.1553069343381; Wed, 20 Mar 2019 01:09:03 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.08.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:09:02 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:15 +0800 Message-Id: <20190320080829.52003-5-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 04/18] Hisilicon/D06: Optimize SAS driver for reducing boot time X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" SAS controller is always existed, so accessing SAS register don't depend on PciBusDxe (pci enumeration). Move the SAS module early in D06.fdf for dispatching SAS driver early. This can avoid wait in BDS normally and reduce boot time. This change is only valid after the update to SasDriverDxe in edk2-non-osi has been applied. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D06/D06.fdf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index a937660a09e2..d495ad7f264c 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -165,6 +165,7 @@ [FV.FvMain] INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.inf + INF Platform/Hisilicon/D06/Drivers/Sas/SasDxeDriver.inf # # PI DXE Drivers producing Architectural Protocols (EFI Services) # @@ -296,7 +297,6 @@ [FV.FvMain] # INF Platform/Hisilicon/D06/Drivers/Sm750Dxe/UefiSmi.inf INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - INF Platform/Hisilicon/D06/Drivers/Sas/SasDxeDriver.inf INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf From patchwork Wed Mar 20 08:08:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160637 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp518664jad; Wed, 20 Mar 2019 01:09:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqwPGzxP2pms0kjpkYd4bOvzUuJRFXhlQOscBpuMaVU3Bj3gTRGB/yCZmGMHsBOPmxMEdiw6 X-Received: by 2002:a17:902:f095:: with SMTP id go21mr29344553plb.199.1553069350963; Wed, 20 Mar 2019 01:09:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553069350; cv=none; d=google.com; s=arc-20160816; b=G0vTaC1gRQI0ZzEsl20kQ8F42jzC5icDXzLjz0aLUMM/wlG8QKzqpj6Jwl2SZ6O2qz Un6+Pr8WFGgL7U2QTGPBXy9dll+YOLFkZ1WqFLFNJFW+9l5vCzfffShdt1h2D28D2U89 3cIWaDi/LhnAacYSg1YX9CYUDVr3kGtmuODVxq1kIPgi4FPJjly4kcK32kMbcgGTc6dl btToeOF5ZDRVrTn5/QhhqIj2VSWd2OSsv1sNx++pm70txIu70jzUTKfmdVFCZb7l+W5f lmQAlnWr6aV0gGkBaz07M5y2YErT5ItgeqSt7ucuttdwi81OCnrDDlIvL6hhaLK+2MLX DMvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=kXK4dq/s5CWX01sq4C5Q0jsLxWDNSgZJLcQcIZJhoFw=; b=nqdT44VKaJXSatjeZXfQNewg1EL2IzCnTKsgaPoH5a2JhWqMvvZXCZ1QG7ctQkls2e h9R0oKp9CBiKbPi8nQL+sUJtNad0xtex+gdnl+s8hVD96KL/lX2BaogbFMcxt+e71tnj HyFsXEcdMR53QNnFHl3ogpsagVttOmH0iIrkCz4kAClAI4DKzsvFY2HL+FF9Qi+c6LN1 8bSGwOP1Fa3xbZmBLnmRZDnaSNWHu+PO+HMuFLjmOGZVb2DEHIz3l2y15jyxbE2eyejP miiwSubITHmDRIyXMqbhXsogQ89LSIf8nIAYFyqXVQFSSQzmxANFHoElnG0rYHXDidV4 9/4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=j5NYbA5l; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 012d45bc0214..6668103af027 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -316,7 +316,7 @@ OemConfigUiLibConstructor ( Status = gRT->SetVariable ( OEM_CONFIG_NAME, &gOemConfigGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, sizeof (OEM_CONFIG_DATA), &Configuration ); From patchwork Wed Mar 20 08:08:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160638 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp518757jad; Wed, 20 Mar 2019 01:09:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqz+mHIHCNsg6rZFPddWwDDQy9xQH5f5zmIkhzjchiFBzIpLaaNWKBO02Kv65Cqo1KxU67pr X-Received: by 2002:a62:5797:: with SMTP id i23mr13523390pfj.12.1553069358169; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id b3si1127449pgq.132.2019.03.20.01.09.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:09:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Lt0iotOK; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F0C44211E0924; Wed, 20 Mar 2019 01:09:22 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::443; helo=mail-pf1-x443.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 22663211E0105 for ; Wed, 20 Mar 2019 01:09:22 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id i17so1349072pfo.6 for ; Wed, 20 Mar 2019 01:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MRbvcU1OuLk38U6fCDZjzxsbaCDVrdkPV7fJkZKzkjo=; b=Lt0iotOKL5M6dE7AK+AgBTdxNGHZBIMOvPNjdjH02FOy/u8OG3SZOJel97qPhFSyjv jOuiAwT3/JJ8qiX76t40WNkieny3uRn+Fl7dOJXcY/tctm/x54s20Yoqd/cVwS/ydXw1 aWNknfgWiDhnyz86wKTF+/Yq41qlYivfoNSBguQjik9ImmQxkbr7WrldlYdxQI/IzTVB iuHvBOrM0vVAM7m4o/kWtlfkMcXxZ8mxs0Li2orSjaStTjSJJfp+EZKanpbiVeZiLG1m Ue4/9Hum/2ZDbNvtOxhVGUYU+ICWzBl2ztMROwRRVIyWdu4uYyi5fE5q9DUiYBIciS/6 C0QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MRbvcU1OuLk38U6fCDZjzxsbaCDVrdkPV7fJkZKzkjo=; b=nbffARYkRM6HnKd6R1BbVtdglIlqXVKYlpq4LR4Xm5H+ilcBItVPdLpT372LreelTJ fJXhHZ0y0deON0+7tkqi4DFhBfEDy8+T/5eiBSA6rU3lxwToK5FeFZOQnL12OVM1nNak rgSaa2tPUpfX4Ktjn2omfo0Nxf4y7INP3+T3ezcSavFKoa2e57uwU6e7RYyojI9Nz087 rLi3ziVkWP1TkgYcGPhBcDf9lV4TErZg5aFuvvigbYOA51UmdeCVhhqfLYVQ2wIKRxro u6UOsZZDdl/2ksHuiWyRkFJjvIdfK5J/5QDxQ11tB1Z87rBkVx76y+peiwj09sf+du2r AItw== X-Gm-Message-State: APjAAAWBVZ/KPBpDAD9eZBD0tFBkMaRrslFqF4ELunGkUQWzDJRk5aur uL5AISgzs9t9st7rAIJYjorV5g== X-Received: by 2002:a17:902:8d89:: with SMTP id v9mr30616806plo.254.1553069361843; Wed, 20 Mar 2019 01:09:21 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.09.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:09:21 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:18 +0800 Message-Id: <20190320080829.52003-8-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 07/18] Hisilicon/D06: Add more PCIe port INT-x support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Since NVMe riser width is 6*X4, need add the related port's INT-x support to match OS driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 37 +++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 0f2d11bb952b..4d9d9d95be68 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -41,11 +41,21 @@ Scope(_SB) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A Package () {0x4FFFF,1,0,641}, // INT_B Package () {0x4FFFF,2,0,642}, // INT_C Package () {0x4FFFF,3,0,643}, // INT_D + Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A Package () {0x8FFFF,1,0,641}, // INT_B Package () {0x8FFFF,2,0,642}, // INT_C @@ -56,6 +66,11 @@ Scope(_SB) Package () {0xCFFFF,2,0,642}, // INT_C Package () {0xCFFFF,3,0,643}, // INT_D + Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D + Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C @@ -759,11 +774,21 @@ Device (PCI6) // adding RPx INTx configure deponds on hardware board topology, // if UEFI enables RPx, RPy, RPz... related INTx configure // should be added + Package () {0x2FFFF,0,0,640}, // INT_A + Package () {0x2FFFF,1,0,641}, // INT_B + Package () {0x2FFFF,2,0,642}, // INT_C + Package () {0x2FFFF,3,0,643}, // INT_D + Package () {0x4FFFF,0,0,640}, // INT_A Package () {0x4FFFF,1,0,641}, // INT_B Package () {0x4FFFF,2,0,642}, // INT_C Package () {0x4FFFF,3,0,643}, // INT_D + Package () {0x6FFFF,0,0,640}, // INT_A + Package () {0x6FFFF,1,0,641}, // INT_B + Package () {0x6FFFF,2,0,642}, // INT_C + Package () {0x6FFFF,3,0,643}, // INT_D + Package () {0x8FFFF,0,0,640}, // INT_A Package () {0x8FFFF,1,0,641}, // INT_B Package () {0x8FFFF,2,0,642}, // INT_C @@ -774,11 +799,21 @@ Device (PCI6) Package () {0xCFFFF,2,0,642}, // INT_C Package () {0xCFFFF,3,0,643}, // INT_D + Package () {0xEFFFF,0,0,640}, // INT_A + Package () {0xEFFFF,1,0,641}, // INT_B + Package () {0xEFFFF,2,0,642}, // INT_C + Package () {0xEFFFF,3,0,643}, // INT_D + Package () {0x10FFFF,0,0,640}, // INT_A Package () {0x10FFFF,1,0,641}, // INT_B Package () {0x10FFFF,2,0,642}, // INT_C Package () {0x10FFFF,3,0,643}, // INT_D - }) + + Package () {0x12FFFF,0,0,640}, // INT_A + Package () {0x12FFFF,1,0,641}, // INT_B + Package () {0x12FFFF,2,0,642}, // INT_C + Package () {0x12FFFF,3,0,643}, // INT_D + }) Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111, From patchwork Wed Mar 20 08:08:19 2019 Content-Type: text/plain; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id t26si1095999pgu.504.2019.03.20.01.09.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:09:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aUidOURU; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 44132211E092C; Wed, 20 Mar 2019 01:09:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::442; helo=mail-pf1-x442.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 270EF211E010C for ; Wed, 20 Mar 2019 01:09:29 -0700 (PDT) Received: by mail-pf1-x442.google.com with SMTP id v64so1365220pfb.1 for ; Wed, 20 Mar 2019 01:09:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k1V6hzpPybG54f/e6nZ95Pi12w1ONqa2XY+DvcTgtak=; b=aUidOURU2rXtEJqYyAX62Fb/v8fiXDOEzoDaP+HD52vZXIywAsTuMglkgC32ObsS1t 8Wbpbkew9azUGLK+x9ONTtu9lng0PcuprjvzQ95cSn4nWZwRaWilsblOcK3iQ/npX54C ePhoXK5vFgGnEF/yWCaIkPYh8i5AgIi8jhX7O/5ggVZt3Q0J1zJMQAyjJm/KblJaqkZ1 56haaAvBKsDoeC4H99IwDGFToKC525Lk0EVFqzlVKMoEd4U4fLYU4W5cMBwCj2d2eiTr 7efdU1TuzebEzF0WXhcgojHkWSHTETvqUkKHJl1o7TbwQKFLAPN04ohHgBKfRKYIrWn1 IfDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k1V6hzpPybG54f/e6nZ95Pi12w1ONqa2XY+DvcTgtak=; b=O+eL6O0IqN6dlKyPFiItj4dXiRpP9eGvYw2W6FhGJY/oltjMsd5JtCDnDwsZYJr5+I G2Syl1rHMoYMtoUjNZ58Jyhz32dLgXwAq0u6kfc4vCAsfAbQPJjdTXcXY6QMMErgMAss AhZ2SIJ8UGCMxMW+00WiuvlcGCl3tSpsdKzKCM5B+fljLVE6F4cmde10S2TMfFu+HWoJ wKWQNwDghoveDgsVEgBaXCfHh4JfUY/DN8lSnrl3k4xMxumVnoCG87KacBR28+LQ5leO dEd9jpFU+vtffeso5CHMvI8IFJGTpJN55RrE1hqehAeLQ3/cAClSyew4Fq4q8nRRaVnh 1o8g== X-Gm-Message-State: APjAAAWvglZXrcICWKnjMJOTyrWmBVJu09QnQLT/d99P6LZZAPsGhkwU kEkd0ksJIaHPBvmlpARSWihUVw== X-Received: by 2002:a65:4203:: with SMTP id c3mr6620166pgq.271.1553069368724; Wed, 20 Mar 2019 01:09:28 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.09.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:09:28 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:19 +0800 Message-Id: <20190320080829.52003-9-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 08/18] Hisilicon/D06: Add OemGetCpuFreq to encapsulate difference X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, xingjiang tang , huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: xingjiang tang Implementation OemGetCpuFreq() to get cpu frequency from cpld to encapsulate project difference, for some projects don't support get cpu frequency by this way. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D06/Include/Library/CpldD06.h | 4 ++++ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h index ec9b49f4e70d..8eb333de529c 100644 --- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h +++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h @@ -36,4 +36,8 @@ #define CPLD_X8_X8_X8_BOARD_ID 0x92 #define CPLD_X16_X8_BOARD_ID 0x93 +#define CPLD_CLOCK_FLAG 0xFD +#define CPLD_BOM_VER_FLAG 0x0B +#define CPLD_BOARD_REVISION_4TH 0x4 + #endif /* __CPLDD06_H__ */ diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index c5cb77696031..c8f71ecf890a 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -206,3 +206,19 @@ OemIsNeedDisableExpanderBuffer ( { return TRUE; } + +UINTN OemGetCpuFreq (UINT8 Socket) +{ + UINT8 BoardRevision; + + BoardRevision = MmioRead8 (CPLD_BASE_ADDRESS + CPLD_BOM_VER_FLAG); + + // Board revision 4 and higher run at 2.5GHz + // Earlier revisions run at 2GHz + if (BoardRevision >= CPLD_BOARD_REVISION_4TH) { + return 2500000000; + } else { + return 2000000000; + } +} + From patchwork Wed Mar 20 08:08:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160641 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519074jad; Wed, 20 Mar 2019 01:09:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyXWPD7G0qFqxsQ01ZgK9K+SzsXC+tem9FAYuvx0g6h7zRLhDim5BzRoq8i3GDqul1aKf2Y X-Received: by 2002:a17:902:2888:: with SMTP id f8mr30407093plb.244.1553069377829; Wed, 20 Mar 2019 01:09:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553069377; cv=none; d=google.com; s=arc-20160816; b=IciLP3BbRtf1QdXGgzu2ZFqE8zZ9h9GYYMKFyE6pmDEJDsIjOMzQCdyma1nCp9JPMf of7dIT8RPOb7BdhZCnNpn+qtYdnZk4Rbz6iXVjnq4JBUC58p3uSqF1BWRzwviFQZ3g0A zt+Nawk+eehQ4cKKV0LyGdXAHyjP5su8Aw69wVuwQpV9IDXhZKVX5+xvHTx3pVC6fUOc lva0/hSuPZxTEwR5geG1PzA40h9Ww1u3o9Ij332SFCsBOaTD6lTgUY22MecEEiZdAeeq SrKpYocoaoJlGlTIVaenqGMvyLAtMrXD9UGCdt9ZrBp4t6oGLGzQQF2tenmwPEiUxGfz 6+Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=t6/aR3IgCz6eJFRAtYZ83aHSSLB6oCflul341M0PESo=; b=HO1ku9jciYkIIHS7G3+Kg4fsGB75rzHDNWVG0TaXFDAVfTVXoKOvAx1R2na6BmYcTK pbDTXpQHj/ouAOysuxHifEgbnrPcJH1FYb71Ing5XGh0usdK4tnm64EKdeuGbsrwHUIP kyzJAUih40vJBpCMNnHW1A3z+wAaPnSQ5MDkDv9EhOIbrY8eM2XUwYdCwfkOuTkw4us7 MgjfxSr1r3FE6Vx6EjgG1OslneIhhhKpXeY8DfFREsJgo0k3vg3Csww/IDdhq0EjWv1q 7BsM22ZKO/LFSDF8Dq0vpVsf/UF4UJeFowcZCRA+EmR4y6F4IRENFj66owfLhYp3luh/ ghCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QLcfagBU; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id z3si1107137pfa.121.2019.03.20.01.09.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:09:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QLcfagBU; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 73CD4211E0927; Wed, 20 Mar 2019 01:09:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::442; helo=mail-pf1-x442.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EE25A211E0105 for ; Wed, 20 Mar 2019 01:09:35 -0700 (PDT) Received: by mail-pf1-x442.google.com with SMTP id c8so1337339pfd.10 for ; Wed, 20 Mar 2019 01:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=huPM1xyQBvgR2zj7FjA1NIoSieT8pmpwv40RhIgLmYo=; b=QLcfagBUE0tANrftAvuhVRN19DyC+XdAYc06UcnwoSV2D1kFxHYNBa1LpIKjaWfXKd GjeB5FH1lZkfGf3jR2goTU69jS+CyjQpVaG7a3Lf6Nm8ViqQ/3ZTGa9UDc00f1FDLiv4 TxgzY86gzOadK10L0x1QzxLt1TK1Kf2OLLibCHLq8iGagh9CCuJFHmT2L9NMUjf3fkQt +SUMaj8AeuSt344plXbsuklsCD3XCJUHKlXBZXfQQ0HRMfVQEqRH484sJmt62U4e99pL /fff8oanb7XMZQEkEty67COIGyIk/4WvV6Xz/+LVLHfFxL2EFeIUeHAEChiAV1+5mvD6 wVhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=huPM1xyQBvgR2zj7FjA1NIoSieT8pmpwv40RhIgLmYo=; b=NMIJ/2m75mqyU1dSeq3LLusU8doHDeS9cB+JfQvYM5OnPQaweFnoAUyYWhbGQMkEcg +dHrtRQKzW1eFxMiS8o+GOhwIq41Auco2aKgWZoz3KeUJKpNh7sVJC33VYyFawPFGa3t kDqF0uCfRVJMVWTyolkEfa1Wc006jJoYYVPYdTfjSgMkN/RugUYNkW3VPaW81WSvjo+r OBOu1XvDkhxJ4a8l0o1e+MGOaTJ7Uj3l1/BpREUGB1SGeJNVVTh8E/TP1MdeoFSFUNws xOpChdSYVGXTxBH4d+lGecTdzvqduTjBbFsB/lRM7qcvGwab6smPiQJyxd7THT6dsdqy bMxg== X-Gm-Message-State: APjAAAVX47S27pxLKBOeYEGFTIgVwiq/wQFmEozsuQ8ZrF+K21TwY8Dh DhDcGby7t5V7sMamm5uVq8gBbA== X-Received: by 2002:a62:4214:: with SMTP id p20mr6516563pfa.204.1553069375622; Wed, 20 Mar 2019 01:09:35 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.09.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:09:35 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:20 +0800 Message-Id: <20190320080829.52003-10-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 09/18] Hisilicon/D0x: Rename StartupAp() function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" As suggestion of community, 'AP' is a bit unfortunate to use in EDK2 context. PI specifies 'BSP' for Boot-strap Processor, as the one executing all of the EDK2 code. It then uses 'AP' to refer to Additional Processors, which can be assigned tasks using the EFI_MP_SERVICES_PROTOCOL. In a TianoCore context, this should be 'BSP'. So, Rename StartupAp() to StartUpBSP. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c | 2 +- Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 3 ++- Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 2 +- 5 files changed, 6 insertions(+), 5 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c index 97cf6b8d8757..dacd9e871faf 100644 --- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c @@ -83,7 +83,7 @@ void QResetAp(VOID) //SCCL A if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp(); + StartUpBSP (); } } diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c index b57fdfa68e45..c8a9da73bbca 100644 --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -133,7 +133,7 @@ VOID CoreSelectBoot(VOID) { if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); } return; diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c index 76a055cbe980..b374347e5c4d 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -35,7 +35,7 @@ QResetAp ( (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp(); + StartUpBSP (); } } diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c index 4c4c944dbead..a1458da7f0a3 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -96,7 +96,7 @@ UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) VOID CoreSelectBoot(VOID) { if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); } return; @@ -128,3 +128,4 @@ BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) { return TRUE; } + diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c index 0790f7941ae7..a8261d370626 100644 --- a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c @@ -78,7 +78,7 @@ QResetAp ( //SCCL A if (!PcdGet64 (PcdTrustedFirmwareEnable)) { - StartupAp (); + StartUpBSP (); } } From patchwork Wed Mar 20 08:08:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160642 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519192jad; Wed, 20 Mar 2019 01:09:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqzUcmIdzGbsjy8CcvlQRq1gKM8tTxLt00IzbGv+JEMoHxBS09MFxUDerlmPt4W1KkV3GZ6G X-Received: by 2002:a65:62c5:: with SMTP id m5mr26835041pgv.77.1553069387026; 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Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index c8f71ecf890a..758157525f40 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -222,3 +222,11 @@ UINTN OemGetCpuFreq (UINT8 Socket) } } +UINTN +OemGetHccsFreq ( + VOID + ) +{ + return HCCS_PLL_VALUE_2600; +} + From patchwork Wed Mar 20 08:08:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160643 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519305jad; Wed, 20 Mar 2019 01:09:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqwf/QLZGzEaTWO7PSkP6acjKdId+8UuZy0EqyWOip6ikblzugYPEp0igKt/zA1qgi8R6GJE X-Received: by 2002:a63:441b:: with SMTP id r27mr5842569pga.36.1553069395412; Wed, 20 Mar 2019 01:09:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553069395; cv=none; d=google.com; s=arc-20160816; b=T3dMHIiNrAF1bA7vaZlYDcIvBd+3RnQzKo+SZWaVezvhEl0fSALgos0i6svsSa8Yte fZXVji825+RVNRZpZx7YFzcjEkZhUErwYgTt/uaH0x90+4RcG951d3Kkhk3CbJp57ytN qnFDvImdvqbnTrzABzBhqBEvG+0xZcN+pJLtEqGkxlU4CMtTQdSHtecQ1+xynawothyT /cmwjOsQuSWUIEWPKs/79/vvWxAMfY3+1hSvhp5/um0qmmyag2wZkZeN/moBCeTd/PML Ygap3OCmJqEoAGfNp3uZNeNYw5P3qCWiibizp5HNzxf0XjljfB8lB4nKE3+QSKrY4rn1 ev7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=nwwpNqmDtwlbXaDw6m2HtBsxuBjdlMFz2XL4DfkHDsg=; b=BOr1bexjkv/6tsmYRGzzuOq9oFX5r/fEPlSqlrBOdw+Z+1xpPxiGTchTgkZkgnMk/r 0vA29uRIwPE4jjx6to01BOmd+JUulfMBRc0JF/xuA6O2l8CmYB8RtipEHJymzqibxUKt 2pmiz8r5JEM2YDFmTsLhkj6GjFLC6hBTqQVmgcNdKBP1tmGGSl1PH4spmZdyS+DsH9kr 0mJj6N7V4Ys7/pnsAUVC6qlg2rElV2B/k+DL01M5Od+5zq0Ao6vh7KO6avJJ6TGDCbED z6q6pOZQA631ABJJGEUAAyvGv3BYTxGC6kzb479qqu92pKxQZxDsA2vo3cRuJjptJQ8U TJyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SkU4Apku; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id u6si1092109pgr.456.2019.03.20.01.09.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:09:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SkU4Apku; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DE91F211E0930; Wed, 20 Mar 2019 01:09:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C625B211E010C for ; Wed, 20 Mar 2019 01:09:53 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id a22so1185604pgg.13 for ; Wed, 20 Mar 2019 01:09:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V3ItXfFJZwQwpwUZXFKJWc489lp1ta/w32zRZrrsbR4=; b=SkU4ApkuCHPxPvBn1HHjRzlSlnWoUEx2AOTprfJPacKZ/mBgm8i/ZqT8Wdjqyc8j9K Bg8DMFs2OoH6XVWeG3E1/lKLV/tIoHCYJ38ij4AVo1u94KSOBcZvs2VUkQwCS7UUnH+y 82149G87R5zezedNSpOTJqG/GVXSrofy+J1obDt737ksDLIkVopVDkQGbrxmBzRVoxK5 iEdjqQKkA9kNNDcgJK0eDjE8Bq1sN+If5lmLkCyOukKcv+XQz+cvOin/M9Oln+MkeQn1 vH7MKhZNBLE0/1ZhkSEO9KhqY9Om1Cwk2uWGeHEXDt96ZMelHl28n7SyBiVIFfZoyfhU Px/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V3ItXfFJZwQwpwUZXFKJWc489lp1ta/w32zRZrrsbR4=; b=hBBZlA3MErFkxBChw4kMBL1VmZ1OgJOu3wDv6D++4beVZjyK0ige0KXR2psStx31sP 9qIDlolc2oMJElPxiOVUHNsb/0HFbdVURk4Z7go/Dx3C5Yn5OCyUJDvbo6TWpdWc2cTD r0kVLYM1Cq7mw2jTxUvGFjSlUEL6S5knQyTZLfFPJSLwEOZi2ImwA++4kQ0YgdwfP6tc Y6Yv2R9qU4G7h5NCehBwQ003nXl3pDeujQCF78X/VgOfen61+lVkfh7jOrxUIRGOB6Y0 ADYF4YwdcZBCwBNVqT+ia1ifNpFSO91ZWbkrtvpWSp4aw1O8BA9G7d0/Kl06cDsf7o+P M9QA== X-Gm-Message-State: APjAAAUEG/SKolUVsiD3S17FGODR8SG8sqWNOtLPNwikuf+zcRGPe4l1 VgYFAPHVoQZKwblzPN5q7uitxw== X-Received: by 2002:a63:c64c:: with SMTP id x12mr6150933pgg.285.1553069393318; Wed, 20 Mar 2019 01:09:53 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.09.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:09:52 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:22 +0800 Message-Id: <20190320080829.52003-12-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 11/18] Hisilicon/D06: Add PCI_OSC_SUPPORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add PCI_OSC_SUPPORT for remaining host bridges to remove fail output in kernel: [ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND); Add PCI_OSC_SUPPORT_HOTPLUG to rewrite _OSC of PCI0 and PCI6. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 200 +++++++++++--------- 1 file changed, 106 insertions(+), 94 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 4d9d9d95be68..6dc380f27fa2 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -17,6 +17,90 @@ **/ //#include "ArmPlatform.h" + +/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + +#define PCI_OSC_SUPPORT_HOTPLUG() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Always allow native PME, AER (no dependencies) */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x1D,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + Scope(_SB) { Device (PCI0) @@ -139,53 +223,7 @@ Scope(_SB) Return (RBUF) } // Method(_CRS), this method return RBUF! - // - // OS Control Handoff - // - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - Method(_OSC,4) { - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - - // Only allow native hot plug control if OS supports: - // ASPM - // Clock PM - // MSI/MSI-X - If(LNotEqual(And(SUPP, 0x16), 0x16)) { - And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) - } - - // Always allow native PME, AER (no dependencies) - - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC + PCI_OSC_SUPPORT_HOTPLUG () Method (_HPX, 0) { Return (Package(2) { @@ -270,6 +308,8 @@ Device (PCI1) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -333,6 +373,8 @@ Device (PCI2) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -382,6 +424,8 @@ Device (PCI3) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -431,6 +475,8 @@ Device (PCI4) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -505,6 +551,8 @@ Device (PCI5) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -870,53 +918,7 @@ Device (PCI6) Return (RBUF) } // Method(_CRS), this method return RBUF! - // - // OS Control Handoff - // - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - Method(_OSC,4) { - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - - // Only allow native hot plug control if OS supports: - // ASPM - // Clock PM - // MSI/MSI-X - If(LNotEqual(And(SUPP, 0x16), 0x16)) { - And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) - } - - // Always allow native PME, AER (no dependencies) - - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC + PCI_OSC_SUPPORT_HOTPLUG () Method (_HPX, 0) { Return (Package(2) { @@ -1002,6 +1004,8 @@ Device (PCI7) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1066,6 +1070,8 @@ Device (PCI8) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1115,6 +1121,8 @@ Device (PCI9) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1164,6 +1172,8 @@ Device (PCIA) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -1238,6 +1248,8 @@ Device (PCIB) Return (RBUF) } // Method(_CRS), this method return RBUF! + PCI_OSC_SUPPORT () + Method (_STA, 0x0, NotSerialized) { Return (0xf) From patchwork Wed Mar 20 08:08:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160644 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519353jad; Wed, 20 Mar 2019 01:10:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqwhoXCNHOufATUS5/1jKAcGP7Mauel9GuYQf20QAaLmWut2xgwrK6WJeKJVbjzNsUe3gaIj X-Received: by 2002:a62:a50c:: with SMTP id v12mr6962826pfm.206.1553069400464; Wed, 20 Mar 2019 01:10:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553069400; cv=none; d=google.com; s=arc-20160816; b=Ani3mpR4GvRfntAXvY22NtYG07fOYmc1g8Zc8hzN3UgFQRJnXWv0jNY7VGKEbW27MI 2a+f3gqX6bJd6lBh5w+RFxSfhkESWFaJ7qX7U/HEySXZ2ASy0iQ+50TNKmcVn7fSh2Xd C7XWDTMynclD5/Q5xF2+5yTf/hGsth9e/ky1eNnBhijDfizS/mjH5upPhcUwIhae1pfM j2AWP+W0Oh+O4QQFoVG1P/pXsbkMNRCZ+FqeSvlDo6MjfgGV1ZUmtxC0Zk/z6/+yHrhM DGNBORSI7fiM4wQLQwHsdJnmBE/2eM93hAesZrhKQQifpyq7CZp1e4aIgkmFCLi1Y0ay 03VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=HG3I7lP9BdxZy/e4ifkdYfMx8emAegiMMvNbqiKEMWg=; b=ihk34emmcOVNsQESm+GTf1qxovJJWp+xSZ4RBoLSe11+bHh/BdQ8qqkvyyWTVG+kum 7r9veq4I4ypFhtnE1aHZ8gEsgZLcZpsQeApDoy1n+6k80C2SLfFz5Tag1HPG6UdWdNcO mtWncRjJ8mGdv6KAgvB3m97iasp4oEMcozAS/zqArKfSu+dLMKhB9LlemNUwSmiOuWnB RZEsrtldj5QtgaFV0JDG8gNV6E8MXS+NzvSzY3UBREC16VefpNJygaGO0dt6svenrJVt hhdjmbNNi2GsmYtsvFSnF6MzehEQccBc7xj39OMdE+CZoZFGYLwaM/DMSou03b3mnWyF F56g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TW4SPaiM; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id r15si1256277pls.374.2019.03.20.01.10.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:10:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TW4SPaiM; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1C3A2211E0932; Wed, 20 Mar 2019 01:10:00 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4F64C211E0115 for ; Wed, 20 Mar 2019 01:09:59 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id v1so1216822pgi.5 for ; Wed, 20 Mar 2019 01:09:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cut6ectixtybHzCfDcbwZI+ElltgcLMCAoocCw209eg=; b=TW4SPaiMopQ08DcbhKx+l2D8mvRlsGBvY0KAXp9MOUvm+aYNTxBBStw2G+R/g0MflZ VcBQGz9TFDcSHKRNom3YITjbmIsVYFWtsZL3bMAla0npnz6x5eyoKA9bfxx8TuBJAEQ+ PDlinJP/F+NM/NMpFFxWvEFPqx0j8hc6K25IYZmL28C6+pqw0Cjf8qLJ1PlUrokNsZaS lKYDxA3GxyFzc0xCR8u9wFli+yahXrS7GRu06FdW2tJRNcXEy/D9QA7OGZN+uYavQCZc bhgEJAAFkHsxtoUHFA+8/QKxi2Cf7GzB7foU9q6mCB8ovVCd8SMC6mEYuTLXLND+R54s PQtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cut6ectixtybHzCfDcbwZI+ElltgcLMCAoocCw209eg=; b=fqDqg9EsuRSrZivWlUl8AYxH2tAjQ6rluodODt/TzTkF14oKAG8TRNuUy3fqUpIUM7 gXLtbJV3q1qZkWDFATV3tRE0OdepAHECi5teMIQqQkSaeYInudO2xvfEMQpXZQ+O+o2j 2mxqSB33ib7/ho+2Ge6Lq3J/w5iYbh2xsZnRwXc83Bn6DEYDgzWBgcgN/WAnyjcrT5Xi vYHwwOW2H+Ski0JBBAGEmPf/FfVEI+jMwBjRvslg3DlpfrGHhLA009OB9KpnQ9KfFYde sDnh+w1LD5lNh4uX/T0M7WQMssumuYa8VbTzHXTIzsth6FtScSEnqQPz4DML5Qvb697V Txkg== X-Gm-Message-State: APjAAAXjHko+fxYwAlUJm10T1KmrQuWIShWZrG1myJLh3RSg7SIU9IUu 9NBX+j8aC7h9DUZlUbq8hUXfGA== X-Received: by 2002:a17:902:b60c:: with SMTP id b12mr29689295pls.261.1553069398866; Wed, 20 Mar 2019 01:09:58 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.09.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:09:58 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:23 +0800 Message-Id: <20190320080829.52003-13-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 12/18] Hisilicon/D06: Modify for IMP self-Adapte support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" As new IMP(Cortex-M7) firmware support self-adapte, so do not need BIOS to implement some function, remove useless funtions and report CPU0/CPU1 Nic NCL offset to IMP. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c | 281 ++++---------------- 1 file changed, 54 insertions(+), 227 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c index aaf990216982..678c2107bdd3 100644 --- a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c +++ b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c @@ -21,44 +21,21 @@ #include #define CPU2_SFP2_100G_CARD_OFFSET 0x25 -#define CPU1_SFP1_LOCATE_OFFSET 0x16 -#define CPU1_SFP0_LOCATE_OFFSET 0x12 -#define CPU2_SFP1_LOCATE_OFFSET 0x21 -#define CPU2_SFP0_LOCATE_OFFSET 0x19 -#define CPU2_SFP2_10G_GE_CARD_OFFSET 0x25 -#define SFP_10G_SPEED 10 -#define SFP_25G_SPEED 25 -#define SFP_100G_SPEED 100 -#define SFP_GE_SPEED 1 - -#define SFP_GE_SPEED_VAL_VENDOR_FINISAR 0x0C -#define SFP_GE_SPEED_VAL 0x0D -#define SFP_10G_SPEED_VAL 0x67 -#define SFP_25G_SPEED_VAL 0xFF +#define SOCKET1_NET_PORT_100G 1 +#define SOCKET0_NET_PORT_NUM 4 +#define SOCKET1_NET_PORT_NUM 2 #define CARD_PRESENT_100G (BIT7) -#define CARD_PRESENT_10G (BIT0) -#define SELECT_SFP_BY_INDEX(index) (1 << (index - 1)) -#define SPF_SPEED_OFFSET 12 - -#define SFP_DEVICE_ADDRESS 0x50 -#define CPU1_9545_I2C_ADDR 0x70 -#define CPU2_9545_I2C_ADDR 0x71 - -#define FIBER_PRESENT 0 -#define CARD_PRESENT 1 -#define I2C_PORT_SFP 4 -#define CPU2_I2C_PORT_SFP 5 - -#define SOCKET_0 0 -#define SOCKET_1 1 #define EEPROM_I2C_PORT 4 #define EEPROM_PAGE_SIZE 0x40 #define MAC_ADDR_LEN 6 #define I2C_OFFSET_EEPROM_ETH0 (0xc00) #define I2C_SLAVEADDR_EEPROM (0x52) +#define SRAM_NIC_NCL1_OFFSET_ADDRESS 0xA0E87FE0 +#define SRAM_NIC_NCL2_OFFSET_ADDRESS 0xA0E87FE4 + #pragma pack(1) typedef struct { UINT16 Crc16; @@ -114,204 +91,6 @@ UINT16 CrcTable16[256] = { 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, }; -EFI_STATUS -GetSfpSpeed ( - UINT16 Socket, - UINT16 SfpNum, - UINT8* FiberSpeed - ) -{ - EFI_STATUS Status; - I2C_DEVICE SpdDev; - UINT8 SfpSelect; - UINT8 SfpSpeed; - UINT32 RegAddr; - UINT16 I2cAddr; - UINT32 SfpPort; - - SfpSpeed = 0x0; - if (Socket == SOCKET_1) { - I2cAddr = CPU2_9545_I2C_ADDR; - SfpPort = CPU2_I2C_PORT_SFP; - } else { - I2cAddr = CPU1_9545_I2C_ADDR; - SfpPort = I2C_PORT_SFP; - } - - Status = I2CInit (Socket, SfpPort, Normal); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Socket%d Call I2CInit failed! p1=0x%x.\n", - __FUNCTION__, __LINE__, Socket, Status)); - return Status; - } - - SpdDev.Socket = Socket; - SpdDev.DeviceType = DEVICE_TYPE_SPD; - SpdDev.Port = SfpPort; - SpdDev.SlaveDeviceAddress = I2cAddr; - RegAddr = 0x0; - SfpSelect = SELECT_SFP_BY_INDEX (SfpNum); - - Status = I2CWrite (&SpdDev, RegAddr, 1, &SfpSelect); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "I2CWrite Error =%r.\n", Status)); - return Status; - } - - SpdDev.Socket = Socket; - SpdDev.DeviceType = DEVICE_TYPE_SPD; - SpdDev.Port = SfpPort; - SpdDev.SlaveDeviceAddress = SFP_DEVICE_ADDRESS; - - RegAddr = SPF_SPEED_OFFSET; - Status = I2CRead (&SpdDev, RegAddr, 1, &SfpSpeed); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "I2CRead Error =%r.\n", Status)); - return Status; - } - - DEBUG ((DEBUG_INFO, "BR, Nominal, Nominal signalling rate, SfpSpeed: 0x%x\n", - SfpSpeed)); - - if (SfpSpeed == SFP_10G_SPEED_VAL) { - *FiberSpeed = SFP_10G_SPEED; - } else if (SfpSpeed == SFP_25G_SPEED_VAL) { - *FiberSpeed = SFP_25G_SPEED; - } else if ((SfpSpeed == SFP_GE_SPEED_VAL) || - (SfpSpeed == SFP_GE_SPEED_VAL_VENDOR_FINISAR)) { - *FiberSpeed = SFP_GE_SPEED; - } - - return EFI_SUCCESS; -} - -//Fiber1Type/Fiber2Type/Fiber3Type return: SFP_10G_SPEED, SFP_100G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu2FiberType ( - UINT8* Fiber1Type, - UINT8* Fiber2Type, - UINT8* Fiber100Ge - ) -{ - EFI_STATUS Status; - UINT16 SfpNum1; - UINT8 SfpSpeed1; - UINT16 SfpNum2; - UINT8 SfpSpeed2; - - SfpNum1 = 0x1; - SfpSpeed1 = SFP_10G_SPEED; - SfpNum2 = 0x2; - SfpSpeed2 = SFP_10G_SPEED; - *Fiber100Ge = 0x0; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - - if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { - // 100 Ge card - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - *Fiber100Ge = SFP_100G_SPEED; - DEBUG ((DEBUG_ERROR,"Detect Fiber SFP_100G is Present, Set 100Ge\n")); - } else if ((ReadCpldReg (CPU2_SFP2_10G_GE_CARD_OFFSET) & CARD_PRESENT_10G) != 0) { - *Fiber100Ge = 0x0; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - if (ReadCpldReg (CPU2_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) { - // Fiber detected in CPU2 slot0, read speed via i2c - Status = GetSfpSpeed (SOCKET_1, SfpNum1, &SfpSpeed1); - if (EFI_ERROR (Status)) { - DEBUG((DEBUG_ERROR, - "Get Socket1 Sfp%d Speed Error: %r.\n", - SfpNum1, - Status)); - return Status; - } - if (SfpSpeed1 == SFP_25G_SPEED) { - // P1 don't support 25G, so set speed to 10G - *Fiber1Type = SFP_10G_SPEED; - } else { - *Fiber1Type = SfpSpeed1; - } - } else { - // No fiber, set speed to 10G - *Fiber1Type = SFP_10G_SPEED; - } - - if (ReadCpldReg (CPU2_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) { - // Fiber detected in CPU2 slot1, read speed via i2c - Status = GetSfpSpeed (SOCKET_1, SfpNum2, &SfpSpeed2); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status)); - return Status; - } - if (SfpSpeed2 == SFP_25G_SPEED) { - *Fiber2Type = SFP_10G_SPEED; - } else { - *Fiber2Type = SfpSpeed2; - } - } else { - // No fiber, set speed to 10G - *Fiber2Type = SFP_10G_SPEED; - } - } else { - // 100Ge/10Ge/Ge Fiber is not found. - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - *Fiber100Ge = 0x0; - } - - return EFI_SUCCESS; -} - -//Fiber1Type/Fiber2Type return: SFP_10G_SPEED, SFP_25G_SPEED, SFP_GE_SPEED -UINT32 -GetCpu1FiberType ( - UINT8* Fiber1Type, - UINT8* Fiber2Type - ) -{ - EFI_STATUS Status; - UINT16 SfpNum1; - UINT8 SfpSpeed1; - UINT16 SfpNum2; - UINT8 SfpSpeed2; - - SfpNum1 = 0x1; - SfpSpeed1 = SFP_10G_SPEED; - SfpNum2 = 0x2; - SfpSpeed2 = SFP_10G_SPEED; - *Fiber1Type = SFP_10G_SPEED; - *Fiber2Type = SFP_10G_SPEED; - // Fiber detected in CPU1 slot0, read speed via i2c - if (ReadCpldReg (CPU1_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) { - Status = GetSfpSpeed (SOCKET_0, SfpNum1, &SfpSpeed1); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Get Socket0 Sfp%d Speed Error: %r.\n", - SfpNum1, Status)); - return Status; - } - *Fiber1Type = SfpSpeed1; - } else { - *Fiber1Type = SFP_10G_SPEED; - } - - // Fiber detected in CPU1 slot1, read speed via i2c - if (ReadCpldReg (CPU1_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) { - Status = GetSfpSpeed (SOCKET_0, SfpNum2, &SfpSpeed2); - if (EFI_ERROR (Status)) { - *Fiber2Type = SFP_10G_SPEED; - DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status)); - return Status; - } - *Fiber2Type = SfpSpeed2; - } else { - *Fiber2Type = SFP_10G_SPEED; - } - - return EFI_SUCCESS; -} - UINT16 MakeCrcCheckSum ( UINT8 *Buffer, UINT32 Length @@ -567,3 +346,51 @@ OemIsInitEth ( { return TRUE; } + +EFI_STATUS +ConfigCDR ( + UINT32 Socket + ) +{ + return EFI_SUCCESS; +} + +UINT32 +OemGetNclConfOffset ( + UINT32 Socket + ) +{ + UINT32 ConfigurationOffset; + + if (Socket == 0) { + // For 1st socket, the NCL configuration offset is 0 + ConfigurationOffset = 0; + MmioWrite32 (SRAM_NIC_NCL1_OFFSET_ADDRESS, ConfigurationOffset); + return ConfigurationOffset; + } + + // For 2nd Socket + if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { + ConfigurationOffset = SIZE_128KB; + } else { + ConfigurationOffset = SIZE_64KB; + } + MmioWrite32 (SRAM_NIC_NCL2_OFFSET_ADDRESS, ConfigurationOffset); + return ConfigurationOffset; +} + +UINT32 +OemGetNetPortNum ( + UINT32 Socket + ) +{ + if (Socket == 0){ + return SOCKET0_NET_PORT_NUM; + } + + if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) { + return SOCKET1_NET_PORT_100G; + } else { + return SOCKET1_NET_PORT_NUM; + } +} From patchwork Wed Mar 20 08:08:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160645 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519471jad; 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The pcie menu is suppressed for original code as these menus are not ready. This patch remove the suppression for pcie menu, so delete these menus for now. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- 5 files changed, 10 insertions(+), 197 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h index f120e3123c83..c0097d0829f0 100644 --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h @@ -49,6 +49,7 @@ typedef struct { UINT8 OSWdtAction; /*PCIe Config*/ UINT8 PcieSRIOVSupport; + UINT8 PcieDPCSupport; UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr index 08236704fbfe..93ccb99bdc67 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr @@ -62,11 +62,9 @@ formset prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP); - suppressif TRUE; goto PCIE_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); - endif; goto MISC_CONFIG_FORM_ID, prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c index 6668103af027..be4ce8820f73 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( Configuration.OSWdtTimeout = 5; Configuration.OSWdtAction = 1; // + //Set the default value of the PCIe option + // + Configuration.PcieDPCSupport = 0; + // //Set the default value of the Misc option // Configuration.EnableSmmu = 1; diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr index 7cf7cdd29ba2..c65907fe846e 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr @@ -17,203 +17,12 @@ form formid = PCIE_CONFIG_FORM_ID, title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE); - goto VFR_FORMID_PCIE_SOCKET0, - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - goto VFR_FORMID_PCIE_SOCKET1, - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); - - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; endoneof; endform; -form formid = VFR_FORMID_PCIE_SOCKET0, - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); - - goto VFR_FORMID_PCIE_PORT2, - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT4, - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT5, - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT6, - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT7, - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - -endform; - -form formid = VFR_FORMID_PCIE_SOCKET1, - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); - goto VFR_FORMID_PCIE_PORT10, - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT12, - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); - - goto VFR_FORMID_PCIE_PORT13, - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); -endform; - -form formid = VFR_FORMID_PCIE_PORT0, - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); - #undef INDEX - #define INDEX 0 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT1, - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); - - #undef INDEX - #define INDEX 1 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT2, - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); - - #undef INDEX - #define INDEX 2 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT3, - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); - - #undef INDEX - #define INDEX 3 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT4, - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); - - #undef INDEX - #define INDEX 4 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT5, - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); - - #undef INDEX - #define INDEX 5 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT6, - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); - - #undef INDEX - #define INDEX 6 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT7, - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); - - #undef INDEX - #define INDEX 7 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT8, - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); - - #undef INDEX - #define INDEX 8 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT9, - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); - - #undef INDEX - #define INDEX 9 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT10, - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); - - #undef INDEX - #define INDEX 10 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT11, - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); - - #undef INDEX - #define INDEX 11 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT12, - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); - - #undef INDEX - #define INDEX 12 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT13, - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); - - #undef INDEX - #define INDEX 13 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT14, - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); - - #undef INDEX - #define INDEX 14 - #include "PciePortConfig.hfr" - -endform; - -form formid = VFR_FORMID_PCIE_PORT15, - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); - - #undef INDEX - #define INDEX 15 - #include "PciePortConfig.hfr" - -endform; - diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni index d87d30f975b8..0127ea952dee 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni @@ -26,7 +26,8 @@ #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" - +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press to config this port." #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0" From patchwork Wed Mar 20 08:08:25 2019 Content-Type: text/plain; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id c6si1172213pgd.106.2019.03.20.01.10.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:10:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=vwAwHFgt; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 899F1211E0924; Wed, 20 Mar 2019 01:10:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 707CF211E0111 for ; Wed, 20 Mar 2019 01:10:10 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id v21so1330684pfm.12 for ; Wed, 20 Mar 2019 01:10:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ip0V/JyUxL0WXiEF06KmBbPN/FjAEZTo8CxpaLVHztg=; b=vwAwHFgtGWkVynOvOREGmRxdawYqodRlxGl3tBYSQfHn4m4yBKp72eimWgt052vJTy dl0HD4hbAofFTN654VZOK8GiNR/f1PoGo3XVMlWRiDoJdR837R1sUTKwTFLgfr0AbijH mAmQdM/E3rQLWOII9vf/ccAcQkDWvi83djsVgM38IV9YLykjjBJtH5FFJ9V+cMvv6BNp KPaVU70vUNKKje6sYjakvEIdBUGKP8CWYfs2tKHNMdDuFuBHyIK6MxGhhCDWGQxXtOm/ v/BX/HdKpWI/KjyEVbbqs3Y7AfyLAvD/oUEhUfphnDzTzo2FlaiyWCt1CwZ1QEIGb7an MW3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ip0V/JyUxL0WXiEF06KmBbPN/FjAEZTo8CxpaLVHztg=; b=HQYLvEoBBuNrTNjjkYzyzJ2OHmLccnDmrQEPDvHawrgCG8SgOSLK6eAw/iMQRoEjbg QR4ZMvWkr0owfnx+lU8o2nY/y/a/DpOFf8PXjb1rzr6q53UV+ALimKSxT4rN6z8E3W3E NV+p4Dzrl+aJvBc/9sszIqe5/3cLwXVmNBeuUj4XKjLx3aBx9fqLmLAFrxikR3JQenRl t3B5/FOwnooHIw312ER3b9VInz0lZKsa0y0DBYEm/N0iMDS0YIwOtyvjiPIo3Ee4WU/G lT/8pMEvRJWMEqraHORw4JGlTbfvrvuabgoWQQU2A/LT5tCcR6cMiMzAA5pKr3G7skIf JY4g== X-Gm-Message-State: APjAAAXSQgjAphswwHaDDgq+k/7cKlcM+Bmd8EulAKRkUSY/oy+D/sZN qAeWOkdbyCHecYbkHUz5iq4jUmVn3So= X-Received: by 2002:a17:902:2ac3:: with SMTP id j61mr29487244plb.112.1553069410110; Wed, 20 Mar 2019 01:10:10 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.10.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:10:09 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:25 +0800 Message-Id: <20190320080829.52003-15-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 14/18] Hisilicon/D06: Use new flash layout X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" In new flash layout, BIOS fd change from offset 1M to 8M in 16M spi flash. Use the new CustomData.Fv which indicate the offset of fd and which flash area can be updated for BMC. This patch is relative with patch "Use new flash layout" in edk2-non-osi. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D06/D06.fdf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index d495ad7f264c..f72b513352fb 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -29,7 +29,7 @@ [DEFINES] ################################################################################ [FD.D06] -BaseAddress = 0x204100000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +BaseAddress = 0x204800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device ErasePolarity = 1 @@ -124,7 +124,7 @@ [FD.D06] 0x003E0000|0x00010000 0x003F0000|0x00010000 -FILE = Platform/Hisilicon/D0x-CustomData.Fv +FILE = Platform/Hisilicon/D06/CustomData.Fv ################################################################################ # From patchwork Wed Mar 20 08:08:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160647 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519676jad; Wed, 20 Mar 2019 01:10:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqw9ZJ99uXRioCFwFKl/KRBqLxsfBdB/lkrXYNkx57SwabDfy9CK57U6/UUaKrmwjMwsg+zK X-Received: by 2002:a17:902:bb0c:: with SMTP id l12mr6679448pls.108.1553069420065; Wed, 20 Mar 2019 01:10:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553069420; cv=none; d=google.com; s=arc-20160816; b=dyzhztUko0QZrD/yZ+J5/ikasiCkpwoHVfxayxI/J/FHOFbuPDcvj0x2JwdEL1ugPo E3wXTReXot9C4TySS6YfP4Z5Hu5jXxtHydQD5q9eooK6QSXCyGYZIrlbrTgrkf4pCGKc P4RtdvDJ2YsnIJ6ow6pjCmiH/cgekk1+doSig66FSwsTXF8qXt/M0OY72e8gI6UVwk+2 9kvCakFz9VOGyot5gxuImFC4+2v5/AYkMqIlfhM7d7fJV+qvIHLpeHr/OTncci0U6i8J Cr5ub0RLfL4/wVJAsKJm9Hb/n5e52tsgiAIiFyQ/fVY3/KHiB/f4CEwvfYsPmn7ue7lY 3Q2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=FiUM6zru8GOP35mJ07M/VOAKhfYuWupXG7rKbhl/US8=; b=muyR7Sylspfbe5IpCfncjKzBWcBmBfVbtEarF11bWIMOEoB7bfqKlcTS7fLwONOAep TOGZVXNbbLerCPeRoWIjR76E9bYrIAGp65Iqpz2+jEBYp4FkDCzr8JO/TUoaN7etdreu qN9zr38OHM80chErLobzoRzIP/eJPlCUhIQ6pFFiyqF7sE51x7CKN9lTOGN6jWXv0L4R pcTNIUH9489IgB1V4z48IQDvkmtPudePPQpgEIe9SrLzyuh4iBQWdf8R0jC0A96AT/7b 1n8q8B43/7PzTYNJ07hsJR1GIV4uDMMpLAyZGP3JTby9Y0/fCbcMYtwK26C+drdafeA/ V5vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=sVYBv5xA; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id o3si1141032pgh.189.2019.03.20.01.10.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:10:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=sVYBv5xA; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D57A9211E0117; Wed, 20 Mar 2019 01:10:15 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::442; helo=mail-pf1-x442.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4B1012194EB77 for ; Wed, 20 Mar 2019 01:10:15 -0700 (PDT) Received: by mail-pf1-x442.google.com with SMTP id 8so1359216pfr.4 for ; Wed, 20 Mar 2019 01:10:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rTW56E8e7lJ0BSoY4LJGIwlnWA3lMCKScYjutA5zlbI=; b=sVYBv5xAoPUjpgHdXzTI3BVm5L266mwuhd4bzzzfgL/p0Dkg6e7++EPQdIMhsOUkDA jBbvrhN0BAvcYAijhwjZeud6dqDkQq+BHwQyo61HHwQF8+CK4cRv0chhbUC8q2g9tvvw uDyr5esNJLXuopc19+AfWEbnimyiXrmZqaZNpbN4HCq2dOLjtFr2oqdKoqv4esc2M2Y1 CsTgN0MExcc5P02QMAtiELDDbNY1KVi1cm2maudsRja76udOYYrq3AHy00XxLCPdoNbr KEe4S6K5944VomrWg1gjmQ2pM4x2mN7QPtjWEZmKa9iXubq9u4ZqzYmZmqVdAM12KIpB S80g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rTW56E8e7lJ0BSoY4LJGIwlnWA3lMCKScYjutA5zlbI=; b=q8CtJcpr9AcRo1yISk5OhbGGC2wo5QoCFh/z1a7wFZLq5cN8YrPZhSZG5IiMuLviM7 DijawrJf3dFwMmaa+IyUhb1yBm9ypQGCLH8nIrHSIph99kR9aywdYfHqPJblbuRF8Y2j 1+Vk8QQbtJq2zcwQkLdmy4L57NXQwuFmeUuaStGSVGvkdH8olfmnfXDhWLhxp66ljBB+ MSdXOz5iTlpISTI6eeL8I6iWYGJxyDeFzX3HrgcwIYriKkS+ixiTkR9tIGvOfMd2woeG 3FgLLYk0MhkDTdzm08IbgTqTeMPEcTrlYoMqURhm3yWZdZYkJBYR1Y4ex3+jqT0VKH9m iXjw== X-Gm-Message-State: APjAAAU3fh51A4e/pZcJ27La3et2y4Kh6ilEeWSATt8DVjaqaoNkALcR /aAs8p0u/+hAPZG4GKLHsNldOg== X-Received: by 2002:a63:fc62:: with SMTP id r34mr6611436pgk.154.1553069414984; Wed, 20 Mar 2019 01:10:14 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.10.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:10:14 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:26 +0800 Message-Id: <20190320080829.52003-16-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 15/18] Hisilicon/D06: Remove SECURE_BOOT_ENABLE definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" As secure boot is not ready, remove SECURE_BOOT_ENABLE and relative code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D06/D06.dsc | 12 ------------ Platform/Hisilicon/D06/D06.fdf | 11 ----------- 2 files changed, 23 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 6d581337f199..a3a01bfb1e23 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -30,7 +30,6 @@ [Defines] FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf DEFINE NETWORK_IP6_ENABLE = FALSE DEFINE HTTP_BOOT_ENABLE = FALSE - DEFINE SECURE_BOOT_ENABLE = FALSE !include Silicon/Hisilicon/Hisilicon.dsc.inc @@ -87,9 +86,6 @@ [LibraryClasses.common] LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf OemNicLib|Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf -!endif PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciPlatformLib|Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf @@ -290,15 +286,7 @@ [Components.common] MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { - - NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf - } - SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!else MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf -!endif Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index f72b513352fb..e402628a1b35 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -88,17 +88,10 @@ [FD.D06] #Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER -!if $(SECURE_BOOT_ENABLE) == TRUE - #Signature: gEfiAuthenticatedVariableGuid = - # { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} - 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, - 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, -!else #Signature: gEfiVariableGuid = # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, -!endif #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 0xB8, 0xdF, 0x00, 0x00, #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 @@ -183,10 +176,6 @@ [FV.FvMain] INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf -!if $(SECURE_BOOT_ENABLE) == TRUE - INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf -!endif - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf From patchwork Wed Mar 20 08:08:27 2019 Content-Type: text/plain; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id f9si1122940pgo.73.2019.03.20.01.10.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:10:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=p+J67eWZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0F74F211E0936; Wed, 20 Mar 2019 01:10:21 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4777B211E0111 for ; Wed, 20 Mar 2019 01:10:20 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id c8so1338731pfd.10 for ; Wed, 20 Mar 2019 01:10:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KPvaOhlQIrNttpd1zHkY7VkO3sW9z9lwAOQ0UmqlufM=; b=p+J67eWZHtSUty9Glfo4zRnk2eImTJrs/+FsuMDOVHVWD/0Mm9VuxT45YnJo/HYSR6 S2IthsY7WShHibcrR3TmZa1SYR1NFMCoP/fGqhdwKbaxaO38ZGCpytrsktwdnoa7OPP2 UglV9cjhmZihkigMLqJl8zilspsrsEWd85nx3Zz4GYlDvi6M1+nJDnaJuFRLD9O/W6HF L0eJrR3xaoMImcRVbzRAFjvcHRG7dTXtkLv0MxxWt79NN7rLsmxMcnu6m+LjgGkntjQI 432v1bdfw5mlZtHyHVk1U6IaHIkP5EokqoZ7T0CfKyjQVjzBI75YDIrouJv2F0EEnMsZ gtRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KPvaOhlQIrNttpd1zHkY7VkO3sW9z9lwAOQ0UmqlufM=; b=XKOXjlN+t6ye+bY2IqdPURh0j6dPM5BTuEz1hAdg3vGVQlwwSdFSo1bfWie90U8lli bpiDvjtshTKacyCAWw6mB3xxzuP8ikAFX3DZ3/185vZvoisQetHql7jyPfbPiDj7hsoj jQNW34qn7AwvcxsFhqK4Gx5dCwmymO+uya6gG4wMcyeGa8miYPZIRAkh9cLAuVcHndXA JBB/LFQOI+2GLhgVrINW18z8Xrpf39zw8XYuV+hbQKk7kKw58dq0UVnGoFDzBYvlSjZh lh1WqsxgbN6K7hCj40uEv11cwltnCRmRGhRSoEWa587N4QWfYdGdrinacNdXLVChv3DP BpXA== X-Gm-Message-State: APjAAAVB7Y3FN9nx9/wGPXMY3Z6tuSjNS36my1ih5R0n+nh09zv78bG1 2RKAqo1MU1fAdMBOlRwBF2UFrw== X-Received: by 2002:a17:902:8d89:: with SMTP id v9mr30620709plo.254.1553069419973; Wed, 20 Mar 2019 01:10:19 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.10.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:10:19 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:27 +0800 Message-Id: <20190320080829.52003-17-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 16/18] Hisilicon/D0x: Remove SP805 watchdog pcd X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" SP805 watchdog is no used for D0x, so remove it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/D03.dsc | 3 --- Platform/Hisilicon/D05/D05.dsc | 3 --- Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 1 - 3 files changed, 7 deletions(-) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index fe443dd929ad..35b54f8c83be 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -149,9 +149,6 @@ [PcdsFixedAtBuild.common] gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x7 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3 - ## SP805 Watchdog - Motherboard Watchdog - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 - ## Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2F8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 0c4f21fbe056..49bd5b37ea34 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -163,9 +163,6 @@ [PcdsFixedAtBuild.common] gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 - ## SP805 Watchdog - Motherboard Watchdog - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 - ## Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 diff --git a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf index 3563df6e10d1..4ce5f5fea1f3 100644 --- a/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf +++ b/Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf @@ -61,5 +61,4 @@ [FixedPcd] gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gHisiTokenSpaceGuid.PcdSysControlBaseAddress gHisiTokenSpaceGuid.PcdPeriSubctrlAddress - gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase From patchwork Wed Mar 20 08:08:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160649 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519773jad; Wed, 20 Mar 2019 01:10:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqzYoE7UA7KxRBSRHOfOQtWX+jy57VGBezmuJOLNzGJIyHNWOwZrcf6vB5ZGcI6gAwOFxVHV X-Received: by 2002:a65:4108:: with SMTP id w8mr6106730pgp.236.1553069429131; Wed, 20 Mar 2019 01:10:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553069429; cv=none; d=google.com; s=arc-20160816; b=q2P/CcZppYwf2dFM31AFjlBhGFBhUqdZlktpEUhUrKdw27OmDYTgfm1NFPL+RMbt0H wBL7PiqUlt3EFCg/dcrUWn5U7vEMKxTiHsYqRsnnmKckzoNqQii6eMl/NxObKBTjx/0g FNxOmVZpm5h0eJH7CDiw5YM5Zri7QHFzuYHCHo8bm7eJPi4jVEBsMoYVCpv4TZbiz48A LtauO02klwmKFWBneWfnQw/Ijp+iKSsp00vJfTOtrWH4XJdJjef40WjqxNe3K2U+eXyz cfeZVvMl21SGJcoWEHRRB9hiqA/ygi2zi/iAiobZle8CzIlkJQvHs0kxDeMFlAXflotN +9OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=pj09kqIMCY8u+oPkSDPJF5MDuY4qeGNRNwPL/gqOZ1k=; b=pTIzKhTWvJhnUPIqf8muzs67hNS7Q0Pxw++xPyUgCgzadAO7GtJzIFIjmYnwZkKzO7 VX18Funnb6egdjdQbudvRFoeZp2qTWFgLyqDVRfeqQ8AYQc91WT+12U7p8kL/vtj6prm Q0xGPluUb6Kho5TCvPb/+1mix5NxXfKHv6SSPq15orPNu3CJDf+HpIygTEC7TpudDWO9 GUGnAm8HF3zYS33RrUooO9L7hw0zMq9R6lwSuJmJUpmdIkfnFDV7pYyaBk2npV7DM+Pj Wems6Q67rGzX/LOdHzfHq1CSTpYU4PE0lRbgqX+mKG5WJe3VT18HdfI7TO+XgqipEgF3 oHUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=V3pPfgYQ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 62si1371494ple.393.2019.03.20.01.10.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 01:10:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=V3pPfgYQ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3F5F3211E093A; Wed, 20 Mar 2019 01:10:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::442; helo=mail-pf1-x442.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 69DD9211E0927 for ; Wed, 20 Mar 2019 01:10:27 -0700 (PDT) Received: by mail-pf1-x442.google.com with SMTP id 9so1101605pfj.13 for ; Wed, 20 Mar 2019 01:10:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D2GO8YDi/c7moPsk5SNIntPWbx5jh74iUOgZv5Kf+Lc=; b=V3pPfgYQgISA3Ne9NTmVc8L+xmzSWSOVHyq46t2SVoiM6Q29Jv9S3iirbF5Q2nwdBG 6ciIAL08krubhrQRceNOoI25s8epoEVaGn5K1PHp8goEEBvMywtHfPYNsRxRFACLNILE lSlJbBpvL23FWcU+aY1sY/6wV8BGE4Iy14Yey2n8278a0qTz+VylrF/idmKRZ6PhkPFk 1OxKJO8yiQVZ7wN29J0v3Ns92/egN8TsY813K19O5VjhsIrzFNrEHp5JRhN8GalY3OEB fe36Bi+0qYffi9CHCDxtP6+Gm+GmrcdUY3sENe8mwVknt0r1kY3gw/vJgdkGM9NxeO3N zadA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D2GO8YDi/c7moPsk5SNIntPWbx5jh74iUOgZv5Kf+Lc=; b=oERCtPg/QU6oYaKhW/E51tnPzBm4WDRCz4gK8nYh38RPMgo87kXIuImF2+16H6EKU0 hkazAptqUnXyILVTJe27xxbFRMXOOBodzjJWbieW1Fh6lhP+QFxode3ZM0li1fA/NnX5 5ROGGLDxL3NnUK9HLdTkZIZcDlHChBZXi1H807kmpOlUM72igeHN/xY5HcgAbNsVAkt1 bJ4oNKAB4fQysIXfF5qfSjOeJNFJh70XrlnZ6LuwqEXDdCrJnoZcgbnaBNKCtHha6gI/ KFeK4Sf+NgUnlFyO4nfzsbCqZd75BqNcogWnPQLN0PNzvkH35odZJWMT++Z2VYW0480s Ggpw== X-Gm-Message-State: APjAAAUbIiUWwW16eqAa6AndMjYlNbJEtTIZpUCXkKSJLEW69IhEmtQL qn45u6iMInv46pI34R1Mzjo/3Q== X-Received: by 2002:a63:4542:: with SMTP id u2mr6042556pgk.291.1553069427137; Wed, 20 Mar 2019 01:10:27 -0700 (PDT) Received: from localhost.localdomain ([203.160.91.226]) by smtp.gmail.com with ESMTPSA id f9sm1602796pfd.10.2019.03.20.01.10.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 01:10:26 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 20 Mar 2019 16:08:28 +0800 Message-Id: <20190320080829.52003-18-ming.huang@linaro.org> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20190320080829.52003-1-ming.huang@linaro.org> References: <20190320080829.52003-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 17/18] Hisilicon/D06: Fix USB crash issue(4079) X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, xiaojun2@hisilicon.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, zhangfeng56@huawei.com, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Last patch "Modify IORT" change revision id of node type 2 to 1, and 4.19 later kernel will judge the revision id to get root pci bridge DMA informations from IORT. As Hi1620 USB 2.0 don't support 64 bit DMA, but the DMA attribute get from IORT node type 2 is 64 bit. So add _DMA method in USB pci bridge 3 and pci bridge 8 to fix usb crash when usb device is present issue. https://bugs.linaro.org/show_bug.cgi?id=4079 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.9.5 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl index 6dc380f27fa2..c1083dc16a2a 100644 --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl @@ -375,6 +375,29 @@ Device (PCI2) PCI_OSC_SUPPORT () + Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_STA, 0x0, NotSerialized) { Return (0xf) @@ -1077,6 +1100,29 @@ Device (PCI8) Return (0xf) } + Method(_DMA, 0, Serialized) + { + Return (ResourceTemplate() + { + QWORDMemory( + ResourceConsumer, + PosDecode, // _DEC + MinFixed, // _MIF + MaxFixed, // _MAF + Prefetchable, // _MEM + ReadWrite, // _RW + 0, // _GRA + 0x00000000, // _MIN + 0xFFFFFFFF, // _MAX + 0x00000000, // _TRA + 0x100000000, // _LEN + , + , + , + ) + }) + } + Method (_PXM, 0, NotSerialized) { Return(0x02) From patchwork Wed Mar 20 08:08:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 160650 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp519876jad; Wed, 20 Mar 2019 01:10:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqy12pPwGPSxmMRamhTY21LeWuYrqa5lHNBr23xCRct4NNoI+jTnMu7mZu6Izmu4tHSb7Woq X-Received: by 2002:a62:69c3:: with SMTP id e186mr6181042pfc.169.1553069436823; Wed, 20 Mar 2019 01:10:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553069436; cv=none; d=google.com; s=arc-20160816; b=f7pxL1YkX1+8Mq44eovheQZOxf7cZB7QVvl4kERovVGFy4VJI7AOVdxh/yzsSpAmcc CFwHlK1zDSh5aXBJ2PMh4ebbl7nHwMVG3ZYe6Jhds/3AzJQOgffP5HrUxzVsEiIfGnif AS/TNoDWD1vUk2gLP7PgpTXAvNnEE+IcA6om9CGQymARobPUaKziFnbpT1mk89alroAZ 1ctwXhrnumclLJ1hlMWgFVk2KZytZq2yfv+Weo3hBcARaL1J4e3bfxD47UYIC69NexPl EGLEU0aTHkNlk9H0phTyxhQQ4EYO8WV4W05qHb8zTe3O3q+tbW0AnnJOFWkuOlK1WCfI QvfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to; bh=0Y045TQ/n3FW+4pqC3RN/CK878XOkSwsDLAImOhKZDc=; b=NllDgHiS4f71ZCuH320Wu2p/hagvGPUiE9DO5ySuUhCU/0L3beU0jxSYF0YxA/hinI KMNpOIRGgJkVoB5QiurvXFYrN+KLmmKAzvTVtlljhOIk1SpEwreV+dwpGCxXw9dslDp+ gEkToYgG+Xel2UBiHAfmmY6jlkYmbHz5joJhq7UDVgP1807xqWivYuJDnAcvF5EKz2Px uS7MKs2qSgG8RRm6+AtYNHNJC7bN+WcM6CLEiXfUwOIoPfm3t0cmTIG6iCN8D0VE6HkY Wut61bTIfdn0ko53HDOIQs0SlOTTL+wkyaItATm1vgI1nlDaIVcGZ5Gxptrr2fF8/yXN j2wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=oGZ48lD5; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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