From patchwork Wed Nov 23 13:55:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 628260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE431C47088 for ; Wed, 23 Nov 2022 14:00:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237676AbiKWOAv (ORCPT ); Wed, 23 Nov 2022 09:00:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238152AbiKWOAf (ORCPT ); Wed, 23 Nov 2022 09:00:35 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F98261778; Wed, 23 Nov 2022 05:55:43 -0800 (PST) X-UUID: 9bd9575cf7cb47109256347331381474-20221123 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=UcSDibTYH1bgQRg/3JMj/6YombyDzBS4kAvlryq/b8g=; b=aZwc7j2essVmCMsZM8dCu/04DolM6N2UOEq1JpDdXCF9m8LtN2PXMajBl1DwarO/Trdnlq1AR8pH7h1VkWcvp4UW+r2TKWFe0OqoCgv/26sKh6rTikK6NnId8o7cEJou/Cy5KqcaqCvOQ+Yq/8iqLU7mCJvN5gY3emmucYxNnng=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.13, REQID:4cbec618-ebdf-4702-8779-7d9352cf9f1a, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.13, REQID:4cbec618-ebdf-4702-8779-7d9352cf9f1a, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:d12e911, CLOUDID:2eca09dc-6ad4-42ff-91f3-18e0272db660, B ulkID:221123215540I04DUY7B,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 9bd9575cf7cb47109256347331381474-20221123 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1102575380; Wed, 23 Nov 2022 21:55:39 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 23 Nov 2022 21:55:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 23 Nov 2022 21:55:37 +0800 From: Allen-KH Cheng To: Greg Kroah-Hartman , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH v2 1/5] dt-bindings: usb: mtu3: add compatible for mt8186 Date: Wed, 23 Nov 2022 21:55:27 +0800 Message-ID: <20221123135531.23221-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> References: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add a new compatible for mt8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Matthias Brugger Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 80750b0f458a..7168110e2f9d 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt2712-mtu3 - mediatek,mt8173-mtu3 - mediatek,mt8183-mtu3 + - mediatek,mt8186-mtu3 - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 From patchwork Wed Nov 23 13:55:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 628258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 627A9C4332F for ; Wed, 23 Nov 2022 14:01:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238285AbiKWOA7 (ORCPT ); Wed, 23 Nov 2022 09:00:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238197AbiKWOAf (ORCPT ); Wed, 23 Nov 2022 09:00:35 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A450A5E9E1; Wed, 23 Nov 2022 05:55:45 -0800 (PST) X-UUID: a4bff9e288a04cca89ea3b0382910151-20221123 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=OqvYTWnxXrI3EYd1RQCHHYnyQ2I7IUO7KBmbsNLlJ68=; b=PcZpBOdUdZ2BdwtgsHE88KIkTCEozOu93rxZz3dOguQ06gCrQmuhVAT6UDfWmsuLfhFAlfRrjjE0ksaPIsW0dBtY9qmb+7C1oxZ1pBfJlR4/3o0O/sge2k1eAFmRTLItVEZZEk+s44YtcTYiMvkfIIW75vunqa/3Fv3FyaTMqak=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12, REQID:09f4717d-0b09-4d0a-a74e-f51b5a72d4fa, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327, CLOUDID:46ca09dc-6ad4-42ff-91f3-18e0272db660, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: a4bff9e288a04cca89ea3b0382910151-20221123 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 477963619; Wed, 23 Nov 2022 21:55:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 23 Nov 2022 21:55:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 23 Nov 2022 21:55:38 +0800 From: Allen-KH Cheng To: Greg Kroah-Hartman , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , , , Allen-KH Cheng Subject: [PATCH v2 2/5] arm64: dts: mt8186: Add power domains controller Date: Wed, 23 Nov 2022 21:55:28 +0800 Message-ID: <20221123135531.23221-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> References: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add power domains controller for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++ 1 file changed, 188 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index c326aeb33a10..2b03a342b8db 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -332,6 +332,194 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8186-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { + reg = ; + clocks = <&topckgen CLK_TOP_MFG>; + clock-names = "mfg00"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG1 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names = "csirx_top0", "csirx_top1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_ADSP_AO { + reg = ; + clocks = <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + clock-names = "audioadsp", "adsp_bus"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CONN_ON { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_DIS { + reg = ; + clocks = <&topckgen CLK_TOP_DISP>, + <&topckgen CLK_TOP_MDP>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "disp", "mdp", "smi_infra", "smi_common", + "smi_gals", "smi_iommu"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "vdec0", "larb"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>, + <&topckgen CLK_TOP_SENINF2>, + <&topckgen CLK_TOP_SENINF3>, + <&topckgen CLK_TOP_CAMTM>, + <&camsys CLK_CAM2MM_GALS>; + clock-names = "cam-top", "cam0", "cam1", "cam2", + "cam3", "cam-tm", "gals"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { + reg = ; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IMG { + reg = ; + clocks = <&topckgen CLK_TOP_IMG1>, + <&imgsys1 CLK_IMG1_GALS_IMG1>; + clock-names = "img-top", "gals"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_IMG2 { + reg = ; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS_IPE>; + clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", + "ipe-smi", "ipe-gals"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_VENC>, + <&vencsys CLK_VENC_CKE1_VENC>; + clock-names = "venc0", "larb"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_WPE { + reg = ; + clocks = <&topckgen CLK_TOP_WPE>, + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; + clock-names = "wpe0", "larb-ck", "larb-pclk"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8186-wdt", "mediatek,mt6589-wdt"; From patchwork Wed Nov 23 13:55:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 628259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD611C433FE for ; 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Wed, 23 Nov 2022 21:55:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 23 Nov 2022 21:55:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 23 Nov 2022 21:55:39 +0800 From: Allen-KH Cheng To: Greg Kroah-Hartman , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH v2 3/5] arm64: dts: mt8186: Add IOMMU and SMI nodes Date: Wed, 23 Nov 2022 21:55:29 +0800 Message-ID: <20221123135531.23221-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> References: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add iommu and smi nodes for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 173 +++++++++++++++++++++++ 1 file changed, 173 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 2b03a342b8db..c0481f0dc527 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -947,24 +948,113 @@ #reset-cells = <1>; }; + smi_common: smi@14002000 { + compatible = "mediatek,mt8186-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + larb0: smi@14003000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + larb1: smi@14004000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + iommu_mm: iommu@14016000 { + compatible = "mediatek,mt8186-iommu-mm"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "bclk"; + interrupts = ; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 + &larb7 &larb8 &larb9 &larb11 + &larb13 &larb14 &larb16 &larb17 + &larb19 &larb20>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + #iommu-cells = <1>; + }; + wpesys: clock-controller@14020000 { compatible = "mediatek,mt8186-wpesys"; reg = <0 0x14020000 0 0x1000>; #clock-cells = <1>; }; + larb8: smi@14023000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x14023000 0 0x1000>; + clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; + clock-names = "apb", "smi"; + mediatek,larb-id = <8>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; + }; + imgsys1: clock-controller@15020000 { compatible = "mediatek,mt8186-imgsys1"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; + larb9: smi@1502e000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1502e000 0 0x1000>; + clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, + <&imgsys1 CLK_IMG1_LARB9_IMG1>; + clock-names = "apb", "smi"; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; + }; + imgsys2: clock-controller@15820000 { compatible = "mediatek,mt8186-imgsys2"; reg = <0 0x15820000 0 0x1000>; #clock-cells = <1>; }; + larb11: smi@1582e000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1582e000 0 0x1000>; + clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, + <&imgsys2 CLK_IMG2_LARB9_IMG2>; + clock-names = "apb", "smi"; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; + }; + + larb4: smi@1602e000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1602e000 0 0x1000>; + clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; + }; + vdecsys: clock-controller@1602f000 { compatible = "mediatek,mt8186-vdecsys"; reg = <0 0x1602f000 0 0x1000>; @@ -977,12 +1067,65 @@ #clock-cells = <1>; }; + larb7: smi@17010000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + clocks = <&vencsys CLK_VENC_CKE1_VENC>, + <&vencsys CLK_VENC_CKE1_VENC>; + clock-names = "apb", "smi"; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8186-camsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + larb13: smi@1a001000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; + clock-names = "apb", "smi"; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; + }; + + larb14: smi@1a002000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; + }; + + larb16: smi@1a00f000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a00f000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; + clock-names = "apb", "smi"; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: smi@1a010000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; + clock-names = "apb", "smi"; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible = "mediatek,mt8186-camsys_rawa"; reg = <0 0x1a04f000 0 0x1000>; @@ -1001,10 +1144,40 @@ #clock-cells = <1>; }; + larb2: smi@1b002000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1b002000 0 0x1000>; + clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; + clock-names = "apb", "smi"; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + ipesys: clock-controller@1c000000 { compatible = "mediatek,mt8186-ipesys"; reg = <0 0x1c000000 0 0x1000>; #clock-cells = <1>; }; + + larb20: smi@1c00f000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1c00f000 0 0x1000>; + clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; + clock-names = "apb", "smi"; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; + }; + + larb19: smi@1c10f000 { + compatible = "mediatek,mt8186-smi-larb"; + reg = <0 0x1c10f000 0 0x1000>; + clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; + clock-names = "apb", "smi"; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; + }; }; }; From patchwork Wed Nov 23 13:55:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 628793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1BCEC433FE for ; Wed, 23 Nov 2022 14:00:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237333AbiKWOAz (ORCPT ); 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Wed, 23 Nov 2022 21:55:41 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 23 Nov 2022 21:55:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 23 Nov 2022 21:55:40 +0800 From: Allen-KH Cheng To: Greg Kroah-Hartman , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH v2 4/5] arm64: dts: mt8186: Add dsi node Date: Wed, 23 Nov 2022 21:55:30 +0800 Message-ID: <20221123135531.23221-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> References: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add dsi node for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index c0481f0dc527..4a2f7ad3c6f0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -979,6 +979,25 @@ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; + dsi0: dsi@14013000 { + compatible = "mediatek,mt8186-dsi"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + interrupts = ; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + iommu_mm: iommu@14016000 { compatible = "mediatek,mt8186-iommu-mm"; reg = <0 0x14016000 0 0x1000>; From patchwork Wed Nov 23 13:55:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 628794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D102C47089 for ; Wed, 23 Nov 2022 14:00:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238269AbiKWOAx (ORCPT ); Wed, 23 Nov 2022 09:00:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238156AbiKWOAf (ORCPT ); Wed, 23 Nov 2022 09:00:35 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B2FD65841; Wed, 23 Nov 2022 05:55:46 -0800 (PST) X-UUID: 9691b78b84e24b979fed4c196ddb4872-20221123 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=it+Cfe+nep+eXCTEyV1LJbHTkjSienPUhvJ3nl2xO/E=; b=CwLRbujt8a0sLvNUA9KRCZ078kSX6GOtvinpCIZttgk4E7Lg97814f023CmpA63/YveNXxgJgLYZFaElCemokRIazZvjKjRnylpb3pXZxkWT6vF9iXelS7lebquwGLnkgbqIASKZRsxSSIh9OH7XFwZOESpxfQ3ey69oUqQ17ds=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.13, REQID:77546c6e-e740-40fc-94bb-b5bb25d0ae19, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:d12e911, CLOUDID:57ca09dc-6ad4-42ff-91f3-18e0272db660, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 9691b78b84e24b979fed4c196ddb4872-20221123 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1704401998; Wed, 23 Nov 2022 21:55:42 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 23 Nov 2022 21:55:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 23 Nov 2022 21:55:41 +0800 From: Allen-KH Cheng To: Greg Kroah-Hartman , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , , , Allen-KH Cheng Subject: [PATCH v2 5/5] arm64: dts: mt8186: Add mtu3 nodes Date: Wed, 23 Nov 2022 21:55:31 +0800 Message-ID: <20221123135531.23221-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> References: <20221123135531.23221-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add mtu3 nodes for mt8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 75 ++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 4a2f7ad3c6f0..1761211f1464 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -848,6 +848,43 @@ status = "disabled"; }; + ssusb0: usb@11201000 { + compatible = "mediatek,mt8186-mtu3", + "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host0: usb@11200000 { + compatible = "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x420 2>; + wakeup-source; + status = "disabled"; + }; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; @@ -878,6 +915,44 @@ status = "disabled"; }; + ssusb1: usb@11281000 { + compatible = "mediatek,mt8186-mtu3", + "mediatek,mtu3"; + reg = <0 0x11281000 0 0x2dff>, + <0 0x11283e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host1: usb@11280000 { + compatible = "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11280000 0 0x1000>; + reg-names = "mac"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x424 2>; + wakeup-source; + status = "disabled"; + }; + }; + u3phy0: t-phy@11c80000 { compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2";