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[209.51.188.17]) by mx.google.com with ESMTPS id b78-20020ae9eb51000000b006fa190bdc52si2140381qkg.64.2022.11.25.03.54.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Nov 2022 03:54:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lfilWOLQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oyXGC-0005Yn-Mo; Fri, 25 Nov 2022 06:52:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oyXGA-0005Up-Lg for qemu-devel@nongnu.org; Fri, 25 Nov 2022 06:52:46 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oyXG8-00038m-Sf for qemu-devel@nongnu.org; Fri, 25 Nov 2022 06:52:46 -0500 Received: by mail-wm1-x32f.google.com with SMTP id t4so3258677wmj.5 for ; Fri, 25 Nov 2022 03:52:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uOuixkaZOsz8kew6uKue8ojhSe9BS7w0yC1difWNjKs=; b=lfilWOLQOB3NIzj+/afjB3+GXq/10vQPKwV8F1dAUutcnLToFhU1Tkox11QoMvil/Q ny9v+ZFCAdO5+nlbzt2C5NBGZNkOwZPE6tkTOsJF/f2Obu/joL1SgxFouTTNUdlYQ3P7 TOvjg557qtAiDpmNmI8LF+qbq8heed3zuS/VTXJQmOPSLp6wZ6IKCtkSG6Krux4FeqF2 J5LmgwantD0mPgwUe3PjjXkXJ3zcThmwOgvvWbGerhW6nmU0CrjYKc0yTXBg1pg9o3IO 6CjJny/Jj274nYiSjZQlVndaGHxWUtBtUAUfUS31bF8BEcABR/SX7leR26tbWrcH4ukG sg+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uOuixkaZOsz8kew6uKue8ojhSe9BS7w0yC1difWNjKs=; b=WBmtAZ1HmojveH8+ykbmVnLVaGMFoWdxzLoxQYa4uGmu4AJXI9VeAfj78agiI+zOnv CvtJYlJjXbzaZ/NC20zrkTnVc6eS7QUM0bVDQVwC4spqhAPgNUghVHsQgJWJMT8Pcx2d 9WrN92hwAi6uk2dc6PKnie+JNJZUzXAbVRyNO1ldnG3/rET51w3lhfmQ8PPXRVmY+gup hAr9tu77RkHHNGqEASnBAlv7D6GsWvqCwJ7HaWBMNMOo70B9O0/LYgOgJhVxSOXk+U3A +lAjxhdAw1BXgZqljEkqs1mgEV1FbpEryLJjWIwIU0g2fVveAfxzUycUBmnBB5pafVy1 lB2A== X-Gm-Message-State: ANoB5pl32dn26AfP/f2vAmDZ8HAbTMtq8CsoVsvdRA0dgqee9SmlvIMD as7Li2sZPZLPXn28vKcfFu2jrYEswbs6hw== X-Received: by 2002:a05:600c:1c12:b0:3c6:d8ba:eeb5 with SMTP id j18-20020a05600c1c1200b003c6d8baeeb5mr31232379wms.201.1669377163502; Fri, 25 Nov 2022 03:52:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 1/7] hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset Date: Fri, 25 Nov 2022 11:52:34 +0000 Message-Id: <20221125115240.3005559-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_VIRTIO_PCI class to 3-phase reset. This is necessary so that we can convert the subclass TYPE_VIRTIO_VGA_BASE also to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a1c9dfa7bb5..7873083b860 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2008,9 +2008,10 @@ static void virtio_pci_reset(DeviceState *qdev) } } -static void virtio_pci_bus_reset(DeviceState *qdev) +static void virtio_pci_bus_reset_hold(Object *obj) { - PCIDevice *dev = PCI_DEVICE(qdev); + PCIDevice *dev = PCI_DEVICE(obj); + DeviceState *qdev = DEVICE(obj); virtio_pci_reset(qdev); @@ -2071,6 +2072,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); device_class_set_props(dc, virtio_pci_properties); k->realize = virtio_pci_realize; @@ -2080,7 +2082,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_OTHERS; device_class_set_parent_realize(dc, virtio_pci_dc_realize, &vpciklass->parent_dc_realize); - dc->reset = virtio_pci_bus_reset; + rc->phases.hold = virtio_pci_bus_reset_hold; } static const TypeInfo virtio_pci_info = { From patchwork Fri Nov 25 11:52:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 628550 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1005627pvb; Fri, 25 Nov 2022 03:54:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf4/RdrPjr98FzAjJWBRZipH1YlUL5cRtu9hYI9Dgt9nTBRkz0BB0O8JdnS+PUqexQyQH47A X-Received: by 2002:ae9:f106:0:b0:6fa:59b4:f37b with SMTP id k6-20020ae9f106000000b006fa59b4f37bmr31898587qkg.349.1669377281809; Fri, 25 Nov 2022 03:54:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669377281; cv=none; d=google.com; s=arc-20160816; b=iOILQE2mqyPPrjP3CYXGn8jzHW6naH/eLIqkTqfMO/W+q//Nx+71imD7CaTjlC1WX2 EBuUNN+il3nQ9QBmjqaSDHfcaQNI9Ja5Vyh0gfOgYOEYXZmzjL+Z78OTgzHf6BFU4/7h HBH7oLOAW4uOxGM8w/0y3Mk0GVgKHRL8CRgewFpQma2n5D7/xdMKjs+nAgJclKGw/SID wxJ7Ums7cSMUnTKXWl+9iMPRrxJYh+2aoS05qPsP2PP5F5dCzYH1Hpr3h6bEEpvcw+Bc CY/UrE/mZg0pa3QKUlzhGLHqX9dZjYkq9ZYDwn+WMvdhCq5TIAM+Ns3HULNbLM3H1XJg h1GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=s28HkAEMCk57TyI0FXFERjAS9/PKS+59lX976L2sL8o=; b=uaxn7Ir+HopGzJ6DAVFGUspxCyqTEZFnEOIh+5jGdcnptCXdKF+SYKIXV3hAv7EM2F tWGVpXm+FowfM3Ucmh+kJFIVOwCP1uj0fCsUgx+fWdz5t7Lb2Ad7+va36fHtwEhZ9Ny1 E1VbwJviKv45DzIzz7aLpdNG5Vg1YUTH4uye9keR1nUouiSdEhyG03B0JfM4yUq347lF lTDQPm3rYWD5gJBziY5eO25c7On9KRbWYCMxKY/bF1pypvjg5yAjUlxqZ28Cst+eJPzy VTPM5R/uDy3wBG+bukYoT4NsJafBxztZWeGU8DjVB82tPPVs+Hf1jnPMpvY+uyzfEa74 nC+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YSkgwhJo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 2/7] hw/display/virtio-vga: Convert TYPE_VIRTIO_VGA_BASE to 3-phase reset Date: Fri, 25 Nov 2022 11:52:35 +0000 Message-Id: <20221125115240.3005559-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_VIRTIO_VGA_BASE class to 3-phase reset, so we don't need to use device_class_set_parent_reset() any more. Note that this is an abstract class itself; none of the subclasses override its reset method. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/display/virtio-vga.h | 2 +- hw/display/virtio-vga.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/display/virtio-vga.h b/hw/display/virtio-vga.h index 977ad5edc29..0bd9db1ceea 100644 --- a/hw/display/virtio-vga.h +++ b/hw/display/virtio-vga.h @@ -23,7 +23,7 @@ struct VirtIOVGABase { struct VirtIOVGABaseClass { VirtioPCIClass parent_class; - DeviceReset parent_reset; + ResettablePhases parent_phases; }; #endif /* VIRTIO_VGA_H */ diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c index 4dcb34c4a74..e6fb0aa876c 100644 --- a/hw/display/virtio-vga.c +++ b/hw/display/virtio-vga.c @@ -165,13 +165,15 @@ static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) } } -static void virtio_vga_base_reset(DeviceState *dev) +static void virtio_vga_base_reset_hold(Object *obj) { - VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(dev); - VirtIOVGABase *vvga = VIRTIO_VGA_BASE(dev); + VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj); + VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj); /* reset virtio-gpu */ - klass->parent_reset(dev); + if (klass->parent_phases.hold) { + klass->parent_phases.hold(obj); + } /* reset vga */ vga_common_reset(&vvga->vga); @@ -203,13 +205,14 @@ static void virtio_vga_base_class_init(ObjectClass *klass, void *data) VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass); PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); device_class_set_props(dc, virtio_vga_base_properties); dc->vmsd = &vmstate_virtio_vga_base; dc->hotpluggable = false; - device_class_set_parent_reset(dc, virtio_vga_base_reset, - &v->parent_reset); + resettable_class_set_parent_phases(rc, NULL, virtio_vga_base_reset_hold, + NULL, &v->parent_phases); k->realize = virtio_vga_base_realize; pcidev_k->romfile = "vgabios-virtio.bin"; From patchwork Fri Nov 25 11:52:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 628547 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1004985pvb; Fri, 25 Nov 2022 03:53:30 -0800 (PST) X-Google-Smtp-Source: AA0mqf5YnwZjzDS1TjdseCDkU0xsvmRCIem18qRHw+Ybw19NpmyX26mVKeha+tQal6mjTMIcXflz X-Received: by 2002:a05:620a:131b:b0:6fa:330f:77a5 with SMTP id o27-20020a05620a131b00b006fa330f77a5mr31908524qkj.361.1669377210734; Fri, 25 Nov 2022 03:53:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669377210; cv=none; d=google.com; s=arc-20160816; b=DaJB7LIw1XBEO9YtBkEVqjYOJN4rn9/9io5Kt/fBahxyIK9iNTEydq5AizfnhBmM1y ZeJ5EDKB5UAVgvToRJ5ISS4CjXcs9Go+FrNprUHeUPnT3E0vqtMkx3m4HTeh6NKEnvNa YBgnM4/qEZRj2eesc/7l1MJcgRjHtfaXDeFMFW4fSnNQs5TbNVW3GIuLxATZyYhj1kNe yPTbYO22qAQN1HFLfn+oyLwVEWn1111Zc3rn0oSQ/msTYrvOhkBwGzeCrUqifEgfOgsb fD27r+FAEh6JvsMvucUfs9mpy3U484RVAWCw795QRaW6XiqYpewhL4MeqrEDrWlXF+HU Jh/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mCVlswDC9lwKyFBztWRL0YIC/KZJpgpptO+kyEAjxcg=; b=PeznteVzGdfonSfw8rkNiAP50qLndXTnuH58XWTxayVkUliZfFzJWVeBQ3uC89lHkK I+SX4v9g07fnHmKg8tEzt30q0tafsYZpfAHyi/PtDfvwEnd9Z9Iru19Qpqz2tUOXLbDr z4lhHaFDwa5lt8KRi571BXRijw8KiVQZ557nZmEK5+FueyyrLwUa1zZDF7RcfYXUIB2U pVEVatUR/ZXuzrWyFP/dIuJEa/HDZaOYvPUiR9V458s3uAYhQ7Lh9YjHWn3049AMOgZZ 00tvdHB+GLjDEIorMmJQWO5U4ICXwezVdoSW/nkKHpfrUb5RI/5keNINgzTXCJFXPCjg Dzhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w2PUQOIw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 3/7] pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset Date: Fri, 25 Nov 2022 11:52:36 +0000 Message-Id: <20221125115240.3005559-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_PCIE_ROOT_PORT device to 3-phase reset; this is a necessary precursor to converting any of its child classes. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-bridge/pcie_root_port.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 460e48269d4..36bc0bafa7e 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -43,9 +43,10 @@ static void rp_write_config(PCIDevice *d, uint32_t address, pcie_aer_root_write_config(d, address, val, len, root_cmd); } -static void rp_reset(DeviceState *qdev) +static void rp_reset_hold(Object *obj) { - PCIDevice *d = PCI_DEVICE(qdev); + PCIDevice *d = PCI_DEVICE(obj); + DeviceState *qdev = DEVICE(obj); rp_aer_vector_update(d); pcie_cap_root_reset(d); @@ -171,13 +172,14 @@ static void rp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); k->is_bridge = true; k->config_write = rp_write_config; k->realize = rp_realize; k->exit = rp_exit; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->reset = rp_reset; + rc->phases.hold = rp_reset_hold; device_class_set_props(dc, rp_props); } From patchwork Fri Nov 25 11:52:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 628549 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1005490pvb; Fri, 25 Nov 2022 03:54:28 -0800 (PST) X-Google-Smtp-Source: AA0mqf6PB4g/WRbINVP+N+uHYiE5zYMtEHYyeOM0lufMAARqI+bW6W0ZebxcpQLaqRd9De4Z7mQP X-Received: by 2002:a05:622a:a18:b0:3a6:5496:713e with SMTP id bv24-20020a05622a0a1800b003a65496713emr14713575qtb.458.1669377268162; Fri, 25 Nov 2022 03:54:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669377268; cv=none; d=google.com; s=arc-20160816; b=pQSSMri/Bsl3XMzfQUjrpcx0RZa7Z+aCUPzO8EuwT0/UIiZB4ldWkLt7/8kvz308Qn xao/0LT45KCyvYWhUOPzJSt7lff8ws2jtSvNUN8JkejHyuG8WpzYXnLDJlAvYgVCc3hz o6qN2UALoyuOxBtM6iaAd2SfB2Tgy1Bb9cCaZyN4lL509uVMZ5uDdixWn0H1x+rTdm9k j25apxUVQsunem+mcJv33Fq0Rzf7SKqnK8bmIS7SarNlmXORjIVDr/RE/RuZLjjkZg6E CN8Xgr50cXt7UEFC7Brd7+htyA7WQxpPtlS4ValpkwA2W3kXKC/FTUJHMsLfG4w+c6NQ Lk1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IJ4qIWoL++eMLbfkZYy8FK1zBpGEGlxYqMfghUQB7Bo=; b=0vpu2M3AgS7q02U859A07QbgG/OLr0jY8ViwypkMWeOrhqiZI9GMRs168xb41FDD1U oiLuebYMl4C1xIVcq6ru/+HG2nZAhEXg3cQk6jsyBiSei2np7xEMcizcjHcAXV1sh+DX K4xcbZFAOopWxlSraMMvNKa9LFAzbjmbN9sumpSk17mQkmRisvvhfciCQiCUvFSOvnzn K6VGqscC7mMK0bPdC6m5p8wxhOoFTr3jVXHCJsUVy6BOFPnJNuxe+qstCWXiuqpeTcNJ DczQhS6QiWnFdqAxnACc7iAYmtXy24NyB9b0dxpE6KYEr84NVAEmJig+2EM8BEyVzQBP AN/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I03GyLlm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 4/7] pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset Date: Fri, 25 Nov 2022 11:52:37 +0000 Message-Id: <20221125115240.3005559-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to 3-phase reset, so they don't need to use the deprecated device_class_set_parent_reset() function any more. We have to do both in the same commit, because they keep the parent_reset field in their common parent class's class struct. Note that pnv_phb_root_port_class_init() was pointlessly setting dc->reset twice, once by calling device_class_set_parent_reset() and once directly. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- include/hw/pci/pcie_port.h | 2 +- hw/pci-bridge/cxl_root_port.c | 14 +++++++++----- hw/pci-host/pnv_phb.c | 18 ++++++++++-------- 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 7b8193061ac..d9b5d075049 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -80,7 +80,7 @@ DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT, struct PCIERootPortClass { PCIDeviceClass parent_class; DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; uint8_t (*aer_vector)(const PCIDevice *dev); int (*interrupts_init)(PCIDevice *dev, Error **errp); diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index fb213fa06ef..6664783974c 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -138,12 +138,14 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) component_bar); } -static void cxl_rp_reset(DeviceState *dev) +static void cxl_rp_reset_hold(Object *obj) { - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); - CXLRootPort *crp = CXL_ROOT_PORT(dev); + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); + CXLRootPort *crp = CXL_ROOT_PORT(obj); - rpc->parent_reset(dev); + if (rpc->parent_phases.hold) { + rpc->parent_phases.hold(obj); + } latch_registers(crp); } @@ -199,6 +201,7 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PCIDeviceClass *k = PCI_DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc); k->vendor_id = PCI_VENDOR_ID_INTEL; @@ -209,7 +212,8 @@ static void cxl_root_port_class_init(ObjectClass *oc, void *data) k->config_write = cxl_rp_write_config; device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize); - device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL, + &rpc->parent_phases); rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET; rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET; diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 0b26b43736f..c62b08538ac 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -199,14 +199,16 @@ static void pnv_phb_class_init(ObjectClass *klass, void *data) dc->user_creatable = true; } -static void pnv_phb_root_port_reset(DeviceState *dev) +static void pnv_phb_root_port_reset_hold(Object *obj) { - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); - PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); - PCIDevice *d = PCI_DEVICE(dev); + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj); + PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj); + PCIDevice *d = PCI_DEVICE(obj); uint8_t *conf = d->config; - rpc->parent_reset(dev); + if (rpc->parent_phases.hold) { + rpc->parent_phases.hold(obj); + } if (phb_rp->version == 3) { return; @@ -300,6 +302,7 @@ static Property pnv_phb_root_port_properties[] = { static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); @@ -308,9 +311,8 @@ static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, pnv_phb_root_port_properties); device_class_set_parent_realize(dc, pnv_phb_root_port_realize, &rpc->parent_realize); - device_class_set_parent_reset(dc, pnv_phb_root_port_reset, - &rpc->parent_reset); - dc->reset = &pnv_phb_root_port_reset; + resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold, + NULL, &rpc->parent_phases); dc->user_creatable = true; k->vendor_id = PCI_VENDOR_ID_IBM; From patchwork Fri Nov 25 11:52:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 628545 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1004784pvb; Fri, 25 Nov 2022 03:53:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf5PjmBBkmHt0huyY2RJbRDoQn3Dz/8hZi1t8NQo+7whHy3mckmZvZoJrgvNzmbdqv9KDxGO X-Received: by 2002:a05:622a:4a11:b0:3a5:1cc6:ae12 with SMTP id fv17-20020a05622a4a1100b003a51cc6ae12mr34875165qtb.103.1669377191567; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 5/7] hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset() Date: Fri, 25 Nov 2022 11:52:38 +0000 Message-Id: <20221125115240.3005559-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The realize method for the TYPE_ICS class uses qemu_register_reset() to register a reset handler, as a workaround for the fact that currently objects which directly inherit from TYPE_DEVICE don't get automatically reset. However, the reset function directly calls ics_reset(), which is the function that implements the legacy reset method. This means that only the parent class's data gets reset, and a subclass which also needs to handle reset, like TYPE_PHB3_MSI, has to register its own reset function. Make the TYPE_ICS reset function call device_cold_reset() instead: this will handle reset for both the parent class and the subclass, and will work whether the classes are using legacy reset or 3-phase reset. This allows us to remove the reset function that the subclass currently has to set up. Signed-off-by: Peter Maydell Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/xics.c | 2 +- hw/pci-host/pnv_phb3_msi.c | 7 ------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index dcd021af668..dd130467ccc 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -593,7 +593,7 @@ static void ics_reset(DeviceState *dev) static void ics_reset_handler(void *dev) { - ics_reset(dev); + device_cold_reset(dev); } static void ics_realize(DeviceState *dev, Error **errp) diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index 2f4112907b8..ae908fd9e41 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -239,11 +239,6 @@ static void phb3_msi_reset(DeviceState *dev) msi->rba_sum = 0; } -static void phb3_msi_reset_handler(void *dev) -{ - phb3_msi_reset(dev); -} - void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base, uint32_t count) { @@ -272,8 +267,6 @@ static void phb3_msi_realize(DeviceState *dev, Error **errp) } msi->qirqs = qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs); - - qemu_register_reset(phb3_msi_reset_handler, dev); } static void phb3_msi_instance_init(Object *obj) From patchwork Fri Nov 25 11:52:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 628552 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1005857pvb; Fri, 25 Nov 2022 03:55:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf5TTPkA0AcgcmVFWprIPlnwF6/K3XVR9HY+i9vtFWTD6nz11DQlQDMyrGv8049o7PU4951N X-Received: by 2002:a05:6214:1103:b0:4b3:e774:10f2 with SMTP id e3-20020a056214110300b004b3e77410f2mr16707333qvs.23.1669377305416; Fri, 25 Nov 2022 03:55:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669377305; cv=none; d=google.com; s=arc-20160816; b=ROulCyHhqZuipc2dexhH05PmfB/51/dSBhszUADjynt/Ulr4PE50T0EOPlW+4uWdSw u9EZHJwxJUVqLiO4W8yuIB0tJDZ/NqgL3tmITR2/2iGpCYsn5HRsAj8MisVTE/i3T4ky jMFvB4IXFnBNxgJpY3b6NmryMY6SchzamK1Tz0tc6enmU7xFQszpxnOp3DIfAVZt3+NK fzEN3AqA0AVzzkZ7V/PhAqcZ1BGQSmt2qhwjN2UsAzobZpBJ0fMCOvd6Y9PCiJ/dIc8V UVn8FZEYaX/DErKf3/s2D8bUwZcUwaKlZrnRTMDv0SUpe4nAn+70OUyHy9v4FpnVB/+E IX6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=M9Mj8OvxgQeFGTHRLXh76jvK7T283WvCeQVqE6RZnIQ=; b=pFaY2swJ3UaF8deMZ26p4eHbed5mOFl+xRcLs2qgrZ3hsKt/virIFUiOE99VtOQ3vZ VKLaQmSZIfEB6Wea5EKsoLJtTSICCYAQBCBEf7bp5bVL3yOTmUZW1X+fAPeAcZw6F3ms lKTrVh8Bx7hNfUm3vsBCtKdWvK5/Z5Bm/SWpjiodYZa61KhjAziVsjAgUwf5WsYAhRjy fMf+1dm5hxET+3vECUOGASJ5MjMLJDmPecVFmJ+T/z6KCJLsXCNA4iAL31kMPf5mdJyR Ik1vGr/6a37sGPlVTvBnjuNTNATM6KDxU5BtHCMXjHzfEyBCpUMwBekfUafA+dM+1QcK zg7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pd7sKA+N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 6/7] hw/intc/xics: Convert TYPE_ICS to 3-phase reset Date: Fri, 25 Nov 2022 11:52:39 +0000 Message-Id: <20221125115240.3005559-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_ICS class to 3-phase reset; this will allow us to convert the TYPE_PHB3_MSI class which inherits from it. Signed-off-by: Peter Maydell Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/xics.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index dd130467ccc..c7f8abd71e4 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -564,9 +564,9 @@ static void ics_reset_irq(ICSIRQState *irq) irq->saved_priority = 0xff; } -static void ics_reset(DeviceState *dev) +static void ics_reset_hold(Object *obj) { - ICSState *ics = ICS(dev); + ICSState *ics = ICS(obj); g_autofree uint8_t *flags = g_malloc(ics->nr_irqs); int i; @@ -584,7 +584,7 @@ static void ics_reset(DeviceState *dev) if (kvm_irqchip_in_kernel()) { Error *local_err = NULL; - ics_set_kvm_state(ICS(dev), &local_err); + ics_set_kvm_state(ics, &local_err); if (local_err) { error_report_err(local_err); } @@ -688,16 +688,17 @@ static Property ics_properties[] = { static void ics_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); dc->realize = ics_realize; device_class_set_props(dc, ics_properties); - dc->reset = ics_reset; dc->vmsd = &vmstate_ics; /* * Reason: part of XICS interrupt controller, needs to be wired up, * e.g. by spapr_irq_init(). */ dc->user_creatable = false; + rc->phases.hold = ics_reset_hold; } static const TypeInfo ics_info = { From patchwork Fri Nov 25 11:52:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 628551 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1005740pvb; Fri, 25 Nov 2022 03:54:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf5UIfii+zfb+2gduvv4lUhFonAsgYmFGq5U10Vb+88q6+iHaHdwtqvh2rTqGoUic/A3yRkx X-Received: by 2002:a05:622a:514d:b0:3a5:258c:d69c with SMTP id ew13-20020a05622a514d00b003a5258cd69cmr21205563qtb.279.1669377293883; Fri, 25 Nov 2022 03:54:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669377293; cv=none; d=google.com; s=arc-20160816; b=0YMFUWE1UP7ATBEEmYlrjpxyWtOFrzUtspw9gF2/p+owM4UUuu5ZW0J+/CSOjFverK AHZD7K3trq9xudmSqxMkqu9J2OE/s1COc3YXu0MSo2alL2NTsOqzfHHKEjS6abrwwlTO r+cxhVDSVHP6nBig6SpAf8/h+v1nN7KeLCPHpAhHwSWrTL9HkSDGP45VOhxD3GNV6itE VpAjVW4ocMHIQEbjWkFiz7T30cOGvTfofzsszTrNv5QRku2DQhroRGyfkTzVblBiIc48 AEVkz7gvrhkIpfVjDJUjT9uaphNW9dVW4jwdYCL9x+YlpUMs8vgobKoQfZlizE0wogK3 zQEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JK4BwjUjq8SMTmsNOtUO5YdKWY0srVFYt//aP/k+QgA=; b=RFaB+U4OoVWArockrgfeNPBOIhcsvLPhQt5S8RQfpUL+0O0pgmf+I5bReQ7zVrp+8I FRjI2K9Piio71ktaAhjleLvYJqYSGptzLQcKQMhhXUihUAd5QYXjLHUVeHuwzdONPqGl PXYAAcivw4jwiw6JheWmnU+tnlgzmyvt3gNDgmjq+ONlgX2FEm8YvHaHysb2cX4K7euo eqpHBuf70Rg9Ce3Le26IzelF/fAF2F6WHs8gBUS5+R30bsq/cIuxTk29dHRpDCKHdEc+ 3PiQzn+Nq74Wno+LCC3NAYf5q3WJWJ24elnNfYxMGYNQ5sUeMegO7fX28rgK5IWcLcRr Anag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TcMiNe5q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 7/7] hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset Date: Fri, 25 Nov 2022 11:52:40 +0000 Message-Id: <20221125115240.3005559-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_PHB3_MSI class to 3-phase reset, so we can avoid using the device_class_set_parent_reset() function. Signed-off-by: Peter Maydell Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- include/hw/ppc/xics.h | 2 +- hw/pci-host/pnv_phb3_msi.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 00b80b08c27..95ead0dd7c9 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -95,7 +95,7 @@ struct ICSStateClass { DeviceClass parent_class; DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; void (*reject)(ICSState *s, uint32_t irq); void (*resend)(ICSState *s); diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index ae908fd9e41..41e63b066f9 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -228,12 +228,14 @@ static void phb3_msi_resend(ICSState *ics) } } -static void phb3_msi_reset(DeviceState *dev) +static void phb3_msi_reset_hold(Object *obj) { - Phb3MsiState *msi = PHB3_MSI(dev); - ICSStateClass *icsc = ICS_GET_CLASS(dev); + Phb3MsiState *msi = PHB3_MSI(obj); + ICSStateClass *icsc = ICS_GET_CLASS(obj); - icsc->parent_reset(dev); + if (icsc->parent_phases.hold) { + icsc->parent_phases.hold(obj); + } memset(msi->rba, 0, sizeof(msi->rba)); msi->rba_sum = 0; @@ -287,11 +289,12 @@ static void phb3_msi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ICSStateClass *isc = ICS_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); device_class_set_parent_realize(dc, phb3_msi_realize, &isc->parent_realize); - device_class_set_parent_reset(dc, phb3_msi_reset, - &isc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, phb3_msi_reset_hold, NULL, + &isc->parent_phases); isc->reject = phb3_msi_reject; isc->resend = phb3_msi_resend;