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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:19 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang Subject: [PATCH 01/32] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Date: Sun, 4 Dec 2022 20:05:22 +0100 Message-Id: <20221204190553.3274-2-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-2-philmd@linaro.org> Reviewed-by: Igor Mammedov --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c0a2e0ab04..9bffa1b128 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -71,6 +71,8 @@ #define FLASH_SIZE 0x400000 +#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) + typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ @@ -1401,7 +1403,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, + piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true, TYPE_PIIX4_PCI_DEVICE); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); From patchwork Sun Dec 4 19:05:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 630863 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp2137872pvb; Sun, 4 Dec 2022 11:18:56 -0800 (PST) X-Google-Smtp-Source: AA0mqf5nrxv8QYcHH10YRgYt83YKvCIVnopvvVX5GbbRgE54yZGHou+r94M/pz8iLlToW3KRx9Mt X-Received: by 2002:a05:622a:4819:b0:3a6:9d10:ad73 with SMTP id fb25-20020a05622a481900b003a69d10ad73mr8856710qtb.458.1670181535934; Sun, 04 Dec 2022 11:18:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670181535; cv=none; d=google.com; s=arc-20160816; b=QGcOqdmG5BHK8UyysgNCZ+Mcwb4FidjskBucNmBngsZdhKBhN7nHJwbfpDr9vTrFT8 GQ2WjdRX/yz5pzXdhqn4+N0L/tNbqDYuFKXNGuMHwMhC/HwCSlOYZY6U5mSfrMrhTr6Z R/qaJjLmkLPecxvYYS0pRju8zAnhLAdcd6jAzyt1UM9CFK+x1L0o6WEYbp5a1u0FApcF MvtaRH1rgafdcoW4M3U80xpNoh8XDz9RwxIir8wKk1hS0mxC0evbBu7gOsv1NfPjx8ie T92/o7mVs/mBvbH2L5WSjLNKwTs36ZnsPCa6cEXFHGyYXGxdsVM+4P6rRDr9bz4vdAe5 qRpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lMFMoTtlMr7+uTcURApX//gZTvt+E84r/Dv7wPElE8g=; b=on4s2Vyje4cYZVWFIOt4N3dOAwvsechXTuYaRhysk12rR/NS1I08p0d3C9j9RfHUEU 2iWDJ8o4F/9G74Zl3I8KvXs4zuYnFhgW0jVd7iwAzFut8JQ+k6HRNbBpKQFPd51OSK5w n7ydmT0fWn8y4hEhtv2NvEvSfvyk5EJo7QeEE3uOlJh6yGFZBN3nL8L4qrUD/Ho9N5lZ S9Iy4C0PAuTjy5aofJGfb3QEKei7j4OO4O2te4nkn7OVoNmvMdfdTubfn1aLAJOGL612 no6i3bTmA5pkmv95VMcKE1RCGxDqDY8oV9LDwFCPNq3klzbiL/BM2njKIkE3DnB3lLu5 Bbmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=e5l0A+4t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:21 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang Subject: [PATCH 02/32] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Date: Sun, 4 Dec 2022 20:05:23 +0100 Message-Id: <20221204190553.3274-3-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-3-philmd@linaro.org> --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9bffa1b128..c3dcd43f37 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -803,6 +803,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); stw_p(p++, NM_HI2(kernel_entry)); @@ -840,6 +842,9 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] = { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; /* Small bootloader */ @@ -914,6 +919,20 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, #undef cpu_to_gt32 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /* From patchwork Sun Dec 4 19:05:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 630862 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp2137686pvb; Sun, 4 Dec 2022 11:18:22 -0800 (PST) X-Google-Smtp-Source: AA0mqf5R5e9SoiUvL/2t603+BoY7AtMKpyO3c1m9+Fm1Xnal1CfMq4X2yKYBhTCJeOzwNk3teTu6 X-Received: by 2002:a0c:80b1:0:b0:4bb:ae72:da99 with SMTP id 46-20020a0c80b1000000b004bbae72da99mr57335010qvb.29.1670181501849; Sun, 04 Dec 2022 11:18:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670181501; cv=none; d=google.com; s=arc-20160816; b=nQbHgH1TAgcMJ29cth1oYzYcHbDWQgcZ1p/hDedMEoDfh6vMBw6tpdk4YEnM+fjI2k RO/665NyVaY3oiyz6ZMG7X0X4Ai88Xu399wzGVAtL3hYyyFaAf4YZIGx4Ds33nxA7MTT hFOVHQxYSU+35L0ouYkEuVOgeL+PZDP1pwLWWxmHUTnip0RbUWgtKWk4NYeSkTjIdY// e6kqE9nBB9ocMhGKgxs8RmgDQHeTn+eLUHv4x0Kj/udf2QcHgXhqcsQgbsjb2p96bFlJ PBWDwxYwSO325G56xpK6mXmvel/OQf/WgbAdwNogSY2RchuG6QvDSUDdzsrKthgvtWkP 9yVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UICViTJnHcQeaPYE3gN3Gm3w5DqlM81wlE2s7yBTyiA=; b=q5gwF4u9uv2E5jB9s3CYudtffpr6KAQw0hbBs2zPqc6IxvsgiF1U1DvDkqCZJgfXwi /Ij2fbg9tQ0D9MqfZ2QwHkKKZ9qhyocP8M28+ObtUJzna1ruk9FC63YkUJKSWxyAzLyd 8XaYjvlphgL1dhmhWpevPdJG8yQpJGVvQvuaQdjUa5ZqOMyTvx24fSyg3SOa8A7U+1/p BdAMAT5jmt4vWEz4O6ZLWuxx8Ce48c8hOe+udeTlwk2gICHRE9PhAVLbMcrHsv+8oiqD 0UCSd96HgIBj1Tpi4EnLwD3oqEboZNHLHYPyP/vWNnp8NvaZoyZrPvbhd52Mkjk76/Sy uhlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LLJLigkd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[89.12.182.51]) by smtp.gmail.com with ESMTPSA id j10-20020a17090623ea00b00782ee6b34f2sm5359835ejg.183.2022.12.04.11.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 11:07:23 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , John Snow , qemu-block@nongnu.org, Igor Mammedov , Gerd Hoffmann , Aurelien Jarno , Richard Henderson , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang Subject: [PATCH 03/32] hw/isa/piix4: Correct IRQRC[A:D] reset values Date: Sun, 4 Dec 2022 20:05:24 +0100 Message-Id: <20221204190553.3274-4-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-4-philmd@linaro.org> --- hw/isa/piix4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 8fc1db6dc9..0d23e11a39 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -116,10 +116,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 + pci_conf[0x60] = 0x80; + pci_conf[0x61] = 0x80; + pci_conf[0x62] = 0x80; + pci_conf[0x63] = 0x80; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c;