From patchwork Tue Dec 6 05:52:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 631419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00326C3A5A7 for ; Tue, 6 Dec 2022 05:53:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233084AbiLFFxd (ORCPT ); Tue, 6 Dec 2022 00:53:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233443AbiLFFxa (ORCPT ); Tue, 6 Dec 2022 00:53:30 -0500 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A7C626AD2; Mon, 5 Dec 2022 21:53:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670305995; cv=none; d=zohomail.com; s=zohoarc; b=IXR+/KxxXp9HGmlxDhlYiIY7RdIlDRqki80PPtRNA2DhfRCHGHSOpPQBPlAslwJ6rtkZQuTuyk1Nd9nObvlAjmmddKzf84hJ7v9vztEYUG16oy4/fpPJvDZa1jOPZfPt3yokeIsbKEhuGnWoynpJIdocxsxRmr+VNq/mSxmmiho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1670305995; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=BuIw4xDgq4VV/tg/CyfdQWLefl/clo1mTq+M3vk5PqY=; b=jyL6ZUdo3zlWA8k11LtSRvoH2AQK2y0eQtysyl4cFpnkR+zmuNx5TqFZ9sRZfEUO1+ZBeLrA0yp7sT0A6pKzHHh3ZC0ahkiC3TkRUCBbB7esP0+4vVRbDhr9PNrLrhepoWqjrtvfW1bPMGBuzo6bncVvRgP3Plu9fa7r3B4dDXc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1670305995; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=BuIw4xDgq4VV/tg/CyfdQWLefl/clo1mTq+M3vk5PqY=; b=LOWNcfXrbnfUjGAeWSk6wCdxWeK52iK5u2oc34nP+iNuhlBe3nZxoWT1oA6MRc0i RXtMZ7rW0mTbqusodtyOZKu5ft9W8HNI/dnZrOZijVLTQHzXJyNApAnhz83LpVpqwqQ rCuJI2dsuqNVbZId3GMqtTONAlFY+YciwdOy+GP8= Received: from edelgard.fodlan.icenowy.me (120.85.99.143 [120.85.99.143]) by mx.zohomail.com with SMTPS id 1670305993579283.89111808030043; Mon, 5 Dec 2022 21:53:13 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng Subject: [PATCH v3 2/6] dt-bindings: usb: Add binding for Genesys Logic GL850G hub controller Date: Tue, 6 Dec 2022 13:52:24 +0800 Message-Id: <20221206055228.306074-3-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206055228.306074-1-uwu@icenowy.me> References: <20221206055228.306074-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Genesys Logic GL850G is a USB 2.0 Single TT hub controller that features 4 downstream ports, an internal 5V-to-3.3V LDO regulator (can be bypassed) and an external reset pin. Add a device tree binding for its USB protocol part. The internal LDO is not covered by this and can just be modelled as a fixed regulator. Signed-off-by: Icenowy Zheng --- Changes in v3: - Re-introduce GPIO flags. Changes in v2: - Misc fixes suggested by Krzysztof, including property descriptions, single-item "items" and fixing the example's gpio property. - Fixed $id. .../bindings/usb/genesys,gl850g.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/genesys,gl850g.yaml diff --git a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml new file mode 100644 index 000000000000..a9f831448cca --- /dev/null +++ b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/genesys,gl850g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Genesys Logic GL850G USB 2.0 hub controller + +maintainers: + - Icenowy Zheng + +allOf: + - $ref: usb-device.yaml# + +properties: + compatible: + enum: + - usb5e3,608 + + reg: true + + reset-gpios: + description: GPIO controlling the RESET# pin. + + vdd-supply: + description: + the regulator that provides 3.3V core power to the hub. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + usb { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + hub: hub@1 { + compatible = "usb5e3,608"; + reg = <1>; + reset-gpios = <&pio 7 2 GPIO_ACTIVE_LOW>; + }; + }; From patchwork Tue Dec 6 05:52:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 631418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52E27C352A1 for ; Tue, 6 Dec 2022 05:54:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233241AbiLFFyF (ORCPT ); Tue, 6 Dec 2022 00:54:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233396AbiLFFx6 (ORCPT ); Tue, 6 Dec 2022 00:53:58 -0500 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 753E027142; Mon, 5 Dec 2022 21:53:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670306020; cv=none; d=zohomail.com; s=zohoarc; b=LtRxaus840eTgSFHKHI4FiRq3Sc28LDH0d/vsir1aLsM47Dz5lTsmzu9KAKU9UaUn70G3vMEVybA19G2NMezI3cxJeNnXPctmgsredCuDwcU2INW0D6GvUPfE6Ay/U4Ke07sJ8aaLB3EIP93ewd6jY7B+luxviKo9UfqI41kHU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1670306020; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=/k1Z2WEqHllTXos8B4dmbQlQ4/WttliYjSasnsZMvhQ=; b=aZgxRZV+Ut4+VNrJQIBc6M3Ogxo/14bI9TvtCotaf8hrbakldORtxHAntcopZzbE/u3h+WJ+lbcGHbmPJEUPtkK1sAF+SmCqW//vkqIpgugVSJ6CHAKmKrXw77bnJQkKWvvVec3dgTkQDgiDo0oe/rSG98vI66VPOshpnOjb1mk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1670306020; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=/k1Z2WEqHllTXos8B4dmbQlQ4/WttliYjSasnsZMvhQ=; b=N/qlKYX8tYoyB7VdKKHgswYT4lcoDv2xLKWQP2j+JWExnbTnCRCQCrCg5KzDlOHE m7pjEqIlcUMMMUTLGuNwnRP/J7cnP6n3ARLuuyk+wO4YE3QdHsiHwdRtA/w5s8Z3fTb IcL6O8waDQp2ylfJh6vFFeVMWuQ/kcMIAfz9zWAA= Received: from edelgard.fodlan.icenowy.me (120.85.99.143 [120.85.99.143]) by mx.zohomail.com with SMTPS id 167030601851298.70551810068184; Mon, 5 Dec 2022 21:53:38 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng , Krzysztof Kozlowski Subject: [PATCH v3 5/6] dt-bindings: arm: sunxi: add Rongpin RP-H6B board Date: Tue, 6 Dec 2022 13:52:27 +0800 Message-Id: <20221206055228.306074-6-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206055228.306074-1-uwu@icenowy.me> References: <20221206055228.306074-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rongpin RP-H6B is a development board with RP-H6C SoM, which uses an Allwinner H6 SoC. Add compatible strings for it, including the board-specific compatible and the SoM compatible. Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski Reviewed-by: Samuel Holland --- Changes in v3: - Add Samuel's Reviewed tag. Changes in v2: - Add Krzysztof's ACK. Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 3ad1cd50e3fe..482631815f2f 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -792,6 +792,12 @@ properties: - const: rervision,h3-dvk - const: allwinner,sun8i-h3 + - description: Rongpin RP-H6B development board + items: + - const: rongpin,rp-h6b + - const: rongpin,rp-h6c + - const: allwinner,sun50i-h6 + - description: Sinlinx SinA31s Core Board items: - const: sinlinx,sina31s From patchwork Tue Dec 6 05:52:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 631417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14B32C352A1 for ; Tue, 6 Dec 2022 05:54:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233613AbiLFFyZ (ORCPT ); Tue, 6 Dec 2022 00:54:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233668AbiLFFyO (ORCPT ); Tue, 6 Dec 2022 00:54:14 -0500 X-Greylist: delayed 72 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 05 Dec 2022 21:54:12 PST Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4896A27149; Mon, 5 Dec 2022 21:54:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670306036; cv=none; d=zohomail.com; s=zohoarc; b=GW7U3CyC7xDvRppKEBI+TffDuNqtHQT007H2QB+NvJWy7X1z1/ILWmyXbhrNHsVBOa3ciDWUuKboMl73N6s9kAoCwbkS27D6dKr1jmqcgcagdb3nnfd8W09nj/RyKqc+agtpiynHGQgCJi7+kdTHaJ52nHUD4hMKV3UHE/kzAqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1670306036; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=vuHrhe8sB7Z7bW3U1yDEbRSCB55mkUv5FyHpwlQ4u1o=; b=P6+Qjqavs400VfMRUR7axbv9GbsQQ8a/A3CuLLnPRym7U+hDr+lWwLbDfNWGSooqoqngQRNTf71samBT1tWb37jTpF4AkDYvvWNKrt5/EG53cFwA279uzg330Y4NfV2y2s8alh6fKF9lL02mL6OfEKfSxyndsxi7HcdFrYm+SbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1670306036; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=vuHrhe8sB7Z7bW3U1yDEbRSCB55mkUv5FyHpwlQ4u1o=; b=QLfd/CnwZe4M5aPUNAGseZdjknn0shpOV/bDS3LFo//SKkcwIyWTx7bxsHMECCV+ REqxUiCeJ7i15IDnoA32eLRFd7EOgjoA/7SRQi5Q7WWnoSJFRu31RxLXamBirXzvqeh hlgJPNNCx2FN8f+YwZqUr/wnEJt94J9YrVKys/iU= Received: from edelgard.fodlan.icenowy.me (120.85.99.143 [120.85.99.143]) by mx.zohomail.com with SMTPS id 167030603523316.540396765307833; Mon, 5 Dec 2022 21:53:55 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng Subject: [PATCH v3 6/6] arm64: dts: allwinner: h6: add Rongpin RP-H6C SoM and RP-H6B board Date: Tue, 6 Dec 2022 13:52:28 +0800 Message-Id: <20221206055228.306074-7-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221206055228.306074-1-uwu@icenowy.me> References: <20221206055228.306074-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rongpin RP-H6C is an Allwinner H6 SoM by Rongpin, with Allwinner H6 SoC, AXP805 PMIC, LPDDR3 memory and eMMC storage on it. RP-H6B is their official evaluation board of RP-H6C, with an onboard GL850G USB hub, Ampak AP6212 Wi-Fi module and some circuits about LVDS display. It also exports the OTG USB port, the USB 3.0 port, PCIe bus (as mPCIe slot), internal Ethernet PHY, analog audio/video and HDMI port. Add a DTSI file for the SoM and a DTS for the full board. Signed-off-by: Icenowy Zheng Acked-by: Samuel Holland --- Changes in v3: - Fixed bogus comment in 3v3 regulator of AXP. It's also renamed to just vcc-3v3 instead of vcc-3v3-2. - Used new binding for LED. Changes in v2: - Name all regulator nodes regulator-xxx. - Fixed underscores in node names. arch/arm64/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun50i-h6-rp-h6b.dts | 241 ++++++++++++++++++ .../boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi | 179 +++++++++++++ 3 files changed, 421 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 6a96494a2e0a..e289fedcac29 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-rp-h6b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts new file mode 100644 index 000000000000..a1198a8ef267 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Icenowy Zheng + */ +/dts-v1/; + +#include "sun50i-h6-rp-h6c.dtsi" + +#include +#include + +/ { + model = "Rongpin RP-H6B baseboard"; + compatible = "rongpin,rp-h6b", "rongpin,rp-h6c", + "allwinner,sun50i-h6"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + /* + * Prioritize the external RTC because it's powered + * by a cell battery. + */ + rtc0 = &hym8563; + rtc1 = &rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi_connector: connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ + /* + * On the schematics this LED is marked as "lit when + * powering on and blinking when running". + */ + linux,default-trigger = "heartbeat"; + }; + }; + + /* + * The VDD_5V power rail is connected to the internal regulator + * of GL850G, to power up the 3.3V core of it. + */ + reg_v33_hub: regulator-v33-hub { + compatible = "regulator-fixed"; + regulator-name = "v33-hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vdd_5v>; + }; + + /* + * This board inputs 5V to AP6212 via a SS34 diode. Use this + * regulator as the model of the internal regulator of AP6212. + */ + reg_vcc3v3_ap6212: regulator-vcc3v3-ap6212 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3-ap6212"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ps>; + }; + + reg_vdd_5v: regulator-vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_ps>; + }; + + /* For mPCIe slot WWAN modules / PCIe cards */ + reg_vdd_3g: regulator-vdd-3g { + compatible = "regulator-fixed"; + regulator-name = "vdd-3g"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_ps>; + /* + * As a hack for lacking of control of a hub downstream + * port's Vbus. + */ + regulator-always-on; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + post-power-on-delay-ms = <200>; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + /* Genesys Logic GL850G usb hub */ + compatible = "usb5e3,608"; + reg = <1>; + vdd-supply = <®_v33_hub>; + reset-gpios = <&pio 7 2 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_vcc3v3_ap6212>; + vqmmc-supply = <®_bldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + bus-width = <4>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +/* Converted from 12v with a fixed DC-DC on the baseboard */ +®_ps { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +/* Bluetooth */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <1500000>; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_ps>; + vddio-supply = <®_bldo3>; + device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + interrupt-parent = <&r_pio>; + interrupts = <1 1 IRQ_TYPE_EDGE_FALLING>; /* PM1 */ + interrupt-names = "host-wakeup"; + }; +}; + +&uart1_pins { + bias-pull-up; +}; + +&uart1_rts_cts_pins { + bias-pull-up; +}; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + usb0_vbus-supply = <®_vdd_5v>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi new file mode 100644 index 000000000000..c91437b97f23 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2019-2022 Icenowy Zheng + */ + +#include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" +#include "sun50i-h6-gpu-opp.dtsi" + +/ { + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + /* Marked 3.4v~5.5v on SoM schematics */ + reg_ps: regulator-ps { + compatible = "regulator-fixed"; + regulator-name = "ps"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdca>; +}; + +&gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + non-removable; + cap-mmc-hw-reset; + bus-width = <8>; + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_aldo2>; + vcc-pg-supply = <®_bldo3>; +}; + +&r_pio { + /* + * FIXME: We can't add that supply for now since it would + * create a circular dependency between pinctrl, the regulator + * and the RSB Bus. + * + * vcc-pl-supply = <®_aldo1>; + */ + vcc-pm-supply = <®_bldo3>; +}; + +&r_rsb { + status = "okay"; + clock-frequency = <400000>; + + axp805: pmic@745 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&r_intc>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + vina-supply = <®_ps>; + vinb-supply = <®_ps>; + vinc-supply = <®_ps>; + vind-supply = <®_ps>; + vine-supply = <®_ps>; + aldoin-supply = <®_ps>; + bldoin-supply = <®_ps>; + cldoin-supply = <®_ps>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + regulator-enable-ramp-delay = <100000>; + }; + + aldo3 { + /* unused */ + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1160000>; + regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&rtc { + clocks = <&ext_osc32k>; +};