From patchwork Mon Mar 25 09:39:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161055 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3749461jan; Mon, 25 Mar 2019 02:42:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqxLRGj/+Aw51UIxcddqEQ1B0pHCaMlHuVK4KexcxevM77ykLQJMNEzJKGVgjHPRTmKmRXL8 X-Received: by 2002:a63:e848:: with SMTP id a8mr21498019pgk.357.1553506943252; Mon, 25 Mar 2019 02:42:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506943; cv=none; d=google.com; s=arc-20160816; b=tcGHMX6LxTNYDt3leUUn39CaA5iLb5uQhiBZxmV+EdvqeYUKhokCXFgp85J5Kyg5lS X3dj1VYmaMj2yYPxRyKwRnVL7TD3u+NX/czPXNSgKeM8x4yAMu47zXOMwxO2S3ZDO8Wt n/7h4la3EYXYY6yGnJQdssL4eJPaBtUIXrZ+BJGugiCEl64Pu6W+UP4Y6eUJ1YJ9ef2S 5UBq7R+ymIm1uU6/M8EOaNDY8rYSGlIB42dDMzitLIkJ9Omm7eVLVtq9jkkGF5LgJCC1 QSZzm/T0xu78P0w8Ak4hZmqER2u/9KYNn3j8iH2l4jmDjMzAfRImToF9EqLehAH3bQWd z/Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ihkyMdfsHkHD9vI9gQR+6re/ZkoL2kW9Ay/31C8nCOI=; b=S+ZNp0Tg2sxvl1B1WFFJmBoqozOvaRWzTYwF6qJdO/wO7/8TcOPrPD1mi3hjyjQ0aJ 4apHJ1Xp5hT0xC3xPAmHYAavZCt0Lt2Fq3KFGsRsECP4+on9qgifo1n00FiaeZWg50SO 3tp1DajlZnn+HPeeaZJU8cwa+sy1gDoRvJ8DTpIfsDTtTnFIePxtFSZ++IBYAKE044IF pZFhJUz5rEHugykXC5GpnBPlItEwUjxy0P9/F9M6H+GLYL5j8JpXtiseTjMpO2J0A54M Bas7zoba76ZeNhB5LpVCmUtTaiuowoy4c+wJVYiZMPM9tiIjEWK8nw/bqO9oQ7Wj+g8v Zabg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="tvDd6/Wu"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l13si13173673pgg.281.2019.03.25.02.42.22; Mon, 25 Mar 2019 02:42:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="tvDd6/Wu"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730476AbfCYJmW (ORCPT + 31 others); Mon, 25 Mar 2019 05:42:22 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37404 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730399AbfCYJmT (ORCPT ); Mon, 25 Mar 2019 05:42:19 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9g25h012616; Mon, 25 Mar 2019 04:42:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506923; bh=ihkyMdfsHkHD9vI9gQR+6re/ZkoL2kW9Ay/31C8nCOI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tvDd6/WuYmRV/N4/iKEiqyLVnhJqE6JzDh4TPm/S8Xvsd+mSrySJJHW9n2PECusWD X+hEmoWlKvfN4nmLU4EysWMFH3MV35vxN4mfkfaSoAGl7Eo/pKaNLglgabOgQBjsnT HkIDg8UlDTWk8vNtMVDp31XJ1/gtGB3hR27EoIcg= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9g2qx052533 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:42:02 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:42:02 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:42:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaI028077; Mon, 25 Mar 2019 04:41:57 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 03/26] dt-bindings: PCI: keystone: Add "reg-names" binding information Date: Mon, 25 Mar 2019 15:09:24 +0530 Message-ID: <20190325093947.32633-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "reg-names" binding information in order for device tree node to be populated with the correct register strings. This will break old dt compatibility. However Keystone PCI has never worked in upstream kernel due to lack of SERDES support. Before SERDES support is added, cleanup the Keystone PCI dt-bindngs. This new binding will also be used by PCI in AM654 platform. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 2030ee0dc4f9..3a551687cfa2 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -12,8 +12,10 @@ described here as well as properties that are not applicable. Required Properties:- compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. +reg: Three register ranges as listed in the reg-names property +reg-names: "dbics" for the DesignWare PCIe registers, "app" for the + TI specific application registers, "config" for the + configuration space address pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 From patchwork Mon Mar 25 09:39:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161062 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750240jan; Mon, 25 Mar 2019 02:43:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqzgcLCCtZ6jF0kKmIYdDgSXXkId7QHzyYBjnGkilm77Mwq5FNCrYc8EF85jyzKa8tE5/vwT X-Received: by 2002:a62:41dc:: with SMTP id g89mr22409407pfd.109.1553506994766; Mon, 25 Mar 2019 02:43:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506994; cv=none; d=google.com; s=arc-20160816; b=Zx1DI+jKnpeT5iLaoSMuqLaKCZnlXuWF6pve0mWTduKS16vO/seBBVhxGJleYS4rI6 abd852dqtsPx/P2rwpkOBTSGKoNNVgz5Z/cz9WqUZKuqsUBFGcrm32yAk2gV+iSBxEo9 1PIvUN8VcBNemNCPgJyUfKaLgA+REHKkmE7hcwowskYggYQXeqEaozYqiFZyOhIyNMZH g4U2cZeTPhmQU97pxM9V7a6/rQzqtOU0gS0mkkLWm2XqMCzOqkfwvRyxxuu208phrnoK HuuAJPLqd3HKvjIkEAizyfwncaS5v/rRL+UPZ2VONT/bfkxGK80QVomjNTC+6YJZElJX MDhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7srJLFU2H5APGDHmyq9l+0rZG+OkuO025oUKh/xV4Ug=; b=a8zy3uugJNbIsjz/5U6DXAcfLqTnvjomht8Nzk+QUycHe2D2/MPsA1Ti/MDlPpFeym B9Bi4tl1UVYO6+qV6tfBdjKTVGA1N/NDOXbFILkYp5BdAdPYpcPFYEHmHXCQ4+Q2XLNQ 1d0HCVGjwciGqafOpRi8eipfQy3Mx9/C5POIpw9aMHQStWNq1gJupVIEOol3orFG1T63 qRD4OhVGLCr3320WRfk1PZBzJdrF9WFi+KdEtFhJqLV48EMz6zQKiq7q3DCL/uqOywZr qGdLXoMFkF4unQU4HkLfmUSOzUsl0dUr7SvYhSr8u9WBoZvRwaMy7lYCU+UXCpKo2ANN PYOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=orn1cukg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b125si13605942pfb.242.2019.03.25.02.43.14; Mon, 25 Mar 2019 02:43:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=orn1cukg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730594AbfCYJnN (ORCPT + 31 others); Mon, 25 Mar 2019 05:43:13 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37510 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730387AbfCYJnK (ORCPT ); Mon, 25 Mar 2019 05:43:10 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9gZT5012854; Mon, 25 Mar 2019 04:42:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506955; bh=7srJLFU2H5APGDHmyq9l+0rZG+OkuO025oUKh/xV4Ug=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=orn1cukgT2qEleNPLN9Q9iVkyrbiF0c8KHohQOJ5jEqVRhkC/XMvSmVUO44PlQIyH s2bRIkFkZgjqSUfIn82ZSaXx5VzAeswCEROatoeagZIbRO1P7UKBnfqzL4pJmC+FsL aHjPDKLX6LCt97ompEfX4Y8BDgoGxT5eM9pK/Mhs= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9gZm3053275 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:42:35 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:42:35 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:42:35 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaO028077; Mon, 25 Mar 2019 04:42:30 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 09/26] dt-bindings: PCI: Document "atu" reg-names Date: Mon, 25 Mar 2019 15:09:30 +0530 Message-ID: <20190325093947.32633-10-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document "atu" reg-names required to get the register space for ATU in Synopsys designware core version >= 4.80. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index c124f9bc11f3..5561a1c060d0 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -4,8 +4,11 @@ Required properties: - compatible: "snps,dw-pcie" for RC mode; "snps,dw-pcie-ep" for EP mode; -- reg: Should contain the configuration address space. -- reg-names: Must be "config" for the PCIe configuration space. +- reg: For designware cores version < 4.80 contains the configuration + address space. For designware core version >= 4.80, contains + the configuration and ATU address space +- reg-names: Must be "config" for the PCIe configuration space and "atu" for + the ATU address space. (The old way of getting the configuration address space from "ranges" is deprecated and should be avoided.) - num-lanes: number of lanes to use From patchwork Mon Mar 25 09:39:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161077 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751764jan; Mon, 25 Mar 2019 02:45:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqx5gZBAMUWvD6qQrNjYU6TeTv+N6fJH5q7+Ac0vvGWVDv75+dzqnnoz0e1jRwnFXQUxNDIO X-Received: by 2002:a62:ee03:: with SMTP id e3mr23436945pfi.241.1553507105911; Mon, 25 Mar 2019 02:45:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507105; cv=none; d=google.com; s=arc-20160816; b=tw/h5szW4CCiyZ9EoTjjZhYyKuA6VRWurY+rkVVsDIwigVfsV9d1psofn2StCMCArp eiiDexMw3ng8zac1ceuhKXF5ArrUAEdR7eDkINZxhG0LBPo3Hx3fTgL+xUzpR1poHN/s VUV3tE+LAVZFNQmTrTPuVmrFSq8Q79ASMauLFsneO6iG/WzFafqnrmYC5/NiPploEC3y zwN5ueKOw5b60L5juGsGgyzw3b9oGz38PYAiPvLemzw35U0szdkz5qevd6EpJegTA/y7 yJQNiuL5H7OglCsTZO4EpN9pL0qwQG5RcRYf/ZXWDJFp+f0CEmCtcNxtbRV0kziNvjqO NKYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=QQnbdjchjriqY7MOSz5Hvpx/cYkzjC8wC0YfZRMaepc=; b=JrKi1qa4WreY1YPxu/7OyNVmJXufR9Tjo8p5qO5efIfIXpxTe4tLWEig+jpbJBlLiw 4Ozz4i4o4z09TpnxZGaNXCN8yLzYzIZQAYpxMvYeS2LTrf7Rs+Nlps1ogQs+q7LEEbb2 5Nd0DPwb8WsRO6MtgGh/l7MG1tFs3e3raF3qcCwo3xj4sN8aS2Tj3seR/YZ7MkjZrIy0 lJQehHkX6fpWSciY+mXEolkpPtaVwmbqsJF4KzhyjDIGyaApVwQpG9gexHHX/xXxRN/j /ao1vZm/vk2rijlbsWwwdzbqNLQZ5oeTuLz9wHud5OhBvyuz/fJssxmdwctZxV1Hpq5e HWLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NDl3Qn7Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f131si13517296pfc.92.2019.03.25.02.45.05; Mon, 25 Mar 2019 02:45:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NDl3Qn7Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730662AbfCYJnZ (ORCPT + 31 others); Mon, 25 Mar 2019 05:43:25 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:44996 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730601AbfCYJnP (ORCPT ); Mon, 25 Mar 2019 05:43:15 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9gphc067981; Mon, 25 Mar 2019 04:42:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506971; bh=QQnbdjchjriqY7MOSz5Hvpx/cYkzjC8wC0YfZRMaepc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NDl3Qn7ZEu82lsf1vt+RnsEdWpkiUl45E1Fcy1ZZNJ4MQ5Rs6PemOxjbDS/1L/mu0 oaUcM7nDgMOpCDvCbURT5JcG1ZHRrN+qKC6H05F/XLBa59BZZG4jP0+8vHFcALnYuK eDIuWgHM05SkM/K3MQZZHiQK8g4/A44hMLdzs2PI= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9gpqu109935 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:42:51 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:42:51 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:42:51 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaR028077; Mon, 25 Mar 2019 04:42:46 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 12/26] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Date: Mon, 25 Mar 2019 15:09:33 +0530 Message-ID: <20190325093947.32633-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org hook_fault_code is an ARM32 specific API for hooking into data abort. Since pci-keystone.c will be used for AM65X platforms which is an ARM64 platform, allow hook_fault_code to be compiled only for ARM32. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index dfe54553d832..93296d434f40 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -710,6 +710,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return ret; } +#ifdef CONFIG_ARM /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -729,6 +730,7 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +#endif static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) { @@ -778,12 +780,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; +#ifdef CONFIG_ARM /* * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" */ hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); +#endif ks_pcie_start_link(pci); dw_pcie_wait_for_link(pci); From patchwork Mon Mar 25 09:39:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161078 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751804jan; Mon, 25 Mar 2019 02:45:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqzeHzQOjX9OLak9Gb+419RFGRqoLmrlxpWpUjC8B2ItRzHD6/emDLkWLtUOCMfxB0gsm/0p X-Received: by 2002:a62:3585:: with SMTP id c127mr22776954pfa.71.1553507108896; Mon, 25 Mar 2019 02:45:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507108; cv=none; d=google.com; s=arc-20160816; b=jWySfE7pVZOvnxDhjT3PEW8YtoedauInFL8S89o49rWhQh4YmGW+QY/zAGmGir1dB9 9k7S+Y0OxQZCrPHqyLBmWSc5Sp5Yc/Ue9rdSj42e+g5+9xgAo0PJ13rIIGLu6PJFjqaw qsfekeQXGhuiDcDGZtjZWToBy1vQyXVdznGOhLbvBhJCkdx5IAO9ZIiQrbPapcagy/Pa 0xPPg1KqMxP9fL8Aap8t+GCJRtuPT6kjN63OcpiajLi3TtYDmB8OMGx8NdUEOl8NJQ9S HtFnMrf+0n8LMsAixmnc7umKHyu4MVerzDUmc/sqOBJOzYznQcZ1EByFBuwwPIg7FIK1 QpOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=95/DYa4qnYNzMEil6XiXEr+BPjzSPAwq2VRbXlmcz/o=; b=eucf7ub6Yy85UYES1tEWh8xJnH+5udT6MzDK+gd1XWtJUGWXOZDpsgiG3l6hZ0D66l 1QiWstmUdCc4soeUCk8IQUzQE24ED5WS2nEmDrVUxuK9Bx+CgD/OzBdqwWpNJ/5hgX9V 9fk+GUoFXSj7UJveFg+eSn66zlByJ44q6ZTr5cpgl8bJitNjOctpcwmXho+YGzQfbR5v cUxCs/ZaLU+R/q5K8f1LYlaMwO2s+AC7Wc39d5E9ztev6hT3/fevMka99/R4EDa3gWSw 5zKDE1BfFUtpJBsZf65tVqv17VTXVks+qrX4oZC8KUSYOQ8Lif66bBJIwLlxmj/F0U6l Wozg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NFgd8o1H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 8ee07197a063..5c60e911b8b1 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -11,7 +11,8 @@ described here as well as properties that are not applicable. Required Properties:- -compatibility: "ti,keystone-pcie" +compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC + Should be "ti,am654-pcie-rc" for RC on AM654x SoC reg: Three register ranges as listed in the reg-names property reg-names: "dbics" for the DesignWare PCIe registers, "app" for the TI specific application registers, "config" for the @@ -20,6 +21,9 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines + (required if the compatible is "ti,keystone-pcie") +msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt + (required if the compatible is "ti,am654-pcie-rc". ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. 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Mon, 25 Mar 2019 04:43:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaT028077; Mon, 25 Mar 2019 04:42:57 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 14/26] PCI: keystone: Add support for PCIe RC in AM654x Platforms Date: Mon, 25 Mar 2019 15:09:35 +0530 Message-ID: <20190325093947.32633-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 161 ++++++++++++++++++++-- 2 files changed, 148 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 6ea74b1c0d94..d1d00833e0b3 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -104,7 +104,7 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" - depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST help diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 93296d434f40..a6a482bd648f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +67,7 @@ #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_AER BIT(5) /* ECRC error */ +#define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ #define ERR_CORR BIT(3) /* Correctable error */ #define ERR_NONFATAL BIT(2) /* Non-fatal error */ @@ -88,8 +91,15 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) +#define AM654_PCIE_DEV_TYPE_MASK 0x3 + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +struct ks_pcie_of_data { + const struct dw_pcie_host_ops *host_ops; + unsigned int version; +}; + struct keystone_pcie { struct dw_pcie *pci; /* PCI Device ID */ @@ -109,6 +119,7 @@ struct keystone_pcie { /* Application register space */ void __iomem *va_app_base; /* DT 1st resource */ struct resource app; + bool is_am6; }; static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) @@ -250,6 +261,16 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); } +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + + dev_vdbg(dev, "dummy function so that DW core doesn't configure MSI\n"); + + return 0; +} + static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -276,10 +297,10 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) if (reg & ERR_CORR) dev_dbg(dev, "Correctable Error\n"); - if (reg & ERR_AXI) + if (!ks_pcie->is_am6 && (reg & ERR_AXI)) dev_err(dev, "AXI tag lookup fatal Error\n"); - if (reg & ERR_AER) + if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) dev_err(dev, "ECRC Error\n"); ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); @@ -377,6 +398,9 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); ks_pcie_clear_dbi_mode(ks_pcie); + if (ks_pcie->is_am6) + return; + val = ilog2(OB_WIN_SIZE); ks_pcie_app_writel(ks_pcie, OB_SIZE, val); @@ -619,6 +643,8 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); if (!intc_np) { + if (ks_pcie->is_am6) + return 0; dev_warn(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } @@ -668,6 +694,12 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); if (!intc_np) { + /* + * Since legacy interrupts are modeled as edge-interrupts in + * AM6, keep it disabled for now. + */ + if (ks_pcie->is_am6) + return 0; dev_warn(dev, "legacy-interrupt-controller node is absent\n"); return -EINVAL; } @@ -749,8 +781,10 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) if (ret) return ret; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); + dw_pcie_dbi_ro_wr_dis(pci); return 0; } @@ -803,6 +837,11 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .scan_bus = ks_pcie_v3_65_scan_bus, }; +static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { + .host_init = ks_pcie_host_init, + .msi_host_init = ks_pcie_am654_msi_host_init, +}; + static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { struct keystone_pcie *ks_pcie = priv; @@ -826,7 +865,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); @@ -836,14 +874,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } -static const struct of_device_id ks_pcie_of_match[] = { - { - .type = "pci", - .compatible = "ti,keystone-pcie", - }, - { }, -}; - static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, @@ -913,14 +943,67 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } +static int ks_pcie_am654_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = AM654_PCIE_DEV_TYPE_MASK; + val = RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + +static const struct ks_pcie_of_data ks_pcie_rc_of_data = { + .host_ops = &ks_pcie_host_ops, + .version = 0x365A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { + .host_ops = &ks_pcie_am654_host_ops, + .version = 0x490A, +}; + +static const struct of_device_id ks_pcie_of_match[] = { + { + .type = "pci", + .data = &ks_pcie_rc_of_data, + .compatible = "ti,keystone-pcie", + }, + { + .data = &ks_pcie_am654_rc_of_data, + .compatible = "ti,am654-pcie-rc", + }, + { }, +}; + static int __init ks_pcie_probe(struct platform_device *pdev) { + const struct dw_pcie_host_ops *host_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + const struct ks_pcie_of_data *data; + const struct of_device_id *match; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + struct gpio_desc *gpiod; + void __iomem *atu_base; struct resource *res; + unsigned int version; void __iomem *base; u32 num_viewport; struct phy **phy; @@ -930,6 +1013,14 @@ static int __init ks_pcie_probe(struct platform_device *pdev) int irq; int i; + match = of_match_device(of_match_ptr(ks_pcie_of_match), dev); + data = (struct ks_pcie_of_data *)match->data; + if (!data) + return -EINVAL; + + version = data->version; + host_ops = data->host_ops; + ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) return -ENOMEM; @@ -950,9 +1041,13 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + ks_pcie->is_am6 = true; + pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; + pci->version = version; ret = of_property_read_u32(np, "num-viewport", &num_viewport); if (ret < 0) { @@ -1011,6 +1106,15 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; + gpiod = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset GPIO\n"); + goto err_link; + } + ret = ks_pcie_enable_phy(ks_pcie); if (ret) { dev_err(dev, "failed to enable phy\n"); @@ -1025,10 +1129,39 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; + if (pci->version >= 0x480A) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + atu_base = devm_ioremap_resource(dev, res); + if (IS_ERR(atu_base)) { + ret = PTR_ERR(atu_base); + goto err_get_sync; + } + + pci->atu_base = atu_base; + + ret = ks_pcie_am654_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } else { + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Mar 25 09:39:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161065 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750452jan; Mon, 25 Mar 2019 02:43:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqzPLigUEv+r0r+aP1RxTHzO3MZJSZ0RTT/pOFfQKRqihXTebLbJPTyjY0l9f0PmDuApRrTT X-Received: by 2002:a62:1d8c:: with SMTP id d134mr23055438pfd.185.1553507009698; Mon, 25 Mar 2019 02:43:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507009; cv=none; d=google.com; s=arc-20160816; b=tlL1P3Uivlih1v/fwU90U7kNXw0WaCU5hK/HXbpI4NKSYOOkYX8nTFWaUg/k1t1BBQ WNQeSiHm2WYrwIg+P/QkOT8STal9QEtc3KNXlnOrSGtdP9UE0+i2G+CVKl8vFieGupzm ZZM0nNSw2C73rREUxTjVx0h94PF73Zi6ciZ/X228rGEOa0+U8+54WTcNtjGsUCztaVHF tyW2VQrLML401UDhL4LkQXsKnzXtlyJRy42pRtVG3/p6/ttV+v8RN2fhJmBUTLT5fXvj V4ycjFjuhvvD4fE85JQeuSj/2z9ORbhtKYYjUkARHlgS6IIgPjuv9GKrd66zS4XkBXlk 8uIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=9+2eOM3oSY0oLj93leiipPk6vycQ1SmzvQwVGhiyl5g=; b=yW+/nR3wVnuZ+9YvB9YaZ5rf6ocMoLclRKoKSDUK3KGUQSU41HuRcxV645J0wdEzXk jJmjbniwXm0yAtCSVnAUSekgeVnKOFVyBfnvET9dWYC1NKnLLGfPLqbrH0nhlaQP40TR tT5V5SkS7WNmqOi+O/+qUzJBstkGG3/Z0kAzPUENSlgJsIkHS88k4dw71bR5pFHI9nOC ZOcf7I0dn6kO6p3PRDdccWf5oun4DdKtKqBrQ78hBvhNJgrGWtMwdEZFxwuRF+mDTkkd saCDVYG4959bj7HUJpqai4PspfH7O/C/UkWTsmFR45BKZTa8GHontoRq53cdfRk93ptr 9c7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YO9CTCdC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k91si14007095pld.87.2019.03.25.02.43.29; Mon, 25 Mar 2019 02:43:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YO9CTCdC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730688AbfCYJn2 (ORCPT + 31 others); Mon, 25 Mar 2019 05:43:28 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45026 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730435AbfCYJnW (ORCPT ); Mon, 25 Mar 2019 05:43:22 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9h8n3068127; Mon, 25 Mar 2019 04:43:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506988; bh=9+2eOM3oSY0oLj93leiipPk6vycQ1SmzvQwVGhiyl5g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YO9CTCdCJSieMAZhaoTOAlkvr0OIWpR2ryFIhDLMmlp659M9YnWOFIsUdrGcxM2DD TT4IQHI3GzypY70iWRApg6vS2EwHccc84Zd2z+GdYq7tFAd/KpqSV5/nK6qnjiqvbd htKq/Yh+Nck8AXW/CcGTh2MiCr2IGOEV/rl6vbu0= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9h8MB049310 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:08 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:08 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:08 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaU028077; Mon, 25 Mar 2019 04:43:02 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 15/26] PCI: keystone: Invoke phy_reset API before enabling PHY Date: Mon, 25 Mar 2019 15:09:36 +0530 Message-ID: <20190325093947.32633-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SERDES connected to the PCIe controller in AM654 requires power on reset enable (POR_EN) to be set in the SERDES. The SERDES driver sets POR_EN in the reset ops and it has to be invoked before init or enable ops. In order for SERDES driver to set POR_EN, invoke phy_reset API in pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index a6a482bd648f..e4a816f53b8e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -897,6 +897,10 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) int num_lanes = ks_pcie->num_lanes; for (i = 0; i < num_lanes; i++) { + ret = phy_reset(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + ret = phy_init(ks_pcie->phy[i]); if (ret < 0) goto err_phy; From patchwork Mon Mar 25 09:39:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161066 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750561jan; Mon, 25 Mar 2019 02:43:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqx+lqz1dafhllbvncNoBgXNmqByPFLx502fZj2YWDw5GdhfI2MEOCtearxgLBGPwKPS6gk3 X-Received: by 2002:a63:9246:: with SMTP id s6mr22670064pgn.316.1553507018229; Mon, 25 Mar 2019 02:43:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507018; cv=none; d=google.com; s=arc-20160816; b=dLMTH3XgN6ywwBwXO1cxZ5wstaARWMJJOi0/WsrTufNxCp8UQEnUT0Fv+YWX4MZA3O StRIYdAU3U7V0GPa0IUbXfwjdMDIGxzJP/xISs9PP7LWYJP7sPj27/OUulYhq0H+DHdh gHnMhKTevqV1P9j4aeP2coJ2sRWDk9V2fQZReLdhPRjPl5nI5nvZA3oyHSFhDsEg6aS5 VctkgQ0ng8t+Tg/a+rVMuSzte2x9uZv2E9Z2yo5UG7gqplr0b9p5aRRKLzu7fq32R3NO b5j8uw7M1EAjzFaxCCYU2OSo4ajCuCJ6JlBx4OXsWJXUTeuO13n6BKpC8RwlbFLZV4cr u4hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dFVQ4pidiC5cYCJgE2pe5Ra71CSY84AMLd39Zm5xel0=; b=xRUmrM/Q0ktd9ERSszb4q5y82zTAML1S0mXpbwDqf7HE3pY6MCSHpD7gbLSxwMCsX2 +3qaydMylM4eF7z5IY3tiYP12aYQUysIYx+z9R9h7nWPMxieGAFDtvgK1uG9xNSmichk 6j0dW4ZSrLqM9aD+qKYuI3Jdb5L/N0C1bua9orml9Ifz42m/fErUhfqdWOrkLCnPNooH WVejMB8oeNxqGQFjKOlmoAxS7CJ1RYPVXGRlgEci+C7Jcab6XSsJ2XvU9SzEBTCVZLLn 2vdMSDD+ubWcCTr9LTcdDWJiNL2ao0rrw/MNY08EttfhI4AwhYuydQ3g7Uxy8npRn/g3 Atjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oFHlQN+Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d12si14578030pla.80.2019.03.25.02.43.37; Mon, 25 Mar 2019 02:43:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oFHlQN+Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730699AbfCYJng (ORCPT + 31 others); Mon, 25 Mar 2019 05:43:36 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45066 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730377AbfCYJnf (ORCPT ); Mon, 25 Mar 2019 05:43:35 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hEch068172; Mon, 25 Mar 2019 04:43:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506994; bh=dFVQ4pidiC5cYCJgE2pe5Ra71CSY84AMLd39Zm5xel0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oFHlQN+Zv+DIffg/ycZ53VEn1IUGxVmlUKoeiP8RnPqGdybNpVAGllBlBFJE9vh2Z s0nuMAs52kkB9fcgUF4M24KU3LAuBMhgayQZznmirlbGSwsCTX7YXayqWQ5x/2L+ma +Vd54kIfzbMRBn5JicZL6XdH2ntnKe5yyAB9MLJ4= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hEjs015765 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:14 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:13 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:13 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaV028077; Mon, 25 Mar 2019 04:43:08 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson , Sekhar Nori Subject: [PATCH v3 16/26] PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers Date: Mon, 25 Mar 2019 15:09:37 +0530 Message-ID: <20190325093947.32633-17-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled. Make of_pci_get_max_link_speed() to be also used by PCI Endpoint controllers with just CONFIG_PCI_ENDPOINT enabled. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/Makefile | 2 +- drivers/pci/of.c | 44 +++++++++++++++++++++++--------------------- 2 files changed, 24 insertions(+), 22 deletions(-) -- 2.17.1 Acked-by: Bjorn Helgaas diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 657d642fcc67..28cdd8c0213a 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -10,10 +10,10 @@ obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o \ ifdef CONFIG_PCI obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_SYSFS) += slot.o -obj-$(CONFIG_OF) += of.o obj-$(CONFIG_ACPI) += pci-acpi.o endif +obj-$(CONFIG_OF) += of.o obj-$(CONFIG_PCI_QUIRKS) += quirks.o obj-$(CONFIG_PCIEPORTBUS) += pcie/ obj-$(CONFIG_HOTPLUG_PCI) += hotplug/ diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 3d32da15c215..8095933f8452 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -15,6 +15,7 @@ #include #include "pci.h" +#ifdef CONFIG_PCI void pci_set_of_node(struct pci_dev *dev) { if (!dev->bus->dev.of_node) @@ -196,27 +197,6 @@ int of_get_pci_domain_nr(struct device_node *node) } EXPORT_SYMBOL_GPL(of_get_pci_domain_nr); -/** - * This function will try to find the limitation of link speed by finding - * a property called "max-link-speed" of the given device node. - * - * @node: device tree node with the max link speed information - * - * Returns the associated max link speed from DT, or a negative value if the - * required property is not found or is invalid. - */ -int of_pci_get_max_link_speed(struct device_node *node) -{ - u32 max_link_speed; - - if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || - max_link_speed > 4) - return -EINVAL; - - return max_link_speed; -} -EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); - /** * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only * is present and valid @@ -537,3 +517,25 @@ int pci_parse_request_of_pci_ranges(struct device *dev, return err; } +#endif /* CONFIG_PCI */ + +/** + * This function will try to find the limitation of link speed by finding + * a property called "max-link-speed" of the given device node. + * + * @node: device tree node with the max link speed information + * + * Returns the associated max link speed from DT, or a negative value if the + * required property is not found or is invalid. + */ +int of_pci_get_max_link_speed(struct device_node *node) +{ + u32 max_link_speed; + + if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || + max_link_speed > 4) + return -EINVAL; + + return max_link_speed; +} +EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); From patchwork Mon Mar 25 09:39:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161067 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750608jan; Mon, 25 Mar 2019 02:43:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwxXFsGXy8LyDZz6OxiqfCtuhSHXI4CN2qH5kR9VxNRBzW3Dr2h3e+ccIfFR+6e2jcfcbWG X-Received: by 2002:a17:902:7c0f:: with SMTP id x15mr23624056pll.98.1553507021937; Mon, 25 Mar 2019 02:43:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507021; cv=none; d=google.com; s=arc-20160816; b=NB5PUH+Bg2EyVV7QOqtSyHNwx8QH/Nl0McVcmSKrytAU5p+NP3ui1fQHQXyVeSIrFq X/3ZS8G9Sqa/ok4BcfXuJHPx+TFkI5HUqZXEKPvoPj9VTLsBADCo2xEpY42cfPZeUDTc CwFnzXRGQsIY8on7tNStmSli/ZQPnMrep74cE1FF2lCaHN6vNQfAd2lM7xZgCdItZEx8 X/uUO9ujEfiduWTxVtbgPAxM8fa+neoP4y3scggRkcC9qqgfB8ltcVNBwZhsHvjTVmke UiAwxRhrCaCP414gLvwC6JUbCB0Ey0Rri+7ZGBdLixVLPMXGNusT0KcX8priCTvcvYob lpDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=chMDM1S73N5348Ke4wiey3wF6sgdC3UveRlW6BwAUuY=; b=yjv7+LBi4w+sDKKGF+OgLRpW0tZ9Pj5VciljrGMtvhKLQRDXd3mU21qiaFI2sykf0t YMW4BG+1GlIIJXygvg7wxb5kB2v/ZBmyfJECe08zUx6zFfvgOZsmKDREoyZFKYxVAe6b /k2fcWVxwBTFujwgupFyrzlJKn+iAWJ4dgM3Tk346ZiiyQ4QjZwzxVljhh6X2wkak3o2 8gv15Bd7Vd5mBNGruVmOPtzbw27CYEtfFfVtbTQmAxZ4XyHunr98YVcIT2bd96fjFMn/ 9eFq8NYLjJgpEKizDAOdUEN4K4UGVezRH9JvXKqvq7wDch94UKi0CMmWN44ixVHKHsxy xxAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="XocAwBs/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d12si14578030pla.80.2019.03.25.02.43.41; Mon, 25 Mar 2019 02:43:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="XocAwBs/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730711AbfCYJnk (ORCPT + 31 others); Mon, 25 Mar 2019 05:43:40 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37620 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730377AbfCYJni (ORCPT ); Mon, 25 Mar 2019 05:43:38 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hJiE013307; Mon, 25 Mar 2019 04:43:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506999; bh=chMDM1S73N5348Ke4wiey3wF6sgdC3UveRlW6BwAUuY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XocAwBs/92tYgDwGP41RltrF4uz0r5BUbqpDCAG58QkcqXggkGCKzL82SH9nYC73A Lm4dQP2MnHhaFAI5buWz/mMs4xXjXTkn3JFzwcnmxSEztoL58AnXevIN2J6bFZ0y5W eyGqvnHdLmiD3W3nd+U0xQiqifw72L6AGmRRNgn8= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hJLt015902 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:19 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:19 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:19 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaW028077; Mon, 25 Mar 2019 04:43:14 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 17/26] PCI: keystone: Add support to set the max link speed from DT Date: Mon, 25 Mar 2019 15:09:38 +0530 Message-ID: <20190325093947.32633-18-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCIe in TI's AM654 devices is by default configured to work in GEN3 mode. However PCIe doesn't work reliably in GEN3 mode because of SERDES configuration. Add support to set the link speed to GEN1, GEN2 or GEN3 based on "max-link-speed" dt property with GEN2 as the default speed if "max-link-speed" is absent. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e4a816f53b8e..312fd0c49bbb 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -28,6 +28,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE_VENDORID_MASK 0xffff @@ -89,6 +90,8 @@ #define LEG_EP 0x1 #define RC 0x2 +#define EXP_CAP_ID_OFFSET 0x70 + #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 @@ -971,6 +974,31 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; } +static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed) +{ + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP); + if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { + val &= ~((u32)PCI_EXP_LNKCAP_SLS); + val |= link_speed; + dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP, + val); + } + + val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2); + if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { + val &= ~((u32)PCI_EXP_LNKCAP_SLS); + val |= link_speed; + dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2, + val); + } + + dw_pcie_dbi_ro_wr_dis(pci); +} + static const struct ks_pcie_of_data ks_pcie_rc_of_data = { .host_ops = &ks_pcie_host_ops, .version = 0x365A, @@ -1011,6 +1039,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) void __iomem *base; u32 num_viewport; struct phy **phy; + int link_speed; u32 num_lanes; char name[10]; int ret; @@ -1165,6 +1194,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) gpiod_set_value_cansleep(gpiod, 1); } + link_speed = of_pci_get_max_link_speed(np); + if (link_speed < 0) + link_speed = 2; + + ks_pcie_set_link_speed(pci, link_speed); + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) From patchwork Mon Mar 25 09:39:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161068 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750675jan; Mon, 25 Mar 2019 02:43:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqz39ZpkagGbhXTic/ZL455cDm979IkqjPyXNzRhpNhel4u15mD6GfyXDkvS1j8WeOC8NASY X-Received: by 2002:a63:4a4d:: with SMTP id j13mr22052728pgl.16.1553507026133; Mon, 25 Mar 2019 02:43:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507026; cv=none; d=google.com; s=arc-20160816; b=UDf+3YoiJNP83AdZtWTR35baMcloFn4NgXWf4c9beeK+IOCinI2Mt9bKsLsXM+LVle jAQP3AoCil+Rkf1r8eKRlIZ1i/qpQTAmWCLiCh9A5g/OAD7uDz/9OzkU3bihyDwtDxZM 6PJy9DWVlXoOhm7/5w+PXoLvxiSN4nzSlvjo9k5BAGRaaawUcEOxeGLI5Lo7Oq1/rqI4 AqzFgTF8IJxCmaCYQwVb/N1ROIWnPeZUdw/7b+GSu9gYWviPQT13GZhguZNMGIhOPnEK Z57coBXq0imjo6BjOGVpKoQwzWzIOSGJMlhwRMy4HdAtpRQ1CIBxMTFB9yM+575eauUp To1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=FQifuCUrENL8NGdaDyObLGabN5HL+zMUVCN85TUbVgM=; b=pB5GBQfXStR03v5CNt4vsmBtd0poTIkvoBSCoPrcgGogbYzwyMuT6RBNvnDq3VM6Ic fqVnAmq9gcxYrByFusDu++tiK32I+7q6KvTIIvpzo64VDuZfIbwj/z6ZmunfZDmd9amO 5h03Th1/CFZWVgjd9BvBSQCF40/coNJOrs8Hle/t3EFYySwcqKOazakYkdZWf4HR2t4t df31qTqnOPzrx+Ve4lK9Z2WMyFxbkEx0OL4GumNgkpG9IiUe1sTPzLE9MWYVJ5fBGwGW o2s2uLO0UfsmGVYg0QnynSQgB3L0JG6kTysNceaBzLqSAynmuhRQJ0Msyg7V7xQctJxD +hWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nlPQcs5q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b38si14443486plb.249.2019.03.25.02.43.45; Mon, 25 Mar 2019 02:43:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nlPQcs5q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730724AbfCYJno (ORCPT + 31 others); Mon, 25 Mar 2019 05:43:44 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33508 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730354AbfCYJnn (ORCPT ); Mon, 25 Mar 2019 05:43:43 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hPd4011039; Mon, 25 Mar 2019 04:43:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507005; bh=FQifuCUrENL8NGdaDyObLGabN5HL+zMUVCN85TUbVgM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nlPQcs5qQJ4Ue+c8U7Tk4rTpjRn3ZCJsiFDqYD8LXv8BMT/oldhNbH7Oveo1sC2mW ZPdfbCXiOQ8toxuSeJY7SgDCq+i9EXLPyVbdogfMaCc1zhqHtEm6KqlZKS71lHBEL1 5iHFQbkeWCR4PUdKzZgJJ0CW2QsuRmyyy0q3q7YQ= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hPto054497 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:25 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:24 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaX028077; Mon, 25 Mar 2019 04:43:19 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 18/26] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Date: Mon, 25 Mar 2019 15:09:39 +0530 Message-ID: <20190325093947.32633-19-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Modify pci_epf_alloc_space API to take alignment size as argument in order to argument in order to allocate aligned buffers to be mapped to BARs. Add 'align' parameter to epc_features which can be used by platform drivers to specifiy the BAR allocation alignment requirements and use this while invoking pci_epf_alloc_space. This is mainly required for Synopsys Designware PCIe core which masks the lower bits based on the BAR size (See "I/O and MEM Match Modes" section in DesignWare Cores PCI Express Controller Databook version 4.90a). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/functions/pci-epf-test.c | 5 +++-- drivers/pci/endpoint/pci-epf-core.c | 10 ++++++++-- include/linux/pci-epc.h | 2 ++ include/linux/pci-epf.h | 3 ++- 4 files changed, 15 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index d0b91da49bf4..c0786ca74312 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -438,7 +438,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) epc_features = epf_test->epc_features; base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg), - test_reg_bar); + test_reg_bar, epc_features->align); if (!base) { dev_err(dev, "Failed to allocated register space\n"); return -ENOMEM; @@ -453,7 +453,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) if (!!(epc_features->reserved_bar & (1 << bar))) continue; - base = pci_epf_alloc_space(epf, bar_size[bar], bar); + base = pci_epf_alloc_space(epf, bar_size[bar], bar, + epc_features->align); if (!base) dev_err(dev, "Failed to allocate space for BAR%d\n", bar); diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 8bfdcd291196..fb1306de8f40 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -109,10 +109,12 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); * pci_epf_alloc_space() - allocate memory for the PCI EPF register space * @size: the size of the memory that has to be allocated * @bar: the BAR number corresponding to the allocated register space + * @align: alignment size for the allocation region * * Invoke to allocate memory for the PCI EPF register space. */ -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align) { void *space; struct device *dev = epf->epc->dev.parent; @@ -120,7 +122,11 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) if (size < 128) size = 128; - size = roundup_pow_of_two(size); + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL); if (!space) { diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index c3ffa3917f88..f641badc2c61 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -109,6 +109,7 @@ struct pci_epc { * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs * @bar_fixed_size: Array specifying the size supported by each BAR + * @align: alignment size required for BAR buffer allocation */ struct pci_epc_features { unsigned int linkup_notifier : 1; @@ -117,6 +118,7 @@ struct pci_epc_features { u8 reserved_bar; u8 bar_fixed_64bit; u64 bar_fixed_size[BAR_5 + 1]; + size_t align; }; #define to_pci_epc(device) container_of((device), struct pci_epc, dev) diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index ec02f58758c8..2d6f07556682 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -149,7 +149,8 @@ void pci_epf_destroy(struct pci_epf *epf); int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); void pci_epf_unregister_driver(struct pci_epf_driver *driver); -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar); +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align); void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); int pci_epf_bind(struct pci_epf *epf); void pci_epf_unbind(struct pci_epf *epf); From patchwork Mon Mar 25 09:39:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161069 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750843jan; Mon, 25 Mar 2019 02:43:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqwlMLfggqWF6RtUyrxNks4lsSZfhVw1z1yhTyq+JnQtF+BUJRuS6wjmTvPXBRE4HkPr5TOP X-Received: by 2002:a62:1346:: with SMTP id b67mr23763321pfj.195.1553507035235; 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index ae84a69ae63a..b287dbf6914c 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -406,7 +406,7 @@ dra7xx_pcie_get_features(struct dw_pcie_ep *ep) return &dra7xx_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dra7xx_pcie_ep_init, .raise_irq = dra7xx_pcie_raise_irq, .get_features = dra7xx_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index a42c9c3ae1cc..be61d96cc95e 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -79,7 +79,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, } } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = ls_pcie_ep_init, .raise_irq = ls_pcie_ep_raise_irq, .get_features = ls_pcie_ep_get_features, diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index dba83abfe764..d00252bd8fae 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -444,7 +444,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, }; diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 932dbd0b34b6..b58fdcbc664b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -106,7 +106,7 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep) return &dw_plat_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dw_plat_pcie_ep_init, .raise_irq = dw_plat_pcie_ep_raise_irq, .get_features = dw_plat_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 90a5b1215344..e36941ff7cf6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -196,7 +196,7 @@ struct dw_pcie_ep_ops { struct dw_pcie_ep { struct pci_epc *epc; - struct dw_pcie_ep_ops *ops; + const struct dw_pcie_ep_ops *ops; phys_addr_t phys_base; size_t addr_size; size_t page_size; From patchwork Mon Mar 25 09:39:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161070 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751001jan; Mon, 25 Mar 2019 02:44:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqysxsqlN1BpKOyj9rUtjISWVCGtcFypyBZJykZbFtP6wPM+QTALLbK6cqpY5JKsgZQYMTnK X-Received: by 2002:a17:902:758f:: with SMTP id j15mr24255886pll.211.1553507046589; Mon, 25 Mar 2019 02:44:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507046; cv=none; d=google.com; s=arc-20160816; b=dZDTwk2ntTq7akOEkwibiEk+KgUiHj9DaSWrLfri224eoC2+8B3iof3v754ZrNLG+i 83u/9T1JA5UWY3HHT5GLLA9KbM0Esb4DbVGVH1wjTA2BK190uLzJbDTSzWZSHf2rSOKk 9gT/PGMHlDxmeAl+YklGW6p2GCe8P97H2I7umgeKmFeC0TTSg9NTNUO61QAbT2VACInH gVODzPlwbN+oqbGIx0kq3qdk4sW017Xe+41jOccqA8fmfXT1WroDDnlmOH6xLMaxr6oJ b2E1pKWo0mGAvZYyHhc+1tlqWyoMnYhb7Ta/eIjpygnYU1oiCgreIoPfi6bz2Bs6Clrc cA4A== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id e67si14744205plb.107.2019.03.25.02.44.06; Mon, 25 Mar 2019 02:44:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lk0jUiMT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730766AbfCYJoF (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:05 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33588 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730332AbfCYJoD (ORCPT ); Mon, 25 Mar 2019 05:44:03 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hZ77011109; Mon, 25 Mar 2019 04:43:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507016; bh=F1vNw6974A4SxeLsowTyiNZ0yV33iVQDSJNdrli8b/8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lk0jUiMTO3bL980SrgGsvlkPHcorS0hl3VaUCKbJoAfkqj6xXOv+du67c1KxSu2dV /S4+iDcjCrq1XoaWiAtkq+h/swtVcOfHVJ8wGj5BwllEPUDJgU9tf8W4z+l6xKO6J5 sZe2RPj+Sxe/EXMW5My1ycpdTsk3F5XBe3d+7DtQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hZRt054894 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:35 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:35 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:35 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaZ028077; Mon, 25 Mar 2019 04:43:30 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 20/26] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Date: Mon, 25 Mar 2019 15:09:41 +0530 Message-ID: <20190325093947.32633-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and __dw_pcie_ep_find_next_cap for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present. This is because of incorrect ordering of "next_cap_ptr" check. Fix it here. Fixes: beb4641a787df79a142 ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index dc6a4bbd3ace..74477ad7467f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -46,16 +46,19 @@ static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, u8 cap_id, next_cap_ptr; u16 reg; + if (!cap_ptr) + return 0; + reg = dw_pcie_readw_dbi(pci, cap_ptr); - next_cap_ptr = (reg & 0xff00) >> 8; cap_id = (reg & 0x00ff); - if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) + if (cap_id > PCI_CAP_ID_MAX) return 0; if (cap_id == cap) return cap_ptr; + next_cap_ptr = (reg & 0xff00) >> 8; return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } @@ -67,9 +70,6 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); next_cap_ptr = (reg & 0x00ff); - if (!next_cap_ptr) - return 0; - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } From patchwork Mon Mar 25 09:39:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161071 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751077jan; Mon, 25 Mar 2019 02:44:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqyvzFIz7x5K01hyjxX/WC4m3v0IMoJ3WotMnRj/N4m++9m2C0f7bd2MnrM6AYRMvu5HzJ93 X-Received: by 2002:a63:da56:: with SMTP id l22mr22855774pgj.127.1553507053153; Mon, 25 Mar 2019 02:44:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507053; cv=none; d=google.com; s=arc-20160816; b=sJnMzLV1jPbmhiXNloyZuzgpu4yzDzSPhrPiMSMuy4+jB+FKmNTcA0RiLEC9BCuW2j tWF14BJukiZfv9XMy24cCTfBZCV+UTSmhZOCQjyVK+Th3l9+Hx/rKXOG/30tgpCqyoN6 ziAaINsdbGJsIDlKR6xWC9SBMCqQ/SHHCkGah3Z4ROKcKe9eivabLEcVNbvdrZmqCSBU N3D++f0oOaBZBX8ndicElRxR1VHKGjsmGu90pVhzVAdhioEmRD40GQKtVNmYLxlLNoFc dDRUJCFccwcKjq9dBt6k9JMqAvIxB3FJ5s/hKZ8QFcAb19wY+rKeSDYHDcAvicuFZLgw rCiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Wc+XF/2XYAC9KKW6IhKBmYfzdM6YFlYUH2nHoSNvQ4Q=; b=aRJwC+M7PH6Xy749rFQYHaUHuGj65NYJRLZV06jsMeKPpl/agoDHVZRtoyRTVoJR9E +0o2CLwOivVmClr6bF+nzEB2Em+4AIhCQkfwSBzJrlwaG/3ycciQtepeIXQqh2PL90cR dJ5aWSNWx/gI5z6EmzK731RJVb2ku7aBWtlH8qMvTdFVNnvVp7sOdaLVkNVy+s8Uc/Vw 5RQZXuateAA12bkzZ6QW0Ju05ATU6sInrsyRQAGqtpa1gHBwzPR5AVERSPzbxU0+O9YC w4v925G+TB6vOMB11cx8MUVLWs/aCrqNuSmz7pwZ/7e+Chw1LRUWYfsrYapNqnQPqHnZ MYOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NBU2joGD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t17si5593108pfe.250.2019.03.25.02.44.12; Mon, 25 Mar 2019 02:44:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NBU2joGD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730793AbfCYJoL (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:11 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37700 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730757AbfCYJoF (ORCPT ); Mon, 25 Mar 2019 05:44:05 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hkp9013517; Mon, 25 Mar 2019 04:43:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507026; bh=Wc+XF/2XYAC9KKW6IhKBmYfzdM6YFlYUH2nHoSNvQ4Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NBU2joGDTrDFfB2dGfrHbF5b+FBSrSmCwQzXuOL+S16DWe8w9R034Lzo3letuG4tn WoEhoItHujbrjWah9Z/FcluknJiA0SrdBUt+7izuRfo3nd6Ex1IXGMJIU2LBg9NiZY dFkSy4hVYXZiq0iE6wplaIgUEivHalkBmEDtxs1E= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hkZ7055066 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:46 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:46 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:46 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feab028077; Mon, 25 Mar 2019 04:43:41 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 22/26] PCI: keystone: Add support for PCIe EP in AM654x Platforms Date: Mon, 25 Mar 2019 15:09:43 +0530 Message-ID: <20190325093947.32633-23-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe EP support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 23 +- drivers/pci/controller/dwc/pci-keystone.c | 242 +++++++++++++++++++--- 2 files changed, 236 insertions(+), 29 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index d1d00833e0b3..b450ad2823a5 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -105,14 +105,33 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) - depends on PCI_MSI_IRQ_DOMAIN - select PCIE_DW_HOST help Say Y here if you want to enable PCI controller support on Keystone SoCs. The PCI controller on Keystone is based on DesignWare hardware and therefore the driver re-uses the DesignWare core functions to implement the driver. +if PCI_KEYSTONE + +config PCI_KEYSTONE_HOST + bool "PCI Keystone Host Mode" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + default y + help + Enables support for the PCIe controller in the Keystone SoC to work in + host mode. + +config PCI_KEYSTONE_EP + bool "PCI Keystone Endpoint Mode" + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Enables support for the PCIe controller in the Keystone SoC to work in + endpoint mode. + +endif + config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 312fd0c49bbb..459485b0f65d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -52,6 +52,12 @@ #define OB_ENABLEN BIT(0) #define OB_WIN_SIZE 8 /* 8MB */ +#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) +#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) +#define PCIE_EP_IRQ_SET 0x64 +#define PCIE_EP_IRQ_CLR 0x68 +#define INT_ENABLE BIT(0) + /* IRQ register defines */ #define IRQ_EOI 0x050 @@ -95,11 +101,16 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 +#define AM654_WIN_SIZE SZ_64K + +#define APP_ADDR_SPACE_0 (16 * SZ_1K) #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct ks_pcie_of_data { + enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; unsigned int version; }; @@ -877,12 +888,139 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } +static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + u32 val; + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_read(base + reg, size, &val); + ks_pcie_clear_dbi_mode(ks_pcie); + return val; +} + +static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_write(base + reg, size, val); + ks_pcie_clear_dbi_mode(ks_pcie); +} + static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, + .read_dbi2 = ks_pcie_am654_read_dbi2, + .write_dbi2 = ks_pcie_am654_write_dbi2, }; +static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + int flags; + + ep->page_size = AM654_WIN_SIZE; + flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); +} + +static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) +{ + struct dw_pcie *pci = ks_pcie->pci; + u8 int_pin; + + int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); + if (int_pin == 0 || int_pin > 4) + return; + + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), + INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); + mdelay(1); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), + INT_ENABLE); +} + +static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + ks_pcie_am654_raise_legacy_irq(ks_pcie); + break; + case PCI_EPC_IRQ_MSI: + dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + break; + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features ks_pcie_am654_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, + .reserved_bar = 1 << BAR_0 | 1 << BAR_1, + .bar_fixed_64bit = 1 << BAR_0, + .bar_fixed_size[2] = SZ_1M, + .bar_fixed_size[3] = SZ_64K, + .bar_fixed_size[4] = 256, + .bar_fixed_size[5] = SZ_1M, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +ks_pcie_am654_get_features(struct dw_pcie_ep *ep) +{ + return &ks_pcie_am654_epc_features; +} + +static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { + .ep_init = ks_pcie_am654_ep_init, + .raise_irq = ks_pcie_am654_raise_irq, + .get_features = &ks_pcie_am654_get_features, +}; + +static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, + struct platform_device *pdev) +{ + int ret; + struct dw_pcie_ep *ep; + struct resource *res; + struct device *dev = &pdev->dev; + struct dw_pcie *pci = ks_pcie->pci; + + ep = &pci->ep; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + return 0; +} + static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { int num_lanes = ks_pcie->num_lanes; @@ -950,7 +1088,8 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } -static int ks_pcie_am654_set_mode(struct device *dev) +static int ks_pcie_am654_set_mode(struct device *dev, + enum dw_pcie_device_mode mode) { struct device_node *np = dev->of_node; struct regmap *syscon; @@ -963,7 +1102,18 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; mask = AM654_PCIE_DEV_TYPE_MASK; - val = RC; + + switch (mode) { + case DW_PCIE_RC_TYPE: + val = RC; + break; + case DW_PCIE_EP_TYPE: + val = EP; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + return -EINVAL; + } ret = regmap_update_bits(syscon, 0, mask, val); if (ret) { @@ -1006,6 +1156,13 @@ static const struct ks_pcie_of_data ks_pcie_rc_of_data = { static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { .host_ops = &ks_pcie_am654_host_ops, + .mode = DW_PCIE_RC_TYPE, + .version = 0x490A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { + .ep_ops = &ks_pcie_am654_ep_ops, + .mode = DW_PCIE_EP_TYPE, .version = 0x490A, }; @@ -1019,16 +1176,22 @@ static const struct of_device_id ks_pcie_of_match[] = { .data = &ks_pcie_am654_rc_of_data, .compatible = "ti,am654-pcie-rc", }, + { + .data = &ks_pcie_am654_ep_of_data, + .compatible = "ti,am654-pcie-ep", + }, { }, }; static int __init ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; const struct ks_pcie_of_data *data; const struct of_device_id *match; + enum dw_pcie_device_mode mode; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; @@ -1053,6 +1216,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) version = data->version; host_ops = data->host_ops; + ep_ops = data->ep_ops; + mode = data->mode; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -1078,16 +1243,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->is_am6 = true; pci->dbi_base = base; + pci->dbi_base2 = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; pci->version = version; - ret = of_property_read_u32(np, "num-viewport", &num_viewport); - if (ret < 0) { - dev_err(dev, "unable to read *num-viewport* property\n"); - return ret; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "missing IRQ resource: %d\n", irq); @@ -1136,7 +1296,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->pci = pci; ks_pcie->link = link; ks_pcie->num_lanes = num_lanes; - ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; gpiod = devm_gpiod_get_optional(dev, "reset", @@ -1172,7 +1331,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->atu_base = atu_base; - ret = ks_pcie_am654_set_mode(dev); + ret = ks_pcie_am654_set_mode(dev, mode); if (ret < 0) goto err_get_sync; } else { @@ -1181,29 +1340,58 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - /* - * "Power Sequencing and Reset Signal Timings" table in - * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 - * indicates PERST# should be deasserted after minimum of 100us - * once REFCLK is stable. The REFCLK to the connector in RC - * mode is selected while enabling the PHY. So deassert PERST# - * after 100 us. - */ - if (gpiod) { - usleep_range(100, 200); - gpiod_set_value_cansleep(gpiod, 1); - } - link_speed = of_pci_get_max_link_speed(np); if (link_speed < 0) link_speed = 2; ks_pcie_set_link_speed(pci, link_speed); - pci->pp.ops = host_ops; - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); - if (ret < 0) - goto err_get_sync; + switch (mode) { + case DW_PCIE_RC_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + ret = of_property_read_u32(np, "num-viewport", &num_viewport); + if (ret < 0) { + dev_err(dev, "unable to read *num-viewport* property\n"); + return ret; + } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + + ks_pcie->num_viewport = num_viewport; + pci->pp.ops = host_ops; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + case DW_PCIE_EP_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + pci->ep.ops = ep_ops; + ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } ks_pcie_enable_error_irq(ks_pcie); From patchwork Mon Mar 25 09:39:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161076 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751599jan; Mon, 25 Mar 2019 02:44:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwYSDtYKwv0rDZTf3ypjfzR0P0d/xPaMEDYhQrsEAFyv/3Vx37q84bMQx+hKwjSpApE3iMk X-Received: by 2002:a17:902:8c8b:: with SMTP id t11mr23842907plo.148.1553507094609; Mon, 25 Mar 2019 02:44:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507094; cv=none; d=google.com; s=arc-20160816; b=vqQqIqoShPhTh/WkvZ5inTgqGjHHULF9Oy61G/h8JKg0GklOIIGbCaRpCOl3fBqupA tWKvOqkfLse6m4IQmOHVBFaiFmJqyusxpuDyI5V1q/PaEeJkbvh7kGeQ8FWzzZEgjbfu Azh6lzXElZkBR8meZBZz+fjuLN/y0pe1CLKSXw5NOpI4CR9ICFxUpo6Nsu09QoPYv5+/ wFdL1gRPxgtAk48MijBL+CG5Dw3bFUKtUbwJmHI7SuIKhvs941HLf0qbvvker29TaI2X MvulNEUREJtM1NbzKc+N3Xt4cSe84pwsaLnOO0Y9+Sjprhr0zgZkkdPZVW1Ohhb98sBV kNeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=q3j+eLddVjEWh3KTfPJhB6vOyzvGXKalq1Td4n5w/YE=; b=M4Gh6ZBFD4a4CjFIXUmNMZd4U3vFfgSITWGNfFZ7mb6QGykmNSfFR0Z4rt/GHOANTK hni44WPZizaSsq9bYxcL9V9qEBLpykrQqFUlODCkfQyyfqbnl5N+bLD0ZCYMlKRhiE/6 QoPYoh2nyWvaIyZH8B9gWb/lbgPgcRPdhSJ1z4PBT6s8yEMD11TK3rBZU/Q6CW/09g0o YbeB/SfujvyQQWTd4TxtRLNzId5P6u9/oW+nx9ax9JAH0skvIefwdwrEHHGWdvwFb4DV eEWh5CF2dTEkP7j3s8THYVSDi6J1DHkB1vBNRegMmauVBpNl3N6lXk87FcgCUluWfQYm kPjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dib0lyw+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e6si13226846pfc.201.2019.03.25.02.44.54; Mon, 25 Mar 2019 02:44:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dib0lyw+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730861AbfCYJox (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:53 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46586 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730540AbfCYJou (ORCPT ); Mon, 25 Mar 2019 05:44:50 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hqXh075705; Mon, 25 Mar 2019 04:43:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507032; bh=q3j+eLddVjEWh3KTfPJhB6vOyzvGXKalq1Td4n5w/YE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dib0lyw+ZZqLtvVBmb5/4k//xg5E4076Nq4KJt1KEAdB5hG/zd3Vd1EpTGklXVhn+ OB5+s1HlAyusd4nU+xCy35xbFCdBBM8dZXOpeFDzy35IcCTz6aNj4qHLg1Ucwu8Ksl KFoXHMXag9F+pDbpDsC+1/cQMB54x4AUFIPFiKgk= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hqAV111677 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:52 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:51 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:51 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feac028077; Mon, 25 Mar 2019 04:43:46 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 23/26] PCI: designware-ep: Configure RESBAR to advertise the smallest size Date: Mon, 25 Mar 2019 15:09:44 +0530 Message-ID: <20190325093947.32633-24-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Configure RESBAR capability to advertise the smallest size (1MB) for couple of reasons. A) Host side resource allocation of BAR fails for larger sizes. B) Endpoint function driver does not allocate memory for all supported sizes in RESBAR capability. If and when there is a usecase required to add more flexibility using RESBAR, this can be revisited. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 74477ad7467f..0c208b9bda43 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -504,10 +504,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) pci_epc_mem_exit(epc); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + int dw_pcie_ep_init(struct dw_pcie_ep *ep) { + int i; int ret; + u32 reg; void *addr; + unsigned int nbars; + unsigned int offset; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; @@ -591,6 +613,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (offset) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + dw_pcie_dbi_ro_wr_en(pci); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); + dw_pcie_dbi_ro_wr_dis(pci); + } + dw_pcie_setup(pci); return 0; From patchwork Mon Mar 25 09:39:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161072 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751164jan; Mon, 25 Mar 2019 02:44:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqxqCJmI3jMPzEc+q0v7xTkIMFRuAqz4/MqQKTvJ6lA52Vyg8ZIDH9Tdz+s1ur1VKFI4mULM X-Received: by 2002:a17:902:7e05:: with SMTP id b5mr11568906plm.127.1553507061485; Mon, 25 Mar 2019 02:44:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507061; cv=none; d=google.com; s=arc-20160816; b=V5vCV6S9tEZDG2Fr2AXmJ1c0SasX8jrsnCfEmJC4oEx3+J7EXnplXudEG+rnY0rWzU jF2OVOX2qN6lUFTHrZNhr5BItSe2uxnqCuVrNkv7KcVbGqGVB4LnMBbvIXJdFS0YbdUM iVx1H1GY81a2Vk+GArGyEC5iyD7x8TazZL19xvJPrHPSHmZgWN8kRUQpoUJ52f6voJ6N AswC26Wbz2+spmuhIWviO2PKSzGa+Qc7uCE+6BUG4wrQmXYfpKLaDoNeC/kRDgPbP1KM qI8Y8vD/oLr8kTGF8K1Tz6rbxodJvKQRklzkho5Op+iM1kAHShknzUiKQc2yDpCJUArN DRnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=c3UBlJ2/J/eUILjH1LmTrngxtCdjzgHiiyV0ibrE7Fc=; b=Fcl4NbCdUr0S0J9uUVJMT2OV1KZwhXLrDmJpaOOsJIYGcvFQ72ioDyQgAA/YI/VKmC JDeJUm2ZLfp2zGL/8kleosZGpIZ1td9nXXvLmia1r36EDYhlntVr6lTEihb2rhcrHQyT Jf2ntJnj4PunmlkZj4ntk927ac1m6ubO9Dbi1b1OuU+pNrR05MxzzZK5xeAACzMXVgG9 kvdwoVTLgDeowonVdLQ/9DEMvAD5YkUcU9y5vmNGKwjlTfuwE7eQzc1QJatEEgNj52J2 sIO2S52yWMT/copTBVJ0EnNtDm+SoBh5moEOLHn5kBZIbWZ4w0qIuWJUxEh62AIhIryu 3tqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Xx+6TG67; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j13si7186424pgm.73.2019.03.25.02.44.21; Mon, 25 Mar 2019 02:44:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Xx+6TG67; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730818AbfCYJoU (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:20 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45176 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730757AbfCYJoR (ORCPT ); Mon, 25 Mar 2019 05:44:17 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hvfM068411; Mon, 25 Mar 2019 04:43:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507037; bh=c3UBlJ2/J/eUILjH1LmTrngxtCdjzgHiiyV0ibrE7Fc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Xx+6TG67rlTZNWox5cCKm1CIXzIrJ/3ZGkd8A/+4NfqEMvyrzKYWZXv2evRtDV8Pa EODDlHSveYHeGXIsPucosbjNEP+p8itvmSkLMZvoDzzs6Yp/ut/y/i7FA2btMFsrem MxD0Uk3prVEHLuOnwIFyXgyNxnB4RQKhCSRUBkxw= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hvR5055269 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:57 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:56 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:57 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9fead028077; Mon, 25 Mar 2019 04:43:52 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 24/26] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Date: Mon, 25 Mar 2019 15:09:45 +0530 Message-ID: <20190325093947.32633-25-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configre a aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0c208b9bda43..2bf5a35c0570 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; + unsigned int aligned_offset; u16 msg_ctrl, msg_data; u32 msg_addr_lower, msg_addr_upper, reg; u64 msg_addr; @@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_readw_dbi(pci, reg); } - msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; + aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); + msg_addr = ((u64)msg_addr_upper) << 32 | + (msg_addr_lower & ~aligned_offset); ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, epc->mem->page_size); if (ret) return ret; - writel(msg_data | (interrupt_num - 1), ep->msi_mem); + writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); From patchwork Mon Mar 25 09:39:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161073 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751206jan; Mon, 25 Mar 2019 02:44:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqyBPGR+/Pr4LRgayg0Qgq9NZwNm6Vb/6bZn/hHi4yzC+iE0vEhAAMv2+oBr2h8yzOO/n+/a X-Received: by 2002:a17:902:b210:: with SMTP id t16mr969540plr.84.1553507065490; Mon, 25 Mar 2019 02:44:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507065; cv=none; d=google.com; s=arc-20160816; b=zz4Xbuu7P8XWf3uVT5MwFbJHzbBtC6GeYjohRj4Mrvs0mR5cuSEI91QrxrRfIb5dxZ zi7U7+IjrDO9jyUowJIdLb1bJlSrDJiPjxfaLBzwstDgefsU+saFj6JqEsXGXtVfhzpk eMd4syF2gCnceiS3lL+QSDRHCIcZl9y+QornYxPSUf2TtOqzTr2xqBT/v7wVzx3MxKKU cGXCT3Vm6hvU8LpwCnLBFIikapluwLwyPWqUtcZUxq5YqzIO2g/YO4JGvXAooFkAWZ1W qqkA5Dag/DOW8NzwUhdGMFa33RhkK+fKuroajLHfz0JYzflc2tz2eitRFTOA6ais6sNu 85ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ecY/+Ui4SK2VPooZ8MRoP5X7hto+xBrP5+SVRZo/EkI=; b=Gju37RMd9pLxAxeNE7xhPH+wMCYFj5b8Xr0sKUpO05xPXlsChaRp91zT09IsLhqssf C+RcN3b5QRvfov1+ghOrYJIAfY9nWLaMQuWJuYXMRatMcx6hS5XsVVwtBLhJB26yrO5t 9OtaNH2keuBt6/hgYv7mOk2J9XonaNzyWKzgRDk0SAVlL3DEXptjq+kDVnEdQ97nQhJ5 Pe8EONjXeQ89QF3Cg4eKD9a42QSzQqh4hPA/kJ5Ge7XNyQlIOktVnLHrcFkDBv0YCwd7 b92DpCXfgMS/IZukyv/oKflualUas7Vs6YozUMVFGu7HOh1AegfUa8tR7jTH31e84EuD UuuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QI2e4DOd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e2si13188504pgs.387.2019.03.25.02.44.25; Mon, 25 Mar 2019 02:44:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QI2e4DOd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730530AbfCYJoX (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:23 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37788 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730810AbfCYJoT (ORCPT ); Mon, 25 Mar 2019 05:44:19 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9i3bg013630; Mon, 25 Mar 2019 04:44:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507043; bh=ecY/+Ui4SK2VPooZ8MRoP5X7hto+xBrP5+SVRZo/EkI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QI2e4DOdMrnzxiGAiwFTboYR0mKzar6nFJ4DmJjfdCATaCNs7vRXHZ/qmdDLWV8va dzFASKWIDlSrhfd9BVFbcSyWJfX2ctJc38fsSZLu1xViwqvTT0KSFgoZJpp4gvzwP9 XzXl3/rCTte832QFKgswKYYIudZodf72JZx2H7OE= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9i32b112003 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:44:03 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:44:02 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:44:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feae028077; Mon, 25 Mar 2019 04:43:57 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 25/26] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Date: Mon, 25 Mar 2019 15:09:46 +0530 Message-ID: <20190325093947.32633-26-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to application registers. "PCIe Inbound Address Translation" section in AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 is reserved. Configure pci_endpoint_test to use BAR_2 instead. Also set alignment to 64K since "PCIe Subsystem Address Translation" section in TRM indicates minimum ATU window size is 64K. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 29582fe57151..e015e8fa9bd3 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -75,6 +75,11 @@ #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 +#define PCI_DEVICE_ID_TI_AM654 0xb00c + +#define is_am654_pci_dev(pdev) \ + ((pdev)->device == PCI_DEVICE_ID_TI_AM654) + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -588,6 +593,7 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, int ret = -EINVAL; enum pci_barno bar; struct pci_endpoint_test *test = to_endpoint_test(file->private_data); + struct pci_dev *pdev = test->pdev; mutex_lock(&test->mutex); switch (cmd) { @@ -595,6 +601,8 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, bar = arg; if (bar < 0 || bar > 5) goto ret; + if (is_am654_pci_dev(pdev) && bar == BAR_0) + goto ret; ret = pci_endpoint_test_bar(test, bar); break; case PCITEST_LEGACY_IRQ: @@ -785,11 +793,20 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) pci_disable_device(pdev); } +static const struct pci_endpoint_test_data am654_data = { + .test_reg_bar = BAR_2, + .alignment = SZ_64K, + .irq_type = IRQ_TYPE_MSI, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) }, { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), + .driver_data = (kernel_ulong_t)&am654_data + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Mon Mar 25 09:39:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161074 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751246jan; Mon, 25 Mar 2019 02:44:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqydv3eJ6fErrOyl/UTKZm3ipeV/GGg+AEu5ah4S7jWMWXGFJLqr2lpnOJz+FMKiDy8MLAC+ X-Received: by 2002:a62:1a06:: with SMTP id a6mr22819518pfa.18.1553507069656; Mon, 25 Mar 2019 02:44:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507069; cv=none; d=google.com; s=arc-20160816; b=Ne+6rpo/r8NrWOFl+O+3D7U/cHb91TqJBzUl466m5oPLOJAen7QNNDgHkWkDwlDceo 2i1Oh9RH1VQQJu/GP4wOAiQTzn1SlYMA57fOPJfNTDkgnqfBWD+Ry382vkSgI1xp1CcU 9BPbsSs6+UKuBNPLTe0tWq/zMjMp7vflGYGm8Acf0iyssce0asCSDjdJS3VHxlbUpMxD zVB24AyIAlIHTjAl/uK0BwxbJM4yMai4f7eleDYg1KMt5KrT3MwwJCRUlUjpUnHdxKLv fVYN5pckO5qs0Ep2sOMKlSfL4M2aVHYXlbhK/8LLnVQ5zMq2kNWNdD4adXZ0bDLxrKV9 pcsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2++9Tg54a9f6hIecMipMBo4Cbzj6epb7v0EYAzsW2ns=; b=0NOms4lUtmMOUjEm9hAMMk0czyxVFSHMtD6FuBkgrzSSCeHjtYA0+t6+PSjLlg2q2q tY+WGDO933KRZ8iaj6JIW7r+Y4RgdSG/e2LXl/xrvVRKR3J+zXCNDAfAEXOp45WhxGWa M1XFkelksp2kW+QeMySjs/sRkudi1Vd4BMqtvAcakZjFccrScTmla7L+cugygn9mAxEW eIV1rZsQCeb5K9x2uA5JBfaXbpcmOpuz8vPZaruFH6yjB97l1tR58xbsoPvvIHZzoOOM TATD0kdnu20K3Ufo3gVnPekS6FR+kmCXfP93iPEzUQSKT8MtI+/2w66vYPYbl98hXr5f Ghgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xC7zVjEm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e2si13188504pgs.387.2019.03.25.02.44.29; Mon, 25 Mar 2019 02:44:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xC7zVjEm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730846AbfCYJo2 (ORCPT + 31 others); Mon, 25 Mar 2019 05:44:28 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33706 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730525AbfCYJo0 (ORCPT ); Mon, 25 Mar 2019 05:44:26 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9i8ie011385; Mon, 25 Mar 2019 04:44:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507048; bh=2++9Tg54a9f6hIecMipMBo4Cbzj6epb7v0EYAzsW2ns=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xC7zVjEmGIGSwxwMa7ujENOVn5bfh0qrEbrWEt2siiuK6wTJX6XidurqTtAICTdRY a74R8iq9BpF2jw/DaNvdq9ixtaelieErWLeFdF176j6RiD5/7nxOpf5OGytScYSQzk fDE+iYwwza7GalOYQm456v3fTTONfz3duvba49Ho= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9i8uO055981 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:44:08 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:44:08 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:44:08 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaf028077; Mon, 25 Mar 2019 04:44:03 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 26/26] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Date: Mon, 25 Mar 2019 15:09:47 +0530 Message-ID: <20190325093947.32633-27-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org commit 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR") while adding test_reg_bar in order to map PCI_ENDPOINT_TEST regs to be mapped to any BAR failed to update test_reg_bar in pci_endpoint_test. This results in test_reg_bar having invalid value when used outside probe. Fix it here. Fixes: 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR") Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index e015e8fa9bd3..7b015f2a1c6f 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -670,6 +670,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, data = (struct pci_endpoint_test_data *)ent->driver_data; if (data) { test_reg_bar = data->test_reg_bar; + test->test_reg_bar = test_reg_bar; test->alignment = data->alignment; irq_type = data->irq_type; }