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Iglesias" , David Gibson Subject: [PATCH-for-8.0 1/4] cputlb: Restrict SavedIOTLB to system emulation Date: Wed, 7 Dec 2022 18:41:26 +0100 Message-Id: <20221207174129.77593-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221207174129.77593-1-philmd@linaro.org> References: <20221207174129.77593-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in case of reset") added the SavedIOTLB structure -- which is system emulation specific -- in the generic CPUState structure. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 4 ++-- include/hw/core/cpu.h | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6f1c00682b..0ea96fbcdf 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1395,7 +1395,7 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, hwaddr mr_offset) { -#ifdef CONFIG_PLUGIN +#if defined(CONFIG_PLUGIN) && !defined(CONFIG_USER_ONLY) SavedIOTLB *saved = &cs->saved_iotlb; saved->section = section; saved->mr_offset = mr_offset; @@ -1699,7 +1699,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, return qemu_ram_addr_from_host_nofail(p); } -#ifdef CONFIG_PLUGIN +#if defined(CONFIG_PLUGIN) && !defined(CONFIG_USER_ONLY) /* * Perform a TLB lookup and populate the qemu_plugin_hwaddr structure. * This should be a hot path as we will have just looked this path up diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8830546121..bc3229ae13 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -222,7 +222,7 @@ struct CPUWatchpoint { QTAILQ_ENTRY(CPUWatchpoint) entry; }; -#ifdef CONFIG_PLUGIN +#if defined(CONFIG_PLUGIN) && !defined(CONFIG_USER_ONLY) /* * For plugins we sometime need to save the resolved iotlb data before * the memory regions get moved around by io_writex. @@ -406,9 +406,11 @@ struct CPUState { #ifdef CONFIG_PLUGIN GArray *plugin_mem_cbs; +#if !defined(CONFIG_USER_ONLY) /* saved iotlb data from io_writex */ SavedIOTLB saved_iotlb; -#endif +#endif /* !CONFIG_USER_ONLY */ +#endif /* CONFIG_PLUGIN */ /* TODO Move common fields from CPUArchState here. */ int cpu_index; From patchwork Wed Dec 7 17:41:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 631557 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp420011pvb; Wed, 7 Dec 2022 09:42:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf48jd0ZpbXuqCb64NCwnBmbXc2tEX06LTHGXoq2E93Uy78O01dfJkKaoGuAyVn4CMaddUdv X-Received: by 2002:ac8:47c7:0:b0:3a7:e2fb:69b1 with SMTP id d7-20020ac847c7000000b003a7e2fb69b1mr12673028qtr.88.1670434971854; Wed, 07 Dec 2022 09:42:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670434971; cv=none; d=google.com; s=arc-20160816; b=GZmed7q6TJYipHu1YOioLao1KKy5IMGPa0Af9oj/VnTY6YSUWNaUnBvhtSqzqi1YTX emUFZkA4ffNDomE4bkTgDec2OWDGBx5gqxQiXz3304jAfG3BFlCQqsMlWIEOGGL2bSOi 6/JOQsXMNhCrHwEbvLHqMkB5SMJ1OtHS7Eqt7zAm6PggzGhjjLoNCNwMan1NTN/hxEgo ueLDcKW289hME7Ph0gglv+UxG+keXuqb7E1EcIVdmQtLnsrHW70QkpXxE6VGkQe7NP43 KOY4ApUi/aSRdPslserjOGSB2eI3gdXk3RMSxG5Ik9wX20528UdlEG9KobwMS2v6d/hj 5yxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=J5B6vDbFr2pk0CR4IzEviq/2sUbcV4f8oxGB7SYBHu8=; b=U31dMzAOK+KYiJInLY1tmjsMSG+vW7rl2h1icK4BfaaBaDmQlJg0+uH601uaSQlEmB YUS/5yG473/4RUbIb9CJlYu8GfuoOhFEaFzTC8QAvGzdGcDy+xZSAuhSt4LwDL5Ab3I7 xahWfZakstE6N3aBIcsYkUmg9D0ugGstY8LvmA3rHGTsz+OSQ7Yd1/dwtIVYGPJy3oLf QlEZMCsRz5vRPMQhubeTDiVOus89LXb5yg8Q5Q5tt6vQ02L+bE36Gfad0pvp5i4GD9LZ 7iWZMao5VyYZqw+ks2JL5mdch0C8rg+mNELe3Q4FFFDsHP853++YNeFI1TgAtiYJ9qa8 Ef6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dvBcbiDF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , David Gibson Subject: [PATCH-for-8.0 2/4] gdbstub: Use vaddr type for generic insert/remove_breakpoint() API Date: Wed, 7 Dec 2022 18:41:27 +0100 Message-Id: <20221207174129.77593-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221207174129.77593-1-philmd@linaro.org> References: <20221207174129.77593-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both insert/remove_breakpoint() handlers are used in system and user emulation. We can not use the 'hwaddr' type on user emulation, we have to use 'vaddr' which is defined as "wide enough to contain any #target_ulong virtual address". Signed-off-by: Philippe Mathieu-Daudé --- gdbstub/internals.h | 6 ++++-- include/sysemu/accel-ops.h | 6 +++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index eabb0341d1..b23999f951 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -9,9 +9,11 @@ #ifndef _INTERNALS_H_ #define _INTERNALS_H_ +#include "exec/cpu-common.h" + bool gdb_supports_guest_debug(void); -int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); -int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); +int gdb_breakpoint_insert(CPUState *cs, int type, vaddr addr, vaddr len); +int gdb_breakpoint_remove(CPUState *cs, int type, vaddr addr, vaddr len); void gdb_breakpoint_remove_all(CPUState *cs); #endif /* _INTERNALS_H_ */ diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 8cc7996def..30690c71bd 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -10,7 +10,7 @@ #ifndef ACCEL_OPS_H #define ACCEL_OPS_H -#include "exec/hwaddr.h" +#include "exec/cpu-common.h" #include "qom/object.h" #define ACCEL_OPS_SUFFIX "-ops" @@ -48,8 +48,8 @@ struct AccelOpsClass { /* gdbstub hooks */ bool (*supports_guest_debug)(void); - int (*insert_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); - int (*remove_breakpoint)(CPUState *cpu, int type, hwaddr addr, hwaddr len); + int (*insert_breakpoint)(CPUState *cpu, int type, vaddr addr, vaddr len); + int (*remove_breakpoint)(CPUState *cpu, int type, vaddr addr, vaddr len); void (*remove_all_breakpoints)(CPUState *cpu); }; From patchwork Wed Dec 7 17:41:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 631559 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp420294pvb; Wed, 7 Dec 2022 09:43:25 -0800 (PST) X-Google-Smtp-Source: AA0mqf7ieV13QqWsoiTqKUTXSnrbryRnNUrrIRXeUrDQNnr1EEWYhuK5x6AU3Hq8OvcYS/evjp0R X-Received: by 2002:a37:a52:0:b0:6fe:cb0f:70ca with SMTP id 79-20020a370a52000000b006fecb0f70camr9052214qkk.227.1670435004839; Wed, 07 Dec 2022 09:43:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670435004; cv=none; d=google.com; s=arc-20160816; b=xQVIHDROjThoVeTnbSWhwEW2z2HQOQqRfujyEsMKXljmAxgNmKUd5OZoMKXZeYhfNS SP4DMEurKlaKGgZFqIVvpe23VInxZsnYWiau1Spc4BawGIIfDCM0qwdHL5bDzCieDqCC Szoh+RKy6mfdTj2B7uTUtsNdfZFU8eR4wBr70o7Mk4xpsPA7fc9lEUdf0hFO/c1gxWAK f26oRWQjSxfQGMH02O+jQpSubOnLWDEwvcNLIvgrEheqWKYOQdQTH1cgB6lPJMSj6SQA qXCY+tC0O9B+1G5N4tp8swpw0O5DBMG3DE2l2taJQzUDdv1vde0d4Tp4Hf03PvId5QAm IeVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/wW9LiFCKARmD4hRBz59RrV0Rj+GlZgz9wI66xG8a8k=; b=LF4yPi5sTkUJkiA2A9lytLLS477EzrPG0QPKQWh5NQRTlQNxlKibOGMmncqpzbAQHR z2xZLigMjVIjaX2u8Cs3JzfuyRH5hc7a801kZ454K9/s6TWS1Ozh2VkeTpa/6MxzvNUf OAk+tIKyuGPRXuiv8pfN+TwNtNsH6zT2/XLirtDhWAFThTfmz/5P3qrRiUzVAW8IfeUy AUQKLsZOIh1o3RdYyls7bk2CmDGQqLmTC1e9jAELl+EGFurVU8LYAaRCTGS9I5J1J2r6 yvk5iy7LEhZz7H1XTfp0WxxNV6fwcyAfkArw0sSSRI9F59QSsX4SikLzapkZ3ow8nxdN YaEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZuQYvQZ5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , David Gibson Subject: [PATCH-for-8.0 3/4] target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu Date: Wed, 7 Dec 2022 18:41:28 +0100 Message-Id: <20221207174129.77593-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221207174129.77593-1-philmd@linaro.org> References: <20221207174129.77593-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_get_phys_page_debug() is a system-emulation specific handler. Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.h | 2 +- target/cris/cpu.h | 3 +-- target/hppa/cpu.h | 2 +- target/m68k/cpu.h | 2 +- target/nios2/cpu.h | 2 +- target/openrisc/cpu.h | 3 ++- target/ppc/cpu.h | 2 +- target/rx/cpu.h | 2 +- target/rx/helper.c | 4 ++-- target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 3 ++- target/xtensa/cpu.h | 2 +- 12 files changed, 15 insertions(+), 14 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d0abc949a8..5e67304d81 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -276,9 +276,9 @@ extern const VMStateDescription vmstate_alpha_cpu; void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); +hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); -hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index e6776f25b1..71fa1f96e0 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -193,12 +193,11 @@ bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); -hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); - int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6f3b6beecf..b595ef25a9 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -322,11 +322,11 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } void cpu_hppa_change_prot_id(CPUHPPAState *env); #endif -hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); #ifndef CONFIG_USER_ONLY +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 3a9cfe2f33..68ed531fc3 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -176,9 +176,9 @@ struct ArchCPU { #ifndef CONFIG_USER_ONLY void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); +hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index f85581ee56..2f43b67a8f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -262,7 +262,6 @@ void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -288,6 +287,7 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) } #ifndef CONFIG_USER_ONLY +hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 1d5efa5ca2..31a4ae5ad3 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -312,7 +312,6 @@ struct ArchCPU { void cpu_openrisc_list(void); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); @@ -321,6 +320,8 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #ifndef CONFIG_USER_ONLY +hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 81d4263a07..6a7a8634da 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1346,12 +1346,12 @@ static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu) #endif /* CONFIG_USER_ONLY */ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu); const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); #endif diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5655dffeff..555d230f24 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -123,11 +123,11 @@ const char *rx_crname(uint8_t cr); #ifndef CONFIG_USER_ONLY void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); +hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void rx_translate_init(void); void rx_cpu_list(void); diff --git a/target/rx/helper.c b/target/rx/helper.c index f34945e7e2..dad5fb4976 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -144,9 +144,9 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } -#endif /* !CONFIG_USER_ONLY */ - hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { return addr; } + +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 727b829598..02bfd612ea 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -214,7 +214,6 @@ struct ArchCPU { void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, @@ -225,6 +224,7 @@ void sh4_translate_init(void); void sh4_cpu_list(void); #if !defined(CONFIG_USER_ONLY) +hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index e478c5eb16..ed0069d0b1 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -569,10 +569,11 @@ struct ArchCPU { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_sparc_cpu; + +hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif void sparc_cpu_do_interrupt(CPUState *cpu); -hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 579adcb769..b7a54711a6 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -576,9 +576,9 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, unsigned *n_regs, unsigned *n_core_regs); int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); From patchwork Wed Dec 7 17:41:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 631556 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp419973pvb; Wed, 7 Dec 2022 09:42:47 -0800 (PST) X-Google-Smtp-Source: AA0mqf4uVw0yCXTWIMPDl8jObREB+DlU6FfEU3+3WsxFAbs02yHGRi6YGAvGG48phJ/83alKCK4M X-Received: by 2002:a37:e114:0:b0:6e0:8579:db8b with SMTP id c20-20020a37e114000000b006e08579db8bmr63920521qkm.451.1670434967407; Wed, 07 Dec 2022 09:42:47 -0800 (PST) ARC-Seal: i=1; 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Iglesias" , David Gibson Subject: [PATCH-for-8.0 4/4] target/sparc: Cleanup around sparc_cpu_do_unaligned_access() Date: Wed, 7 Dec 2022 18:41:29 +0100 Message-Id: <20221207174129.77593-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221207174129.77593-1-philmd@linaro.org> References: <20221207174129.77593-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Commit caac44a52a ("target/sparc: Make sparc_cpu_tlb_fill sysemu only") restricted mmu_helper.c to system emulation. Checking whether CONFIG_USER_ONLY is defined is now pointless. Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/mmu_helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 919448a494..a7e51e4b7d 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -924,7 +924,6 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } -#ifndef CONFIG_USER_ONLY G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -942,4 +941,3 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } -#endif /* !CONFIG_USER_ONLY */