From patchwork Thu Dec 8 14:19:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABE89C63703 for ; Thu, 8 Dec 2022 14:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229788AbiLHOTR (ORCPT ); Thu, 8 Dec 2022 09:19:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbiLHOTQ (ORCPT ); Thu, 8 Dec 2022 09:19:16 -0500 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ABEDD2FD for ; Thu, 8 Dec 2022 06:19:15 -0800 (PST) Received: by mail-lj1-x22d.google.com with SMTP id x6so1687884lji.10 for ; Thu, 08 Dec 2022 06:19:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Zee3YNW88hhZh1L7P1Y/lqj8Rf3TbJlBPbbl5HQ00WQ=; b=KmZ6nQNBkZV4OK5WS9FnD+qMCvPHHmybYxMD1fGYiDZDi+5B6NtbBY8b/CzrGuvMDH eKoqGSM/9KdF4l9QeWUfNgDi/IPhqZEtJNBNWQvMVh0bAO/2ZFhSV2l8a3dC6S/QKdQy qXnztYeRpmfqQS4DFwqVh6/xtSbBlg+QRpUxlXNr+D++Mi/LUQQfgeq4WBUvI1ULsJCq FbtQ3HRgtf5j1ZRyw0Jrcrc7k/DbKFNxwijRxNGc70VyucSBKxVyZeIQRbClhXeXOnls lchaLs4HJ2ck3jtksxU5GI+s10VM56sEbOcomN6p0Irg5eTXevrwqMsx5IR47Pape2o3 3F4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Zee3YNW88hhZh1L7P1Y/lqj8Rf3TbJlBPbbl5HQ00WQ=; b=IcYdOWz40lmRH5HjU728PPyAvbhFqSFzAPMCaEGrSPAx/+kQr000IfbcwxFSQEBGPJ E1emjoyR9hZns0fKw4VvljNB2x2dALSp3FXdLCijau+rSFyhig+ISuSCqlWKJ1tWmgCr MzDB81UrsvYedzVXTRjnvrH0IFTtsQECAwGMPTLf69V/8jDUXtK90NDho6JeQbpnjDTV ZXYcLJU4x4vTTdM9/6Ay13+4EswYG4RsbFZbxCWm3r+xxkQ/YM9OqVoyClJnSIvcWPZH QIKZsoPK1gjU+7qJseLrHyuhQr6GDlAoI5R81+Of8kKglBylm8lcf4zcU5ix2lv8yOQv 8AFQ== X-Gm-Message-State: ANoB5pnUIUcozGkD5G2Ud7VUZO11qmm1dTg6nGiPBxsNOVRSymxQ/PWo IENIvHrm3HdkYTrqXsrfg/J/ww== X-Google-Smtp-Source: AA0mqf5EZ2ebcJ+J2+Q8WnkiDedlhZOJxuYOVR2/nsY20/svgIxR+ihixwWD28oGtlnkBcDKl7w0IA== X-Received: by 2002:a2e:9eca:0:b0:279:c410:958a with SMTP id h10-20020a2e9eca000000b00279c410958amr11256395ljk.327.1670509153834; Thu, 08 Dec 2022 06:19:13 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id s17-20020a056512203100b004b578e52d81sm1514692lfs.176.2022.12.08.06.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 06:19:13 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/3] clk: qcom: dispcc-sm6115: use parent_hws for disp_cc_mdss_rot_clk Date: Thu, 8 Dec 2022 17:19:10 +0300 Message-Id: <20221208141912.47262-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework disp_cc_mdss_rot_clk to use parent_hws isntead of parent_names. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm6115.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index 818bb8f4637c..1937edf23f21 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -466,8 +466,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_rot_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &disp_cc_mdss_rot_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Thu Dec 8 14:19:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D164BC6370A for ; Thu, 8 Dec 2022 14:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229479AbiLHOTS (ORCPT ); Thu, 8 Dec 2022 09:19:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229769AbiLHOTR (ORCPT ); Thu, 8 Dec 2022 09:19:17 -0500 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1793183E97 for ; Thu, 8 Dec 2022 06:19:16 -0800 (PST) Received: by mail-lj1-x230.google.com with SMTP id n1so1705038ljg.3 for ; Thu, 08 Dec 2022 06:19:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UO1TEW6mwkKcKD4IayGIVkWwiVVV46OKlU5ps43+4is=; b=CsAofK6OyYMnXAgeApqUg2MPrmmMY8eJTIFtvEBb4YEUkaOxW7/zf8lXvpdOo1VYXi aevlFgn34zjY4w9jln7EYTuYyovC1yo+FDEUSKRYl2VkoM5meWj+fC2n3lOqKPdQNoqn zYYAoAzFHt4z42k2x6CY561BlByCt/y0UZFk9PUEV1SdgIivYiSNRBQtz/oYP7YPWhxB Zx2EkLDn/JD9733uLZC1/9VEXT3u2SrZWJ8LbYIs20uMbLVbEe+EJvSQ1qYQQ8oYK6zI cSNn6LGtgK2aSIPTkyCFgA3j3GgAYTmcvyAzdtNU6+GIYrvWe/tc+c3Tz7zZja9eJrGW 6k0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UO1TEW6mwkKcKD4IayGIVkWwiVVV46OKlU5ps43+4is=; b=TVPvcLX13t2oQeVTrxywXlexw62l8ZJ1EipKF+d6kBMMLWzTB11dT6CAmA4zUrkDb7 HNoKVn7bsptRyKTmY0GxNGNU5ht9Efcz/i3tjJq61ej+fmsWHPJQFV2vW5pX3vPM+Aeu 8YFAM9er1Rbj+j6td14sf9asIaFLwS0dqx0gibAcFqoNJ+HGcrPEztUvkb4/Ku7BKZoV R5iAnozKuR5kzs1Uo6vHmBash1FSbg1m5D87U0GOhddj6+mNzFq7gvval74J5mbY46tl 4cWhC7yOI1SbiK/eycsfDxQMvUY6B2ynYV8V6fo8YYNdB1wea/ZPhLZD5hSLoxATGE19 /K9Q== X-Gm-Message-State: ANoB5pnzEPNwrg9VXhD4iEbu0+tZC3UbsnjNlQPZgSasMB8K8zbD/PUs +mMB7D7hGAJ8miGfza1yuLF4KA== X-Google-Smtp-Source: AA0mqf5cqqRQF2vMLl6TY3qA+zMpUnQwHPaRKivsk1a5Zaht2c0oLsos3/D0YTg+i5H0e3N+jZI8uA== X-Received: by 2002:a2e:b6c5:0:b0:279:d61b:181 with SMTP id m5-20020a2eb6c5000000b00279d61b0181mr9519245ljo.166.1670509154435; Thu, 08 Dec 2022 06:19:14 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id s17-20020a056512203100b004b578e52d81sm1514692lfs.176.2022.12.08.06.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 06:19:14 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/3] clk: qcom: gcc-sm6375: use parent_hws for gcc_disp_gpll0_div_clk_src Date: Thu, 8 Dec 2022 17:19:11 +0300 Message-Id: <20221208141912.47262-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221208141912.47262-1-dmitry.baryshkov@linaro.org> References: <20221208141912.47262-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change gpll0 to use parent_hws isntead of parent_names for gcc_disp_gpll0_div_clk_src clock. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/clk/qcom/gcc-sm6375.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 89a1cc90b145..6d75f735a7a6 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -2330,8 +2330,9 @@ static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_disp_gpll0_clk_src", - .parent_names = - (const char *[]){ "gpll0" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_regmap_div_ops, }, From patchwork Thu Dec 8 14:19:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDCFDC63708 for ; Thu, 8 Dec 2022 14:19:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229809AbiLHOTU (ORCPT ); Thu, 8 Dec 2022 09:19:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229772AbiLHOTT (ORCPT ); Thu, 8 Dec 2022 09:19:19 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D741A83E9B for ; Thu, 8 Dec 2022 06:19:16 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id 1so2264364lfz.4 for ; Thu, 08 Dec 2022 06:19:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ulFqK8V316aETE4Ne37fO3IN4UHXQqpRxVPaabpLF6E=; b=BSvurBtwjIzjcJNqyaS7g6Cxh2qEG1NwcW05TihXUHKtSXRamKuWF1vwhSDzEsimnh NNKPAQGHV1N4tGrQ8a7QRorTVsIAqSKuunlhfHKsyb5h58E1H/Vs533MTg3f+zJeSETU +NsyX+GKuHmed2Ovyx3q4S/HSNjQbhhoflPKUPZaN75vn/0cG9Ze4UiFssRFb6xSWP0A KoCMXn9Bu8TVpe6oPEd4VqeJH8oOwlqztLe0Bhz9lvYXfTfYilfY4W4pF/dHL+KWQEib bw/jrWZUBHVk4TsiCvR79G+kN0Tm1AZ6djvd2ZYYu2BqFJrU2t3bAYBN6YrXwhWjRnZB GyRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ulFqK8V316aETE4Ne37fO3IN4UHXQqpRxVPaabpLF6E=; b=BgTlo/+P0bsxh6OB5O3n77vC1U4rXquonuiZSv96J69xyCOupp/62T4Cs5+xKV74QI F3Z0UHaAkhXljAvL3DbWoRc5PG7LIRqp1Kk+m5yrLU1N1MlIIuJa9ss96TBj4lNokfNc XMLzz9b3oIkvRKXm/nT11HR37VUxSjOcNKmz/XMRbY7MO4poaNiGbCP5JLkH4zHYwgbX kRSxLl3uJyoiXh2BfsS6QhFHA/TizS4IH2ngZxfFaKRW7FYsQ9v9tX4LQtKQdrmRYvFT euE6z71c8px6GZBiOd63LDdts4uBSkeRPVYnPh5wOlH3yWujw1GLOvVhczm6wjES4MXd +pAQ== X-Gm-Message-State: ANoB5plyKw+U+H433EAgD+JXfmgoO7tX/+D2A/1UD7SwUjIRtL074vnJ vYHs/gxlchwpkAFEyhOmiIuWBw== X-Google-Smtp-Source: AA0mqf5SZMh9V2bV3ltqX4P0jg79/x38K1zR08WMSV117ZSxjpzlw6h83/kNPjJVYKHzAX+U7Vetyw== X-Received: by 2002:a19:6559:0:b0:4b5:6e66:7bbc with SMTP id c25-20020a196559000000b004b56e667bbcmr6198345lfj.487.1670509155119; Thu, 08 Dec 2022 06:19:15 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id s17-20020a056512203100b004b578e52d81sm1514692lfs.176.2022.12.08.06.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 06:19:14 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 3/3] clk: qcom: gcc-sm6375: use parent_hws where possible Date: Thu, 8 Dec 2022 17:19:12 +0300 Message-Id: <20221208141912.47262-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221208141912.47262-1-dmitry.baryshkov@linaro.org> References: <20221208141912.47262-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change several parent_data entries with only .hw entries to parent_hws instead. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sm6375.c | 252 +++++++++++++++++----------------- 1 file changed, 126 insertions(+), 126 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 6d75f735a7a6..ad3c4833990d 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -1766,8 +1766,8 @@ static struct clk_branch gcc_camss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1784,8 +1784,8 @@ static struct clk_branch gcc_camss_cci_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cci_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_cci_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_cci_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1802,8 +1802,8 @@ static struct clk_branch gcc_camss_cci_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cci_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_cci_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_cci_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1820,8 +1820,8 @@ static struct clk_branch gcc_camss_cphy_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1838,8 +1838,8 @@ static struct clk_branch gcc_camss_cphy_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1856,8 +1856,8 @@ static struct clk_branch gcc_camss_cphy_2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1874,8 +1874,8 @@ static struct clk_branch gcc_camss_cphy_3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_cphy_3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1892,8 +1892,8 @@ static struct clk_branch gcc_camss_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi0phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_csi0phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1910,8 +1910,8 @@ static struct clk_branch gcc_camss_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi1phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_csi1phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1928,8 +1928,8 @@ static struct clk_branch gcc_camss_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi2phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_csi2phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1946,8 +1946,8 @@ static struct clk_branch gcc_camss_csi3phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_csi3phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_csi3phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1964,8 +1964,8 @@ static struct clk_branch gcc_camss_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_mclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1982,8 +1982,8 @@ static struct clk_branch gcc_camss_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_mclk1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2000,8 +2000,8 @@ static struct clk_branch gcc_camss_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_mclk2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2018,8 +2018,8 @@ static struct clk_branch gcc_camss_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_mclk3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2036,8 +2036,8 @@ static struct clk_branch gcc_camss_mclk4_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_mclk4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_mclk4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_mclk4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2067,8 +2067,8 @@ static struct clk_branch gcc_camss_ope_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_ope_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_ope_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_ope_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2085,8 +2085,8 @@ static struct clk_branch gcc_camss_ope_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_ope_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_ope_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_ope_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2116,8 +2116,8 @@ static struct clk_branch gcc_camss_tfe_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2134,8 +2134,8 @@ static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_0_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2152,8 +2152,8 @@ static struct clk_branch gcc_camss_tfe_0_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_0_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_0_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_0_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2170,8 +2170,8 @@ static struct clk_branch gcc_camss_tfe_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2188,8 +2188,8 @@ static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_1_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2206,8 +2206,8 @@ static struct clk_branch gcc_camss_tfe_1_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_1_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_1_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_1_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2224,8 +2224,8 @@ static struct clk_branch gcc_camss_tfe_2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2242,8 +2242,8 @@ static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_2_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2260,8 +2260,8 @@ static struct clk_branch gcc_camss_tfe_2_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_tfe_2_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_tfe_2_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_tfe_2_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2278,8 +2278,8 @@ static struct clk_branch gcc_camss_top_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_camss_top_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_camss_top_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_camss_top_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2298,8 +2298,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2345,8 +2345,8 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = { .enable_mask = BIT(20), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_disp_gpll0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_disp_gpll0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2408,8 +2408,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2426,8 +2426,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2444,8 +2444,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2477,8 +2477,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gpll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2494,8 +2494,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0_out_even.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gpll0_out_even.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2555,8 +2555,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pdm2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2717,8 +2717,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2735,8 +2735,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2753,8 +2753,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2771,8 +2771,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2789,8 +2789,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2807,8 +2807,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2851,8 +2851,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2869,8 +2869,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2887,8 +2887,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2905,8 +2905,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .enable_mask = BIT(24), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2923,8 +2923,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2941,8 +2941,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3032,8 +3032,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3052,8 +3052,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3083,8 +3083,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3103,8 +3103,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, @@ -3121,8 +3121,8 @@ static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3141,8 +3141,8 @@ static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3176,8 +3176,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3196,8 +3196,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3216,8 +3216,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3262,8 +3262,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3280,8 +3280,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3298,8 +3298,8 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3368,8 +3368,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3488,8 +3488,8 @@ static struct clk_branch gcc_video_vcodec0_sys_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_vcodec0_sys_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_video_venus_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_video_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3506,8 +3506,8 @@ static struct clk_branch gcc_video_venus_ctl_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_video_venus_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_video_venus_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]) { + &gcc_video_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT,