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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/29] hw/arm/virt: Introduce virt_set_high_memmap() helper Date: Thu, 15 Dec 2022 12:49:41 +0000 Message-Id: <20221215125009.980128-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan This introduces virt_set_high_memmap() helper. The logic of high memory region address assignment is moved to the helper. The intention is to make the subsequent optimization for high memory region address assignment easier. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Reviewed-by: Marc Zyngier Tested-by: Zhenyu Zhang Message-id: 20221029224307.138822-2-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 74 ++++++++++++++++++++++++++++----------------------- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b8713508561..ca300281939 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1690,6 +1690,46 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) return arm_cpu_mp_affinity(idx, clustersz); } +static void virt_set_high_memmap(VirtMachineState *vms, + hwaddr base, int pa_bits) +{ + int i; + + for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { + hwaddr size = extended_memmap[i].size; + bool fits; + + base = ROUND_UP(base, size); + vms->memmap[i].base = base; + vms->memmap[i].size = size; + + /* + * Check each device to see if they fit in the PA space, + * moving highest_gpa as we go. + * + * For each device that doesn't fit, disable it. + */ + fits = (base + size) <= BIT_ULL(pa_bits); + if (fits) { + vms->highest_gpa = base + size - 1; + } + + switch (i) { + case VIRT_HIGH_GIC_REDIST2: + vms->highmem_redists &= fits; + break; + case VIRT_HIGH_PCIE_ECAM: + vms->highmem_ecam &= fits; + break; + case VIRT_HIGH_PCIE_MMIO: + vms->highmem_mmio &= fits; + break; + } + + base += size; + } +} + static void virt_set_memmap(VirtMachineState *vms, int pa_bits) { MachineState *ms = MACHINE(vms); @@ -1745,39 +1785,7 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits) /* We know for sure that at least the memory fits in the PA space */ vms->highest_gpa = memtop - 1; - for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { - hwaddr size = extended_memmap[i].size; - bool fits; - - base = ROUND_UP(base, size); - vms->memmap[i].base = base; - vms->memmap[i].size = size; - - /* - * Check each device to see if they fit in the PA space, - * moving highest_gpa as we go. - * - * For each device that doesn't fit, disable it. - */ - fits = (base + size) <= BIT_ULL(pa_bits); - if (fits) { - vms->highest_gpa = base + size - 1; - } - - switch (i) { - case VIRT_HIGH_GIC_REDIST2: - vms->highmem_redists &= fits; - break; - case VIRT_HIGH_PCIE_ECAM: - vms->highmem_ecam &= fits; - break; - case VIRT_HIGH_PCIE_MMIO: - vms->highmem_mmio &= fits; - break; - } - - base += size; - } + virt_set_high_memmap(vms, base, pa_bits); if (device_memory_size > 0) { ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); From patchwork Thu Dec 15 12:49:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634176 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp127219pvb; Thu, 15 Dec 2022 04:50:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf5yPNg6LO9h7H3XQnne1sX6dit9k6u06ptW1gSxiaE2jyDFQ4kudCrjTlxv+kv3c2uhGPFz X-Received: by 2002:ad4:5109:0:b0:4c7:26a4:908e with SMTP id g9-20020ad45109000000b004c726a4908emr37587089qvp.47.1671108654968; Thu, 15 Dec 2022 04:50:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671108654; cv=none; d=google.com; s=arc-20160816; b=FTh1J+MSIX8bCrZJ25HNJ+1/j3K8hAIlLFeleOeUQFSn4XhlWdby9PZI4FW8eKZ4qI ihHAvPl5htM1rjhC04BjODOU/hvZLFx+BcsulmnNmQqO68DkOvpuhbpNCB7lN7bJRbdT oQYicAtRXxc9SwrMepItMEbTKnYTTdpQlpswmaO8e9brd7rfsitOunRRVKL2cICyM1+J QuawKdqdJ/p5I3bnE3TkJd0LstDrHB7cpDx4miu/PCwtomy+8rlpyDgvnmzhYH+vor/Y 5yf3ElYmcZYVLoZAzYGGv/JmkQsQ8rOaNkflGNZSYqJMa9UuDBTSs4+ZiJKUqG3alSqh KJCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lm7NlrrFf1C1nltmeU5bGZsKO+xvFdHgekkB5rtA8G0=; b=IczrIkI/WNFFqQRTFPasMMb7DAaSlnxZcY+1KPTz6+e+Wnt2PsybChX2mot/EgWf9q M5iuRQUAFCRQSEfh49EXfC2o9GrzK1NFQsGor3EmOL4SKg3OconpdbIdJM1FB3L9ygPy erermbXqgTvk01htKa6T7d6mroVbRS7A+PD3i+8ZQtAV4pc/WXK82ETwiR/JhtL+jUGZ cb8tpUCIjFfrSlMZ/vMvAkcNyEzIu2z+wzWCcwfy6kJXqRJuxe/YtNnhjtvc4SWdP1Nl Ap0E9kZeVP0LhENyBR52H79F9wXiZjTs3zBA7NvqTGMZQD/vFUrfps3t18uuBe6nPIKm QXlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=luxavzBR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap() Date: Thu, 15 Dec 2022 12:49:42 +0000 Message-Id: <20221215125009.980128-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan This renames variable 'size' to 'region_size' in virt_set_high_memmap(). Its counterpart ('region_base') will be introduced in next patch. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Reviewed-by: Marc Zyngier Tested-by: Zhenyu Zhang Message-id: 20221029224307.138822-3-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ca300281939..2659f4db15c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1693,15 +1693,16 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) static void virt_set_high_memmap(VirtMachineState *vms, hwaddr base, int pa_bits) { + hwaddr region_size; + bool fits; int i; for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { - hwaddr size = extended_memmap[i].size; - bool fits; + region_size = extended_memmap[i].size; - base = ROUND_UP(base, size); + base = ROUND_UP(base, region_size); vms->memmap[i].base = base; - vms->memmap[i].size = size; + vms->memmap[i].size = region_size; /* * Check each device to see if they fit in the PA space, @@ -1709,9 +1710,9 @@ static void virt_set_high_memmap(VirtMachineState *vms, * * For each device that doesn't fit, disable it. */ - fits = (base + size) <= BIT_ULL(pa_bits); + fits = (base + region_size) <= BIT_ULL(pa_bits); if (fits) { - vms->highest_gpa = base + size - 1; + vms->highest_gpa = base + region_size - 1; } switch (i) { @@ -1726,7 +1727,7 @@ static void virt_set_high_memmap(VirtMachineState *vms, break; } - base += size; + base += region_size; } } From patchwork Thu Dec 15 12:49:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634198 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp138310pvb; Thu, 15 Dec 2022 05:09:37 -0800 (PST) X-Google-Smtp-Source: AA0mqf4G1ObNUhCibTiJeEI1Glc+BWbaF0WZ6LfevYDjbd/s6KKqyEHKUA4PI7cTkyJQsCwIiRUu X-Received: by 2002:ac8:674f:0:b0:3a8:2e48:349f with SMTP id n15-20020ac8674f000000b003a82e48349fmr6965419qtp.61.1671109777665; Thu, 15 Dec 2022 05:09:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109777; cv=none; d=google.com; s=arc-20160816; b=tZx33cUyK9HWfq4Kv3JvG+GxIuqoDDx2nTV0FugXcMBo0LPV3JFI43D+/kXNbOQ3Ar jwTbG6FBamoUSlNK0vPOTJzeEisW6kJOUa/g6YJ+bEz8suNa+VP4kU0onNLjl95ipewv 0E4+zmRLr0LbowlAl/SodP3PbH5hE5852QUjfMzq72NKnWcYIKiXxNa0T1BE62TgDfxC Ek4agR/qkbgVeqj+lvKB/FsRwMjvark0Uj3N7u0d6jJ156Lc7Gm9DB8eaHQ3B7EkMLVd dn4I0qoFz4qpOZyrozu76C1c3QV+8fnv331tb0CfiVQhKwq6StU3bIFJJxajiDjiQFVW By7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aZPssVEhQbiKPfXn/XHsh9hjfGaH9CjO9zQb7G+virQ=; b=LGZJvVRtVjsHXcjEAaw99jLuzQ1AZXvYM7gjHwZya+yd2KxRfcEXhdllK6lIQYgrWM Ubely3aLA5RYE6X8sQ5UouPnqS0pYoSp+OkYTccB25WO2Due7ELlNYlTY9pfScfys14/ LnwTzb/+qHScsms95EpPRfPyJZzRe7eKm1bQAvCdXs1O6tTP/cms1PcfGTrB0ZSYkFpW 0LKh7Of0dqubk87qdkrN5V5bO/G+STWQB1MkJ6Dqp1GOCBywQbEuS2N1uMgZ/RN7X7BC 8b7Us8ziC9eu7xhyAa1rCEYFdoV/sikvEIByaiMspCZXOq6uKozn7XhKmYGKMS4+lSH7 IJAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e3HvTfEg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/29] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap() Date: Thu, 15 Dec 2022 12:49:43 +0000 Message-Id: <20221215125009.980128-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan This introduces variable 'region_base' for the base address of the specific high memory region. It's the preparatory work to optimize high memory region address assignment. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Reviewed-by: Marc Zyngier Tested-by: Zhenyu Zhang Message-id: 20221029224307.138822-4-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2659f4db15c..3bb1bf079ff 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1693,15 +1693,15 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) static void virt_set_high_memmap(VirtMachineState *vms, hwaddr base, int pa_bits) { - hwaddr region_size; + hwaddr region_base, region_size; bool fits; int i; for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { + region_base = ROUND_UP(base, extended_memmap[i].size); region_size = extended_memmap[i].size; - base = ROUND_UP(base, region_size); - vms->memmap[i].base = base; + vms->memmap[i].base = region_base; vms->memmap[i].size = region_size; /* @@ -1710,9 +1710,9 @@ static void virt_set_high_memmap(VirtMachineState *vms, * * For each device that doesn't fit, disable it. */ - fits = (base + region_size) <= BIT_ULL(pa_bits); + fits = (region_base + region_size) <= BIT_ULL(pa_bits); if (fits) { - vms->highest_gpa = base + region_size - 1; + vms->highest_gpa = region_base + region_size - 1; } switch (i) { @@ -1727,7 +1727,7 @@ static void virt_set_high_memmap(VirtMachineState *vms, break; } - base += region_size; + base = region_base + region_size; } } From patchwork Thu Dec 15 12:49:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634192 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp130784pvb; Thu, 15 Dec 2022 04:58:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf6xcRCVBkYDlWDlBh0TRMMZrtfIHAELThGJC5fePgi0jDmz2Wdq6hMxxmrH1/OkgODgwT71 X-Received: by 2002:a05:622a:1b89:b0:39c:da21:6c13 with SMTP id bp9-20020a05622a1b8900b0039cda216c13mr48576399qtb.21.1671109121997; Thu, 15 Dec 2022 04:58:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109121; cv=none; d=google.com; s=arc-20160816; b=nz0mOU9ULpb7GjBD0XcmbixfjG4LDsuv9NgtKVpDw0O++piPpVOaF46Fw7IljJ+ii3 myylajO/5Ssdsej6MEGuhBDjQBxtOZ4Dsc+NMGf7XKqRBjnzxJdq+I+HoZtgku1ZEVbK BWK8RiByYyto4yzrw5+vUB14LYx+8Ngj8M5Bu2tS97iHnL/dUEmdxC7OEFJDchP6iRuO 92l9fthzAVGK0wg1aAOj5IzO5amC7hYaSLi5qlqa83IIidhKmAB04tGT6Q7o5Yap5jMi yymC0j0BnOKlEmcbspRq6MYdJ+mPd6jMHv4qm8wEMHDdsUfygf4E3rNTaM47I+8iM4H1 En9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HwbRvl+35CTPIyxpkdvHciwwdNBHg4iIhCv/TONaLwM=; b=nzuJrG65UkyJvk6ue5W35a3z+jsmZlNY4qURNztS/k7OT2mNCLyW/HZnspWcK2IIql 7tjdg6ThfClEcFMCitKdB6yR8SFl1UzihPk4BFK1gXQem8q9DnhRmykvVtxGs5DA3Ij+ P3OkKb6bqcuOZ8CAXZI3gjRAubw+A7iPsbSKj2xamuv1Tu3h81gNjBAdwOZFTOMW/zr3 f23QLBuI1hTUwonKDiPhriGtt/t0h3xJtc78ZxJKm9fDx7x0vuqCqyuuUvFnsOVzeCHo nr1De0CPx67rKJCXyfYNs7bvk0r7QzArbZgkoaJiqXu84p+dhikxfpXz+ATfRxliQEh5 hY1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jzQUC7Gi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper Date: Thu, 15 Dec 2022 12:49:44 +0000 Message-Id: <20221215125009.980128-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan This introduces virt_get_high_memmap_enabled() helper, which returns the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will be used in the subsequent patches. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Reviewed-by: Marc Zyngier Tested-by: Zhenyu Zhang Message-id: 20221029224307.138822-5-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3bb1bf079ff..7689337470a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1690,14 +1690,31 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) return arm_cpu_mp_affinity(idx, clustersz); } +static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, + int index) +{ + bool *enabled_array[] = { + &vms->highmem_redists, + &vms->highmem_ecam, + &vms->highmem_mmio, + }; + + assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == + ARRAY_SIZE(enabled_array)); + assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); + + return enabled_array[index - VIRT_LOWMEMMAP_LAST]; +} + static void virt_set_high_memmap(VirtMachineState *vms, hwaddr base, int pa_bits) { hwaddr region_base, region_size; - bool fits; + bool *region_enabled, fits; int i; for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { + region_enabled = virt_get_high_memmap_enabled(vms, i); region_base = ROUND_UP(base, extended_memmap[i].size); region_size = extended_memmap[i].size; @@ -1715,18 +1732,7 @@ static void virt_set_high_memmap(VirtMachineState *vms, vms->highest_gpa = region_base + region_size - 1; } - switch (i) { - case VIRT_HIGH_GIC_REDIST2: - vms->highmem_redists &= fits; - break; - case VIRT_HIGH_PCIE_ECAM: - vms->highmem_ecam &= fits; - break; - case VIRT_HIGH_PCIE_MMIO: - vms->highmem_mmio &= fits; - break; - } - + *region_enabled &= fits; base = region_base + region_size; } } From patchwork Thu Dec 15 12:49:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634180 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp127248pvb; Thu, 15 Dec 2022 04:50:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf4tC0EB+IWIMkU8tNHwm1DlLY2kXCRvkMZJn6LsX7IEm+RpPi5p+OiM8r+x7jI5JIkCGU3i X-Received: by 2002:ac8:668d:0:b0:3a8:1ced:d2e1 with SMTP id d13-20020ac8668d000000b003a81cedd2e1mr17230140qtp.2.1671108658500; Thu, 15 Dec 2022 04:50:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671108658; cv=none; d=google.com; s=arc-20160816; b=k/rFzoGKhBpIBfSt5qD4NtV9vnqvMA2gL0HZ5Nnp6VN5TB7dbD4nyhUqLvp3fgUHQj Kl5mYMkbpjSAfJnZQ6i16Nf3HuvT+v0sOcG+Vp5fvDgknVDpveUeR05rSceWqbT1+z79 XyzHRzvD0s6XZ2+pgh337PEOQNUtqbePQ0GC4Eb8yn2pCFR3Xd28gwANWSBEvISpiJMg HpGZM6bBTINE0lMqdLjzQZ9LeWze9vrwcTWQ7HciWuGT6l4BN0a7hV5yAXDQkpIsBUTj C5psVCNkpY1T80mty31ayXxsNlMiel2mtSB15d7O2D8ojPbF03ITZO/a4DrXEENZ9cG4 sy6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8crXX2Vz1e8DxMP/PXNKOUHg5I2gJfVv7C5htrZV0hQ=; b=AgrTCh0jwbs5RGqN0c8synwFLR0krTfppr5AriyPIEn368QO+DU6Hk9D3USqPgS9kt dufPwUJwNmA2wBp0vv/e6jRfnLa3le3urnGV2cY4+ArQVtq6unZo3eAkVU9Pnhd0xbVC Ajtp81fCjspFnWmmfqm854thY6s4oTs1OLRWLKCaoAbAZT9IL1L3StEw+AqApCcYi9v1 B/an61VY0e2JjisHSWLNpH2U/guDxN2dukFLNns5dJMyHKHqBdwsQtEmAzpFw/mOgqOk J8bU0AwS/MOILZtnIhFCAkQJGmhz6ZQtBwm4mUs4e18y100STsh3ZFdlfKL55UuYnr2e TmrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zGTncryI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/29] hw/arm/virt: Improve high memory region address assignment Date: Thu, 15 Dec 2022 12:49:45 +0000 Message-Id: <20221215125009.980128-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan There are three high memory regions, which are VIRT_HIGH_REDIST2, VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses are floating on highest RAM address. However, they can be disabled in several cases. (1) One specific high memory region is likely to be disabled by code by toggling vms->highmem_{redists, ecam, mmio}. (2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is 'virt-2.12' or ealier than it. (3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded on 32-bits system. (4) One specific high memory region is disabled when it breaks the PA space limit. The current implementation of virt_set_{memmap, high_memmap}() isn't optimized because the high memory region's PA space is always reserved, regardless of whatever the actual state in the corresponding vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and 'vms->highest_gpa' are always increased for case (1), (2) and (3). It's unnecessary since the assigned PA space for the disabled high memory region won't be used afterwards. Improve the address assignment for those three high memory region by skipping the address assignment for one specific high memory region if it has been disabled in case (1), (2) and (3). The memory layout may be changed after the improvement is applied, which leads to potential migration breakage. So 'vms->highmem_compact' is added to control if the improvement should be applied. For now, 'vms->highmem_compact' is set to false, meaning that we don't have memory layout change until it becomes configurable through property 'compact-highmem' in next patch. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Reviewed-by: Marc Zyngier Tested-by: Zhenyu Zhang Message-id: 20221029224307.138822-6-gshan@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 15 ++++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 6ec479ca2b7..709f6237412 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -144,6 +144,7 @@ struct VirtMachineState { PFlashCFI01 *flash[2]; bool secure; bool highmem; + bool highmem_compact; bool highmem_ecam; bool highmem_mmio; bool highmem_redists; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7689337470a..807175707e7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1722,18 +1722,23 @@ static void virt_set_high_memmap(VirtMachineState *vms, vms->memmap[i].size = region_size; /* - * Check each device to see if they fit in the PA space, - * moving highest_gpa as we go. + * Check each device to see if it fits in the PA space, + * moving highest_gpa as we go. For compatibility, move + * highest_gpa for disabled fitting devices as well, if + * the compact layout has been disabled. * * For each device that doesn't fit, disable it. */ fits = (region_base + region_size) <= BIT_ULL(pa_bits); - if (fits) { - vms->highest_gpa = region_base + region_size - 1; + *region_enabled &= fits; + if (vms->highmem_compact && !*region_enabled) { + continue; } - *region_enabled &= fits; base = region_base + region_size; + if (fits) { + vms->highest_gpa = base - 1; + } } } From patchwork Thu Dec 15 12:49:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634199 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp139020pvb; Thu, 15 Dec 2022 05:10:45 -0800 (PST) X-Google-Smtp-Source: AA0mqf64ixlMHPs+dvKhbt/dQkHx0w9JkXyXv//EmgpgGBtkwx5aqPKCyHdY5eoHlk3GkaHDiYHd X-Received: by 2002:ac8:6b47:0:b0:39c:da20:616 with SMTP id x7-20020ac86b47000000b0039cda200616mr14503200qts.32.1671109845316; Thu, 15 Dec 2022 05:10:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109845; cv=none; d=google.com; s=arc-20160816; b=Mmpl+NB3IfUPVT5o1ZQ+c71WtFGrJjAwQ3qBgUZ2wLuExNAyNG+5RnlKPosSNGxURC gNx4cMGNaZPYONNDJTu0fl4wn8/lnKj8ntPjm4+i7P0YQeGd9suTCqYH84aBaqMISV1P se5/9e02v+NYHHdzyr1WJsNmYTRZE3ZClcOzOOKJ8tTgOBhJR8aSKqcWBTe7DMfpxVlP TtmOtUzaqv98NdU6UOp2XRTugngDRgPg+j/86V4j2it+wLJj0i+Ttd2FOxuyJ7RJPTXU JVUI19Ifdxt6WVKL8Hjr6pC404PegvG7fb4GIn0W6/5TMKs9Nf4umSiiS/61bFYu4pPi Lj2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=43MiuXznHIayB9l6fFgVondZWwTBp4HePNm+IfE5j/Q=; b=wzCSeftm53riVY5DJiChrLKczaIfEk5qzH354b6LtG1Ua0Rb1Mt5sbDqJJx+jiR0hY dogf6VuW+vwHty2ggFUH9yK3DMXxpTV9Z1RSuBcwxKNaRthsi+4/IB8U0gzfPO1zxDTT zRx+4JIcKKyEclIiIHlCmz3g9OdTWfmx0hiKtyuiFj7lOIiUpH9uIgqRXSsjBIlicAS/ I+lgERDEaagS9FtR/Kj8DXds5fRRYMh54GE9DcypSy8Xd2CpuTl+aPI+8w/8NnOycA0s I6UEHDTuuvIS7MJEfcDwsvr27AoFmF/Teof907E3uuuq+2bX+DUX8VKrItpJGu3VISSz Rv7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DUxo+B7C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/29] hw/arm/virt: Add 'compact-highmem' property Date: Thu, 15 Dec 2022 12:49:46 +0000 Message-Id: <20221215125009.980128-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan After the improvement to high memory region address assignment is applied, the memory layout can be changed, introducing possible migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region is disabled or enabled when the optimization is applied or not, with the following configuration. The configuration is only achievable by modifying the source code until more properties are added to allow users selectively disable those high memory regions. pa_bits = 40; vms->highmem_redists = false; vms->highmem_ecam = false; vms->highmem_mmio = true; # qemu-system-aarch64 -accel kvm -cpu host \ -machine virt-7.2,compact-highmem={on, off} \ -m 4G,maxmem=511G -monitor stdio Region compact-highmem=off compact-highmem=on ---------------------------------------------------------------- MEM [1GB 512GB] [1GB 512GB] HIGH_GIC_REDISTS2 [512GB 512GB+64MB] [disabled] HIGH_PCIE_ECAM [512GB+256MB 512GB+512MB] [disabled] HIGH_PCIE_MMIO [disabled] [512GB 1TB] In order to keep backwords compatibility, we need to disable the optimization on machine, which is virt-7.1 or ealier than it. It means the optimization is enabled by default from virt-7.2. Besides, 'compact-highmem' property is added so that the optimization can be explicitly enabled or disabled on all machine types by users. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Reviewed-by: Marc Zyngier Tested-by: Zhenyu Zhang Message-id: 20221029224307.138822-7-gshan@redhat.com Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 4 ++++ include/hw/arm/virt.h | 1 + hw/arm/virt.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 20442ea2c13..4454706392c 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -94,6 +94,10 @@ highmem address space above 32 bits. The default is ``on`` for machine types later than ``virt-2.12``. +compact-highmem + Set ``on``/``off`` to enable/disable the compact layout for high memory regions. + The default is ``on`` for machine types later than ``virt-7.2``. + gic-version Specify the version of the Generic Interrupt Controller (GIC) to provide. Valid values are: diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 709f6237412..c7dd59d7f1f 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -125,6 +125,7 @@ struct VirtMachineClass { bool no_pmu; bool claim_edge_triggered_timers; bool smbios_old_sys_ver; + bool no_highmem_compact; bool no_highmem_ecam; bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */ bool kvm_no_adjvtime; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 807175707e7..3d1371c05c0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -174,6 +174,12 @@ static const MemMapEntry base_memmap[] = { * Note the extended_memmap is sized so that it eventually also includes the * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last * index of base_memmap). + * + * The memory map for these Highmem IO Regions can be in legacy or compact + * layout, depending on 'compact-highmem' property. With legacy layout, the + * PA space for one specific region is always reserved, even if the region + * has been disabled or doesn't fit into the PA space. However, the PA space + * for the region won't be reserved in these circumstances with compact layout. */ static MemMapEntry extended_memmap[] = { /* Additional 64 MB redist region (can contain up to 512 redistributors) */ @@ -2352,6 +2358,20 @@ static void virt_set_highmem(Object *obj, bool value, Error **errp) vms->highmem = value; } +static bool virt_get_compact_highmem(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->highmem_compact; +} + +static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->highmem_compact = value; +} + static bool virt_get_its(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -2970,6 +2990,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) "Set on/off to enable/disable using " "physical address space above 32 bits"); + object_class_property_add_bool(oc, "compact-highmem", + virt_get_compact_highmem, + virt_set_compact_highmem); + object_class_property_set_description(oc, "compact-highmem", + "Set on/off to enable/disable compact " + "layout for high memory regions"); + object_class_property_add_str(oc, "gic-version", virt_get_gic_version, virt_set_gic_version); object_class_property_set_description(oc, "gic-version", @@ -3054,6 +3081,7 @@ static void virt_instance_init(Object *obj) /* High memory is enabled by default */ vms->highmem = true; + vms->highmem_compact = !vmc->no_highmem_compact; vms->gic_version = VIRT_GIC_VERSION_NOSEL; vms->highmem_ecam = !vmc->no_highmem_ecam; @@ -3123,8 +3151,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 2) static void virt_machine_7_1_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_7_2_options(mc); compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); + /* Compact layout for high memory regions was introduced with 7.2 */ + vmc->no_highmem_compact = true; } DEFINE_VIRT_MACHINE(7, 1) From patchwork Thu Dec 15 12:49:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634196 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp134178pvb; Thu, 15 Dec 2022 05:03:45 -0800 (PST) X-Google-Smtp-Source: AA0mqf5PQ4Pq70Ud/jjRcJk0x7+3+CK3TgJsTulHogSLIx2cYIgI6x1RqG3jDIv6qrvt+SaYQf9v X-Received: by 2002:a05:6870:2886:b0:144:b157:ddb3 with SMTP id gy6-20020a056870288600b00144b157ddb3mr13059478oab.51.1671109425667; Thu, 15 Dec 2022 05:03:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109425; cv=none; d=google.com; s=arc-20160816; b=rUbi4L8B3BkytxtWpwvHmZ6xMPdEoD0+wJlGkjD9a9I8tqhwng2L5pSxvVqKGyrWqi 4IWqwxykdMJ5IM3MB6XNJAyXzZrVXQv6bKmAYVIlZqTAjTVEOswCId2ScPLAcXCdhyeQ BcW7e4UwUYwQg2OsR7ONzqv6J95/3XZDhMiT6Uq/eaMWfR6/bBY1eerJ1YcznxBO8hOm 3EGCAIjIrdu7LtYBQYtKK9jqe/Rs4D7o6ARL2ETqJ+YlxmGfGKnOdx0lGpvpiBwcwQR0 +g8lk9rY7aZz+7YhM9pGuBWWqIK2sJyY6iIHlKNG7DR3vJYbGALKIL6YEHADPTO/Agy6 +ZlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5dJXVk6Pxoxg5miy1GeHW56WuXWRVzOcLZ8zV52nDko=; b=i2DvbusYlvqab5twBQNXezwDtkZ5Wu+hh3O7PLaFY8/8lEOlY937m0Cp1aXrMlZH5/ wwUg2YBYwaMc9/b/Yzoun5KwxMFGswcZMLxum85MfJWkyDR6ONGcYYkPqs3V3xApmgK8 uHsdE+SJHjK75kY8zb97mudG/+cktuVatyWPcDoShbklerLkW6KPX8M5UifvJSepAdoM DHTY0D/gxqxgsW3LCNVX96AWCRTr6iB9Zccvh2gk7GbA51HiwcyPPw44R0wtsPtOR+/l VlnWNr4iXc5X+7g91FCCKGy992haaP2Kfpaj/0ZacsihBl6vssPdfflCAgwZCfWeqrJg 9Wpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E2Bhoyqa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/29] hw/arm/virt: Add properties to disable high memory regions Date: Thu, 15 Dec 2022 12:49:47 +0000 Message-Id: <20221215125009.980128-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gavin Shan The 3 high memory regions are usually enabled by default, but they may be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2. This leads to waste in the PA space. Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to allow users selectively disable them if needed. After that, the high memory region for GICv3 or GICv4 redistributor can be disabled by user, the number of maximal supported CPUs needs to be calculated based on 'vms->highmem_redists'. The follow-up error message is also improved to indicate if the high memory region for GICv3 and GICv4 has been enabled or not. Suggested-by: Marc Zyngier Signed-off-by: Gavin Shan Reviewed-by: Marc Zyngier Reviewed-by: Cornelia Huck Reviewed-by: Eric Auger Message-id: 20221029224307.138822-8-gshan@redhat.com Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 13 +++++++ hw/arm/virt.c | 75 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 86 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 4454706392c..188a4f211f4 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -98,6 +98,19 @@ compact-highmem Set ``on``/``off`` to enable/disable the compact layout for high memory regions. The default is ``on`` for machine types later than ``virt-7.2``. +highmem-redists + Set ``on``/``off`` to enable/disable the high memory region for GICv3 or + GICv4 redistributor. The default is ``on``. Setting this to ``off`` will + limit the maximum number of CPUs when GICv3 or GICv4 is used. + +highmem-ecam + Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM. + The default is ``on`` for machine types later than ``virt-3.0``. + +highmem-mmio + Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO. + The default is ``on``. + gic-version Specify the version of the Generic Interrupt Controller (GIC) to provide. Valid values are: diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3d1371c05c0..0acb71be962 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2096,14 +2096,20 @@ static void machvirt_init(MachineState *machine) if (vms->gic_version == VIRT_GIC_VERSION_2) { virt_max_cpus = GIC_NCPU; } else { - virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + - virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); + virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); + if (vms->highmem_redists) { + virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); + } } if (max_cpus > virt_max_cpus) { error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " "supported by machine 'mach-virt' (%d)", max_cpus, virt_max_cpus); + if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { + error_printf("Try 'highmem-redists=on' for more CPUs\n"); + } + exit(1); } @@ -2372,6 +2378,49 @@ static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) vms->highmem_compact = value; } +static bool virt_get_highmem_redists(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->highmem_redists; +} + +static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->highmem_redists = value; +} + +static bool virt_get_highmem_ecam(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->highmem_ecam; +} + +static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->highmem_ecam = value; +} + +static bool virt_get_highmem_mmio(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->highmem_mmio; +} + +static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->highmem_mmio = value; +} + + static bool virt_get_its(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -2997,6 +3046,28 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) "Set on/off to enable/disable compact " "layout for high memory regions"); + object_class_property_add_bool(oc, "highmem-redists", + virt_get_highmem_redists, + virt_set_highmem_redists); + object_class_property_set_description(oc, "highmem-redists", + "Set on/off to enable/disable high " + "memory region for GICv3 or GICv4 " + "redistributor"); + + object_class_property_add_bool(oc, "highmem-ecam", + virt_get_highmem_ecam, + virt_set_highmem_ecam); + object_class_property_set_description(oc, "highmem-ecam", + "Set on/off to enable/disable high " + "memory region for PCI ECAM"); + + object_class_property_add_bool(oc, "highmem-mmio", + virt_get_highmem_mmio, + virt_set_highmem_mmio); + object_class_property_set_description(oc, "highmem-mmio", + "Set on/off to enable/disable high " + "memory region for PCI MMIO"); + object_class_property_add_str(oc, "gic-version", virt_get_gic_version, virt_set_gic_version); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/29] hw/arm/virt: build SMBIOS 19 table Date: Thu, 15 Dec 2022 12:49:48 +0000 Message-Id: <20221215125009.980128-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Mihai Carabas Use the base_memmap to build the SMBIOS 19 table which provides the address mapping for a Physical Memory Array (from spec [1] chapter 7.20). This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5 ("SMBIOS: Build aggregate smbios tables and entry point"). [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf The absence of this table is a breach of the specs and is detected by the FirmwareTestSuite (FWTS), but it doesn't cause any known problems for guest OSes. Signed-off-by: Mihai Carabas Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0acb71be962..bf59784aefa 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1614,9 +1614,11 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) static void virt_build_smbios(VirtMachineState *vms) { MachineClass *mc = MACHINE_GET_CLASS(vms); + MachineState *ms = MACHINE(vms); VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); uint8_t *smbios_tables, *smbios_anchor; size_t smbios_tables_len, smbios_anchor_len; + struct smbios_phys_mem_area mem_array; const char *product = "QEMU Virtual Machine"; if (kvm_enabled()) { @@ -1627,7 +1629,11 @@ static void virt_build_smbios(VirtMachineState *vms) vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, true, SMBIOS_ENTRY_POINT_TYPE_64); - smbios_get_tables(MACHINE(vms), NULL, 0, + /* build the array of physical mem area from base_memmap */ + mem_array.address = vms->memmap[VIRT_MEM].base; + mem_array.length = ms->ram_size; + + smbios_get_tables(ms, &mem_array, 1, &smbios_tables, &smbios_tables_len, &smbios_anchor, &smbios_anchor_len, &error_fatal); From patchwork Thu Dec 15 12:49:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634182 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp127433pvb; Thu, 15 Dec 2022 04:51:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf4ynbyiSH4EKnP5WGnZ+3GkMkg+p9Ao+Xefbs9m+Po5kZg0CMjEpg6yk+6u7Qfo7i2c8OGG X-Received: by 2002:ac8:5e52:0:b0:3a5:17f0:e718 with SMTP id i18-20020ac85e52000000b003a517f0e718mr49236043qtx.14.1671108677798; Thu, 15 Dec 2022 04:51:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671108677; cv=none; d=google.com; s=arc-20160816; b=T8e5mNJhBIQ59LmBQv+5ug44IRQPUS+N+mc8YqQq4qjmapcb6uy072oYDrMLojv9Tz 67CTylcTOzZRQjrQ/ECwRxv6ljw0PQISFF7eE6lRR1abumlTSACRsiJbj6AypCb0PkzO HoJVFosiwqHN2cMOD2+4/d0DEc3qiATT8v/P8mDYfdC08LrfE3lsVnJhLc75TByEMZe/ 01dnHcKSV1rVnAv7lQh5OZpt2preefgzkBIXJ1enodJWLfT70sQSuqZ8P7idQoH2k6CM RA+AaMbw9B3gsdORFSJYrgyKgB8yt1iHnY+51f/aGu665xdFCvvhkPgyZWrP5qcYkDaD R8AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UcEEPbA9TVrn0lA237GLQjyDDGjqynsdLl9q4ZxOLp8=; b=QeiBAg2xonFjWqQ9P55FKHXoaewbrBIregpicY0yCf32I6qyRZR5Qmc6zh1VAsj16M 3yB5+63Ar0ZNzKFvoNu0JFKleWaR2CVRAhTKPYbAwQHGrEBD4EFskeuW7LJ4tAt9zb4P Kc0hU2mJLSh34jY7RABZdlTdc++/NhpgHLXnVrgm1ivUF/ETYmgOUmP60hfD8j/+b+LF IEuiVrvEWBevy6tnB7QZTZEzLHmTh7dPQvZRiTGVqNbs/majzHHmGGO/HXlON25L7HuY ej+CwdQJoBstn1OYOmH67a8liG2zaUodjxPU6QpermTqr0MkOcHSu7hY75UDakuplJSY 0TVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fK2KfFjP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/29] target/arm: Add Cortex-A55 CPU Date: Thu, 15 Dec 2022 12:49:49 +0000 Message-Id: <20221215125009.980128-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Timofey Kutergin The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular it supports the Privileged Access Never (PAN) feature. Add a model of this CPU, so you can use a CPU type on the virt board that models a specific real hardware CPU, rather than having to use the QEMU-specific "max" CPU type. Signed-off-by: Timofey Kutergin Message-id: 20221121150819.2782817-1-tkutergin@gmail.com [PMM: tweaked commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 188a4f211f4..1cab33f02e3 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -54,6 +54,7 @@ Supported guest CPU types: - ``cortex-a15`` (32-bit; the default) - ``cortex-a35`` (64-bit) - ``cortex-a53`` (64-bit) +- ``cortex-a55`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) - ``cortex-a76`` (64-bit) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index bf59784aefa..a2dd48dfb80 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -207,6 +207,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a15"), ARM_CPU_TYPE_NAME("cortex-a35"), ARM_CPU_TYPE_NAME("cortex-a53"), + ARM_CPU_TYPE_NAME("cortex-a55"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3d74f134f57..cec64471b4e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -792,6 +792,74 @@ static void aarch64_a53_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } +static void aarch64_a55_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a55"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr = 0x82000023; + cpu->ctr = 0x84448004; /* L1Ip = VIPT */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_dfr0 = 0x04010088; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x01011121; + cpu->isar.id_isar6 = 0x00000010; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01260000; + cpu->isar.id_mmfr3 = 0x02122211; + cpu->isar.id_mmfr4 = 0x00021110; + cpu->isar.id_pfr0 = 0x10010131; + cpu->isar.id_pfr1 = 0x00011011; + cpu->isar.id_pfr2 = 0x00000011; + cpu->midr = 0x412FD050; /* r2p0 */ + cpu->revidr = 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ + cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ + + /* From B2.96 SCTLR_EL3 */ + cpu->reset_sctlr = 0x30c50838; + + /* From B4.45 ICH_VTR_EL2 */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + cpu->gic_pribits = 5; + + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x13211111; + cpu->isar.mvfr2 = 0x00000043; + + /* From D5.4 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 = 0x410b3000; +} + static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -1243,6 +1311,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, From patchwork Thu Dec 15 12:49:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634183 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp127823pvb; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement Date: Thu, 15 Dec 2022 12:49:50 +0000 Message-Id: <20221215125009.980128-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Luke Starrett The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER register: "indicates the maximum SPI INTID that the GIC implementation supports" As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted for the internal 16x SGI's and 16x PPI's. However, the original GICv3 model subtracted off the SGI/PPI. Cosmetically this can be seen at OS boot (Linux) showing 32 shy of what should be there, i.e.: [ 0.000000] GICv3: 224 SPIs implemented Though in hw/arm/virt.c, the machine is configured for 256 SPI's. ARM virt machine likely doesn't have a problem with this because the upper 32 IRQ's don't actually have anything meaningful wired. But, this does become a functional issue on a custom use case which wants to make use of these IRQ's. Additionally, boot code (i.e. TF-A) will only init up to the number (blocks of 32) that it believes to actually be there. Signed-off-by: Luke Starrett Message-id: AM9P193MB168473D99B761E204E032095D40D9@AM9P193MB1684.EURP193.PROD.OUTLOOK.COM Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_dist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index eea03681187..d599fefcbcf 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -390,9 +390,9 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, * MBIS == 0 (message-based SPIs not supported) * SecurityExtn == 1 if security extns supported * CPUNumber == 0 since for us ARE is always 1 - * ITLinesNumber == (num external irqs / 32) - 1 + * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1) */ - int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; + int itlinesnumber = (s->num_irq / 32) - 1; /* * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and * "security extensions not supported" always implies DS == 1, From patchwork Thu Dec 15 12:49:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634191 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp130728pvb; Thu, 15 Dec 2022 04:58:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf5FCCm/+y5/YqJtiirAg4yczGwafuPVQ8LerD8Avzk7DGk7I88mxhWg5FV8wEQdlJdBFirQ X-Received: by 2002:ad4:4d49:0:b0:4d7:45fb:f5ac with SMTP id m9-20020ad44d49000000b004d745fbf5acmr29639985qvm.23.1671109113859; Thu, 15 Dec 2022 04:58:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109113; cv=none; d=google.com; s=arc-20160816; b=Ko858RKv2DPXowezBNNx+UUo5/YBicDyqnE7evrIDMNzCUjSBlXpcohHFEWiXCcE1C 0HVda0Z5C7Y1z1IDtgHKiWEVYZTza2StX4MqhWRtNH5OUhO8FvO0pBEbx8+ER9UbUrSn 1lbLw8TDvDURK+hvF47UYoggcIE9RQXdGqpvfXWSCyWfNpTayX3WwoIiHWThwZbd6Zq8 vhuDGqwlZZmO4DOhBsPamCihRRqFouMvySpomWbSmksJc5qLcdy6UtxFZDaoRIZtv6DZ UuBrZ5LsLioazMvObvUTuc77aPpv8F03VweZm3gc9SYLZod+cuIuFGC7G2YAZ0EWKqeE djig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uupKhb0u/oKN7bGek/c6f+4vzO/X9cJUo24FKyvg7uE=; b=wkZVyl3Jg5PMIMAUULph3CqZ9EJAOZb0irbyCFqRw3kAbEhjWEN3kC8kZNvilIDjJq OrTicczogxZm7PbagMwp56OehvNkXdM3KTF+rXN9x6jrX6xvsP3mqeIAz0k+PpyEYPSN Su+MSH30J/c9ZZ5BKpF93udHjGYkBBVu2WUVh3SsLhKU3BwPrUXxNyuNwjewyIEm+Aek bCOOzthkmiaJHDsbS5BroShCGHbK/05zQLumzrjr5wT/3BSjsUYjBbEurFm+FvcuyPoJ KrXiH1smm1hGs5n3DFfuz+TvpjDOL2nyz0dKmQlMpnAFRha301jztpUCqNNeOa52+Z+m OLWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GafXR0H6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT Date: Thu, 15 Dec 2022 12:49:51 +0000 Message-Id: <20221215125009.980128-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS, TICAB, TOCU and TID4. These allow the guest to enable trapping of various EL1 instructions to EL2. In this commit, add the necessary code to allow the guest to set these bits if the feature is present; because the bit is always zero when the feature isn't present we won't need to use explicit feature checks in the "trap on condition" tests in the following commits. Note that although full implementation of the feature (mandatory from Armv8.5 onward) requires all five trap bits, the ID registers permit a value indicating that only TICAB, TOCU and TID4 are implemented, which might be the case for CPUs between Armv8.2 and Armv8.5. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 30 ++++++++++++++++++++++++++++++ target/arm/helper.c | 6 ++++++ 2 files changed, 36 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9aeed3c8481..2b4bd20f9d0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3757,6 +3757,16 @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; } +static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; +} + +static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; +} + static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) { return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; @@ -4029,6 +4039,16 @@ static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; } +static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; +} + +static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; @@ -4313,6 +4333,16 @@ static inline bool isar_feature_any_ras(const ARMISARegisters *id) return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); } +static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) +{ + return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); +} + +static inline bool isar_feature_any_evt(const ARMISARegisters *id) +{ + return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d8c8223ec38..751c360ce45 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5267,6 +5267,12 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) } } + if (cpu_isar_feature(any_evt, cpu)) { + valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4; + } else if (cpu_isar_feature(any_half_evt, cpu)) { + valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4; + } + /* Clear RES0 bits. */ value &= valid_mask; From patchwork Thu Dec 15 12:49:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634202 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp152704pvb; Thu, 15 Dec 2022 05:33:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf78i2Azps9dL/YZ6Qc6eDDqxkUwm55K6Y0pvIwNsojiYxIkbDWbOPZIGciBhiTkq8ZD005j X-Received: by 2002:a05:6214:449c:b0:4da:ef71:14b0 with SMTP id on28-20020a056214449c00b004daef7114b0mr32696869qvb.50.1671111233795; Thu, 15 Dec 2022 05:33:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671111233; cv=none; d=google.com; s=arc-20160816; b=Zp40IHbb1EsF3z0lmtLxafrnVpjIGoRp5YJF6LWYvuGazZnS0dwNrT4fZ2QcEOJPzJ fqoOr1mFXfyCl5Jm9eezU9hc/QMOVWvi+xuoFd670FJ7HIvM3XXwQ+PUaSDb5ORDHrnP YfWfOaeF4SXPtIzC4vDWKJYSMD0dT5wWCxe/rZQjqzvDyjVEnKckyt/ePFo31/et//G3 nMUrcI0L6bE9ecArP9Xvv5l+8d2r730rjwrIhPXlIf3azEGrkV5asIXyoO8cHKAm8uJ0 ld3BdI0eJEvcfevVoJLq/JD5vaRnsqogpEBsh1nTn+BWZjVe6ou8pLL7iiZ4+k+T78pw h7+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DrWNKUI5/mIVVsAs8JQZepO2Gy1iWGNfZwBpATQuyTk=; b=1BJOGrIXA9p8Qmkm6kAQJ3rGky0Vypz8qikST3K3lrf6YY+QSoVMn9m2Vl250+4xY9 vihcXJVcPX3NnbuJBaeEe3+6Fhl6sA5HYZLI2vDWtIDsoJWpEpjTeEINFwQI93WFC5Fy aH9v4Q2illm6nKtP1D+BtkfzJV8zodxRz+7FeEqAScrwCar6tXoNNMOFVIFyy0j87s/B 7OO31BvIElYZeSI/j4wdf/c2bpcY8Qy58dG4jXHAG7XEkSxzRvHpMqq+15ePJXxRUWdH 80NSmOc7LEV0Ek2wbTPaiQ4lkfKoLnGaB+8JKmp7jfW11Vpoeeai/UMkpShLl6DB50IP 7e6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MLSzjHd0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps Date: Thu, 15 Dec 2022 12:49:52 +0000 Message-Id: <20221215125009.980128-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of TLB maintenance instructions that operate on the inner shareable domain: AArch64: TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS, TLBI RVALE1IS, and TLBI RVAALE1IS. AArch32: TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS, and TLBIMVAALIS. Add the trapping support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 43 +++++++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 751c360ce45..475b48750e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -362,6 +362,17 @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */ +static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && + (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); @@ -2206,16 +2217,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { static const ARMCPRegInfo v7mp_cp_reginfo[] = { /* 32 bit TLB invalidates, Inner Shareable */ { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbiall_is_write }, { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimva_is_write }, { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbiasid_is_write }, { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimvaa_is_write }, }; @@ -4948,27 +4959,27 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { /* TLBI operations */ { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, @@ -5078,10 +5089,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { #endif /* TLB invalidate last level of translation table walk */ { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimva_is_write }, { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, .writefn = tlbimvaa_is_write }, { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, @@ -6726,19 +6737,19 @@ static const ARMCPRegInfo pauth_reginfo[] = { static const ARMCPRegInfo tlbirange_reginfo[] = { { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, From patchwork Thu Dec 15 12:49:53 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps Date: Thu, 15 Dec 2022 12:49:53 +0000 Message-Id: <20221215125009.980128-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1 use of TLB maintenance instructions that operate on the outer shareable domain: TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS, TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS, TLBI RVALE1OS, and TLBI RVAALE1OS. (There are no AArch32 outer-shareable TLB maintenance ops.) Implement the trapping. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 475b48750e9..0ec1c3ffbd6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -373,6 +373,19 @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +#ifdef TARGET_AARCH64 +/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ +static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && + (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} +#endif + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); @@ -6753,19 +6766,19 @@ static const ARMCPRegInfo tlbirange_reginfo[] = { .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, @@ -6852,27 +6865,27 @@ static const ARMCPRegInfo tlbirange_reginfo[] = { static const ARMCPRegInfo tlbios_reginfo[] = { { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, From patchwork Thu Dec 15 12:49:54 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps Date: Thu, 15 Dec 2022 12:49:54 +0000 Message-Id: <20221215125009.980128-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS and IC IALLUIS cache maintenance instructions. The HCR_EL2.TOCU bit traps all the other cache maintenance instructions that operate to the point of unification: AArch64 IC IVAU, IC IALLU, DC CVAU AArch32 ICIMVAU, ICIALLU, DCCMVAU The two trap bits between them cover all of the cache maintenance instructions which must also check the HCR_TPU flag. Turn the old aa64_cacheop_pou_access() function into a helper function which takes the set of HCR_EL2 flags to check as an argument, and call it from new access_ticab() and access_tocu() functions as appropriate for each cache op. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ec1c3ffbd6..eee95a42f7f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4273,9 +4273,7 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, return CP_ACCESS_OK; } -static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags) { /* Cache invalidate/clean to Point of Unification... */ switch (arm_current_el(env)) { @@ -4286,8 +4284,8 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, } /* fall through */ case 1: - /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ - if (arm_hcr_el2_eff(env) & HCR_TPU) { + /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */ + if (arm_hcr_el2_eff(env) & hcrflags) { return CP_ACCESS_TRAP_EL2; } break; @@ -4295,6 +4293,18 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, return CP_ACCESS_OK; } +static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU); +} + +static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions * Page D4-1736 (DDI0487A.b) */ @@ -4935,15 +4945,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP, - .accessfn = aa64_cacheop_pou_access }, + .accessfn = access_ticab }, { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP, - .accessfn = aa64_cacheop_pou_access }, + .accessfn = access_tocu }, { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, .access = PL0_W, .type = ARM_CP_NOP, - .accessfn = aa64_cacheop_pou_access }, + .accessfn = access_tocu }, { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, .access = PL1_W, .accessfn = aa64_cacheop_poc_access, @@ -4961,7 +4971,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, .access = PL0_W, .type = ARM_CP_NOP, - .accessfn = aa64_cacheop_pou_access }, + .accessfn = access_tocu }, { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, .access = PL0_W, .type = ARM_CP_NOP, @@ -5138,13 +5148,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .writefn = tlbiipas2is_hyp_write }, /* 32 bit cache operations */ { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab }, { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, .type = ARM_CP_NOP, .access = PL1_W }, { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, .type = ARM_CP_NOP, .access = PL1_W }, { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, @@ -5158,7 +5168,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, From patchwork Thu Dec 15 12:49:55 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps Date: Thu, 15 Dec 2022 12:49:55 +0000 Message-Id: <20221215125009.980128-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and their AArch32 equivalents). This is a subset of the registers trapped by HCR_EL2.TID2, which includes all of these and also the CTR_EL0 register. Our implementation already uses a separate access function for CTR_EL0 (ctr_el0_access()), so all of the registers currently using access_aa64_tid2() should also be checking TID4. Make that function check both TID2 and TID4, and rename it appropriately. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index eee95a42f7f..bac2ea62c44 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1895,11 +1895,12 @@ static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) scr_write(env, ri, 0); } -static CPAccessResult access_aa64_tid2(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult access_tid4(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) { - if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { + if (arm_current_el(env) == 1 && + (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) { return CP_ACCESS_TRAP_EL2; } @@ -2130,12 +2131,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, - .accessfn = access_aa64_tid2, + .accessfn = access_tid4, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, .access = PL1_RW, - .accessfn = access_aa64_tid2, + .accessfn = access_tid4, .writefn = csselr_write, .resetvalue = 0, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, @@ -7281,7 +7282,7 @@ static const ARMCPRegInfo ccsidr2_reginfo[] = { { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, .access = PL1_R, - .accessfn = access_aa64_tid2, + .accessfn = access_tid4, .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, }; @@ -7581,7 +7582,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .name = "CLIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, - .accessfn = access_aa64_tid2, + .accessfn = access_tid4, .resetvalue = cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); From patchwork Thu Dec 15 12:49:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634203 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp152709pvb; Thu, 15 Dec 2022 05:33:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf7RmyMCyPAZkYYjsIkRf3jzw2UDQLBp226lqzzANoB9oaX48Lx1hBddMzZfpXX5X6EBFDVb X-Received: by 2002:a05:7500:570b:b0:ea:68a1:6a17 with SMTP id by11-20020a057500570b00b000ea68a16a17mr2942364gab.40.1671111234051; Thu, 15 Dec 2022 05:33:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671111234; cv=none; d=google.com; s=arc-20160816; b=hmbRLdXY3u2fFBBiU61UTcrBcO8uKpE6NL2G7CaTyXuhKY/lYEO+B7KZ4DjsvCS4oG NCvBKGbCpxr9GODuUuT0Utz28KweT+v2UDvYwyznklt9wgJhxx5oSlSXE++S3v+4YVti yptixb+bTBDCeaLehmxEYhxn1UuHqSXT9dEOX0V7M8hvK4BdF1BmhQENEBh+o1FMA9jF ofT41TeoakKCwKf/WIiXTOaK8bCRzXNwN3x1w+hbBsihG5+bb0eY50BjAOa75UU6n+7l S9AnskL0Xr2WVymj3Ab52B2xtRSqY3xC9841b1uCNoNXoHfRZGNi5iBQ0Oq+Y0XRAgGw VO0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PWgRSqdjM6ICBFf0pToxvYsV7w6dTK2uUn0DKaor9os=; b=lqluECg38eZB2UzWolTbzO41vOXb0/yRwGGyg0G9SXIa5tBONGa5pvdEHHkGUkCaeb 3NqbhtCeq4MySgAWSJh+V9IM5rrmH23svZNBnxHQIbnzTr+MOLtv0Stz4bKaEfVEHvMg QygGbefqvp494ixRcy6H9oN+P0N6AqBQ1ahXQUIqe9dHUoOadxTQstsP/nOJTWDtIXX+ Ln/TkoR+t0LkQO7N1TijYfE3ozYgFmkHpZHXgnwYqhPbZtKyhyoRb2vNsnet6wwdTdtK UPhjt55Wi1XzrG0FlRlxqgQVwTeZCAcpR6GTRNbCs3cfRsShIdID2wFoxb6cSM24uPU7 YzrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zMKo2uyg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max' Date: Thu, 15 Dec 2022 12:49:56 +0000 Message-Id: <20221215125009.980128-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Update the ID registers for TCG's '-cpu max' to report the FEAT_EVT Enhanced Virtualization Traps support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index e3af79bb8c9..b33d7c28dc1 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -26,6 +26,7 @@ the following architecture extensions: - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) - FEAT_ETS (Enhanced Translation Synchronization) +- FEAT_EVT (Enhanced Virtualization Traps) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP16 (Half-precision floating-point data processing) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index cec64471b4e..2cf2ca4ce5a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1254,6 +1254,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ + t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ cpu->isar.id_aa64mmfr2 = t; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9a2cef7d05a..568cbcfc524 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -65,6 +65,7 @@ void aa32_max_features(ARMCPU *cpu) t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ + t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ cpu->isar.id_mmfr4 = t; t = cpu->isar.id_mmfr5; From patchwork Thu Dec 15 12:49:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634197 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp134446pvb; Thu, 15 Dec 2022 05:04:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf4MN2eTRVOioq+F3luosziIfAx/qepEwUzgBiXsYKItgeW22mvdq9x+l0C40Sr9VBJi6wwb X-Received: by 2002:a05:6214:4254:b0:4c7:8cba:9093 with SMTP id ne20-20020a056214425400b004c78cba9093mr38188253qvb.48.1671109446129; Thu, 15 Dec 2022 05:04:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109446; cv=none; d=google.com; s=arc-20160816; b=ETHDnpq7XHFLF4CxCx6fm6V5U+ubWjqQ0DSh4W66kOwISiTOhYtz38N9bUUbHF2oin fZctX3/rfv24M3UqSO7ldlCsU2+nesdxBCOo5CEAR9FPdOTx+EDXn4cRDtsgEylLM+z2 v585xyBo9OllIcWE/wQt4opYUDu6vHWvGZAYHCmQDDLYPhPpYciAIAzra2khMpkmmG36 gqD9ab7tP1WhQWiBmWsNc9DBgg+TLSCjCO8w7PCa6hwVFHBWqvjtR0SJ885+EjgVrP3Q uIp5cVntGCIVKHiVKWhNiLtIiIB+zo8ESfi4kGKyHI2mvoXMvOxeOBsemWEOo1lUWT40 MCEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/8/61FsKkax9rY6lVJh9sK4fG7jg73p6fZusY0m7KIE=; b=H/rjUufB4+tDmHYLLUl91zULZ2HXybUT5F0nsKVi6d6OfRpPmezsJjNBSmsjVyFG89 8r65VHMroquw6acmfRnUZDELqmDfZeqyhgx4l1GQ7EGE7ANPoFmL35HbBCoU4fq1oSCU uTueg8FLNGCo8+Jr5Oe1/E6/Kd++B+9Ac1TqvRsRFA1LrIdzsaDLaLwfm+Veo2D6FCW/ 7pQA9rCrDF3RXDUmWezRSk5E/a0XuWJMCWfooyFYQumRJV0fRh+hRYhfOJNNXoKmeFTE INHYwEOg1FUCE4kIyrD03vAVO0332hMcgF3n1xi3wJ8HlOHpno2B8zk3vRgHM+ji27I1 4f4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=deQNOFOD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset Date: Thu, 15 Dec 2022 12:49:57 +0000 Message-Id: <20221215125009.980128-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method doesn't do anything that's invalid in the hold phase, so the conversion is simple and not a behaviour change. Note that we must convert this base class before we can convert the TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable handles "chain to parent class reset" when the base class is 3-phase and the subclass is still using legacy reset, but not the other way around. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org --- hw/arm/smmu-common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e09b9c13b74..220838525d4 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -526,9 +526,9 @@ static void smmu_base_realize(DeviceState *dev, Error **errp) } } -static void smmu_base_reset(DeviceState *dev) +static void smmu_base_reset_hold(Object *obj) { - SMMUState *s = ARM_SMMU(dev); + SMMUState *s = ARM_SMMU(obj); g_hash_table_remove_all(s->configs); g_hash_table_remove_all(s->iotlb); @@ -543,12 +543,13 @@ static Property smmu_dev_properties[] = { static void smmu_base_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass); device_class_set_props(dc, smmu_dev_properties); device_class_set_parent_realize(dc, smmu_base_realize, &sbc->parent_realize); - dc->reset = smmu_base_reset; + rc->phases.hold = smmu_base_reset_hold; } static const TypeInfo smmu_base_info = { From patchwork Thu Dec 15 12:49:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634205 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp153945pvb; Thu, 15 Dec 2022 05:35:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf725yeu3sqgrZf4okuZFmim7fPV8m+Qjj32QSaMFiZKsyAqbcJNfGl25MBbfBV+ExrUXKB/ X-Received: by 2002:a05:7508:138f:b0:47:95:3f5b with SMTP id df15-20020a057508138f00b0004700953f5bmr2720419gbb.9.1671111355085; Thu, 15 Dec 2022 05:35:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671111355; cv=none; d=google.com; s=arc-20160816; b=OR4MB3q+rhjfRfhjUlm/ls+tvlk+faqr4Bs8ylec9C2vbFTwZ4jZjE1QVmYE9eFSpe xjz7ASDoS9k0RBbPCzHHHhL41zPtEgVfnk4yBtcd8Yj1IAA7aXwIeE9TPG+ruVlpjBpg EL9uWfrC7bXMG/mKdOZYSz3/QQojUbBPB6yzEBH/zw70CaXw1hTkRn6TPCUZS8ArYALP PSNcIxIYSyEuM0rR4uthU1gc1tGsWf/wD+kOwKsW5TKHj8wjtCxBlAJ61TXGJCRwSHea zqRBr85zBsXf1a7JCwuehIc/QmlI96fGEFI7O8nnDroH9lDBr265LPljOz2gndNrw96M Wc1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Dw6wotKA3haXzI9jka+bFUKrg99kB/zH8+x+4g05lKY=; b=y764XKVcwKZoAJ0BeeJPuJlEifIz0zDzgPT/gvxj0Snjw3vb/0WEhup4lIhHIXrb8Q YGPpGS5XLj3/w3Itg3Mc8OMRHLNzMiUm2sesdOu4O5SXWx1xaEXuXGHtQ7GEM+yHL+ca 1DgHRNiKBY0EmqoHLTgiGVIiWQTfs0v8qhhfcPkodsCCXFLJYJq1fpa9gEcNeA7bscdd 74og56mGLECpQtOxL+Sn+1Pl+XKDEY+rUxFe1bYCm5zNXJXFGiYJVr5FwRcUs/hh7oiR S4aGr6DnlxzM58uguNIt4vB9n2i0aG4zvpBfAu8yWnt6TOW9lhfQvbjJEI1Egw28GYsU dh2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HzPCvfdq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/29] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset Date: Thu, 15 Dec 2022 12:49:58 +0000 Message-Id: <20221215125009.980128-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy reset method doesn't do anything that's invalid in the hold phase, so the conversion only requires changing it to a hold phase method, and using the 3-phase versions of the "save the parent reset method and chain to it" code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org --- include/hw/arm/smmuv3.h | 2 +- hw/arm/smmuv3.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index c641e60735e..f1921fdf9e7 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -77,7 +77,7 @@ struct SMMUv3Class { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; }; #define TYPE_ARM_SMMUV3 "arm-smmuv3" diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index daa80e9c7b6..955b89c8d59 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1431,12 +1431,14 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev) } } -static void smmu_reset(DeviceState *dev) +static void smmu_reset_hold(Object *obj) { - SMMUv3State *s = ARM_SMMUV3(dev); + SMMUv3State *s = ARM_SMMUV3(obj); SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); - c->parent_reset(dev); + if (c->parent_phases.hold) { + c->parent_phases.hold(obj); + } smmuv3_init_regs(s); } @@ -1520,10 +1522,12 @@ static void smmuv3_instance_init(Object *obj) static void smmuv3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); SMMUv3Class *c = ARM_SMMUV3_CLASS(klass); dc->vmsd = &vmstate_smmuv3; - device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset); + resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL, + &c->parent_phases); c->parent_realize = dc->realize; dc->realize = smmu_realize; } From patchwork Thu Dec 15 12:49:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634194 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp130893pvb; Thu, 15 Dec 2022 04:58:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf7aSUjDqEn+ieyjMSawxLw6O8Mih3mB+qqk9iXB4TWYR9plS4OGpRYLmK0u89EC5/a96bWy X-Received: by 2002:ad4:4485:0:b0:4e8:178d:7ec7 with SMTP id m5-20020ad44485000000b004e8178d7ec7mr14160003qvt.26.1671109138731; Thu, 15 Dec 2022 04:58:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109138; cv=none; d=google.com; s=arc-20160816; b=ogFAoLmek0iiqKBiOU0ZMMFIQcekwcuzLrCgZB1xVlFTDipNZPb3XkLWNkqtSoWnIf A4spa4UNRqkAHcOoGmQamCkAzU58veMelrcOr2pV9yObb0AdWM7faDZLG806Wfbito6H WDvTS8ACQ5UmTGPNrDFPcuNqfCYdmYRSwsyhRat2uT/yIs4l7SDMVmzAu6v58FACxY4g b4dhxITIy2+zzZiSnJn1G/FG4zFCLdUC+dLGXkq3JfIJsqukgpZnYTRGpaz7WpFs0wxa yxwj95UKWEAOsuIApPpd0KObwjFLkcnX4xUx42oDOtY19TZre9YfFftyxuAoP4P789jl Os4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0TV5qsA14dk+cYd8jhe+sXqAEhXPrpR+F1VJLlzHiEs=; b=so7Hqj1AawhPySmRA870qqKlbZnLBVjN/EZJAVjmRZvfROMNMFCc9nfy6K/+xx8uDy WhimVHaiKDq5iDTw5Im2HuXfWfTA8o7bn2BykETSqnbJm0KTopmqB39n8tERfhFmXOuY tMPD43hhCLrJDvqQ8VT8gezoxjhZWb31pq59XRXm2tXCmpJGwjDsjNDFtEUNknLPTbFJ P4XlmwLDLgRWwcAoR1t++1dUfiypj0njptpd4yTngS+GL3PF6cbPlPK6KHH+rBv7IrLH YXWGyZT4nCYsbgxinwzUHJB2nPpLNbuzqcow3Fc49SJLLN1DeZ2IwD0/EFt7rZYfq9Lx Zmdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="QBLi2Zt/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset Date: Thu, 15 Dec 2022 12:49:59 +0000 Message-Id: <20221215125009.980128-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset. This is a simple no-behaviour-change conversion. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20221109161444.3397405-4-peter.maydell@linaro.org --- hw/intc/arm_gic_common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 7b44d5625b6..a379cea3959 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -261,9 +261,9 @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu, } } -static void arm_gic_common_reset(DeviceState *dev) +static void arm_gic_common_reset_hold(Object *obj) { - GICState *s = ARM_GIC_COMMON(dev); + GICState *s = ARM_GIC_COMMON(obj); int i, j; int resetprio; @@ -364,9 +364,10 @@ static Property arm_gic_common_properties[] = { static void arm_gic_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); - dc->reset = arm_gic_common_reset; + rc->phases.hold = arm_gic_common_reset_hold; dc->realize = arm_gic_common_realize; device_class_set_props(dc, arm_gic_common_properties); dc->vmsd = &vmstate_gic; From patchwork Thu Dec 15 12:50:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634193 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp130867pvb; Thu, 15 Dec 2022 04:58:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf7ZLCU5KEBU8H9cnqVe/B53G9rd/4mt7deDqzyrbp+LJmTwJgb9/QismznXGk5V52/+vTks X-Received: by 2002:ac8:4a17:0:b0:3a7:e2df:e868 with SMTP id x23-20020ac84a17000000b003a7e2dfe868mr35839111qtq.41.1671109133293; Thu, 15 Dec 2022 04:58:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109133; cv=none; d=google.com; s=arc-20160816; b=sz+kFHJvMQp7/K87vN2ljwEkaZ312I+9Z1zrxVYPts3jBjKN7M/nfLRdguBBqxi1JA h8toxMG4xw9QaLjhus1L27Xj0alzVA9tpDLDxU/8SuXMHY0OP/sTZb9RQ4jUQtzW2BsB dSENL07BKkYzyR4ihrF4qn03RVpmvDi34/mHoYR9Zy/ptjwNi9vmqSzG7HQIZcgpoQEG 5dHjAXx6ZgpO49tEgPyktRfkLWaM5WXPIwesK0qEw8wbqKr2286A3bDvQ49zyIKeZqKy 6JNHEBRP7B+P7r9u9wI+65SFhG6qYbyaoknSD2Xm6315zTjUO523eUMcvtFFdyROsW0Z F4Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Sb8rZwHrNhrvr6X/OgCKlqVcv8NJTW1C2wl4Tbc0DMM=; b=IPn2hvoDz70obYEBvG6o90gs7ZMEQ135B1Q7H0xNIIDRS+tySBrjMA6dxBVMRJCN4o 7SPkUpLyd51KPmuqpr+QTI4wMFWMwhhrqyD0d5eoHnvzO25cGqjet4qNHgVl9KvjiWqG kbCV8r48UfLU8QZfxb2xkIyQqy4HNczM9B1YKYTswOummQI6KYr1LTJ586L34OIb28rz o8kTMb8r0E6Uh2t681Hw8FYe78h+sZTKiiSg1ZNir6uqz/dL89ZOzrKGS00nGkXaiFnK Khk+I1YRAxSgs5NunuWNr/8LT121kvOiiU5vjztqBHs5xIz814ZiO6Es4oa+h/ChvmAa S8iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rkth8aY0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/29] hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset Date: Thu, 15 Dec 2022 12:50:00 +0000 Message-Id: <20221215125009.980128-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now we have converted TYPE_ARM_GIC_COMMON, we can convert the TYPE_ARM_GIC_KVM subclass to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221109161444.3397405-5-peter.maydell@linaro.org --- hw/intc/arm_gic_kvm.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 7d2a13273a4..1d588946bce 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -38,7 +38,7 @@ DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass, struct KVMARMGICClass { ARMGICCommonClass parent_class; DeviceRealize parent_realize; - void (*parent_reset)(DeviceState *dev); + ResettablePhases parent_phases; }; void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level) @@ -473,12 +473,14 @@ static void kvm_arm_gic_get(GICState *s) } } -static void kvm_arm_gic_reset(DeviceState *dev) +static void kvm_arm_gic_reset_hold(Object *obj) { - GICState *s = ARM_GIC_COMMON(dev); + GICState *s = ARM_GIC_COMMON(obj); KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s); - kgc->parent_reset(dev); + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj); + } if (kvm_arm_gic_can_save_restore(s)) { kvm_arm_gic_put(s); @@ -593,6 +595,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) static void kvm_arm_gic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass); KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass); @@ -600,7 +603,8 @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data) agcc->post_load = kvm_arm_gic_put; device_class_set_parent_realize(dc, kvm_arm_gic_realize, &kgc->parent_realize); - device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, kvm_arm_gic_reset_hold, NULL, + &kgc->parent_phases); } static const TypeInfo kvm_arm_gic_info = { From patchwork Thu Dec 15 12:50:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634190 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp130441pvb; Thu, 15 Dec 2022 04:57:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf6CFQPHlkKPLAMgbeWPrgSfF525c4vFsmxKdRAWPmNsPAr419QIqwOSzTj2qs3b0EyqYsQe X-Received: by 2002:a05:6214:1804:b0:4c7:2ab5:9268 with SMTP id o4-20020a056214180400b004c72ab59268mr39387877qvw.12.1671109075309; Thu, 15 Dec 2022 04:57:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671109075; cv=none; d=google.com; s=arc-20160816; b=ME+NYKV2VbdcMAgofh8q+USZmh3EEN/OYUPKnRAd1SZ84YY+TbYl9/5mtXCzQcW8Oa MqGIIS+/Wlh3A6ECTvl7WzJIdrYme8/lVkXbDu8hO9TK/jzZRpZAeM8Pwxkw7RIaTJDw /klHFotyZcOJD2+1NJzpAbwc73AkvveVNmmEyhZlIhnz/oo55hCl9IvMJdYxXLu51QCo BzqNtYFdtVEf6pOCYTHJa+MVRpioExMfniWWvbL5QzT5JhYefWnHDHWECMctC2yPsiK9 MNVQz4B+wzG1k27nN2BUe7pnxxCI3Z2mLPRARrTRh3P6r8diqYdBYKRWK7U0MTMBwfub eNOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3CXHTArsm4UuNjlPNq5RxTfGkxiav15C2fGC40drAkY=; b=JG8quPRFV0r9kTZ+ICQVwo7V802jgbaXdaIrg9O7ACuXrzL4pszvJFKMVOA2QasAMo cJfVOEQT6rzoKLzs9kVG1vFv3+ziGep5fLxfWTvNjzhELkqJiJiXpNrcBWuD4Kzf7jVQ CrT8+RozDsr1vsFRItf3Oy0XbkKvBTpV6WvQnOWXZt8G07pARfGgU7fqL4xy1Q6hDAf7 x67wX3XA9nA1JW8ObxHj5UsIi1ZSjFkUMymEXYKBTS/23NsQsGLaou7ey5pJQ/ugdjdc hZiY0uf4ApHIRyr0AH2pZoXgCRjD5EbU3nZ8CpH1g+HiS5Bbs47E9CiucUsTLv6h85gA 3ntw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MISN9LGB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset Date: Thu, 15 Dec 2022 12:50:01 +0000 Message-Id: <20221215125009.980128-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221109161444.3397405-6-peter.maydell@linaro.org --- hw/intc/arm_gicv3_common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 351843db4aa..642a8243ed4 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -450,9 +450,9 @@ static void arm_gicv3_finalize(Object *obj) g_free(s->redist_region_count); } -static void arm_gicv3_common_reset(DeviceState *dev) +static void arm_gicv3_common_reset_hold(Object *obj) { - GICv3State *s = ARM_GICV3_COMMON(dev); + GICv3State *s = ARM_GICV3_COMMON(obj); int i; for (i = 0; i < s->num_cpu; i++) { @@ -578,9 +578,10 @@ static Property arm_gicv3_common_properties[] = { static void arm_gicv3_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); - dc->reset = arm_gicv3_common_reset; + rc->phases.hold = arm_gicv3_common_reset_hold; dc->realize = arm_gicv3_common_realize; device_class_set_props(dc, arm_gicv3_common_properties); dc->vmsd = &vmstate_gicv3; From patchwork Thu Dec 15 12:50:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634185 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp128308pvb; Thu, 15 Dec 2022 04:53:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf7/CdrX3FLyBZ9NiFx3JtVq+jeieHohzNlxireCq79pjwxyA/tpgexIBEoPzdZL81wo/bdh X-Received: by 2002:a05:6102:c5:b0:3b3:3acc:46dd with SMTP id u5-20020a05610200c500b003b33acc46ddmr15492136vsp.8.1671108780094; Thu, 15 Dec 2022 04:53:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671108780; cv=none; d=google.com; s=arc-20160816; b=okvHuquU1pbihGeMJxGNiBfJ9aTbOxh6zlOoJSpWoiU7UDAZ3UtQtH6a2s4ybkJ1gD 4qtnvpE987UV0f2oQx7smWXDVChAZlv2V40ndyMJbuKNMng7R5SQPDziEeARMNsrNYW4 qagQGIthjwZCerjbK+JQzB2iLyBta8mbCJA2zBFzYLppwGaY80J4YeMbCt2RR3eRSgJt OX5Ra8vXuI0WDncFm7qbIvvuCthA1kfsmJMsfg9Q/CYp1GGiIHWCo/bFyiYMJMHD91KV uEytN7a80uwV6bu7GLYIICqV9n1i+95+qcA+ZMBv9ICOphOeLC6gm0olLJH22sICspsc 0mdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YeQ3kvahs94WhbLIqT4du5oVyKuAmCQx8YIV7LpenHE=; b=cu91YgjyOtCROceZdTzl/4iFKMn2E17eJKri2MXJHSa82lPAtbI1VpqbeGUAeHzD99 quefUekWATvTAMx8VHC67tucR+sA5PjhD3O86W7ZJpJHsEp/JJDrO8k4EDnljMjKFGym EmW/C3XYVlM4DoEdhnQTaGaALjNW4yxiJLe1UL1xSMCJteS8O42qMUAGavNANjeFLw2c YBLzo1HQeC3UG3jZEphDb4xHY0P/zQ8ItXDWQ6uKVB/T35Fdw43CUO5qXqDnOym7IDLG yq7OtBVqNKlCcR3tn71W9UF+YIwtMXtZUykvV0Q5DP8dP4LCokFn7Jm1T7wPKCuDfPCX jGcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tBVpKu3w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset Date: Thu, 15 Dec 2022 12:50:02 +0000 Message-Id: <20221215125009.980128-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221109161444.3397405-7-peter.maydell@linaro.org --- hw/intc/arm_gicv3_kvm.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 3ca643ecba4..72ad916d3db 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -77,7 +77,7 @@ DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class, struct KVMARMGICv3Class { ARMGICv3CommonClass parent_class; DeviceRealize parent_realize; - void (*parent_reset)(DeviceState *dev); + ResettablePhases parent_phases; }; static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) @@ -703,14 +703,16 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; } -static void kvm_arm_gicv3_reset(DeviceState *dev) +static void kvm_arm_gicv3_reset_hold(Object *obj) { - GICv3State *s = ARM_GICV3_COMMON(dev); + GICv3State *s = ARM_GICV3_COMMON(obj); KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); DPRINTF("Reset\n"); - kgc->parent_reset(dev); + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj); + } if (s->migration_blocker) { DPRINTF("Cannot put kernel gic state, no kernel interface\n"); @@ -890,6 +892,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); @@ -897,7 +900,8 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) agcc->post_load = kvm_arm_gicv3_put; device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, &kgc->parent_realize); - device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL, + &kgc->parent_phases); } static const TypeInfo kvm_arm_gicv3_info = { From patchwork Thu Dec 15 12:50:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634187 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp129528pvb; Thu, 15 Dec 2022 04:55:47 -0800 (PST) X-Google-Smtp-Source: AA0mqf5zLZ+iQU0YhaB3tyADQmLyhCtTbFo3lk/ZCwAfWKR3UEtZOCyt2prGFfG1lqtBWhd473IU X-Received: by 2002:a0c:c708:0:b0:4c7:38a1:d2e4 with SMTP id w8-20020a0cc708000000b004c738a1d2e4mr40122876qvi.42.1671108947297; Thu, 15 Dec 2022 04:55:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671108947; cv=none; d=google.com; s=arc-20160816; b=GOxn/t3rodTtG8DxzSPELk/SyPFtbQHOsl8FI6nrYGkvdw03iq3Xe95Mblsz3niVZ8 5KleYPyu3UnraUgCvqQkSyD72XTmJt4zCgPZUmIfJGfGBdX+TVRDUkbAjqgnGbesuS8q sHNW3SRqfQcMU54CbXF1F6a+NyNrbecqtNS4k0UEoucYZvviP/UAe4Iy0Fe598t4GA6Y hkKoK5Yj8Tj2a+7ndaQoXwVm5TWmlnh0y9pGDYD/tT1ytO4KzIHAKHi8lKKkujf4WLCL T9MRvAcBVlCTtjaYgF5hXtgAvH9lFduJ7pPwYqXwydiRpW1u6uJ2a8fCj8dn6l0Ni0An pjFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FQo9Y/PQ+gSmSXMPIhENR7hhWLKzE50YR9SZb6U2RxE=; b=DOB8cGSvQfdqeZ9R/+N15vwYPkZFSfPT/GwG/4goKz6gbRQtr/o4h1yyTO4BFAxU+r hr2AfRZU3f/Ktj5tgEuSkaXtgQ5c1icJE2FLnfQX9oeJXQa90TBjxeiT/bMHw1HliKBd XeTjJD8EjdZdreeL4UrFRsHnPTiZlF+Ra21gS82tQxwGOik2+GVS6KyudCgD3GkE/5Rc t4wRu1UpFYiGPHRibvLAYo8lT6V8onNb5kDjpyzo0AuXggICn4KwkKAJ0BSTUmrq2LKB B3WVG27nLxMuAaB7YhbWwaeEGEemYPG2wleFB+4VMZ3ilgxu6L6JLwK4dFQpkfn85W8q LMqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u7lqJVvX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset Date: Thu, 15 Dec 2022 12:50:03 +0000 Message-Id: <20221215125009.980128-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20221109161444.3397405-8-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its_common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 90b85f1e25c..d7532a7a899 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -122,9 +122,9 @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, msi_nonbroken = true; } -static void gicv3_its_common_reset(DeviceState *dev) +static void gicv3_its_common_reset_hold(Object *obj) { - GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); s->ctlr = 0; s->cbaser = 0; @@ -137,8 +137,9 @@ static void gicv3_its_common_reset(DeviceState *dev) static void gicv3_its_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - dc->reset = gicv3_its_common_reset; + rc->phases.hold = gicv3_its_common_reset_hold; dc->vmsd = &vmstate_its; } From patchwork Thu Dec 15 12:50:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634200 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp143311pvb; Thu, 15 Dec 2022 05:17:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf5Yk+zbd3xLvRym4oEAYgqcgznY2lFLLIOHjofTC5n3kW5nLhxlAYUm8diK6gbMY6svbQBJ X-Received: by 2002:a05:6214:a08:b0:4e1:bb55:1d84 with SMTP id dw8-20020a0562140a0800b004e1bb551d84mr17369777qvb.8.1671110270535; Thu, 15 Dec 2022 05:17:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671110270; cv=none; d=google.com; s=arc-20160816; b=ydZdY5ekkQOLqwSfzbZSjtI2Fvt0h97UXkNFwPJd476W//e99AByjrjGbdmAsBcfEh So3noSJJm33LFF9iDIEj+Tbuqmo9Z/sc/p4XV4SW37O0w/g6OyZeO9lnjEH33wi/QZ7o 04sCeHLlKYdL1sxCfQQ+q4Zqw2SmGbZRXuTTpE+KEKyKOHtfR7/bTmrwcQ2/d8LmvPnR Ns/uap+gZt6DiS0Wdjfew41wZtGtsxHxM7Svp/eYJ43ZHxXnsmFraCQm7iyWEGRoD64v lzpVHgjz0oUBJBW6FFyV+PpbNjgOrqYazv6nftNa0IFUOZtXSvNIpkHdEtk9+RWRjIzd B8Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NdfqtkLWyZ9Oq9V2fhNGIBisTuR7jxFRlD6CQdAIeIY=; b=btKNTkLLxUx/hIzB7Uh4isl/shYcgKiQESAJR0X88Yf8/xHb8lCalFYPJjGmD/dpvo vsQEXztRhd0IYlSzHyfHG8xxJzN4EuTew/vj2b7iRT/ATbxGfxIttQL/GgSbJu0G7jjH gD/QbqTwtwVE8OCbrE1YKXqvA9N8IkUWPanYMFibFrQEsXmP5BaovUjJapE5iciJU8Wo 2r7T0VIGPVdduZPxjIfIRp/PO3sJpBpRvzQBaIXlzFFf+9iDdICQ1CWl8ql/Xi9GW5dp w4ATN94DJHrcHFLY7Vpi5+cc9TyqnlG+FU3tuA+FWHv61aKfEbnfBff+mlvhup9TfIDO RlAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZIqHdKSo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/29] hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset Date: Thu, 15 Dec 2022 12:50:04 +0000 Message-Id: <20221215125009.980128-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221109161444.3397405-9-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 2ff21ed6bbe..57c79da5c55 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -27,7 +27,7 @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass, struct GICv3ITSClass { GICv3ITSCommonClass parent_class; - void (*parent_reset)(DeviceState *dev); + ResettablePhases parent_phases; }; /* @@ -1953,12 +1953,14 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) } } -static void gicv3_its_reset(DeviceState *dev) +static void gicv3_its_reset_hold(Object *obj) { - GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s); - c->parent_reset(dev); + if (c->parent_phases.hold) { + c->parent_phases.hold(obj); + } /* Quiescent bit reset to 1 */ s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1); @@ -2012,12 +2014,14 @@ static Property gicv3_its_props[] = { static void gicv3_its_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass); GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); dc->realize = gicv3_arm_its_realize; device_class_set_props(dc, gicv3_its_props); - device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset); + resettable_class_set_parent_phases(rc, NULL, gicv3_its_reset_hold, NULL, + &ic->parent_phases); icc->post_load = gicv3_its_post_load; } From patchwork Thu Dec 15 12:50:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634186 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp128355pvb; Thu, 15 Dec 2022 04:53:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf5SG9Ls1f876eEDtXDMpJfAjsAyQnQGKe5m2v88YNWtKMSCszk0ujhHYEHedjRj7Xj7J3OM X-Received: by 2002:a05:622a:8c7:b0:3a6:8ece:9f03 with SMTP id i7-20020a05622a08c700b003a68ece9f03mr41609253qte.42.1671108786600; Thu, 15 Dec 2022 04:53:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671108786; cv=none; d=google.com; s=arc-20160816; b=NxQIzvZYAHE4BJBPit78zq59iEkQvZIvq/e/TQiShc6sTRdpugeu2gUSPadwcnRpTT IN79PYHthpnsmpUlV8B8cL5ZE1vtHjui6sEWpw6E4YiaKcEKUuqbFN0wvy1WA7y91ulj kBXjVAThK+6ERhNcqMP8LPhq6Zj0HpXBPzdut23y7b1Aqkk0/L65ThGjnv/8Wevz1qXb ucvqCgAd/TtlfyzjN3hkODf8000LxkLK/0vmnwmfbKTH5z0lna6VDpsGZH1gYAKvJH7U 1fA8YFxW4T4VQ16Zdpmk6R0/s+ss0ipkjF+gyznrPg94WvMbaY2TZexmWmbPirPI7zd9 +zQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gbsPptG/9NycljswTXfQ1MSykEPoHxgef4kzxlHWXjY=; b=toMtq2iW9M11Opv+IXpQ0mtIoGPDTFWNsijEdhhc6084+PwUzcJgLO84tpoGltI4Qx xAlDoklUFhEOqNDqxSRO3ks0LShU/pHouR9cG8kpZqPcz1n86Wf8DlP23orHWvXodY/v MZ5Hs5ze+Ir7cxnDXWcAewTRQ2ScBroLPP0zYgam2yHiaVtMQsAMYOo3NelJJBVs4Vt+ adDwnvnjxXIU/am9BPRl+sc04apZM0bPj21Qmj2jBNSKd0IIg8J3IliNs11JE3b8MS2G KvRanE4mHc7E4XXyfBlvM4g6j7fvjhlrnTZ5CsVOWg4i46YgbbH3Aq6oHR5LM6me06oN nDQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Reaz40tN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset Date: Thu, 15 Dec 2022 12:50:05 +0000 Message-Id: <20221215125009.980128-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_KVM_ARM_ITS device to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221109161444.3397405-10-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its_kvm.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 529c7bd4946..7eda9fb86ea 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -37,7 +37,7 @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass, struct KVMARMITSClass { GICv3ITSCommonClass parent_class; - void (*parent_reset)(DeviceState *dev); + ResettablePhases parent_phases; }; @@ -197,13 +197,15 @@ static void kvm_arm_its_post_load(GICv3ITSState *s) GITS_CTLR, &s->ctlr, true, &error_abort); } -static void kvm_arm_its_reset(DeviceState *dev) +static void kvm_arm_its_reset_hold(Object *obj) { - GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s); int i; - c->parent_reset(dev); + if (c->parent_phases.hold) { + c->parent_phases.hold(obj); + } if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, KVM_DEV_ARM_ITS_CTRL_RESET)) { @@ -241,12 +243,14 @@ static Property kvm_arm_its_props[] = { static void kvm_arm_its_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass); dc->realize = kvm_arm_its_realize; device_class_set_props(dc, kvm_arm_its_props); - device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset); + resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL, + &ic->parent_phases); icc->send_msi = kvm_its_send_msi; icc->pre_save = kvm_arm_its_pre_save; icc->post_load = kvm_arm_its_post_load; From patchwork Thu Dec 15 12:50:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634204 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp153409pvb; Thu, 15 Dec 2022 05:35:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf4LU9JE2asz84Zu01HvOTLMVfaGLAt73/IlqSLXhNSa9EgLZRT+rUBSCpez89KvPOxjUL2s X-Received: by 2002:ac8:6798:0:b0:3a6:8b5a:7d02 with SMTP id b24-20020ac86798000000b003a68b5a7d02mr15902698qtp.30.1671111306724; Thu, 15 Dec 2022 05:35:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671111306; cv=none; d=google.com; s=arc-20160816; b=vKWvdg7BiNGfvguYUCf9L5I3/b7p8jWGPZwPAk4p1OiaGvas8JXtPxLPqUrCLl77DA W2/DDmZtgb3B1oAQezmR1K35g81k/EczOtbQBsa10A4pqmsWH3up4ojlueRYflnUX+Zv qcrFlUbOVV1Kx9CR5Q/xAqBa3LUoCT/CWOerz4tYsBZ/vXAKMDq7nsv+ozivYToD2eYb AFJBzPDozvlSAnCLQBR3S01mTS+yqH7PK4ixq+/BJXEwj5Y3tCsO1i6WZxv6zFidCe2y azbJWI8LNZ8vL5uLrCDQKDel0NeYy+GnV1MBIIHrmFTurOR2wamcWEz/wPwCx4AEWpzv TTPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=14LvpKp7/VTsP7I0u8An5rfr4jPKW0e5uC6loLOGGqM=; b=ZanPaHpS9ljV36SPtFLqFs7N9KNQyKCPQC++n8Nowbs4Hu2OCWH02jb6qhdgggtuTy XA1UmseasU1f8hM2w0bpDlggpNdM1wjuYvq7NUJWUgVWoHFiHWVtOg8AgyOu+DWBzLg9 V/UiZX1PuKyzZRBbjtIhSDHgHQvi2oepwwLjsnPZfs77ZL7qGHIquspQWFqRA5diw7b9 p3OwsrGCKg2AsZGyV86rexSTUVlEKNW9OWyGxo01m1s4uYor4DwXdeWFgsvlQKKoEv9X vekGrL36vAvN6Tejjgcw3yRxJk4MBb7+Z01z6UNqQ5o9PvP6wJnIQJljO7YUOukTK1v9 a4oQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i9Lc8fig; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/29] hw/arm/boot: set initrd with #address-cells type in fdt Date: Thu, 15 Dec 2022 12:50:06 +0000 Message-Id: <20221215125009.980128-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Schspa Shi We use 32bit value for linux,initrd-[start/end], when we have loader_start > 4GB, there will be a wrong initrd_start passed to the kernel, and the kernel will report the following warning. [ 0.000000] ------------[ cut here ]------------ [ 0.000000] initrd not fully accessible via the linear mapping -- please check your bootloader ... [ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355 arm64_memblock_init+0x158/0x244 [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 6.1.0-rc3-13250-g30a0b95b1335-dirty #28 [ 0.000000] Hardware name: Horizon Sigi Virtual development board (DT) [ 0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.000000] pc : arm64_memblock_init+0x158/0x244 [ 0.000000] lr : arm64_memblock_init+0x158/0x244 [ 0.000000] sp : ffff800009273df0 [ 0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000 [ 0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000 [ 0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000 [ 0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020 [ 0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261 [ 0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000 [ 0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000 [ 0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69 [ 0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88 [ 0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056 [ 0.000000] Call trace: [ 0.000000] arm64_memblock_init+0x158/0x244 [ 0.000000] setup_arch+0x164/0x1cc [ 0.000000] start_kernel+0x94/0x4ac [ 0.000000] __primary_switched+0xb4/0xbc [ 0.000000] ---[ end trace 0000000000000000 ]--- [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000001000000000-0x0000001007ffffff] This doesn't affect any machine types we currently support, because for all of our machine types the RAM starts well below the 4GB mark, but it does demonstrate that we're not currently writing the device-tree properties quite as intended. To fix it, we can change it to write these values to the dtb using a type width matching #address-cells. This is the intended size for these dtb properties, and is how u-boot, for instance, writes them, although in practice the Linux kernel will cope with them being any width as long as they're big enough to fit the value. Signed-off-by: Schspa Shi Message-id: 20221129160724.75667-1-schspa@gmail.com [PMM: tweaked commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/boot.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 15c2bf1867f..3d7d11f782f 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -656,15 +656,17 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, } if (binfo->initrd_size) { - rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", - binfo->initrd_start); + rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", + acells, binfo->initrd_start); if (rc < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); goto fail; } - rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", - binfo->initrd_start + binfo->initrd_size); + rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", + acells, + binfo->initrd_start + + binfo->initrd_size); if (rc < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); goto fail; From patchwork Thu Dec 15 12:50:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634201 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp152115pvb; Thu, 15 Dec 2022 05:33:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf4aP8WtvY4CBuPU3qAxHpMt2w/CW6Mpi9hSGxSpmaw+6a+lxmdEwxdB7T/4f+E6O/nwzJh2 X-Received: by 2002:a05:6808:f93:b0:355:1de8:cd46 with SMTP id o19-20020a0568080f9300b003551de8cd46mr16005007oiw.4.1671111182218; Thu, 15 Dec 2022 05:33:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671111182; cv=none; d=google.com; s=arc-20160816; b=HpzRmnfrBMrMOVjzbvg5vXQAjI0AJDzjpi30UvydWRKCG4gsawM6ifkON4NJwpe6ki hPdyRuF5S4cC42T3GGuTa3ho+1slAtUS9fCPjE1sZP0fR8xiv4v/BexO5woaRqUV1lAB oeXffFr6Cc7W1TSwehPmtyftegGtH8QSny3rqmdggwyjKLyf7Wd6j0+ppcMgQlcxFWQN Zp/l1vA9QWYYkPNF1Hui5xj9xM2zaWTdX/T+ua0pKvjhUOj1BvuEZoDBqJ5XibbEx5Io gnNM35xAYjWRPzqvru0XiHckz3VUk4smpeIFIZJllY33RIa9vlrHmalFYu+xxlnSsua4 tgGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RK1UPNBesBVFKDD7ufhJMalSW0NQP8K9iyGi9aR9dj4=; b=wQy8nS/ykl7BP/iYBFuzO1IidxTAU9T0cvxIgbqie8fPNhZKvonboR34PlWFDN/rSx XydFF6SoABsti+/Jd5XX6EGTsFpBBhgfju32RPN8spvzbjWBjwnZfg4f1IuymVy8nfkB nCjdGo+mTg6RKT/7cEW8K8IehkoK1g7EZA3jkDfGd/JeJTG4j4jF8aOQZVuSxxgWImhz IuANPYEXyczeWVtFfQ9VIP8gvxisOLGt3CfX3kKNf2jJhDmXpQRB0/0XkISGFggMWBf1 xcQmVduCh8T1mrSWkfxF7mFyHR5ebHxxaaHw22sQDu+taP4LgJrPAyLtCByq2+080T+n QDqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AswGKamN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/29] target/arm: align exposed ID registers with Linux Date: Thu, 15 Dec 2022 12:50:07 +0000 Message-Id: <20221215125009.980128-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zhuojia Shen In CPUID registers exposed to userspace, some registers were missing and some fields were not exposed. This patch aligns exposed ID registers and their fields with what the upstream kernel currently exposes. Specifically, the following new ID registers/fields are exposed to userspace: ID_AA64PFR1_EL1.BT: bits 3-0 ID_AA64PFR1_EL1.MTE: bits 11-8 ID_AA64PFR1_EL1.SME: bits 27-24 ID_AA64ZFR0_EL1.SVEver: bits 3-0 ID_AA64ZFR0_EL1.AES: bits 7-4 ID_AA64ZFR0_EL1.BitPerm: bits 19-16 ID_AA64ZFR0_EL1.BF16: bits 23-20 ID_AA64ZFR0_EL1.SHA3: bits 35-32 ID_AA64ZFR0_EL1.SM4: bits 43-40 ID_AA64ZFR0_EL1.I8MM: bits 47-44 ID_AA64ZFR0_EL1.F32MM: bits 55-52 ID_AA64ZFR0_EL1.F64MM: bits 59-56 ID_AA64SMFR0_EL1.F32F32: bit 32 ID_AA64SMFR0_EL1.B16F32: bit 34 ID_AA64SMFR0_EL1.F16F32: bit 35 ID_AA64SMFR0_EL1.I8I32: bits 39-36 ID_AA64SMFR0_EL1.F64F64: bit 48 ID_AA64SMFR0_EL1.I16I64: bits 55-52 ID_AA64SMFR0_EL1.FA64: bit 63 ID_AA64MMFR0_EL1.ECV: bits 63-60 ID_AA64MMFR1_EL1.AFP: bits 47-44 ID_AA64MMFR2_EL1.AT: bits 35-32 ID_AA64ISAR0_EL1.RNDR: bits 63-60 ID_AA64ISAR1_EL1.FRINTTS: bits 35-32 ID_AA64ISAR1_EL1.BF16: bits 47-44 ID_AA64ISAR1_EL1.DGH: bits 51-48 ID_AA64ISAR1_EL1.I8MM: bits 55-52 ID_AA64ISAR2_EL1.WFxT: bits 3-0 ID_AA64ISAR2_EL1.RPRES: bits 7-4 ID_AA64ISAR2_EL1.GPA3: bits 11-8 ID_AA64ISAR2_EL1.APA3: bits 15-12 The code is also refactored to use symbolic names for ID register fields for better readability and maintainability. Signed-off-by: Zhuojia Shen Message-id: DS7PR12MB6309BC9133877BCC6FC419FEAC0D9@DS7PR12MB6309.namprd12.prod.outlook.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 79 insertions(+), 17 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bac2ea62c44..6efc632b20d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7864,31 +7864,89 @@ void register_cp_regs_for_features(ARMCPU *cpu) #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { { .name = "ID_AA64PFR0_EL1", - .exported_bits = 0x000f000f00ff0000, - .fixed_bits = 0x0000000000000011 }, + .exported_bits = R_ID_AA64PFR0_FP_MASK | + R_ID_AA64PFR0_ADVSIMD_MASK | + R_ID_AA64PFR0_SVE_MASK | + R_ID_AA64PFR0_DIT_MASK, + .fixed_bits = (0x1 << R_ID_AA64PFR0_EL0_SHIFT) | + (0x1 << R_ID_AA64PFR0_EL1_SHIFT) }, { .name = "ID_AA64PFR1_EL1", - .exported_bits = 0x00000000000000f0 }, + .exported_bits = R_ID_AA64PFR1_BT_MASK | + R_ID_AA64PFR1_SSBS_MASK | + R_ID_AA64PFR1_MTE_MASK | + R_ID_AA64PFR1_SME_MASK }, { .name = "ID_AA64PFR*_EL1_RESERVED", - .is_glob = true }, - { .name = "ID_AA64ZFR0_EL1" }, + .is_glob = true }, + { .name = "ID_AA64ZFR0_EL1", + .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK | + R_ID_AA64ZFR0_AES_MASK | + R_ID_AA64ZFR0_BITPERM_MASK | + R_ID_AA64ZFR0_BFLOAT16_MASK | + R_ID_AA64ZFR0_SHA3_MASK | + R_ID_AA64ZFR0_SM4_MASK | + R_ID_AA64ZFR0_I8MM_MASK | + R_ID_AA64ZFR0_F32MM_MASK | + R_ID_AA64ZFR0_F64MM_MASK }, + { .name = "ID_AA64SMFR0_EL1", + .exported_bits = R_ID_AA64SMFR0_F32F32_MASK | + R_ID_AA64SMFR0_B16F32_MASK | + R_ID_AA64SMFR0_F16F32_MASK | + R_ID_AA64SMFR0_I8I32_MASK | + R_ID_AA64SMFR0_F64F64_MASK | + R_ID_AA64SMFR0_I16I64_MASK | + R_ID_AA64SMFR0_FA64_MASK }, { .name = "ID_AA64MMFR0_EL1", - .fixed_bits = 0x00000000ff000000 }, - { .name = "ID_AA64MMFR1_EL1" }, + .exported_bits = R_ID_AA64MMFR0_ECV_MASK, + .fixed_bits = (0xf << R_ID_AA64MMFR0_TGRAN64_SHIFT) | + (0xf << R_ID_AA64MMFR0_TGRAN4_SHIFT) }, + { .name = "ID_AA64MMFR1_EL1", + .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, + { .name = "ID_AA64MMFR2_EL1", + .exported_bits = R_ID_AA64MMFR2_AT_MASK }, { .name = "ID_AA64MMFR*_EL1_RESERVED", - .is_glob = true }, + .is_glob = true }, { .name = "ID_AA64DFR0_EL1", - .fixed_bits = 0x0000000000000006 }, - { .name = "ID_AA64DFR1_EL1" }, + .fixed_bits = (0x6 << R_ID_AA64DFR0_DEBUGVER_SHIFT) }, + { .name = "ID_AA64DFR1_EL1" }, { .name = "ID_AA64DFR*_EL1_RESERVED", - .is_glob = true }, + .is_glob = true }, { .name = "ID_AA64AFR*", - .is_glob = true }, + .is_glob = true }, { .name = "ID_AA64ISAR0_EL1", - .exported_bits = 0x00fffffff0fffff0 }, + .exported_bits = R_ID_AA64ISAR0_AES_MASK | + R_ID_AA64ISAR0_SHA1_MASK | + R_ID_AA64ISAR0_SHA2_MASK | + R_ID_AA64ISAR0_CRC32_MASK | + R_ID_AA64ISAR0_ATOMIC_MASK | + R_ID_AA64ISAR0_RDM_MASK | + R_ID_AA64ISAR0_SHA3_MASK | + R_ID_AA64ISAR0_SM3_MASK | + R_ID_AA64ISAR0_SM4_MASK | + R_ID_AA64ISAR0_DP_MASK | + R_ID_AA64ISAR0_FHM_MASK | + R_ID_AA64ISAR0_TS_MASK | + R_ID_AA64ISAR0_RNDR_MASK }, { .name = "ID_AA64ISAR1_EL1", - .exported_bits = 0x000000f0ffffffff }, + .exported_bits = R_ID_AA64ISAR1_DPB_MASK | + R_ID_AA64ISAR1_APA_MASK | + R_ID_AA64ISAR1_API_MASK | + R_ID_AA64ISAR1_JSCVT_MASK | + R_ID_AA64ISAR1_FCMA_MASK | + R_ID_AA64ISAR1_LRCPC_MASK | + R_ID_AA64ISAR1_GPA_MASK | + R_ID_AA64ISAR1_GPI_MASK | + R_ID_AA64ISAR1_FRINTTS_MASK | + R_ID_AA64ISAR1_SB_MASK | + R_ID_AA64ISAR1_BF16_MASK | + R_ID_AA64ISAR1_DGH_MASK | + R_ID_AA64ISAR1_I8MM_MASK }, + { .name = "ID_AA64ISAR2_EL1", + .exported_bits = R_ID_AA64ISAR2_WFXT_MASK | + R_ID_AA64ISAR2_RPRES_MASK | + R_ID_AA64ISAR2_GPA3_MASK | + R_ID_AA64ISAR2_APA3_MASK }, { .name = "ID_AA64ISAR*_EL1_RESERVED", - .is_glob = true }, + .is_glob = true }, }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); #endif @@ -8206,8 +8264,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { { .name = "MIDR_EL1", - .exported_bits = 0x00000000ffffffff }, - { .name = "REVIDR_EL1" }, + .exported_bits = R_MIDR_EL1_REVISION_MASK | + R_MIDR_EL1_PARTNUM_MASK | + R_MIDR_EL1_ARCHITECTURE_MASK | + R_MIDR_EL1_VARIANT_MASK | + R_MIDR_EL1_IMPLEMENTER_MASK }, + { .name = "REVIDR_EL1" }, }; modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); #endif From patchwork Thu Dec 15 12:50:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634195 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp130924pvb; Thu, 15 Dec 2022 04:59:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf4OQhU9yeq9qIIi32pB0lf34O3dViUuugCzj6JyHF6DEC9TTbwxDkstMp+Tc3IXcwPa+0ZA X-Received: by 2002:ad4:4181:0:b0:4bb:bfc6:13bf with SMTP id e1-20020ad44181000000b004bbbfc613bfmr35225087qvp.6.1671109142304; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss Date: Thu, 15 Dec 2022 12:50:08 +0000 Message-Id: <20221215125009.980128-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as poisoned in common code, so the files that include this header have to be added to specific_ss and recompiled for each, qemu-system-arm and qemu-system-aarch64. However, since the kvm headers are only optionally used in kvm-constants.h for some sanity checks, we can additionally check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro, so kvm-constants.h can also be used from "common" files (without the sanity checks - which should be OK since they are still done from other target-specific files instead). This way, and by adjusting some other include statements in the related files here and there, we can move some files from specific_ss into softmmu_ss, so that they only need to be compiled once during the build process. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221202154023.293614-1-thuth@redhat.com Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +- target/arm/kvm-consts.h | 8 ++++---- hw/misc/imx6_src.c | 2 +- hw/misc/iotkit-sysctl.c | 1 - hw/misc/meson.build | 11 +++++------ 5 files changed, 11 insertions(+), 13 deletions(-) diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h index b8ca9434afb..c3bf3c1583b 100644 --- a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h @@ -13,7 +13,7 @@ #include "hw/sysbus.h" #include "hw/register.h" -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index faacf96fdc7..09967ec5e64 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -14,16 +14,16 @@ #ifndef ARM_KVM_CONSTS_H #define ARM_KVM_CONSTS_H +#ifdef NEED_CPU_H #ifdef CONFIG_KVM #include #include - #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y) +#endif +#endif -#else - +#ifndef MISMATCH_CHECK #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0) - #endif #define CP_REG_SIZE_SHIFT 52 diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index 7b0e968804a..a9c64d06ebc 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -15,7 +15,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/module.h" -#include "arm-powerctl.h" +#include "target/arm/arm-powerctl.h" #include "hw/core/cpu.h" #ifndef DEBUG_IMX6_SRC diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 7147e2f84e6..e664215ee67 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -30,7 +30,6 @@ #include "hw/qdev-properties.h" #include "hw/arm/armsse-version.h" #include "target/arm/arm-powerctl.h" -#include "target/arm/cpu.h" REG32(SECDBGSTAT, 0x0) REG32(SECDBGSET, 0x4) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 95268eddc07..ed0598dc9eb 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -51,6 +51,7 @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx25_ccm.c', 'imx31_ccm.c', 'imx6_ccm.c', + 'imx6_src.c', 'imx6ul_ccm.c', 'imx7_ccm.c', 'imx7_gpr.c', @@ -84,8 +85,8 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( )) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) -specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) -specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( 'xlnx-versal-xramc.c', @@ -101,6 +102,7 @@ softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c')) softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c')) softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c')) softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c')) +softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c')) softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c')) softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c')) softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c')) @@ -126,15 +128,12 @@ softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c')) specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c')) -specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c')) -specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c')) - specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c')) specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c')) specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) -specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) +softmmu_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) # HPPA devices softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c')) From patchwork Thu Dec 15 12:50:09 2022 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator Date: Thu, 15 Dec 2022 12:50:09 +0000 Message-Id: <20221215125009.980128-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé When building with --disable-tcg on Darwin we get: target/arm/cpu.c:725:16: error: incomplete definition of type 'struct TCGCPUOps' cc->tcg_ops->do_interrupt(cs); ~~~~~~~~~~~^ Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt() handler to sysemu") limited this block to system emulation, but neglected to also limit it to TCG. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Fabiano Rosas Message-id: 20221209110823.59495-1-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 38d066c294d..0f55004d7e7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -528,7 +528,7 @@ static void arm_cpu_reset(DeviceState *dev) arm_rebuild_hflags(env); } -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el, @@ -725,7 +725,8 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) cc->tcg_ops->do_interrupt(cs); return true; } -#endif /* !CONFIG_USER_ONLY */ + +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ void arm_cpu_update_virq(ARMCPU *cpu) {