From patchwork Wed Dec 21 00:02:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6125C4167B for ; Wed, 21 Dec 2022 00:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234291AbiLUADD (ORCPT ); Tue, 20 Dec 2022 19:03:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234198AbiLUADA (ORCPT ); Tue, 20 Dec 2022 19:03:00 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B3DD1EEF0; Tue, 20 Dec 2022 16:02:59 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id co23so13445084wrb.4; Tue, 20 Dec 2022 16:02:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3bwX/rCMg/rUB7jj3GnuFZ4IZO0Zw8FzaOg+ESeEo9Q=; b=b1OTjaIpk+JKeoGTM68BP+sJYMuxNLAiS/4/0W8Y9v8rSqQAbRbNyqvc6CWeufDGSn 3tEnRaU1MS+V2jGeVf3mzQ49wr1wS6c6s5z3qL6hENcAUStc8C8nAeG05/BzwvDjxLGh 9CJ5sQOHvt5SLNgZMPx9/CCureWQmfnfigZEAOz4KC5Z2l19ijZeGYsgktJHiZCHwwBE D5qRUB0AxFIT3Jmg4HQluy+6uMMphzy5Erd2Lqgma/7NV6Js5hWHVVMIvNJR8eJF5UCA f4S9VE3nSClAid77RcqIRi+3IDzh80XQPXOCFG+VpPcQyliyKUJIYhT8tEZ5zxAL+ARF afxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3bwX/rCMg/rUB7jj3GnuFZ4IZO0Zw8FzaOg+ESeEo9Q=; b=Z5yUGP25S5nGRuVBi0XVGXuUpsZblLQIhWsB7HqLrU4P481xrG8fPh+k9zarcpwUQG bI0G2jbptFHRfRXH/jFelQqkMeL23eUCs1ISWWiqBVoVCUnN6HGMb/p4BcSNoLkHuLxC /srotJosl6g1i9Cj3wFWuo2pSl5EIwQG05dDLG7YSe3ddT+sVXLAXaM5iPvSaMUz3XLj u0WpuMs4m0N7YYEZl2tn3riprxa+2IN4i1nEpXwB5u0Kzsg3Bw/JzKZjmbyCf9BC4Epn q+i5kCkWqrn2WdRhGHUNuTjySfEip4zv3bpoUGyXQAjTfU9lHHkO1FclzK/PWWm+Vwsf GXkw== X-Gm-Message-State: ANoB5pm0bCnMp4+hA4N/Bet2dqGyFbfKbxSOLnp0uRA3n/VhW/jQRtFl ldYhxv7IymDQSP992FTmM9A= X-Google-Smtp-Source: AA0mqf5jTQZpZ8O5ZfcmE8bSLLb/W6heJH9CKxlFPiwUk8slEhmpBai+Py3peAbF+n4kSZdZQaKEmA== X-Received: by 2002:a05:6000:1e16:b0:242:8177:62a3 with SMTP id bj22-20020a0560001e1600b00242817762a3mr44829407wrb.21.1671580977687; Tue, 20 Dec 2022 16:02:57 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:02:57 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas, rzg2l-irqc: Document RZ/G2UL SoC Date: Wed, 21 Dec 2022 00:02:34 +0000 Message-Id: <20221221000242.340202-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC the only difference being it can support BUS_ERR_INT for which it has additional registers. Hence new generic compatible string "renesas,rzg2ul-irqc" is added for RZ/G2UL SoC. Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC interrupt-names property is added so that we can parse them based on names. While at it updated the example node to four spaces and added interrupt-names property. Signed-off-by: Lad Prabhakar --- v1- > v2 * Dropped RB tags * Added generic compatible string for rzg2ul * Added interrupt-names * Added checks for RZ/G2UL to make sure interrupts are 42 and interrupt-names * Updated example node with interrupt-names * Used 4 spaces for example node --- .../renesas,rzg2l-irqc.yaml | 240 +++++++++++++----- 1 file changed, 180 insertions(+), 60 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index 33b90e975e33..6a0cf57698ab 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -19,16 +19,19 @@ description: | - NMI edge select (NMI is not treated as NMI exception and supports fall edge and stand-up edge detection interrupts) -allOf: - - $ref: /schemas/interrupt-controller.yaml# - properties: compatible: - items: - - enum: - - renesas,r9a07g044-irqc # RZ/G2{L,LC} - - renesas,r9a07g054-irqc # RZ/V2L - - const: renesas,rzg2l-irqc + oneOf: + - items: + - enum: + - renesas,r9a07g044-irqc # RZ/G2{L,LC} + - renesas,r9a07g054-irqc # RZ/V2L + - const: renesas,rzg2l-irqc + + - items: + - enum: + - renesas,r9a07g043u-irqc # RZ/G2UL + - const: renesas,rzg2ul-irqc '#interrupt-cells': description: The first cell should contain external interrupt number (IRQ0-7) and the @@ -44,7 +47,96 @@ properties: maxItems: 1 interrupts: - maxItems: 41 + minItems: 41 + items: + - description: NMI interrupt + - description: IRQ0 interrupt + - description: IRQ1 interrupt + - description: IRQ2 interrupt + - description: IRQ3 interrupt + - description: IRQ4 interrupt + - description: IRQ5 interrupt + - description: IRQ6 interrupt + - description: IRQ7 interrupt + - description: GPIO interrupt, TINT0 + - description: GPIO interrupt, TINT1 + - description: GPIO interrupt, TINT2 + - description: GPIO interrupt, TINT3 + - description: GPIO interrupt, TINT4 + - description: GPIO interrupt, TINT5 + - description: GPIO interrupt, TINT6 + - description: GPIO interrupt, TINT7 + - description: GPIO interrupt, TINT8 + - description: GPIO interrupt, TINT9 + - description: GPIO interrupt, TINT10 + - description: GPIO interrupt, TINT11 + - description: GPIO interrupt, TINT12 + - description: GPIO interrupt, TINT13 + - description: GPIO interrupt, TINT14 + - description: GPIO interrupt, TINT15 + - description: GPIO interrupt, TINT16 + - description: GPIO interrupt, TINT17 + - description: GPIO interrupt, TINT18 + - description: GPIO interrupt, TINT19 + - description: GPIO interrupt, TINT20 + - description: GPIO interrupt, TINT21 + - description: GPIO interrupt, TINT22 + - description: GPIO interrupt, TINT23 + - description: GPIO interrupt, TINT24 + - description: GPIO interrupt, TINT25 + - description: GPIO interrupt, TINT26 + - description: GPIO interrupt, TINT27 + - description: GPIO interrupt, TINT28 + - description: GPIO interrupt, TINT29 + - description: GPIO interrupt, TINT30 + - description: GPIO interrupt, TINT31 + - description: Bus error interrupt + + interrupt-names: + minItems: 41 + items: + - const: nmi + - const: irq0 + - const: irq1 + - const: irq2 + - const: irq3 + - const: irq4 + - const: irq5 + - const: irq6 + - const: irq7 + - const: tint0 + - const: tint1 + - const: tint2 + - const: tint3 + - const: tint4 + - const: tint5 + - const: tint6 + - const: tint7 + - const: tint8 + - const: tint9 + - const: tint10 + - const: tint11 + - const: tint12 + - const: tint13 + - const: tint14 + - const: tint15 + - const: tint16 + - const: tint17 + - const: tint18 + - const: tint19 + - const: tint20 + - const: tint21 + - const: tint22 + - const: tint23 + - const: tint24 + - const: tint25 + - const: tint26 + - const: tint27 + - const: tint28 + - const: tint29 + - const: tint30 + - const: tint31 + - const: bus-err clocks: maxItems: 2 @@ -72,6 +164,23 @@ required: - power-domains - resets +allOf: + - $ref: /schemas/interrupt-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,rzg2ul-irqc + then: + properties: + interrupts: + minItems: 42 + interrupt-names: + minItems: 42 + required: + - interrupt-names + unevaluatedProperties: false examples: @@ -80,55 +189,66 @@ examples: #include irqc: interrupt-controller@110a0000 { - compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; - reg = <0x110a0000 0x10000>; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, - <&cpg CPG_MOD R9A07G044_IA55_PCLK>; - clock-names = "clk", "pclk"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_IA55_RESETN>; + compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; + reg = <0x110a0000 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31"; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; }; From patchwork Wed Dec 21 00:02:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72A1CC41535 for ; Wed, 21 Dec 2022 00:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234286AbiLUADC (ORCPT ); Tue, 20 Dec 2022 19:03:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234238AbiLUADB (ORCPT ); Tue, 20 Dec 2022 19:03:01 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 439A31C900; Tue, 20 Dec 2022 16:03:00 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id y16so13456597wrm.2; Tue, 20 Dec 2022 16:03:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M1g/qK+wITcmMNBzaKxGBCpgwiK6fj9WTq342zlrl9U=; b=Ua0sxbOPrzWv+NNn2uxUgOEQEzqxLhlVwhO637MFvOZWWBlgRQH/rREgDkhXAl9y9b mIcOn1TuRwM4UwuxFF6hyc2pBvlrEsdsTSeEz7WFUgWRBaDZRP7f9NBE0UBXe7u/xpOg 3yiL3Cixg8QeJJgPEEMoaB0waB8s2MkBHW/aXXQH74ETLk31uLHJdskA91I3MnD7gZxQ zQqK5n7r+OYz06PbohEtHTNIIrzEjLXiwclY6QMGB1yut1YxmI8YNwh2L/SRWc37dMIN IAoOYRG71JYE/FuPib/NijuoDl1M6s0oxEVq8exQBmXAyQZJrmkvvJ4LvUj1KkllsT21 1+PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M1g/qK+wITcmMNBzaKxGBCpgwiK6fj9WTq342zlrl9U=; b=KH2jO9IGmflZOWMn7UXigkX73vkTVRP2QJqzx1y4wSWBrm/B7NXRkldmYRG9yin9v3 FuxJxgdAS80ym3AtsagFz97hQFw6oapINr4MIcoixDPM42Plk4JunvQsgsTp1ri0woYL EuPTYkS8Ru0WXyauurjddQS8D7663wpXm4g8PqtxHcpc/o0/rctXt0URP+UacjHWvCYN nieiTFbxMphwVAbSdcso/i5/eS4vagVpx0qii0g44cOgf8fEldqkMU2Oh+XqVs/qFSW1 RftlgQ0hXfnEbtw4nHrqjOJUh1yPYBmmuSWei9/uZFDFjbPZhO2qe7bh8LtzUp8XGGts T/tA== X-Gm-Message-State: ANoB5pmBfDsSJEnjnC/F9c1y1CsZAzOgtA1IDoImR7pws+GC5WteTYr7 CCufYbVpkZwfFfA5X5VvZKc= X-Google-Smtp-Source: AA0mqf49swmiA1NfsE48IIYpD/gm+EK08KkuDqNydVay+PXkoEPAOluFubQk/lNISxWQzkd4bPiYsw== X-Received: by 2002:adf:f3cd:0:b0:241:f95f:eef8 with SMTP id g13-20020adff3cd000000b00241f95feef8mr27395099wrp.11.1671580978710; Tue, 20 Dec 2022 16:02:58 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:02:58 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 2/9] dt-bindings: interrupt-controller: irqc-rzg2l: Drop RZG2L_NMI macro Date: Wed, 21 Dec 2022 00:02:35 +0000 Message-Id: <20221221000242.340202-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar NMI interrupt is not an external interrupt as compared to IRQ0-7 and TINT0-31 on RZ/G2L SoC, so there is no need for RZG2L_NMI macro. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski --- v1 -> v2 * New patch --- include/dt-bindings/interrupt-controller/irqc-rzg2l.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h index 34ce778885a1..dd2da795208d 100644 --- a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -9,9 +9,6 @@ #ifndef __DT_BINDINGS_IRQC_RZG2L_H #define __DT_BINDINGS_IRQC_RZG2L_H -/* NMI maps to SPI0 */ -#define RZG2L_NMI 0 - /* IRQ0-7 map to SPI1-8 */ #define RZG2L_IRQ0 1 #define RZG2L_IRQ1 2 From patchwork Wed Dec 21 00:02:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A00EC4332F for ; Wed, 21 Dec 2022 00:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234295AbiLUADD (ORCPT ); Tue, 20 Dec 2022 19:03:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234279AbiLUADC (ORCPT ); Tue, 20 Dec 2022 19:03:02 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63E531EEFD; Tue, 20 Dec 2022 16:03:01 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id y16so13456624wrm.2; Tue, 20 Dec 2022 16:03:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=za2L0CKEB7yf2ik8Iuj/BZryf3LCWxSxvd2XuC3OlRk=; b=X/t0b3H3+hjQwrCd7kME8ld6CwGzkx1Sjj3O8mKERT01ouSPCaqiklUT3UTBUCKSIh k8wZX0/dK4zJmDFAsw/LGHkn3BdI037YIjGcDUK6auDDqVPa6Z+Fjy2UyhVGpkvVmgAa rYeogGch+W0v2/YhTtRU5SLw55o8De8tcZUokc8bWTooFiVDsdXSBHfpLUwhPq9VpdNB rdYC0vRcXWsKsHMry5T5tis1+J7IrLaQUQEcvcvQme9stNtSFZaLbRCsRKxdSXJYg+wa LgTjrWdVzL3jpo5toTCT0Jl3v+FEkzuPs/Oyk5daqj9zgbwKqxBl6bENjndXS9kAskQF 8Ajw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=za2L0CKEB7yf2ik8Iuj/BZryf3LCWxSxvd2XuC3OlRk=; b=dAr+guZ5RhInNn3FOrf9laFPw1QcNorI2k3eCAQxWhIYxXvlM9FxdH977ak1pv85OD u9TZhLMuhakTmXUplWp0928MyV1CcomF+6hs06X3g77TaLCVJlNBB0oN+JrraTrPoaNw 5nMUSYqwo5XDySZAQDRzAea6OrL+fLMPIcGtOZdCaCwFNcQTqdpbu7DWBnCEfBIU7ob1 6ZE5scxFE1JSJhLKATfcBnQUlXi6xIKacJBf7kuy4Zw4xdW/Nf8bSiry4LcbHX2ePhTv 1f0hZKJoMZT4tbk28N5o1tWK5RCwlD/vgI1uID/eDdKw4KUTahuRIc6DKhuvH9w1U48O ksrw== X-Gm-Message-State: AFqh2kpj+RfdraKLiqjVjxy75umz08K1BmtcMAgzkZuvSkFmRdKhioOO 1lb8wAAAS8nZT18MEwuI6D4= X-Google-Smtp-Source: AMrXdXu6jEh2mcbeZvR7xwuBfasOURRH24VBC4lgSlkhlPru3BjcxJmCfN4Lda+xirYzlxyl5+iX3w== X-Received: by 2002:a05:6000:819:b0:242:192c:9b34 with SMTP id bt25-20020a056000081900b00242192c9b34mr2762999wrb.59.1671580979914; Tue, 20 Dec 2022 16:02:59 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.02.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:02:59 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 3/9] irqchip: irq-renesas-rzg2l: Skip mapping NMI interrupt as part of hierarchy domain Date: Wed, 21 Dec 2022 00:02:36 +0000 Message-Id: <20221221000242.340202-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar NMI interrupt is not an external interrupt as compared to the IRQ0-7 and TINT0-31, this means we need to install the irq handler for NMI in the IRQC driver and not include it as part of IRQ domain. This patch skips mapping NMI interrupt as part of the IRQ domain hierarchy. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Lad Prabhakar --- v1 -> v2 * New patch --- drivers/irqchip/irq-renesas-rzg2l.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 25fd8ee66565..7918fe201218 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -23,7 +23,8 @@ #define IRQC_IRQ_COUNT 8 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) + /* IRQ0-7 + TINT0-31 */ +#define IRQC_NUM_HIERARCHY_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT - 1) #define ISCR 0x10 #define IITSR 0x14 @@ -58,7 +59,8 @@ struct rzg2l_irqc_priv { void __iomem *base; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + /* IRQ0-7 + TINT0-31 will be part of hierarchy domain */ + struct irq_fwspec fwspec[IRQC_NUM_HIERARCHY_IRQ]; raw_spinlock_t lock; }; @@ -99,7 +101,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) rzg2l_irq_eoi(d); - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) rzg2l_tint_eoi(d); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); @@ -109,7 +111,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) { unsigned int hw_irq = irqd_to_hwirq(d); - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); @@ -129,7 +131,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) { unsigned int hw_irq = irqd_to_hwirq(d); - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned long tint = (uintptr_t)d->chip_data; u32 offset = hw_irq - IRQC_TINT_START; @@ -228,7 +230,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) ret = rzg2l_irq_set_type(d, type); - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) ret = rzg2l_tint_set_edge(d, type); if (ret) return ret; @@ -280,7 +282,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, return -EINVAL; } - if (hwirq > (IRQC_NUM_IRQ - 1)) + if (!hwirq || hwirq > IRQC_NUM_HIERARCHY_IRQ) return -EINVAL; ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, @@ -288,7 +290,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, if (ret) return ret; - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq - 1]); } static const struct irq_domain_ops rzg2l_irqc_domain_ops = { @@ -304,12 +306,12 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, unsigned int i; int ret; - for (i = 0; i < IRQC_NUM_IRQ; i++) { + for (i = 1; i <= IRQC_NUM_HIERARCHY_IRQ; i++) { ret = of_irq_parse_one(np, i, &map); if (ret) return ret; of_phandle_args_to_fwspec(np, map.args, map.args_count, - &priv->fwspec[i]); + &priv->fwspec[i - 1]); } return 0; @@ -366,7 +368,7 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) raw_spin_lock_init(&priv->lock); - irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, + irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_HIERARCHY_IRQ, node, &rzg2l_irqc_domain_ops, priv); if (!irq_domain) { From patchwork Wed Dec 21 00:02:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85B69C3DA7C for ; Wed, 21 Dec 2022 00:03:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234316AbiLUADE (ORCPT ); Tue, 20 Dec 2022 19:03:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234285AbiLUADC (ORCPT ); Tue, 20 Dec 2022 19:03:02 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77F8C1EEF0; Tue, 20 Dec 2022 16:03:01 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id co23so13445167wrb.4; Tue, 20 Dec 2022 16:03:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DCfRvbbOD2D27Yei+Ee5t2Ldffe1NcizZHQtkKVsvFA=; b=Z3QXuzSAH+aXUB4psYxh2X7MVJ8ucTq0yUEvm+70ttsTLOwSTR33wPfhZbHg7VPZf4 pyzVXUhramQTJU/XQVsMy6t3Up65ccrKDiBuIO8jP5WqVkL5q6TiVUNnWFktuLXVVQvS qEPosa3PxAX/DuuMHV6Qd4944WILphlqOlxcNMlG6ZKNzfoB2M4g26l67ndJso3EQOcD lGq53WgcxYjnYArej4gn0rVxfsURKA7QNODVDCdiRu7bPMKQfgEFFLJT81bPRSW81sES TSfBDdJKzMAu4wiry7o6FiFOTaVdZ9ORb2khquAuJNd5tgAbz1N9QW/HYxUz/nNFf9tP aMxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DCfRvbbOD2D27Yei+Ee5t2Ldffe1NcizZHQtkKVsvFA=; b=gc2V8T+7iDndkdnybFHjctAK2gw3JbmcwE1j1ipHK8letqkO4ecdcNhu/gLOwEk3Yo 2KLw9EzMvk/AgHhgKPmR7a6Do6jMn/riUy6bBK8+Rd3SEvUVprq3fbXdOlNhEuKp2gyN N8VXZ5RL94ie0fz9aq4m5OgW6xqweQNxszcThe+7rJvD2iGApf1vT2rl8CeOjID0qYq+ FrJUIa64WgN6BKAMQ9yygNPUmvjRHUjc36LwLHKhYTvkfRxxA4ufT01t8MiAvzO4skOX R6Il/gALSLbZTBgyMvzXj4HyZDwxH4ySQBMhSVY2bu39SUlT6fYi5nYg6xegFkQ1YibM y0hw== X-Gm-Message-State: AFqh2kqeJyQtedG0Y59ppKcXSTYn4vueuNoVlBri2lWgYHyteqEleVQz GoBPDbIaREsSaufN6Vf6GyaB9qNFfTSSIcpo X-Google-Smtp-Source: AMrXdXu0DEjfbtMPh3b8k1OlUhuL/EcStKWzHWPjgufRmXBCbeHIufjD2XkSfTDOP0j24jASYeRjGQ== X-Received: by 2002:a5d:574a:0:b0:26a:5040:78f6 with SMTP id q10-20020a5d574a000000b0026a504078f6mr400675wrw.46.1671580980975; Tue, 20 Dec 2022 16:03:00 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.03.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:03:00 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 4/9] irqchip: irq-renesas-rzg2l: Add support for RZ/G2UL SoC Date: Wed, 21 Dec 2022 00:02:37 +0000 Message-Id: <20221221000242.340202-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar The IRQC block on RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC the only difference being it can support BUS_ERR_INT for which it has additional registers. This patch adds a new entry for "renesas,rzg2ul-irqc" compatible string and now that we have interrupt-names property the driver code parses the interrupts based on names and for backward compatibility we fallback to parse interrupts based on index. For now we will be using rzg2l_irqc_init() as a callback for RZ/G2UL SoC too and in future when the interrupt handler will be registered for BUS_ERR_INT we will have to implement a new callback. Signed-off-by: Lad Prabhakar --- v1 -> v2 * New patch --- drivers/irqchip/irq-renesas-rzg2l.c | 80 ++++++++++++++++++++++++++--- 1 file changed, 74 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 7918fe201218..5bdf0106ef51 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -299,19 +299,86 @@ static const struct irq_domain_ops rzg2l_irqc_domain_ops = { .translate = irq_domain_translate_twocell, }; -static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, - struct device_node *np) +static int rzg2l_irqc_parse_interrupt_to_fwspec(struct rzg2l_irqc_priv *priv, + struct device_node *np, + unsigned int index, + unsigned int fwspec_index) { struct of_phandle_args map; + int ret; + + ret = of_irq_parse_one(np, index, &map); + if (ret) + return ret; + + of_phandle_args_to_fwspec(np, map.args, map.args_count, + &priv->fwspec[fwspec_index]); + + return 0; +} + +static int rzg2l_irqc_parse_interrupt_by_name_to_fwspec(struct rzg2l_irqc_priv *priv, + struct device_node *np, + char *irq_name, + unsigned int fwspec_index) +{ + int index; + + index = of_property_match_string(np, "interrupt-names", irq_name); + if (index < 0) + return index; + + return rzg2l_irqc_parse_interrupt_to_fwspec(priv, np, index, fwspec_index); +} + +/* Parse hierarchy domain interrupts ie only IRQ0-7 and TINT0-31 */ +static int rzg2l_irqc_parse_hierarchy_interrupts(struct rzg2l_irqc_priv *priv, + struct device_node *np) +{ + struct property *pp; unsigned int i; int ret; + /* + * first check if interrupt-names property exists if so parse them by name + * or else parse them by index for backward compatibility. + */ + pp = of_find_property(np, "interrupt-names", NULL); + if (pp) { + char *irq_name; + + /* parse IRQ0-7 */ + for (i = 0; i < IRQC_IRQ_COUNT; i++) { + irq_name = kasprintf(GFP_KERNEL, "irq%d", i); + if (!irq_name) + return -ENOMEM; + + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, i); + kfree(irq_name); + if (ret) + return ret; + } + + /* parse TINT0-31 */ + for (i = 0; i < IRQC_TINT_COUNT; i++) { + irq_name = kasprintf(GFP_KERNEL, "tint%d", i); + if (!irq_name) + return -ENOMEM; + + ret = rzg2l_irqc_parse_interrupt_by_name_to_fwspec(priv, np, irq_name, + i + IRQC_IRQ_COUNT); + kfree(irq_name); + if (ret) + return ret; + } + + return 0; + } + for (i = 1; i <= IRQC_NUM_HIERARCHY_IRQ; i++) { - ret = of_irq_parse_one(np, i, &map); + ret = rzg2l_irqc_parse_interrupt_to_fwspec(priv, np, i, i - 1); if (ret) return ret; - of_phandle_args_to_fwspec(np, map.args, map.args_count, - &priv->fwspec[i - 1]); } return 0; @@ -343,7 +410,7 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - ret = rzg2l_irqc_parse_interrupts(priv, node); + ret = rzg2l_irqc_parse_hierarchy_interrupts(priv, node); if (ret) { dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); return ret; @@ -389,6 +456,7 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) +IRQCHIP_MATCH("renesas,rzg2ul-irqc", rzg2l_irqc_init) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR("Lad Prabhakar "); MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); From patchwork Wed Dec 21 00:02:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91FB2C41535 for ; Wed, 21 Dec 2022 00:03:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234096AbiLUADG (ORCPT ); Tue, 20 Dec 2022 19:03:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234320AbiLUADF (ORCPT ); Tue, 20 Dec 2022 19:03:05 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE9361EEFD; Tue, 20 Dec 2022 16:03:03 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id a17so12270011wrt.11; Tue, 20 Dec 2022 16:03:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wjd5YDPhn942L8jKBVO5rptp/aSFWfLH0S6vcuBxa1o=; b=MAWwVA5ZqYcEQHuO7lddEIMZ+eZa9SJUgRafWpUin47IlTQ0uODzZ1Uu3gSM7R7c7t 8S3NsYttU4t4D/WrqPQm97OdSxK8OjlJLsDeK8D/K0maIzhWLTCxuYaqs+NoHTwypsyb 6+DA9X/XqjbM4MLvb5nyT05mDY7oa/b//+g//bI1F4bwMW0nHMNP5I+qFP6RBEMfup73 OddWQ6sJeBQ0uL4gdAMfJuSrJpScwIrAni2X30MnqXnw8nQ7ab3S2ZX/bqzzdJtE2jLv pvaNpwnwq8e39Nt1mck77ytkGOoWwI4nJYQ9TknSsRaHhOsxOBcov75CM6B/4YbVXYpY PXfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wjd5YDPhn942L8jKBVO5rptp/aSFWfLH0S6vcuBxa1o=; b=3iTuy7NpQ1JKU5VzSWg9gZdDpi//w56bn/6B4coUQe1X8LQpFfdcazITRrAhnhaa6m u0s9340W3RZ688RmG6cwvHiupJ6j2XwhBXsXsEOTQPFcbmDyQtDaG2rnqz0uc4tA32Nd vKgxOQjEoEsa4ckMZz4LbdbGZCKrzBUWkN7BScvwx+3b2X5qF2aJe/ZIOoUADpbTBTgi BPaAMUoBkThhd5J+YRVcaaBfpH7uwP3Q23CbtJRMjvQntc5HS3SCif0Z7SLOpp59C22T lmCr3D5XUea4h6N4yZRtPpDnqWOGx9yirU6lPv0fqrhsbqLQAaP/tp4spq+l28oyBcXX 2rgw== X-Gm-Message-State: AFqh2kpeS5sWvzMD9ollWWhrKbxRSBOkMrvKeQtwers7Qvq0C5OHo96i VgSjM2JYCTWW9unGsRJ6yMo= X-Google-Smtp-Source: AMrXdXuiLD+CQEuTZAWD6gq9auAmNhVIMsylO30/cwcrDlnzgKed5ffnq+Jzvn0QZoXkOzQQeYduSA== X-Received: by 2002:adf:e281:0:b0:26a:cede:b651 with SMTP id v1-20020adfe281000000b0026acedeb651mr122759wri.36.1671580982064; Tue, 20 Dec 2022 16:03:02 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.03.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:03:01 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 5/9] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Date: Wed, 21 Dec 2022 00:02:38 +0000 Message-Id: <20221221000242.340202-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also the pin configs are completely different. This patch makes sure we use the appropriate pin configs for each SoC (which is passed as part of the OF data) while configuring the GPIO pin as interrupts instead of using rzg2l_gpio_configs[] for all the SoCs. Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1 -> v2 * Fixed comments pointed by Geert for variable naming * Added RB tag --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4e79b2961232..03e9462f39b1 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -127,6 +127,7 @@ struct rzg2l_dedicated_configs { struct rzg2l_pinctrl_data { const char * const *port_pins; const u32 *port_pin_configs; + unsigned int n_ports; struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; @@ -1121,7 +1122,7 @@ static struct { } }; -static int rzg2l_gpio_get_gpioint(unsigned int virq) +static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) { unsigned int gpioint; unsigned int i; @@ -1130,13 +1131,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq) port = virq / 8; bit = virq % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); + gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); return gpioint; } @@ -1236,7 +1237,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); if (gpioint < 0) return gpioint; @@ -1310,8 +1311,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, port = offset / 8; bit = offset % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= pctrl->data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) clear_bit(offset, valid_mask); } } @@ -1516,6 +1517,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, + .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), @@ -1524,6 +1526,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = rzg2l_gpio_configs, + .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + From patchwork Wed Dec 21 00:02:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 019BDC3DA7C for ; Wed, 21 Dec 2022 00:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234342AbiLUADR (ORCPT ); Tue, 20 Dec 2022 19:03:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234326AbiLUADF (ORCPT ); Tue, 20 Dec 2022 19:03:05 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0B8E201A3; Tue, 20 Dec 2022 16:03:04 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id f18so13444145wrj.5; Tue, 20 Dec 2022 16:03:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+DAEA+OzMJ+y7qc8/f9pAlMJNduPlcJJtkAkWJtqKPk=; b=DfbUR+JAV41BAWSaslMgK9Rn22HISYIj37yvBSG9dbwFjAUME/dz76yfsip7P4kUXh 3uozgCxFJ1SbUKVFXez9pd0Gn+/ZJo8MZ+pCAA2vg55MYAqqwNHg9I+GP0WZKoh4MWvY w2g4maCwg0g3GGGvXml4rf1WGRoaWA38Js2tFax+rGJAC/UK2P2NEOwSpje2qTarYdWA tQ4aTr5MUYbvsfm1T2Z6b0DPrjL90Gc76yKfgn8yk/H9j2fgfAr5Q09ONOuLDui1TyHN Wdc+Euh8rXLYzwGg1/OviHP425iut421IetER6yjB890xt4HrSHzWDUw+vNikXpcUYSX 29GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+DAEA+OzMJ+y7qc8/f9pAlMJNduPlcJJtkAkWJtqKPk=; b=MKbjWzek9ZlXG4UbfVC9HZRy3OTXvgI00/PDS9okw+MKPBwl4eswktRJAr0X8KI6VU eVdoEb+NyUoiekDVdSISqWOiO1rpaRxtY8D+PiEGOn9O/cJj/qYIl/l4PF2RuIszUdEz iCaxkj4wxb8VKiOjNc2TwF3yYjzH162qq+C8ZATUkmqRoD5YjPM4hA5oX/tWleD5peD0 Aqd5h+KLS26Ixu5unmr7f45itYESgUv4K1sTjt78+c94IbCZ+5XTs1q4ipSMxrbRrp3l tTMBeh1KuvScOQB8lIBS6ZVDfI3lK92zWKQastYGTft8J0aE3cJLLV54LUeVKodFEHRT lL/g== X-Gm-Message-State: ANoB5plBOXfGEnXoZJtIkOG9Jtb26Gza/GeNVEhjgwO3H6H/Z6RqOuUw 7EVYHur1EPpdQtJoY/C2/H0= X-Google-Smtp-Source: AA0mqf6nxxoU7wNuTvAZZ4NmZQscwDQzJEpk+yZ0Zxo++wi+rRc/4uRs5QVSLLPeZ8OT8C75I9uP+A== X-Received: by 2002:a05:6000:1e1d:b0:242:15d5:2c0b with SMTP id bj29-20020a0560001e1d00b0024215d52c0bmr29936252wrb.22.1671580983240; Tue, 20 Dec 2022 16:03:03 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.03.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:03:02 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 6/9] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Date: Wed, 21 Dec 2022 00:02:39 +0000 Message-Id: <20221221000242.340202-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each supported SoC. While at it, for readability set n_port_pins based on the GPIO pin configs and not on GPIO names for r9a07g044_data as done for r9a07g043_data. Suggested-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- v1 -> v2 * New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 03e9462f39b1..8036485f2e92 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1465,6 +1465,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) struct rzg2l_pinctrl *pctrl; int ret; + BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + + BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -1528,7 +1534,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pin_configs = rzg2l_gpio_configs, .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, - .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), + .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), }; From patchwork Wed Dec 21 00:02:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08ED3C4167B for ; Wed, 21 Dec 2022 00:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234338AbiLUADQ (ORCPT ); Tue, 20 Dec 2022 19:03:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234325AbiLUADF (ORCPT ); Tue, 20 Dec 2022 19:03:05 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3B42201A4; Tue, 20 Dec 2022 16:03:04 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id h16so13390490wrz.12; Tue, 20 Dec 2022 16:03:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LNyPY43zgGr1A85XTmiE4/fhVElkNurZ7fW0yqYaRFM=; b=lRmKVfykfWVj0cGXPi8E0tsM5KwgJb18SJe3Z/fYrdQdAQKB+IUvF8OsAWoXgCO2Tt GpZcYc7lQpSLJHIk/XmHTIYGTQoBUeWZcrY3mJdbrqA8ytC3A4llv4o1znbwfQh/oWC2 P46mDecLRqf5R+Auqkv+lFZLzs9hVuZYQx/oQFe8Zn1ftOm2WJvpK2/NkJ4rfOXTSoJ6 FoGANO6oIhCkyEDFw4p/6c9cj8xf8a8DVPMUnM20khuXw2jWnIv5s8PYmSgtVuG2gtuM 10UlhVT7+NJvvLJPnVk+HVrPMH4UjW0Of1E8FTor3BgHsDJ1TevJb42LtiCeZdQIjghS 07VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LNyPY43zgGr1A85XTmiE4/fhVElkNurZ7fW0yqYaRFM=; b=YQBEHN/a/ntKVpxFMl6Ekd9NPb6y8QAKt8UghGj2HfJoeVDOsTAunZy045AC1ZZYLi x//Swso/a9dz3fCMhZM3PbjfAbnGu6fS87QwZdabuNqFBz3EqCk8YX8k/h9bVcXAcDAt ECvlz8zhW5eCZpZ0xgCxpdunBxu4qzd60AcYfp1Tl2+ONuLs56I0ziCmHVOqm2Q/ye33 HCFvuR1RlGnABworeI0pRPWjmbBHCYaK2++L1ltG1QIBXSDYDCCtZn1cFRaibTFvjFns LWnP+Y0pNVWi1rxQzZQA9Go6C/JJd6BNoslwj6JwXrcOzaboOHzJ9ZxmNb3hXZaZ/q6d A1sw== X-Gm-Message-State: ANoB5pmj+ILbMO2Ej92kCFijQ+6ln1EZo1nC4OuwtWuJK7XMrOayXKFa lbsEFZu08G8vx4Fyni9iGsY= X-Google-Smtp-Source: AA0mqf7L/nkpPAcY7TsjGvrq1WYphSjNvzyqhoHR6bVuyaz0Zr7uEW6XOLz78MltwmRi6kbMO4CCEQ== X-Received: by 2002:a05:6000:799:b0:24e:aad5:c48b with SMTP id bu25-20020a056000079900b0024eaad5c48bmr23947136wrb.15.1671580984216; Tue, 20 Dec 2022 16:03:04 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:03:03 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 7/9] arm64: dts: renesas: r9a07g043u: Add IRQC node Date: Wed, 21 Dec 2022 00:02:40 +0000 Message-Id: <20221221000242.340202-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Lad Prabhakar --- v1 -> v2 * Moved irqc node completely to rzg2ul SoC DTSI * Added interrupt-names --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 68 +++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 6af5f3bca2d1..c6e25ad98011 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -52,6 +52,74 @@ timer { &soc { interrupt-parent = <&gic>; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g043u-irqc", + "renesas,rzg2ul-irqc"; + reg = <0 0x110a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, + <&cpg CPG_MOD R9A07G043_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_IA55_RESETN>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed Dec 21 00:02:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D96C4167B for ; Wed, 21 Dec 2022 00:03:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234362AbiLUADa (ORCPT ); Tue, 20 Dec 2022 19:03:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234330AbiLUADH (ORCPT ); Tue, 20 Dec 2022 19:03:07 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2DAC1EEFD; Tue, 20 Dec 2022 16:03:06 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id h10so13433043wrx.3; Tue, 20 Dec 2022 16:03:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=awbhKbYqdDZxY2mihbijUFx+EfQkURzCbhYMpJ68hQ8=; b=KlMCQpPqtvHWQgSJQdmGVT+7pE/SitvLNZndFHphNMHWJK/zZqgKuge4RbTkb1o1ZH 0LW5nSYurUxPhpqvSdV1gpOocSYFLfCY/V3oLIbpF3sTGP6+djqDaauRLnboDj8hgOy/ UXm65S7PfCFTOviHgk5l+kwpzCrk5LUUFXSo/jc+z3E+JLk99aal/DY9v42jY6HV99WW fIKy1CJ0wqqow90Dt5q4AD/Pyfo5OC9U79NGKbYnIxKwW4YBALVcWN2gXx6x9uSOKso1 WT3krOHiuOr0WtYVOJiLL6ohKhCyOs4ohNZsPxGhRWcfGsELMwXdrsPLQzHdRUuYLcaF 2gJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=awbhKbYqdDZxY2mihbijUFx+EfQkURzCbhYMpJ68hQ8=; b=EBCSCqASIY2k2WfqMe087KL1LH4L/SajeJX30CpgEMfQUqkkMXFdFEKVvyYN1KOsuv nPXGb1VjDmOBR6YOu1zQmFoCg7s1GjKN+FDng2zii0T59tXWOQyGjWH03RRQQ57sPdSf Jj81btG4cB7XO1yHsQdTNx4ZpVxyeedxuYJncxnQhllJD6HpjEhClDYYUu9MfHNVVH7F p+pZZ4gpqfmNuAlLxp6rzMigSVgQrNAMtJEN8q2Nr1X0c5Vg10tiZ4a31MPKuz0LrCGw x7ICGczs42IzTAA/e4MKVWKumQkp/Z3NsVCeBFU88iMMmjyC8MSs+geCm1fpkkOsfeLC QJvA== X-Gm-Message-State: AFqh2kqdu8ca8pI0/14LhBKP5nj+eprPf22s/hRuDanSwB8LcLrRpRvD Ke4Xx1lJ+7k8L2xfzGoSSTU= X-Google-Smtp-Source: AMrXdXuGZdQZlCDYdGWNJ63k7gmDEWAMJCSQe/wcIlsu9tQdMtNrukFmoPmXc22QLLx0cvDqeCm21A== X-Received: by 2002:adf:e5cc:0:b0:269:2b79:4cce with SMTP id a12-20020adfe5cc000000b002692b794ccemr1645314wrn.65.1671580985286; Tue, 20 Dec 2022 16:03:05 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.03.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:03:04 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 8/9] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts Date: Wed, 21 Dec 2022 00:02:41 +0000 Message-Id: <20221221000242.340202-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar Add required properties in pinctrl node to handle GPIO interrupts. Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver continues without waiting for IRQC to probe. Signed-off-by: Lad Prabhakar --- v1 -> v2 * No change --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 3f7d451b1199..c8a83e42c4f3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -531,6 +531,8 @@ pinctrl: pinctrl@11030000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 152>; + #interrupt-cells = <2>; + interrupt-controller; clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_GPIO_RSTN>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index c6e25ad98011..a31cc54b8ed6 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -49,6 +49,10 @@ timer { }; }; +&pinctrl { + interrupt-parent = <&irqc>; +}; + &soc { interrupt-parent = <&gic>; From patchwork Wed Dec 21 00:02:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 636498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1702C4167B for ; Wed, 21 Dec 2022 00:03:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234380AbiLUADp (ORCPT ); Tue, 20 Dec 2022 19:03:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234331AbiLUADQ (ORCPT ); Tue, 20 Dec 2022 19:03:16 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC6D41F2C2; Tue, 20 Dec 2022 16:03:07 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id o5so13445757wrm.1; Tue, 20 Dec 2022 16:03:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TDx4PoIIM9s55jr76B6tJoItpMqZgxuY5BT2+9L4lSA=; b=KSvwsEDwSmMQkLfJuZJjF/qg5HVZhKX5+asanYJ14dRgci2s8AXZYUaTAqQrpCqoEy hCt7nBBopzrFTlzr/TC4hFxMXpIiN3tSCx7O1fWgA93bH98oC03E7SekzTSp+pLl5C38 xCeZC8Kfv/t3sMp4nXEeikNjyHb0Yp00R6krutG3bn2fsJiw+zPQP9EAP6A8z4qrl3Hf 01w0zSvZBx5rrhkSd0kSDxsZZFFg3Bov7pdGGZV4sB7VLO/6HKy07O9Vf8Sssk/jUb+a mVk2iI/yz5ZP62UAaI4qeZoHfmUIdmQNR8+VurAChiPN32N69qB6HFuE34YBY7XkxWAi tVQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TDx4PoIIM9s55jr76B6tJoItpMqZgxuY5BT2+9L4lSA=; b=pvEQatrpcSgWL/ol0P4NLg1GKdRxfAfZdLDq/yUPR0+hcEmHMLzjBb0nucsMuZoAwT KOi8YmnNFqCnjjfqKmx5aHL7A11TYX7re4Dy+q46N3QyfUIqCCiRTysdyxCrW5iwzlOL 7V9G4cOiAkyGvyb/Mr9YILS1CmlAGC1MOxIutHR9AEhg5pblMEnxaIcuqPKcOIZR+QLv S9qTMrf6vUslMsfp6qd/blNgbK/4UGkuUqMMLqdExbY02l5vSvz5tkLYgQ1/rGXsh2MS 32eWInKIFIWcG8Z0OoJr/cBkOchy97tXeHDd95G2M9NFVaI6gUmJAe6CjeiR+jfAyrFk Lc2Q== X-Gm-Message-State: AFqh2ko0LP0lC8i5y36yfQX6R/wjr/5rbv5MaLhxcZIZ9qjk9ToQLBxR 3lb+YeAjV/cc84LSB0unWzo= X-Google-Smtp-Source: AMrXdXv9LRP1Qpx2tmKWUDbyQUAHBj7IkpB6m1UmdJalm1DtiW26Q/6lEjvMRCLz7ljioJgYscwvlg== X-Received: by 2002:a05:6000:691:b0:260:6dca:f239 with SMTP id bo17-20020a056000069100b002606dcaf239mr7450448wrb.22.1671580986330; Tue, 20 Dec 2022 16:03:06 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:03:05 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 9/9] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Date: Wed, 21 Dec 2022 00:02:42 +0000 Message-Id: <20221221000242.340202-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar --- v1 -> v2 * No change --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 931efc07d6fb..49ecd33aeeb8 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -104,6 +107,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -151,7 +156,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ }; eth1_pins: eth1 { @@ -169,7 +175,8 @@ eth1_pins: eth1 { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - ; /* ET1_RXD3 */ + , /* ET1_RXD3 */ + ; /* IRQ7 */ }; sdhi0_emmc_pins: sd0emmc {