From patchwork Wed Dec 21 17:12:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjana Hari X-Patchwork-Id: 636558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AB3BC4332F for ; Wed, 21 Dec 2022 17:13:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234822AbiLURNu (ORCPT ); Wed, 21 Dec 2022 12:13:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234702AbiLURN3 (ORCPT ); Wed, 21 Dec 2022 12:13:29 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58EEBDF3B; Wed, 21 Dec 2022 09:12:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1671642772; x=1703178772; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=8IOTuB+8Ad2/OGIgq5ka1v1MJ4sGiD2XFigPFJRuK+c=; b=t/+PR99XzmCjK3WHWp7nRMLJ8MpnEesxhxwZz/oaSRsxwGtCIoRwUFHj uivoHV3f8IppVzvHFC8UONeeBulwUDMog210jzbq8CX1kVRVoJjPmCtAI yr/4tPR+0ZyCRkqTMWjvsI3ryayKqAoUpOWFBT5CFCG5O88mC3VQTfWdJ A=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 21 Dec 2022 09:12:51 -0800 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2022 09:12:51 -0800 Received: from hu-ahari-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 21 Dec 2022 09:12:47 -0800 From: Anjana Hari To: , , , CC: , , , , , , , , , Anjana Hari Subject: [PATCH 1/2] scsi: ufs: core: Add hibernation callbacks Date: Wed, 21 Dec 2022 22:42:21 +0530 Message-ID: <20221221171222.19699-2-quic_ahari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221221171222.19699-1-quic_ahari@quicinc.com> References: <20221221171222.19699-1-quic_ahari@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Add hibernation call backs - freeze, restore and thaw. Add the respective prototypes. Signed-off-by: Anjana Hari --- drivers/ufs/core/ufshcd.c | 80 +++++++++++++++++++++++++++++++++++++++ include/ufs/ufshcd.h | 6 +++ 2 files changed, 86 insertions(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index bda61be5f035..c216a97dc1dd 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -9453,6 +9453,25 @@ static int ufshcd_resume(struct ufs_hba *hba) /* enable the host irq as host controller would be active soon */ ufshcd_enable_irq(hba); + + if (hba->restore) { + /* Configure UTRL and UTMRL base address registers */ + ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), + REG_UTP_TRANSFER_REQ_LIST_BASE_L); + ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), + REG_UTP_TRANSFER_REQ_LIST_BASE_H); + ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), + REG_UTP_TASK_REQ_LIST_BASE_L); + ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), + REG_UTP_TASK_REQ_LIST_BASE_H); + /* Commit the registers */ + mb(); + } + + /* Resuming from hibernate, assume that link was OFF */ + if (hba->restore) + ufshcd_set_link_off(hba); + goto out; disable_vreg: @@ -9616,6 +9635,67 @@ void ufshcd_remove(struct ufs_hba *hba) } EXPORT_SYMBOL_GPL(ufshcd_remove); +int ufshcd_system_freeze(struct device *dev) +{ + + struct ufs_hba *hba = dev_get_drvdata(dev); + int ret = 0; + + /* + * Run time resume the controller to make sure + * the PM work queue threads do not try to resume + * the child (scsi host), which leads to errors as + * the controller is not yet resumed. + */ + pm_runtime_get_sync(hba->dev); + ret = ufshcd_system_suspend(dev); + pm_runtime_put_sync(hba->dev); + + /* + * Ensure no runtime PM operations take + * place in the hibernation and restore sequence + * on successful freeze operation. + */ + if (!ret) + pm_runtime_disable(hba->dev); + + return 0; +} +EXPORT_SYMBOL_GPL(ufshcd_system_freeze); + +int ufshcd_system_restore(struct device *dev) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + int ret = 0; + + hba->restore = true; + ret = ufshcd_system_resume(dev); + + /* + * Now any runtime PM operations can be + * allowed on successful restore operation + */ + if (!ret) + pm_runtime_enable(hba->dev); + + return ret; +} +EXPORT_SYMBOL_GPL(ufshcd_system_restore); + +int ufshcd_system_thaw(struct device *dev) +{ + + struct ufs_hba *hba = dev_get_drvdata(dev); + int ret = 0; + + ret = ufshcd_system_resume(dev); + if (!ret) + pm_runtime_enable(hba->dev); + + return ret; +} +EXPORT_SYMBOL_GPL(ufshcd_system_thaw); + /** * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) * @hba: pointer to Host Bus Adapter (HBA) diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 5cf81dff60aa..dadb3c732be4 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -978,6 +978,9 @@ struct ufs_hba { #endif u32 luns_avail; bool complete_put; + + /* Distinguish between resume and restore */ + bool restore; }; /* Returns true if clocks can be gated. Otherwise false */ @@ -1101,6 +1104,9 @@ extern int ufshcd_runtime_resume(struct device *dev); extern int ufshcd_system_suspend(struct device *dev); extern int ufshcd_system_resume(struct device *dev); #endif +extern int ufshcd_system_freeze(struct device *dev); +extern int ufshcd_system_thaw(struct device *dev); +extern int ufshcd_system_restore(struct device *dev); extern int ufshcd_shutdown(struct ufs_hba *hba); extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, int agreed_gear, From patchwork Wed Dec 21 17:12:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjana Hari X-Patchwork-Id: 636557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD015C4332F for ; Wed, 21 Dec 2022 17:14:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234686AbiLUROU (ORCPT ); Wed, 21 Dec 2022 12:14:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234765AbiLURNl (ORCPT ); Wed, 21 Dec 2022 12:13:41 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECCA924F3B; Wed, 21 Dec 2022 09:13:08 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BLFaIWx020535; Wed, 21 Dec 2022 17:12:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=TaN/2/hOe7knjlG+3Mf6CFZjVzMOiYNhITeGTjKnf1Y=; b=CDJkB+Nj5KM2v0NX5PiHS55KMSvMCTEWsOcSjy8Ewbgc4E9ZpwIl/03f0wvNsjjHwbcg R7EQAqosjJUk/+FlU2ob7vupM9vLjEspKpGfMb1+9AY8y4fbkWU7Nm3aLVBb0afWzPH2 RnyEknxBcj01o3+0JO2DdANS55ucsjkmqz4CZVG7bgShPYoShe8mOGLDmRHpAxvXunH8 afkPJFm2JwbeujSzpyCZUcxO4EEAOTWht8UT/PqxDU+Wu1C4FqsGi9khev3drUWzRk8I +e7+2ywsBy9RMJwUVelouTW1kAqJMjfqR3WZFQ19iL04Y8aH1bbn1se3y31Z1xFTbqzP 5A== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mkcxvbbka-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Dec 2022 17:12:58 +0000 Received: from nasanex01a.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BLHCwt3019004 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Dec 2022 17:12:58 GMT Received: from hu-ahari-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 21 Dec 2022 09:12:53 -0800 From: Anjana Hari To: , , , CC: , , , , , , , , , Anjana Hari Subject: [PATCH 2/2] scsi: ufs: ufs-qcom: Add hibernation callbacks Date: Wed, 21 Dec 2022 22:42:22 +0530 Message-ID: <20221221171222.19699-3-quic_ahari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221221171222.19699-1-quic_ahari@quicinc.com> References: <20221221171222.19699-1-quic_ahari@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bVDn856PkRQa6O9tR-6v-knJw5aFTNLr X-Proofpoint-ORIG-GUID: bVDn856PkRQa6O9tR-6v-knJw5aFTNLr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-21_09,2022-12-21_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 suspectscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212210143 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Adds freeze-thaw-restore callbacks for Qualcomm UFS platform. Signed-off-by: Anjana Hari --- drivers/ufs/host/ufs-qcom.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8ad1415e10b6..ac5685b0e891 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1498,10 +1498,14 @@ MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); #endif static const struct dev_pm_ops ufs_qcom_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) .prepare = ufshcd_suspend_prepare, .complete = ufshcd_resume_complete, + .suspend = ufshcd_system_suspend, + .resume = ufshcd_system_resume, + .freeze = ufshcd_system_freeze, + .restore = ufshcd_system_restore, + .thaw = ufshcd_system_thaw, }; static struct platform_driver ufs_qcom_pltform = {