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[2a01:c23:7c55:d800:fbe:25d2:487e:ae5c]) by smtp.gmail.com with ESMTPSA id d12-20020a170906304c00b007c17b3a4163sm12486807ejd.15.2023.01.01.14.01.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 14:01:55 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, gregkh@linuxfoundation.org, angelogioacchino.delregno@collabora.com, allen-kh.cheng@mediatek.com, nfraprado@collabora.com, sean.wang@mediatek.com, zhiyong.tao@mediatek.com Subject: [PATCH v7 3/7] dt-bindings: mfd: syscon: Add mt8365-syscfg Date: Sun, 1 Jan 2023 23:01:45 +0100 Message-Id: <20230101220149.3035048-4-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101220149.3035048-1-bero@baylibre.com> References: <20230101220149.3035048-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document Mediatek mt8365-syscfg Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 1b01bd0104316..7beeb0abc4db0 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -50,6 +50,7 @@ properties: - marvell,armada-3700-usb2-host-misc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep From patchwork Sun Jan 1 22:01:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 638381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F998C4167B for ; Sun, 1 Jan 2023 22:02:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231593AbjAAWCM (ORCPT ); Sun, 1 Jan 2023 17:02:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231388AbjAAWCA (ORCPT ); Sun, 1 Jan 2023 17:02:00 -0500 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEEE2218E for ; Sun, 1 Jan 2023 14:01:58 -0800 (PST) Received: by mail-ej1-x636.google.com with SMTP id u9so63092146ejo.0 for ; Sun, 01 Jan 2023 14:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=X/YvHElO1B1L96Q/ryL2GcQHBR6R6iwvqncvsZcjNEM=; b=PL/7VFABbftOZo2szu3AblcfijGlLQfJk1ickQXxRfGe9f70BdSj425vyk4U7e6o7M hFKk/96B75Dq+0pT8lOhqVrnmUxmwK9BQkzZEdeupmCq5yq0bwY9BdAjHkh72racR6ef px8R/QvVe7RsAO3Y2QiicJxS6DTXEMfiKNEI3qQQVjGUuPSR6vZ2ZknRWIS1EKmC+8bO WwOWfpLEpXbrMG3bapmvjqQA2ovHXjVP1msf+5FjNeU66QtloJ7e725sljla5EqKpds0 CSu5vnZIrUCJmyvipzIt2c9OUhWtZ72XUV8DTIIwRVgcYaKw0fJdctTFaxs7m5VE7t2o w/3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X/YvHElO1B1L96Q/ryL2GcQHBR6R6iwvqncvsZcjNEM=; b=bECKd0AJQj6CYrmALfMUpWujXf4LW3sygupfExoxxW2LbfHYdtdLqrJBGY7SvJfbcW U2+SrPtMRbjQArkkaS9yVlfin750jHw3/zk0gm1/tUskM2YDwRfeDKIM0tcU/zTHmh+f MnuGMM2iinAGGR9CPAOCv/zJTBIyyRJF7f254KZZ6rOFkx93OpqsvSBG6GZSP3noqTjG Pr1pzWfNO4sW4fFgDEAMYjHp7sAvuF6NzbvnyvFnJL+3zygarriN+q+uYpkDNHNRVyiI 3nMcIjS9UTvTZRCIUfBWsVhwTzX/qJF95jM9z09QP2jRzpIFoP4bJBEzbILlSNyPB6DU Xhxw== X-Gm-Message-State: AFqh2kqsJdily4ap8b2UtsrmJdmx4qEmi4LUDhTlCkw5fgm7z19MS7Ui 40EeAACySOuVDgEMkAevGhS83cWmeT1a4MyAaYU= X-Google-Smtp-Source: AMrXdXvrts/wULFurfFjqpmycwAXrztlaV2mg8bMCc6qPeQ4QiyC75xGMkpWBsvLKTrdOaA1pZ4qrA== X-Received: by 2002:a17:907:7e83:b0:7c0:e6d8:7770 with SMTP id qb3-20020a1709077e8300b007c0e6d87770mr38819922ejc.74.1672610516953; Sun, 01 Jan 2023 14:01:56 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-2a01-0c23-7c55-d800-0fbe-25d2-487e-ae5c.c23.pool.telefonica.de. [2a01:c23:7c55:d800:fbe:25d2:487e:ae5c]) by smtp.gmail.com with ESMTPSA id d12-20020a170906304c00b007c17b3a4163sm12486807ejd.15.2023.01.01.14.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 14:01:56 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, gregkh@linuxfoundation.org, angelogioacchino.delregno@collabora.com, allen-kh.cheng@mediatek.com, nfraprado@collabora.com, sean.wang@mediatek.com, zhiyong.tao@mediatek.com Subject: [PATCH v7 4/7] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Date: Sun, 1 Jan 2023 23:01:46 +0100 Message-Id: <20230101220149.3035048-5-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101220149.3035048-1-bero@baylibre.com> References: <20230101220149.3035048-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkränzer --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 0000000000000..4b96884a1afc7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkränzer + +description: | + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pull up + settings for 2 pull resistors, R0 and R1. User can configure those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + pio-pins { + pins { + pinmux = , ; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + }; + }; From patchwork Sun Jan 1 22:01:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 638380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2653BC4167B for ; Sun, 1 Jan 2023 22:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231658AbjAAWCQ (ORCPT ); Sun, 1 Jan 2023 17:02:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230339AbjAAWCH (ORCPT ); Sun, 1 Jan 2023 17:02:07 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01FF62AE4 for ; Sun, 1 Jan 2023 14:01:59 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id ud5so62991579ejc.4 for ; Sun, 01 Jan 2023 14:01:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yM7tLQukK3ee+o3GHKaxNTtqE120eC/46qEVclUSCs4=; b=6tmSGZwjOUabk0Tay5+t+RCnJxuU/Q+E4bAuPZ5vkzcNaUtgRpVrZL3QZ2PGBDs5nZ MVicZkyjmjnyuhsNwYFAXrKghCMxmNeXdAWaFYzUGsxicEUrTolsYdv+Cgh+JQJ6QJbQ IRzFRnw5oDCIlXfud4JBKTrlTjIhMslkMJtBY9OQtGYJukpQyPnSTupRWot5HvIxj7sO wdwUkGa2wxua4BKqZULIASKBMVn8rTldahPxGcxy3I1e7H0nCJDPdn8s6mNjVAKlFe7H gNa40Bl5e72GGjlcg0mR1U1OS44xc93Gck2NxwMLRc7NEiyA0fb1OPB5unkmt+A+ztz1 bing== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yM7tLQukK3ee+o3GHKaxNTtqE120eC/46qEVclUSCs4=; b=XCqD43esXBkZ4bneKzAVClefoxuB5i1lHOa2b58kBVM2iGKleYwR0I/2Zg9uMS6+Q3 0joMJGrcowsPVODBKu0Z6woZVrHFqwfBcNco4mfLegdGm12a3Tc/IGS5Mv3f5ZLEfGDA 3SVffRMvhUtnOCNFr/YFrs6mGr0YeEaWUbhQ+EYvPQ+CgJEZRAU9rbakoC1txdwn0eHl nXNKYJA2EcI6+QODfiQBf/3c2dwt/iCnWU0dbF6d/YLwpt9LzHQF/J5l0JPCnRDVkbZa zz4tvj3BvISuP9ZzI9K91F+jHOb/FrzawKP2l2o5ofGdYXHwSDksa/aln/nRnMAh/GzU XEBw== X-Gm-Message-State: AFqh2kpTWR44mb1yEpCAFPRWU0GkFjZTmz5I4r2UrCK17qO8t1q/McJR pdGXUru6Q02Px9xjl63Cgpb9vZXdv7g2l4x7FyE= X-Google-Smtp-Source: AMrXdXtgygK9dvnVdrlDMNTfpGZn77OgXyintLIQ1gNB5Dj1uLzbvkQ5s0f0tiODrRQ/1YQ/WBHIaw== X-Received: by 2002:a17:906:f6d7:b0:7c1:5169:3ed6 with SMTP id jo23-20020a170906f6d700b007c151693ed6mr38129337ejb.48.1672610519356; Sun, 01 Jan 2023 14:01:59 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-2a01-0c23-7c55-d800-0fbe-25d2-487e-ae5c.c23.pool.telefonica.de. [2a01:c23:7c55:d800:fbe:25d2:487e:ae5c]) by smtp.gmail.com with ESMTPSA id d12-20020a170906304c00b007c17b3a4163sm12486807ejd.15.2023.01.01.14.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 14:01:59 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, gregkh@linuxfoundation.org, angelogioacchino.delregno@collabora.com, allen-kh.cheng@mediatek.com, nfraprado@collabora.com, sean.wang@mediatek.com, zhiyong.tao@mediatek.com Subject: [PATCH v7 6/7] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings Date: Sun, 1 Jan 2023 23:01:48 +0100 Message-Id: <20230101220149.3035048-7-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230101220149.3035048-1-bero@baylibre.com> References: <20230101220149.3035048-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent [bero@baylibre.com: Cleanups suggested by reviewers] Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index a3c37944c6305..c119caa9ad168 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci reg: