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[209.51.188.17]) by mx.google.com with ESMTPS id g25-20020ac87759000000b003a7f5e516b0si17081505qtu.592.2023.01.04.05.42.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Jan 2023 05:42:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C9+LCnUp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pD3zi-0003cE-DI; Wed, 04 Jan 2023 08:39:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pD3zg-0003bo-1Y for qemu-devel@nongnu.org; Wed, 04 Jan 2023 08:39:48 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pD3ze-0001Tq-CS for qemu-devel@nongnu.org; Wed, 04 Jan 2023 08:39:47 -0500 Received: by mail-wr1-x429.google.com with SMTP id j17so27622603wrr.7 for ; Wed, 04 Jan 2023 05:39:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E0jD820lsyDetFSkA1XxZx75shSUmhMZjVO0KmjpJic=; b=C9+LCnUpiIhP7a3tMDtjoraBbXgzz/uAXZODg5+qaifgoAGd7rC6kuk3+WemmiGEgc 2SIFfG2U8hlb6arfcB1Ffg8kuF9L3p+bQrmTP2S7s1MUE6cGXXOaNKakDAkQLzfewyse E7T3MJ02fvYrciBB4if6SKTbAxlT3m3T3LD+K+RknA+qJzLdPcasFSFdULUK0SS9MCC7 uJBi0joYAOnhq6ZyDbeYIyRZjMm28M8vqz/XirdzQfWTjJ1otOOIREYoytDqtAXCV9+n GX0UREbUqIxNdfVXs0rmxYL3mmB5/J4Mn0hvfu/4iIWejW37Gz8COIplbiQmM4hZjNTY huGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E0jD820lsyDetFSkA1XxZx75shSUmhMZjVO0KmjpJic=; b=7kez+puHQ/0n/Xy+KdaTrQW34K2JKKmsL1vokIjuha3iy9eCBbYycgC+J46Yfeie65 Sw53IPDEKbx0U7YnSQUXgAtL8lZ3xl8jHSpFw/LhJ+rHir4vT/wawbqfORKQbH8OxxQ1 w0ajODEr6f45zpGg7OVjsYuTTxTuFuLoLasiEQ4Q2N8IiMAluSTxzv9HsZTDPEfnw7rb 9BpHFhF6LrKsxHpr4JyJW5GNE2NsKPWjDh/XF1dhMzrSgRpHPGY5olDv/coLrVa2blZ/ zM3JiivdpvCbvZU82ZGOnqO/plXNk/thFbqXIBgmnLx33LXCgQeq8+Kc45yiEy9nC9QX YEfg== X-Gm-Message-State: AFqh2kq4tAxLK1UiLUW6rWAm6xnvCRdFeYfoeEwrx1QTzI3Mxdy9hPmE bHCPCt1G2xq2cqETqIeByzUKZ80egXuhtfMJ X-Received: by 2002:a5d:6da6:0:b0:288:52a3:d0dc with SMTP id u6-20020a5d6da6000000b0028852a3d0dcmr25780321wrs.50.1672839583583; Wed, 04 Jan 2023 05:39:43 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id c17-20020adffb51000000b0027cb20605e3sm26091150wrs.105.2023.01.04.05.39.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 05:39:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Aurelien Jarno , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/6] hw/pci/pci_host: Trace config accesses on unexisting functions Date: Wed, 4 Jan 2023 14:39:30 +0100 Message-Id: <20230104133935.4639-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104133935.4639-1-philmd@linaro.org> References: <20230104133935.4639-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we only emit trace events for existing PCI functions. In order to ease debugging PCI enumeration process, also emit for unexisting functions: $ qemu-system-foo -trace pci_cfg_\* ... pci_cfg_read empty 00:0a.4 @0x0 -> 0xffffffff pci_cfg_read empty 00:0a.5 @0x0 -> 0xffffffff pci_cfg_read empty 00:0a.6 @0x0 -> 0xffffffff pci_cfg_read empty 00:0a.7 @0x0 -> 0xffffffff pci_cfg_read pcnet 00:0b.0 @0x0 -> 0x20001022 pci_cfg_read empty 00:0c.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:0d.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:0e.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:0f.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:10.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:11.0 @0x0 -> 0xffffffff pci_cfg_read cirrus-vga 00:12.0 @0x0 -> 0xb81013 Signed-off-by: Philippe Mathieu-Daudé --- hw/pci/pci_host.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index eaf217ff55..ead1d3e61c 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -118,6 +118,9 @@ void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len) uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); if (!pci_dev) { + trace_pci_cfg_write("empty", extract32(addr, 16, 8), + extract32(addr, 11, 5), extract32(addr, 8, 3), + config_addr, val); return; } @@ -131,6 +134,9 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len) uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1); if (!pci_dev) { + trace_pci_cfg_read("empty", extract32(addr, 16, 8), + extract32(addr, 11, 5), extract32(addr, 8, 3), + config_addr, ~0x0); return ~0x0; } From patchwork Wed Jan 4 13:39:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 639038 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp1749360pvb; Wed, 4 Jan 2023 05:42:09 -0800 (PST) X-Google-Smtp-Source: AMrXdXtIGL66eUXngi7TIKPNlM8+fYtnvBNP68jMWcS7hrZtbNxqVRYt2HcBRuTR8vuhQRI22VF+ X-Received: by 2002:a05:6102:2333:b0:3c7:a4b5:31f with SMTP id b19-20020a056102233300b003c7a4b5031fmr15611936vsa.19.1672839729554; Wed, 04 Jan 2023 05:42:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672839729; cv=none; d=google.com; s=arc-20160816; b=Z9K5NKC22vV9aPoC129o8jprxV5BYnPWQmwnDBKX/94CLICbGr1OR8silTCbjmPHo+ U4NfAwegeHZjo/dTWH07/2wuyN0w3sPTiZ01LTX2YawbCJvFqZIgmigTadO7WUz7IEeW 4upQAiw/Cf+TOJLaukffUFC2dsjgjeCnxcybj9IYrr2liPrbYiyUBDyoLBwPhr3i8tSP gGbMjqfeWvFollpg40t0wBRJH50jnMkuOAYUjZx9nl7lZjlJxpEkNx+7X6dSB1ID3JO0 IVaGempZ2AGuoecuBoLG3nj5njuv5/g9q2I45XfrT4gyI13tmwPwBq2jsR+8ys4Zd6gS JAYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WTE5lvRuyw95tyd7OeeOqOVNz/VGzsf7WbrAe7T/I2s=; b=Z5KjU13Myu5uvSL9TV6bQnnfYsBBgmvBo5MciLO1Lz9hEYzPUaunmigG83jXF5g8LI CvMLm+jENIY95O6b1wS4RD01con68RWATl13armDlWaMViahgvAuZOGNG57Hrz9CXZEv f3iGsk4KAC3XsC7BWu9nRIs7HPu+ro1VKaCreJDK96TK7GtSYJjyi59K0yLvDxcRQdqC sYt3KFRWqG11wZMTMQbGGzEQG+0vBklo6uHnQ9aCuGOiO5Fklkxhi/xHab1a0qwWhyqu zQHToc4lzIm1SgCg4UIMx6ipDZKzwbX+tGBmJRbNn2RxEvfgpKvZ9lF0Oqpd86Ezn1jh 4Mfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cba85Pge; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c0a2e0ab04..e9424150aa 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -106,11 +106,10 @@ static struct _loaderparams { } loaderparams; /* Malta FPGA */ -static void malta_fpga_update_display(void *opaque) +static void malta_fpga_update_display_leds(MaltaFPGAState *s) { char leds_text[9]; int i; - MaltaFPGAState *s = opaque; for (i = 7 ; i >= 0 ; i--) { if (s->leds & (1 << i)) { @@ -123,6 +122,10 @@ static void malta_fpga_update_display(void *opaque) qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text); +} + +static void malta_fpga_update_display_ascii(MaltaFPGAState *s) +{ qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text); } @@ -457,13 +460,13 @@ static void malta_fpga_write(void *opaque, hwaddr addr, /* LEDBAR Register */ case 0x00408: s->leds = val & 0xff; - malta_fpga_update_display(s); + malta_fpga_update_display_leds(s); break; /* ASCIIWORD Register */ case 0x00410: snprintf(s->display_text, 9, "%08X", (uint32_t)val); - malta_fpga_update_display(s); + malta_fpga_update_display_ascii(s); break; /* ASCIIPOS0 to ASCIIPOS7 Registers */ @@ -476,7 +479,7 @@ static void malta_fpga_write(void *opaque, hwaddr addr, case 0x00448: case 0x00450: s->display_text[(saddr - 0x00418) >> 3] = (char) val; - malta_fpga_update_display(s); + malta_fpga_update_display_ascii(s); break; /* SOFTRES Register */ From patchwork Wed Jan 4 13:39:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 639034 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp1748976pvb; Wed, 4 Jan 2023 05:41:09 -0800 (PST) X-Google-Smtp-Source: AMrXdXvIbpUv4jOEzb4/+TtBLuux81sTZv659kx+8cdfuWnmcSu0nnW+9MuyfjHe38EL0CHFAr8j X-Received: by 2002:a67:e1cc:0:b0:3c4:dd81:72fe with SMTP id p12-20020a67e1cc000000b003c4dd8172femr15782636vsl.22.1672839669503; Wed, 04 Jan 2023 05:41:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672839669; cv=none; d=google.com; s=arc-20160816; b=Cit46GzFhtYRnRSzem+u6Gm7IESDCfUnkGLxT1fhDugPpr7ltgI3G1aAvWl0yh3ARr 69rFOo7GJKcacWn+QGvUeEU9a0u/+cA3R6LQlej6puqJ70btucE1L6qFQUEDSQAnCjh+ wKiqzDLEvX5kQfWRl7Q8YHynB4EBLk1DOTcyvHzMvyXMUIpByeTA9Ay8cEVBebImYRK1 isV9xfIbBpqsLG5XsNTA2P2ypx+6h2ytewErhI+MKAD12vpsVIOm6LzsLFDD2AL4+PSX OrR+QxIRSKiAwtzzq77wsrLzV9JmVeePzuQkT0mDbzf4YHiueM1wwuo2mME8QsCjAmca Pu/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZygYmfrmD7qdRbVxXkYivEOl/lZqKFZseEhzh+vRLa0=; b=PnAhTdZDX6rWapGRFZuyupt3osIjqjrz/oZoM2VQVSEnBoiAdH6c23Pbb/nbFtCWI9 IXw1hdDNhDG+MPmAhAAfsHqw3m4w06hzDewSTHqkcIOlcWFpSA3+JhM11GnbJ/WWXT84 BjF6HbXzFvIQ4KmdxVfroMidgJBtIEzqrYgPbHsHzWwCggDWXh2G26QFS5IhdGllWN/d HA9Y7VqBLzRg39L0zKhwJP9VaFaGc2JqqFlAcZUkalqu1XMNbS7bCSwSfr1INGP0r5HS KA6fTf2YGc2pcmDPG35rC9IvrT8TD1m4Xk5Etnt3NTWAuHig+tLdZADybx/xLHaaH58r Visg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mwg1MbN1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f3-20020a05620a408300b006ed88c5e84asi20266191qko.228.2023.01.04.05.41.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Jan 2023 05:41:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mwg1MbN1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pD3zy-0003hk-FJ; Wed, 04 Jan 2023 08:40:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pD3zx-0003hZ-10 for qemu-devel@nongnu.org; Wed, 04 Jan 2023 08:40:05 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pD3zo-0001WY-Jo for qemu-devel@nongnu.org; Wed, 04 Jan 2023 08:39:58 -0500 Received: by mail-wr1-x42b.google.com with SMTP id w1so20861447wrt.8 for ; Wed, 04 Jan 2023 05:39:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZygYmfrmD7qdRbVxXkYivEOl/lZqKFZseEhzh+vRLa0=; b=mwg1MbN1JHjrQ+XT7jHjgHRqIp4sIK2cx14a/2WpLDJV6IgSym7k3wmoV8GPx/Eq8w AUZztOWb1ylTNmYB8Ci+4ilCExn4PyrUyD4/tvzn+nkDMFgllfvEFXFWyg2NC2RY9fLO 74druzXhOI0Cp0tHoG4SDu5TIixROqFrdJKZFme+VCOhBUy5vijjspeAbqYRvpUfMQPj JWZYqP++pGEZaHG0oRKOTvpprxfow3lpc+KI8OiWFt/wRuOuJpvQV+4I2mB5fKbIz6yX BCi2MxJcm+GNl9Y9FLYQrAI3QetayVoDEIE6nfB0DX+qPNyB1jgltMB2tAFHLysfIEit k/pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZygYmfrmD7qdRbVxXkYivEOl/lZqKFZseEhzh+vRLa0=; b=51RoDPubyFNW26+N6lZgUVBR6BHLoVyAaa1J8fiPMdeYOYtLDFoAH3HstZgMjrWvuY wS5JwNDDkD3jxe5dB8Cwh418zREHJy2vRWIkWN/U0kwkFeouw626qkSLJvUwQ2KWrGDe sR8Yn8DEOzE8Z1ZT34WveqdMZ3N2udH6gf/izx13Kf/X1hmgjgFKtxoQyuwXQNvhXHQn sxSMWbtvNI9IQLUHocnZahyy9fytlX5Un60Sjsc0xp/51TvGuytoqj/3gQEq4IVO55Pe IJLiqoiJ2HWAX8x8yQ/b3JGfG/1OZNsKvUwzlqQ2mu4rJxVqsXDjeo3a12ipGuIgsKEt ttVg== X-Gm-Message-State: AFqh2krylcFzStVt/fV/doMpbpo/MRBnlDjDTUa6qPHnjV0po6GpCj6K eoKGwR8XsYMLRQ9RPAhKO7kJXjR9LTX8YDlG X-Received: by 2002:adf:ce0a:0:b0:242:4dd8:a7ee with SMTP id p10-20020adfce0a000000b002424dd8a7eemr30468889wrn.12.1672839593909; Wed, 04 Jan 2023 05:39:53 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id l15-20020a5d410f000000b002683695bf97sm34175987wrp.58.2023.01.04.05.39.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 05:39:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Aurelien Jarno , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 3/6] hw/mips/malta: Trace FPGA LEDs/ASCII display updates Date: Wed, 4 Jan 2023 14:39:32 +0100 Message-Id: <20230104133935.4639-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104133935.4639-1-philmd@linaro.org> References: <20230104133935.4639-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The FPGA LEDs/ASCII display is mostly used by the bootloader to show very low-level debug info. QEMU connects its output to a character device backend, which is not very practical to correlate with ASM instruction executed, interrupts or MMIO accesses. Also, the display discard the previous states. To ease bootloader debugging experience, add a pair of trace events. Such events can be analyzed over time or diff-ed between different runs. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 3 +++ hw/mips/trace-events | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index e9424150aa..44d88a24a7 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -58,6 +58,7 @@ #include "semihosting/semihost.h" #include "hw/mips/cps.h" #include "hw/qdev-clock.h" +#include "trace.h" #define ENVP_PADDR 0x2000 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) @@ -120,12 +121,14 @@ static void malta_fpga_update_display_leds(MaltaFPGAState *s) } leds_text[8] = '\0'; + trace_malta_fpga_leds(leds_text); qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text); } static void malta_fpga_update_display_ascii(MaltaFPGAState *s) { + trace_malta_fpga_display(s->display_text); qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text); } diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 13ee731a48..b5b882c6c2 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -4,3 +4,7 @@ gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value: gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 + +# malta.c +malta_fpga_leds(const char *text) "LEDs %s" +malta_fpga_display(const char *text) "ASCII '%s'" From patchwork Wed Jan 4 13:39:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 639037 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp1749332pvb; Wed, 4 Jan 2023 05:42:05 -0800 (PST) X-Google-Smtp-Source: AMrXdXvNrW196REPF9lC1bNguU4iP1ZoLarCemKko6w/NqOhEizc165z70rbAe/k2rctnMBNIaXe X-Received: by 2002:a0c:ec10:0:b0:531:c3b8:fdbc with SMTP id y16-20020a0cec10000000b00531c3b8fdbcmr18233072qvo.43.1672839724999; Wed, 04 Jan 2023 05:42:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672839724; cv=none; d=google.com; s=arc-20160816; b=qGCvafjKcUql9ILxTwpfYwTsYoZDHfrGibUQ/FpAuPvE4xHZSN+bSrBHYpN8/OW4oL /HbIOK8mTFK5/0y73o7FqLbexVXn3MqLjldidJGb1SV9FQRu1iRmG7XHn+ZLGA1Vai6S vdPFE7xc5lWYbOhi4HufwBNLj2/Tu4sxMwjpnpJ5zVhRaU9fI+PgIOWrZmGdocsEA+C2 O8sJ/nIE2h0yR6vZS4wAScvJHIQGxLQw4Fn7xhurXkBCYfQBFNNLfUPqq3D5XV/wV7gs Wt3LcNhg1su3DtBwrblFvcYB0DL1TFeY0uk7s4sJp0eCE6V0jvYGfc0v4xksXpLIB3Y3 patw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=P/Y2LlHycAcX9mSOeT6G6dar2QR0XkVS2EXSvJD6ZwQ=; b=HHX0sQqWJXWW61CZ6HmMjEeeujZrHx9JY4D9NNu5iRJ2592+U2JzHwX9ZL7xqUOuho dwS4T6JWgK7DcLWI+83SM9diNFaWTnDLkDJLOso6YrFSbEDMQLfLAz1mPyq9ESyJGHsI DPWxORQRfN3exb1B/YgAT90OOX6HAEOtDWwkVCb6WI4ZmvzIcgH/eAiGsRkUEPDZyckK GayWHYdMlWuOuzGR0u9DSocuSSrjFYUCCIYcx6ocorBGD4jId3xb1QeiaQHI4FwiygVG Srrf9FtgcLfz+GQR23NhCV0QW9nfsQA814/90r7dA6GQmPZJdP5GjuEdUMtEQV2PDMWm D1bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U1YvcaiE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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To reduce computational effort, accumulate these as a single memory transaction. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 19d0d9889f..d84c2b7349 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -282,6 +282,8 @@ static void gt64120_isd_mapping(GT64120State *s) hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull; hwaddr length = 0x1000; + memory_region_transaction_begin(); + if (s->ISD_length) { memory_region_del_subregion(get_system_memory(), &s->ISD_mem); } @@ -292,10 +294,14 @@ static void gt64120_isd_mapping(GT64120State *s) s->ISD_start = start; s->ISD_length = length; memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); + + memory_region_transaction_commit(); } static void gt64120_pci_mapping(GT64120State *s) { + memory_region_transaction_begin(); + /* Update PCI0IO mapping */ if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) { /* Unmap old IO address */ @@ -354,6 +360,8 @@ static void gt64120_pci_mapping(GT64120State *s) &s->PCI0M1_mem); } } + + memory_region_transaction_commit(); } static int gt64120_post_load(void *opaque, int version_id) From patchwork Wed Jan 4 13:39:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 639040 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp1749515pvb; Wed, 4 Jan 2023 05:42:30 -0800 (PST) X-Google-Smtp-Source: AMrXdXu7IeIBbpWBsHvi/LMZ2v3kA41+/wc2dkzJJVUJRMuUidmBJjBYD99odacHfrrz9G3UTS9+ X-Received: by 2002:a05:622a:450:b0:3a8:2d3d:7c51 with SMTP id o16-20020a05622a045000b003a82d3d7c51mr96322453qtx.33.1672839750344; Wed, 04 Jan 2023 05:42:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672839750; cv=none; d=google.com; s=arc-20160816; b=j020onfYG/v6ERB01QUhJBckHddqDozfytr2dB9MMAuG01aWyd/l+aXzFnV4GT8lwG TgLGuNxcnmCrxvzenoyTRSbCG1LzZyclj/Xs6FZnktMsoLHo0EVUuPs70/TqgFhO5LTI FKB0ufca6TLZo0EKnq7c/vtFpYzAyOOvDm6W3ACKNQ/M3rtAwi5GDnNHOufgtmsH35SD icgnXd8Zwbr3UYx+xtIyqgZtUf6gRdN2/fp2fvv9xGB8oy6+4Uvbp50QqB81oOmBEU6c PM/3EXI3kSfWWI2jMr80IZp9Fv5Vhj44gQqWGQHDgCAcEnzz+uxJwI8S+lgY54QUYY45 IQVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qrPSllnx4YupvoZF9hNQoszmPPNXIKLtvTqBpG1DBSg=; b=0Dif70W571mB/1IvWAGhxPLseOscZ3/vDOkjjozH/rfMKDPCOfp22rfdQ0JgbgVd/l dUVHtAxV9mc/jWJjmmeC7LNlsygVAjOBk0mcfyU+wHrQcnb5ZTWsVlcDUqayWzg4FeEp g1g4vt/aRQN8jQlzeay3+HdMjDGVfC6NBnNcWnKnH8r8AR03Lr8Qe6L9Kobyf4Y3CyWF h5JI3s8pC/4v8oKUubI5YsSN5FdxwDOeTAcOzzQz0muaAWKn2u8X30ukfVfRTVv/bV7p ihDCEdpQ2p4wYSbjhTaeGLuMKMcv6sC9CjuNv42dYPrDSGSoqP4hrp6k6O41Qv9IUbDj Th8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jpnkc7tL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Instead of complicating how CFGADDR/CFGDATA registers deal with endianness, use the existing MemoryRegionOps from hw/pci/pci_host.c. Doing so also reduce the access to internal PCI_HOST_BRIDGE fields. Map the PCI_HOST_BRIDGE MemoryRegionOps into the corresponding CFGADDR/CFGDATA regions in the ISD MMIO and remove the unused code in the current ISD read/write handlers. Update the mapping when PCI0_CMD register is accessed (in case the endianness is changed). This allows using the GT64120 on a big-endian host (and boot the MIPS Malta machine in little-endian). Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 70 ++++++++++++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 20 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index d84c2b7349..b92536d3ab 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -298,6 +298,50 @@ static void gt64120_isd_mapping(GT64120State *s) memory_region_transaction_commit(); } +static void gt64120_update_pci_cfgdata_mapping(GT64120State *s) +{ + /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */ + static const MemoryRegionOps *pci_host_conf_ops[] = { + &pci_host_conf_be_ops, &pci_host_conf_le_ops + }; + static const MemoryRegionOps *pci_host_data_ops[] = { + &pci_host_data_be_ops, &pci_host_data_le_ops + }; + PCIHostState *phb = PCI_HOST_BRIDGE(s); + + memory_region_transaction_begin(); + + /* + * The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal + * Command Register determines how data transactions from the CPU to/from + * PCI are handled along with the setting of the Endianess bit in the CPU + * Configuration Register. See: + * - Table 16: 32-bit PCI Transaction Endianess + * - Table 158: PCI_0 Command, Offset: 0xc00 + */ + if (memory_region_is_mapped(&phb->conf_mem)) { + memory_region_del_subregion(&s->ISD_mem, &phb->conf_mem); + object_unparent(OBJECT(&phb->conf_mem)); + } + memory_region_init_io(&phb->conf_mem, OBJECT(phb), + pci_host_conf_ops[s->regs[GT_PCI0_CMD] & 1], + s, "pci-conf-idx", 4); + memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2, + &phb->conf_mem, 1); + + if (memory_region_is_mapped(&phb->data_mem)) { + memory_region_del_subregion(&s->ISD_mem, &phb->data_mem); + object_unparent(OBJECT(&phb->data_mem)); + } + memory_region_init_io(&phb->data_mem, OBJECT(phb), + pci_host_data_ops[s->regs[GT_PCI0_CMD] & 1], + s, "pci-conf-data", 4); + memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2, + &phb->data_mem, 1); + + memory_region_transaction_commit(); +} + static void gt64120_pci_mapping(GT64120State *s) { memory_region_transaction_begin(); @@ -389,7 +433,6 @@ static void gt64120_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size) { GT64120State *s = opaque; - PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t saddr = addr >> 2; trace_gt64120_write(addr, val); @@ -592,6 +635,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_PCI0_CMD: case GT_PCI1_CMD: s->regs[saddr] = val & 0x0401fc0f; + gt64120_update_pci_cfgdata_mapping(s); break; case GT_PCI0_TOR: case GT_PCI0_BS_SCS10: @@ -632,15 +676,9 @@ static void gt64120_writel(void *opaque, hwaddr addr, saddr << 2, size, size << 1, val); break; case GT_PCI0_CFGADDR: - phb->config_reg = val & 0x80fffffc; - break; case GT_PCI0_CFGDATA: - if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { - val = bswap32(val); - } - if (phb->config_reg & (1u << 31)) { - pci_data_write(phb->bus, phb->config_reg, val, 4); - } + /* Mapped via in gt64120_pci_mapping() */ + g_assert_not_reached(); break; /* Interrupts */ @@ -698,7 +736,6 @@ static uint64_t gt64120_readl(void *opaque, hwaddr addr, unsigned size) { GT64120State *s = opaque; - PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t val; uint32_t saddr = addr >> 2; @@ -883,17 +920,9 @@ static uint64_t gt64120_readl(void *opaque, /* PCI Internal */ case GT_PCI0_CFGADDR: - val = phb->config_reg; - break; case GT_PCI0_CFGDATA: - if (!(phb->config_reg & (1 << 31))) { - val = 0xffffffff; - } else { - val = pci_data_read(phb->bus, phb->config_reg, 4); - } - if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { - val = bswap32(val); - } + /* Mapped via in gt64120_pci_mapping() */ + g_assert_not_reached(); break; case GT_PCI0_CMD: @@ -1153,6 +1182,7 @@ static void gt64120_reset(DeviceState *dev) gt64120_isd_mapping(s); gt64120_pci_mapping(s); + gt64120_update_pci_cfgdata_mapping(s); } static void gt64120_realize(DeviceState *dev, Error **errp) From patchwork Wed Jan 4 13:39:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 639036 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp1749081pvb; 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Wed, 04 Jan 2023 05:40:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Aurelien Jarno , Jiaxun Yang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 6/6] tests/avocado: Add tests booting YAMON ROM on MIPS Malta machines Date: Wed, 4 Jan 2023 14:39:35 +0100 Message-Id: <20230104133935.4639-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104133935.4639-1-philmd@linaro.org> References: <20230104133935.4639-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add quick tests booting YAMON: $ avocado --show=app,console run -t machine:malta tests/avocado/machine_mips_malta.py (1/2) tests/avocado/machine_mips_malta.py:MaltaMachine.test_mipsel_malta_yamon: console: YAMON ROM Monitor, Revision 02.22. console: Copyright (c) 1999-2007 MIPS Technologies, Inc. - All Rights Reserved. console: For a list of available commands, type 'help'. console: Compilation time = May 24 2013 12:16:34 (pburton) console: Board type/revision = 0x02 (Malta) / 0x00 console: Core board type/revision = 0x01 (CoreLV) / 0x00 console: System controller/revision = Galileo / GT_64120A-B-0 console: FPGA revision = 0x0000 console: MAC address = ff.ff.ff.ff.ff.ff console: Board S/N = 0123456789 console: PCI bus frequency = 33.33 MHz console: Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00 console: Processor ID/revision = 0x93 (MIPS 24Kf) / 0x00 console: Endianness = Little console: CPU/Bus frequency = 333 MHz / 419 MHz console: Coherency = None console: Flash memory size = 4 MByte console: SDRAM size = 128 MByte console: First free SDRAM address = 0x800c32f0 console: WARNING: Environment variable flash area is invalid! console: HINT : Perform "erase -e" console: YAMON> PASS (1.88 s) (2/2) tests/avocado/machine_mips_malta.py:MaltaMachine.test_mips64el_malta_yamon: ... console: System controller/revision = Galileo / GT_64120A-B-0 console: Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00 console: Processor ID/revision = 0x82 (MIPS 20Kc) / 0xa0 ... console: YAMON> PASS (1.89 s) RESULTS : PASS 2 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 4.57 s YAMON does some endian-swapped acceses on the ISD<->PCI CFG/DATA registers. These tests are useful to debug cross-endianness issues, in particular on big-endian host. Signed-off-by: Philippe Mathieu-Daudé --- tests/avocado/machine_mips_malta.py | 52 ++++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/tests/avocado/machine_mips_malta.py b/tests/avocado/machine_mips_malta.py index f1895d59f3..a3b0b55305 100644 --- a/tests/avocado/machine_mips_malta.py +++ b/tests/avocado/machine_mips_malta.py @@ -11,11 +11,13 @@ import gzip import logging -from avocado import skipUnless -from avocado_qemu import QemuSystemTest -from avocado_qemu import wait_for_console_pattern -from avocado.utils import archive from avocado import skipIf +from avocado import skipUnless +from avocado.utils import archive +from avocado_qemu import QemuSystemTest +from avocado_qemu import exec_command_and_wait_for_pattern +from avocado_qemu import interrupt_interactive_console_until_pattern +from avocado_qemu import wait_for_console_pattern NUMPY_AVAILABLE = True @@ -118,3 +120,45 @@ def test_mips_malta_i6400_framebuffer_logo_8cores(self): :avocado: tags=mips:smp """ self.do_test_i6400_framebuffer_logo(8) + +class MaltaMachine(QemuSystemTest): + + def do_test_yamon(self): + """ + :avocado: tags=arch:mipsel + :avocado: tags=arch:mips64el + :avocado: tags=machine:malta + """ + rom_url = ('http://www.imgtec.com/tools/mips-tools/downloads/' + 'yamon/yamon-bin-02.22.zip') + rom_hash = '8da7ecddbc5312704b8b324341ee238189bde480' + zip_path = self.fetch_asset(rom_url, asset_hash=rom_hash) + + archive.extract(zip_path, self.workdir) + yamon_path = os.path.join(self.workdir, 'yamon-02.22.bin') + + self.vm.set_console() + self.vm.add_args('-bios', yamon_path) + self.vm.launch() + + prompt = 'YAMON>' + pattern = 'YAMON ROM Monitor' + interrupt_interactive_console_until_pattern(self, pattern, prompt) + wait_for_console_pattern(self, prompt) + self.vm.shutdown() + + def test_mipsel_malta_yamon(self): + """ + :avocado: tags=arch:mipsel + :avocado: tags=machine:malta + :avocado: tags=endian:little + """ + self.do_test_yamon() + + def test_mips64el_malta_yamon(self): + """ + :avocado: tags=arch:mips64el + :avocado: tags=machine:malta + :avocado: tags=endian:little + """ + self.do_test_yamon()