From patchwork Tue Jan 17 01:40:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 645538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F347CC54EBE for ; Tue, 17 Jan 2023 01:40:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234405AbjAQBkt (ORCPT ); Mon, 16 Jan 2023 20:40:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234550AbjAQBkj (ORCPT ); Mon, 16 Jan 2023 20:40:39 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6EA1298F6; Mon, 16 Jan 2023 17:40:32 -0800 (PST) X-UUID: eb62f5d4960711eda06fc9ecc4dadd91-20230117 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6oPqNoh4XwViDpcqgPnVTYVHmgJBWp1+827qEDxJS0Q=; b=oUzzpq7ebqwSk/gnoBji/C7Uac+qDLRj3G8PgHtARt3uNO4HpgenaZ9BaHQ24DNIqyg3t7U9uaomra2UnSSXHVzYe+tqh4y43Sq38Cnnle8FnIUFkgtfx2TIy8+dg+zzQu6g1BTqtU/3N18jjp4ZCNt0QpmAwb7zRcpzSxVSlng=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18, REQID:42189052-ff89-48be-ab81-0cebf943c609, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:3ca2d6b, CLOUDID:8258d454-dd49-462e-a4be-2143a3ddc739, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: eb62f5d4960711eda06fc9ecc4dadd91-20230117 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1215428695; Tue, 17 Jan 2023 09:40:27 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 17 Jan 2023 09:40:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 17 Jan 2023 09:40:26 +0800 From: Allen-KH Cheng To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , CC: , , , , , Allen-KH Cheng Subject: [PATCH v3 1/2] dt-bindings: watchdog: mtk-wdt: Add reset-by-toprgu support Date: Tue, 17 Jan 2023 09:40:22 +0800 Message-ID: <20230117014023.2993-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230117014023.2993-1-allen-kh.cheng@mediatek.com> References: <20230117014023.2993-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org In some applications, the mtk-wdt requires the TOPRGU (Top Reset Generation Unit) to reset timer after system resets. Add optional mediatek,reset-by-toprgu property to enable it. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index b3605608410c..55b34461df1b 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -52,6 +52,12 @@ properties: description: Disable sending output reset signal type: boolean + mediatek,reset-by-toprgu: + description: The Top Reset Generation Unit (TOPRGU) generates reset signals + and distributes them to each IP. If present, the watchdog timer will be + reset by TOPRGU once system resets. + type: boolean + '#reset-cells': const: 1 From patchwork Tue Jan 17 01:40:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 645537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46CD4C678D8 for ; Tue, 17 Jan 2023 01:40:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235113AbjAQBku (ORCPT ); Mon, 16 Jan 2023 20:40:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235008AbjAQBkk (ORCPT ); Mon, 16 Jan 2023 20:40:40 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A613B26874; Mon, 16 Jan 2023 17:40:33 -0800 (PST) X-UUID: eb64d476960711eda06fc9ecc4dadd91-20230117 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KIYgMczl2d+gSz+cbdTqjNO5HXOYoOO5PWiSiasILCQ=; b=sOiXUME4H62SMbbAj7eRHhgSuX9R3qs6TjJrvHdY2PlH5JGnU3yw4XQKbNl0vbAc0v87CttgAwQtX2G3Xj3jQz1nezyJj7CbkkGhkiTiIwA442NSLrAFjQo+Cd1+MQX1+1vFcW2WJfDqtzalh2xRZG36MPnuhtOhPjOM6zM0hTQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18, REQID:4344885f-de4a-4b7a-a0fd-64d6177cb78a, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:3ca2d6b, CLOUDID:71486f8c-8530-4eff-9f77-222cf6e2895b, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: eb64d476960711eda06fc9ecc4dadd91-20230117 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 248583976; Tue, 17 Jan 2023 09:40:27 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 17 Jan 2023 09:40:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 17 Jan 2023 09:40:26 +0800 From: Allen-KH Cheng To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , CC: , , , , , Allen-KH Cheng Subject: [PATCH v3 2/2] watchdog: mtk_wdt: Add reset_by_toprgu support Date: Tue, 17 Jan 2023 09:40:23 +0800 Message-ID: <20230117014023.2993-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230117014023.2993-1-allen-kh.cheng@mediatek.com> References: <20230117014023.2993-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org In some cases, the MediaTek watchdog requires the TOPRGU to reset timer after system resets. Provide a reset_by_toprgu parameter for configuration. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 3e6212591e69..a9c437598e7e 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -50,6 +50,7 @@ #define WDT_MODE_IRQ_EN (1 << 3) #define WDT_MODE_AUTO_START (1 << 4) #define WDT_MODE_DUAL_EN (1 << 6) +#define WDT_MODE_CNT_SEL (1 << 8) #define WDT_MODE_KEY 0x22000000 #define WDT_SWRST 0x14 @@ -70,6 +71,7 @@ struct mtk_wdt_dev { spinlock_t lock; /* protects WDT_SWSYSRST reg */ struct reset_controller_dev rcdev; bool disable_wdt_extrst; + bool reset_by_toprgu; }; struct mtk_wdt_data { @@ -279,6 +281,8 @@ static int mtk_wdt_start(struct watchdog_device *wdt_dev) reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); if (mtk_wdt->disable_wdt_extrst) reg &= ~WDT_MODE_EXRST_EN; + if (mtk_wdt->reset_by_toprgu) + reg |= WDT_MODE_CNT_SEL; reg |= (WDT_MODE_EN | WDT_MODE_KEY); iowrite32(reg, wdt_base + WDT_MODE); @@ -408,6 +412,9 @@ static int mtk_wdt_probe(struct platform_device *pdev) mtk_wdt->disable_wdt_extrst = of_property_read_bool(dev->of_node, "mediatek,disable-extrst"); + mtk_wdt->reset_by_toprgu = + of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu"); + return 0; }