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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 18-20020a170906311200b0084b89c66eb5sm16179883ejx.4.2023.01.19.05.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 05:22:50 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH] ARM: dts: qcom: apq8064: add second DSI host and PHY Date: Thu, 19 Jan 2023 15:22:49 +0200 Message-Id: <20230119132249.2480022-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add second DSI host and PHY available on the APQ8064 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 69 ++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b7e5b45e1c04..3ae6abd85f3d 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -865,8 +865,8 @@ mmcc: clock-controller@4000000 { <&gcc PLL8_VOTE>, <&dsi0_phy 1>, <&dsi0_phy 0>, - <0>, - <0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, <&hdmi_phy>; clock-names = "pxo", "pll3", @@ -1342,6 +1342,71 @@ dsi0_phy: phy@4700200 { status = "disabled"; }; + dsi1: dsi@5800000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x05800000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&mmcc DSI2_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI2_CLK>, + <&mmcc DSI2_BYTE_CLK>, + <&mmcc DSI2_PIXEL_CLK>, + <&mmcc DSI2_ESC_CLK>; + clock-names = "iface", "bus", "core_mmss", + "src", "byte", "pixel", + "core"; + + assigned-clocks = <&mmcc DSI2_BYTE_SRC>, + <&mmcc DSI2_ESC_SRC>, + <&mmcc DSI2_SRC>, + <&mmcc DSI2_PIXEL_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi0_phy 1>; + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi1_phy>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + + dsi1_phy: dsi-phy@5800200 { + compatible = "qcom,dsi-phy-28nm-8960"; + #clock-cells = <1>; + #phy-cells = <0>; + + reg = <0x05800200 0x100>, + <0x05800300 0x200>, + <0x05800500 0x5c>; + reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; + clock-names = "iface", "ref"; + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&pxo_board>; + status = "disabled"; + }; mdp_port0: iommu@7500000 { compatible = "qcom,apq8064-iommu";