From patchwork Wed Apr 17 20:43:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 162427 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp5955816jan; Wed, 17 Apr 2019 13:44:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqytK4dZMK5JHDEPVFRSdxZIEUVeHfduLctDCerYOHZncA5zztai95OjE+IYDIzWkVeVOumO X-Received: by 2002:a17:902:bf44:: with SMTP id u4mr4286960pls.171.1555533884174; Wed, 17 Apr 2019 13:44:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555533884; cv=none; d=google.com; s=arc-20160816; b=vq64cI3Q63nv8AdprrXFWwTmS0S94xw5j7+Iney51UhvCLAR5fxWh6REsEXAXJLGMG wr5TmJ+kFA+C7cCz3cFHFQhXzVPU8VpxfkVq4oXcQ+IjnOeRGM7PEW/IC54R32I7q939 WD3mOkZtHZ1kA/+MyoreLaiXNZRtwrrYuTRDdLgv79i2cwLyRfl7fDEDecFPp61Gxjcj 28Ox5Rq6BDvdpxqSgKMMmN11ApnY3WKwFmj0pePPxwB4YEz91/3XEQxC6G0I/Ri7WG84 PfUBuNc2+yJfiYNFmGEOoGQxNOYoSuZUV7jfCxXTNrZESTC6ltqGek+iAgIEkPg8oTh1 /8XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=85XK5dFLbNA8+J3uTS62n225ZxyTN5YNEbzJYjOQJYI=; b=Dp224aOoK/uPNDBYgr5NSvfHhw5EYl2lTeszf2U2Qmqy2Eq6jkCZFPtFiNWtgTvBso m5uL02q4Zgs74GG7SjFHU8BZBEbMLSxrciRsCT2c2lGW2t9JJc25g1+hQLFCuSEkE2vd MwsbOPrnWKDdt4rsm5JEYPziLbbxwAVHL2IafLKLZfBDAi8Br1tChGjRL/ZPryg7LxA7 totA8IHZ1zQS7zdchrPAjMGByYGfEGWSXzFyxoPHy7qgrNfvEC7bfIZJ+vTfTxnOBL4n AZRWzFb+693GlLq8iZrrGhMownkymnWhwGdrN0eVIG28A8iKvTmIlOccsofxYWWdf+gV fQ/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=0CMRmUqU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id c20sm98716866wre.28.2019.04.17.13.44.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2019 13:44:06 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] mmc: meson-gx: remove open coded read with timeout Date: Wed, 17 Apr 2019 22:43:49 +0200 Message-Id: <20190417204355.469-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190417204355.469-1-jbrunet@baylibre.com> References: <20190417204355.469-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is already a function available to poll a register until a condition is met. Let's use it instead of open coding it. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 2eba507790e4..2deeacc051b1 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -1100,7 +1101,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) static int meson_mmc_wait_desc_stop(struct meson_host *host) { - int loop; u32 status; /* @@ -1110,20 +1110,10 @@ static int meson_mmc_wait_desc_stop(struct meson_host *host) * If we don't confirm the descriptor is stopped, it might raise new * IRQs after we have called mmc_request_done() which is bad. */ - for (loop = 50; loop; loop--) { - status = readl(host->regs + SD_EMMC_STATUS); - if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) - udelay(100); - else - break; - } - if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) { - dev_err(host->dev, "Timed out waiting for host to stop\n"); - return -ETIMEDOUT; - } - - return 0; + return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status, + !(status & (STATUS_BUSY | STATUS_DESC_BUSY)), + 100, 5000); } static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id) From patchwork Wed Apr 17 20:43:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 162422 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp5955380jan; Wed, 17 Apr 2019 13:44:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqx34ns4uvdbFp+4lH70kbF+g02oMbjhDEcc6BsjgAIGMZj+WD9degUl4dvzxkMcDPKqxocJ X-Received: by 2002:a63:1d26:: with SMTP id d38mr78983813pgd.357.1555533856817; Wed, 17 Apr 2019 13:44:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555533856; cv=none; d=google.com; s=arc-20160816; b=djDUz9Ko/hZ25xaUa/a4p+rJwAkKqEvDNIsL+mChkYdcgDXa7wmN48T9yqqB5Jd6a9 d5iOBSPUKOy6VdmUy5jIoLWCdhvNPOiuuh4aYJDBu/8mJhyj+klWHZo0hq4hBU6BZAV8 CBUR17kNp4bREKBL9GiZ5Uux5ygZvuDhYUoffShwc3qKe2mOy7pcmjHemtSZbWTlVnP6 Lh/lgPfwQw+PnM7kHkY8w6z7ZcNJA4P7wolWtbPFkq/X06gFXz4JvdMkGkvTI5naoncW fNWNUyUrS5jxNc1Csy7Z3qsGxpyIQji0rCvPHMIT0F9VcNfI/XxvNnnQFArrERrythvp SeqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=w1pW48pbPFvZbhJkwoKxPVapl0Fl2yGEGKo5zLNjkdw=; b=O7FiG8EtcPTooVsT6ynkYphje+10xa4DmhPRpsQivIisWJwsre1WOiLiPrvJs5VvVz s/MQJ2Ql5ZNgmZgm0aoZU6oXgZkIvtyHBaEGoFF333XehkgxDIRgZGQ3k2jroahLRAB/ KVlPmzspJ5kU/m7LTHRF4XK1sUh23Dixb3WL/Tk7FuIFFOXqePzdOBN6NY08s5NDjXG9 Qctxi69BcNd50iILACk9+tEDEpOcJ6bx6wIKww5kDUw0d//HjoUTpRTitBHpYj4g+F45 kCKmekWQ2MNca/naxang04nvA/ULh8xKFpThdtzt3u2NXmb8fy+qm7wwF0HEYCCoIqmb oQ+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=1FR1Pacd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id c20sm98716866wre.28.2019.04.17.13.44.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2019 13:44:07 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] mmc: meson-gx: ack only raised irq Date: Wed, 17 Apr 2019 22:43:50 +0200 Message-Id: <20190417204355.469-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190417204355.469-1-jbrunet@baylibre.com> References: <20190417204355.469-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is merely a clean up. It makes sense to only ack raised irqs instead of acking everything all the time. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 2deeacc051b1..8b690ecde4c5 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1082,9 +1082,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) } out: - /* ack all enabled interrupts */ - writel(irq_en, host->regs + SD_EMMC_STATUS); - if (cmd->error) { /* Stop desc in case of errors */ u32 start = readl(host->regs + SD_EMMC_START); @@ -1096,6 +1093,9 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) if (ret == IRQ_HANDLED) meson_mmc_request_done(host->mmc, cmd->mrq); + /* ack all raised interrupts */ + writel(status, host->regs + SD_EMMC_STATUS); + return ret; } From patchwork Wed Apr 17 20:43:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 162423 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp5955421jan; Wed, 17 Apr 2019 13:44:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqx0e8GHrSm2U5f3lPuD3ONqOSmy+4st+BBILoAwxltodDoT5hOMK+QqW1hWKXpLh69Evfh8 X-Received: by 2002:a17:902:bc85:: with SMTP id bb5mr64805151plb.310.1555533859387; Wed, 17 Apr 2019 13:44:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555533859; cv=none; d=google.com; s=arc-20160816; b=VGnWg3IjyXH9vDc8xNcPQgrkZsZp6Vs+fl3EWRBHi/p2shwsQ889bTxf9bXyQSrP2q 7Gn4xux+tTBgQ7ocsWqTmFFtkciKbID5eGiHezteKCCIVA57SjHM/W3cyGEO2h45JRCV nBorQkv4o8bwR3XDFqi/uL3CNzRMa25lGT8/KM/5GnCJtKkeoEeaP0YBGUR5P6RPKnk2 vRZg76FFN8rLt38S0uknVrGVyBNS3TTAMaRzf+TIB0XG3UojUqvzuKn9NFy0TS5a6cBe vd8ESuGX1bMDs13oIc4i/1rKgmitZAKfWo0ld4HByY3zPou6TLxuSJwG+ehmd3XbzLiu sb4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kvQGbdki4sfylBEdmd2o1C+/gcCUzEF0u1B6+PlWzsU=; b=x4eR6KPZKP2mZw9Mfguk4fPbI+maDrJTc/lZgC6+PKsX9n3+47/oKUesx09ah64CsK klIENR2e8UvVcEOPlPh3IMcZKbKe9ITKv+/xVjqNd6uD9hl9Z/eGLtRHRv4gvoovdOk0 JWAs4qwHetcRTUNEIY6mKoDxsi9vL718ztC7izJFLqoYkAn7K9zH9B29GS9M0GN/i0eL T4hWHNAIPrWILhfHdKUwcIX/xLYES1OBQQnGG/weDhT2K05jQ4Ir06WHmPRGQg12VX3Z LmUujntIkxp+3frNhwVpCYk2pUkRXKyrYk7ArRU+z+YHuTVOoWKGct8TWT1NeIk/spfU 3QUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=bLeAeSCD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id c20sm98716866wre.28.2019.04.17.13.44.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2019 13:44:11 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes Date: Wed, 17 Apr 2019 22:43:53 +0200 Message-Id: <20190417204355.469-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190417204355.469-1-jbrunet@baylibre.com> References: <20190417204355.469-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Activating DDR in the Amlogic mmc controller, among other things, will divide the output clock by 2. So by activating it with clock on, we are creating a glitch on the output. Instead, let's deal with DDR when the clock output is off, when setting the clock. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 72 +++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 30 deletions(-) -- 2.20.1 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 118f09da8dfb..f77b9327a590 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -169,6 +169,7 @@ struct meson_host { struct clk *rx_clk; struct clk *tx_clk; unsigned long req_rate; + bool ddr; struct pinctrl *pinctrl; struct pinctrl_state *pins_default; @@ -384,16 +385,6 @@ static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, mmc_get_dma_dir(data)); } -static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios) -{ - if (ios->timing == MMC_TIMING_MMC_DDR52 || - ios->timing == MMC_TIMING_UHS_DDR50 || - ios->timing == MMC_TIMING_MMC_HS400) - return true; - - return false; -} - /* * Gating the clock on this controller is tricky. It seems the mmc clock * is also used by the controller. It may crash during some operation if the @@ -430,36 +421,41 @@ static void meson_mmc_clk_ungate(struct meson_host *host) writel(cfg, host->regs + SD_EMMC_CFG); } -static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) +static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate, + bool ddr) { struct mmc_host *mmc = host->mmc; - unsigned long rate = ios->clock; int ret; u32 cfg; - /* DDR modes require higher module clock */ - if (meson_mmc_timing_is_ddr(ios)) - rate <<= 1; - /* Same request - bail-out */ - if (host->req_rate == rate) + if (host->ddr == ddr && host->req_rate == rate) return 0; /* stop clock */ meson_mmc_clk_gate(host); host->req_rate = 0; + mmc->actual_clock = 0; - if (!rate) { - mmc->actual_clock = 0; - /* return with clock being stopped */ + /* return with clock being stopped */ + if (!rate) return 0; - } /* Stop the clock during rate change to avoid glitches */ cfg = readl(host->regs + SD_EMMC_CFG); cfg |= CFG_STOP_CLOCK; writel(cfg, host->regs + SD_EMMC_CFG); + if (ddr) { + /* DDR modes require higher module clock */ + rate <<= 1; + cfg |= CFG_DDR; + } else { + cfg &= ~CFG_DDR; + } + writel(cfg, host->regs + SD_EMMC_CFG); + host->ddr = ddr; + ret = clk_set_rate(host->mmc_clk, rate); if (ret) { dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n", @@ -471,12 +467,14 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios) mmc->actual_clock = clk_get_rate(host->mmc_clk); /* We should report the real output frequency of the controller */ - if (meson_mmc_timing_is_ddr(ios)) + if (ddr) { + host->req_rate >>= 1; mmc->actual_clock >>= 1; + } dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock); - if (ios->clock != mmc->actual_clock) - dev_dbg(host->dev, "requested rate was %u\n", ios->clock); + if (rate != mmc->actual_clock) + dev_dbg(host->dev, "requested rate was %lu\n", rate); /* (re)start clock */ meson_mmc_clk_ungate(host); @@ -750,6 +748,25 @@ static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); } +static int meson_mmc_prepare_ios_clock(struct meson_host *host, + struct mmc_ios *ios) +{ + bool ddr; + + switch (ios->timing) { + case MMC_TIMING_MMC_DDR52: + case MMC_TIMING_UHS_DDR50: + ddr = true; + break; + + default: + ddr = false; + break; + } + + return meson_mmc_clk_set(host, ios->clock, ddr); +} + static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -819,15 +836,10 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val &= ~CFG_BUS_WIDTH_MASK; val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); - val &= ~CFG_DDR; - if (meson_mmc_timing_is_ddr(ios)) - val |= CFG_DDR; - - err = meson_mmc_clk_set(host, ios); + err = meson_mmc_prepare_ios_clock(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); - writel(val, host->regs + SD_EMMC_CFG); dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val); } From patchwork Wed Apr 17 20:43:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 162425 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp5955498jan; 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id c20sm98716866wre.28.2019.04.17.13.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2019 13:44:13 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] mmc: meson-gx: remove Rx phase tuning Date: Wed, 17 Apr 2019 22:43:54 +0200 Message-Id: <20190417204355.469-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190417204355.469-1-jbrunet@baylibre.com> References: <20190417204355.469-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This remove all the code related to phase settings. Using the Rx phase for tuning has not been reliable. We had several issues over the past months, on both v2 and v3 mmc chips After discussing the issue matter with Amlogic, They suggested to set a phase shift of 180 between Core and Tx and use signal resampling for the tuning. Since we won't be playing with the phase anymore, let's remove all the clock code related to it and set the appropriate value on init. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 290 ++------------------------------ 1 file changed, 13 insertions(+), 277 deletions(-) -- 2.20.1 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index f77b9327a590..50b03c167435 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -49,6 +49,8 @@ #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) +#define CLK_PHASE_0 0 +#define CLK_PHASE_180 2 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) #define CLK_V2_ALWAYS_ON BIT(24) @@ -57,10 +59,6 @@ #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) #define CLK_V3_ALWAYS_ON BIT(28) -#define CLK_DELAY_STEP_PS 200 -#define CLK_PHASE_STEP 30 -#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) - #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask) #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask) #define CLK_ALWAYS_ON(h) (h->data->always_on) @@ -165,9 +163,8 @@ struct meson_host { void __iomem *regs; struct clk *core_clk; + struct clk *mux_clk; struct clk *mmc_clk; - struct clk *rx_clk; - struct clk *tx_clk; unsigned long req_rate; bool ddr; @@ -209,90 +206,6 @@ struct meson_host { #define CMD_RESP_MASK GENMASK(31, 1) #define CMD_RESP_SRAM BIT(0) -struct meson_mmc_phase { - struct clk_hw hw; - void __iomem *reg; - unsigned long phase_mask; - unsigned long delay_mask; - unsigned int delay_step_ps; -}; - -#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw) - -static int meson_mmc_clk_get_phase(struct clk_hw *hw) -{ - struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); - unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); - unsigned long period_ps, p, d; - int degrees; - u32 val; - - val = readl(mmc->reg); - p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask); - degrees = p * 360 / phase_num; - - if (mmc->delay_mask) { - period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, - clk_get_rate(hw->clk)); - d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask); - degrees += d * mmc->delay_step_ps * 360 / period_ps; - degrees %= 360; - } - - return degrees; -} - -static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc, - unsigned int phase, - unsigned int delay) -{ - u32 val; - - val = readl(mmc->reg); - val &= ~mmc->phase_mask; - val |= phase << __ffs(mmc->phase_mask); - - if (mmc->delay_mask) { - val &= ~mmc->delay_mask; - val |= delay << __ffs(mmc->delay_mask); - } - - writel(val, mmc->reg); -} - -static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees) -{ - struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw); - unsigned int phase_num = 1 << hweight_long(mmc->phase_mask); - unsigned long period_ps, d = 0, r; - uint64_t p; - - p = degrees % 360; - - if (!mmc->delay_mask) { - p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num); - } else { - period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, - clk_get_rate(hw->clk)); - - /* First compute the phase index (p), the remainder (r) is the - * part we'll try to acheive using the delays (d). - */ - r = do_div(p, 360 / phase_num); - d = DIV_ROUND_CLOSEST(r * period_ps, - 360 * mmc->delay_step_ps); - d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask)); - } - - meson_mmc_apply_phase_delay(mmc, p, d); - return 0; -} - -static const struct clk_ops meson_mmc_clk_phase_ops = { - .get_phase = meson_mmc_clk_get_phase, - .set_phase = meson_mmc_clk_set_phase, -}; - static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data) { unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC; @@ -492,8 +405,6 @@ static int meson_mmc_clk_init(struct meson_host *host) struct clk_init_data init; struct clk_mux *mux; struct clk_divider *div; - struct meson_mmc_phase *core, *tx, *rx; - struct clk *clk; char clk_name[32]; int i, ret = 0; const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; @@ -501,9 +412,11 @@ static int meson_mmc_clk_init(struct meson_host *host) u32 clk_reg; /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - clk_reg = 0; - clk_reg |= CLK_ALWAYS_ON(host); + clk_reg = CLK_ALWAYS_ON(host); clk_reg |= CLK_DIV_MASK; + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); writel(clk_reg, host->regs + SD_EMMC_CLOCK); /* get the mux parents */ @@ -539,9 +452,9 @@ static int meson_mmc_clk_init(struct meson_host *host) mux->mask = CLK_SRC_MASK >> mux->shift; mux->hw.init = &init; - clk = devm_clk_register(host->dev, &mux->hw); - if (WARN_ON(IS_ERR(clk))) - return PTR_ERR(clk); + host->mux_clk = devm_clk_register(host->dev, &mux->hw); + if (WARN_ON(IS_ERR(host->mux_clk))) + return PTR_ERR(host->mux_clk); /* create the divider */ div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL); @@ -552,7 +465,7 @@ static int meson_mmc_clk_init(struct meson_host *host) init.name = clk_name; init.ops = &clk_divider_ops; init.flags = CLK_SET_RATE_PARENT; - clk_parent[0] = __clk_get_name(clk); + clk_parent[0] = __clk_get_name(host->mux_clk); init.parent_names = clk_parent; init.num_parents = 1; @@ -562,192 +475,19 @@ static int meson_mmc_clk_init(struct meson_host *host) div->hw.init = &init; div->flags = CLK_DIVIDER_ONE_BASED; - clk = devm_clk_register(host->dev, &div->hw); - if (WARN_ON(IS_ERR(clk))) - return PTR_ERR(clk); - - /* create the mmc core clock */ - core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL); - if (!core) - return -ENOMEM; - - snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev)); - init.name = clk_name; - init.ops = &meson_mmc_clk_phase_ops; - init.flags = CLK_SET_RATE_PARENT; - clk_parent[0] = __clk_get_name(clk); - init.parent_names = clk_parent; - init.num_parents = 1; - - core->reg = host->regs + SD_EMMC_CLOCK; - core->phase_mask = CLK_CORE_PHASE_MASK; - core->hw.init = &init; - - host->mmc_clk = devm_clk_register(host->dev, &core->hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk))) + host->mmc_clk = devm_clk_register(host->dev, &div->hw); + if (WARN_ON(IS_ERR(host->mmc_clk))) return PTR_ERR(host->mmc_clk); - /* create the mmc tx clock */ - tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL); - if (!tx) - return -ENOMEM; - - snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev)); - init.name = clk_name; - init.ops = &meson_mmc_clk_phase_ops; - init.flags = 0; - clk_parent[0] = __clk_get_name(host->mmc_clk); - init.parent_names = clk_parent; - init.num_parents = 1; - - tx->reg = host->regs + SD_EMMC_CLOCK; - tx->phase_mask = CLK_TX_PHASE_MASK; - tx->delay_mask = CLK_TX_DELAY_MASK(host); - tx->delay_step_ps = CLK_DELAY_STEP_PS; - tx->hw.init = &init; - - host->tx_clk = devm_clk_register(host->dev, &tx->hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk))) - return PTR_ERR(host->tx_clk); - - /* create the mmc rx clock */ - rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL); - if (!rx) - return -ENOMEM; - - snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev)); - init.name = clk_name; - init.ops = &meson_mmc_clk_phase_ops; - init.flags = 0; - clk_parent[0] = __clk_get_name(host->mmc_clk); - init.parent_names = clk_parent; - init.num_parents = 1; - - rx->reg = host->regs + SD_EMMC_CLOCK; - rx->phase_mask = CLK_RX_PHASE_MASK; - rx->delay_mask = CLK_RX_DELAY_MASK(host); - rx->delay_step_ps = CLK_DELAY_STEP_PS; - rx->hw.init = &init; - - host->rx_clk = devm_clk_register(host->dev, &rx->hw); - if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk))) - return PTR_ERR(host->rx_clk); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000); ret = clk_set_rate(host->mmc_clk, host->mmc->f_min); if (ret) return ret; - clk_set_phase(host->mmc_clk, 180); - clk_set_phase(host->tx_clk, 0); - clk_set_phase(host->rx_clk, 0); - return clk_prepare_enable(host->mmc_clk); } -static void meson_mmc_shift_map(unsigned long *map, unsigned long shift) -{ - DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM); - DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM); - - /* - * shift the bitmap right and reintroduce the dropped bits on the left - * of the bitmap - */ - bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM); - bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift, - CLK_PHASE_POINT_NUM); - bitmap_or(map, left, right, CLK_PHASE_POINT_NUM); -} - -static void meson_mmc_find_next_region(unsigned long *map, - unsigned long *start, - unsigned long *stop) -{ - *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start); - *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start); -} - -static int meson_mmc_find_tuning_point(unsigned long *test) -{ - unsigned long shift, stop, offset = 0, start = 0, size = 0; - - /* Get the all good/all bad situation out the way */ - if (bitmap_full(test, CLK_PHASE_POINT_NUM)) - return 0; /* All points are good so point 0 will do */ - else if (bitmap_empty(test, CLK_PHASE_POINT_NUM)) - return -EIO; /* No successful tuning point */ - - /* - * Now we know there is a least one region find. Make sure it does - * not wrap by the shifting the bitmap if necessary - */ - shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM); - if (shift != 0) - meson_mmc_shift_map(test, shift); - - while (start < CLK_PHASE_POINT_NUM) { - meson_mmc_find_next_region(test, &start, &stop); - - if ((stop - start) > size) { - offset = start; - size = stop - start; - } - - start = stop; - } - - /* Get the center point of the region */ - offset += (size / 2); - - /* Shift the result back */ - offset = (offset + shift) % CLK_PHASE_POINT_NUM; - - return offset; -} - -static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode, - struct clk *clk) -{ - int point, ret; - DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM); - - dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n", - __clk_get_name(clk)); - bitmap_zero(test, CLK_PHASE_POINT_NUM); - - /* Explore tuning points */ - for (point = 0; point < CLK_PHASE_POINT_NUM; point++) { - clk_set_phase(clk, point * CLK_PHASE_STEP); - ret = mmc_send_tuning(mmc, opcode, NULL); - if (!ret) - set_bit(point, test); - } - - /* Find the optimal tuning point and apply it */ - point = meson_mmc_find_tuning_point(test); - if (point < 0) - return point; /* tuning failed */ - - clk_set_phase(clk, point * CLK_PHASE_STEP); - dev_dbg(mmc_dev(mmc), "success with phase: %d\n", - clk_get_phase(clk)); - return 0; -} - -static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) -{ - struct meson_host *host = mmc_priv(mmc); - int adj = 0; - - /* enable signal resampling w/o delay */ - adj = ADJUST_ADJ_EN; - writel(adj, host->regs + host->data->adjust); - - return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk); -} - static int meson_mmc_prepare_ios_clock(struct meson_host *host, struct mmc_ios *ios) { @@ -796,9 +536,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) /* disable signal resampling */ writel(0, host->regs + host->data->adjust); - /* Reset rx phase */ - clk_set_phase(host->rx_clk, 0); - break; case MMC_POWER_ON: @@ -1225,7 +962,6 @@ static const struct mmc_host_ops meson_mmc_ops = { .get_cd = meson_mmc_get_cd, .pre_req = meson_mmc_pre_req, .post_req = meson_mmc_post_req, - .execute_tuning = meson_mmc_execute_tuning, .card_busy = meson_mmc_card_busy, .start_signal_voltage_switch = meson_mmc_voltage_switch, };