From patchwork Wed Feb 1 13:58:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649163 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp300261pva; Wed, 1 Feb 2023 06:01:16 -0800 (PST) X-Google-Smtp-Source: AK7set8/xEs53ywnSBC1hy08n1IaKj92UjM4rEVuz3Azj+t90CvWQWf0Qm6gvYdej8whE6FKQcQh X-Received: by 2002:a05:6808:df8:b0:378:69f4:7f6c with SMTP id g56-20020a0568080df800b0037869f47f6cmr1046367oic.43.1675260076625; Wed, 01 Feb 2023 06:01:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260076; cv=none; d=google.com; s=arc-20160816; b=rZgiPnBe6VdvB8tCn3UONbmCam5xyF1gQr8a752UAQd6/q5poPBo61jf3L4Fh0oCln 53r7158dP3HfoTVJ4rw/ANS+01etM80oF82TLyPJcws+nu5MPp9AJxwEmFUIctUKG2hq kwAqP8GxEadPPeTFD9qzkB8qfsknP9asllG1HNLZunHfY0a7l3MSxG6avV1KfVcZF4G2 g11mAOrZXW3f/nwuZBj3GI5zpMCD3GnhDKzirmx8Q3xh/wtunL45TCv061HQJQHxib/c y2PMKifqnq0YWHVM0c/RZC9qjTttMv5BVem4ap7POpU+3l2exJkczWGSFOe31GutYvnD Ug/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=c6KJR1dXWQfbUVvWqz3TDKFjYpVTl3dj4ftXimlQA7Q=; b=YjxkjRk1qftEUi2/wGYT7x5B23Hw36VIwzOorklCI0WcUpXb0LXMHl7JpPjGC0RKNx ZzmBdtUojDL8DQt3tWkMr3imjB15Jz4wwwlklfTWirfkRWx9bJBvRqTpxYwYlDlX6Q6O Z5Z5eu1iFlH7lhGtkFoWRCcHxKi8j2E9M+LuQWdQGH9H5Mcri8l1XnyxxW2mrxk28Rj+ Mcs/yYJQutktKIIq8nZ1EK1m4FXGjhr0TPNWeiUk0sDjPw9beH9JKo/+e9G6V4IA0ppU JqJN2EPQoRfqmMSQSde73cqiPmDkT0BESvMsDTA1kWGSIekg8WxRisCFLtnN0mpfIMNg 9b0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oV7cLCaf; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id fb20-20020a0568083a9400b0036e3679a517si16802093oib.72.2023.02.01.06.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:01:16 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oV7cLCaf; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8DE9A85C79; Wed, 1 Feb 2023 14:59:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="oV7cLCaf"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 98EF1854C7; Wed, 1 Feb 2023 14:59:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9559385C62 for ; Wed, 1 Feb 2023 14:59:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x102f.google.com with SMTP id cq16-20020a17090af99000b0022c9791ac39so2251576pjb.4 for ; Wed, 01 Feb 2023 05:59:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c6KJR1dXWQfbUVvWqz3TDKFjYpVTl3dj4ftXimlQA7Q=; b=oV7cLCafCeSYNiYllvsaHvFTLH7Zyefad3ry78BNWQDDlZS8IDkGP2ldVxdIOR/s9/ 1uol2pxgWxKdfTWdbA2jmzAY719N0jxXmgKo+TyV4RFYHKa6iSxKPTy+hBFaIw5BPRLj tCOHpnfy9WJ7p8UbSAkEL7RY7gB0WhDKcq8CxTe1uJteWFfHFEVyUyBYoYNS0Gz+1dmU DNOUnxdtyZ+PQfwbLj+vjZ8x5P198fDdp0MRQo33U/5OPdo4h+0nSlVq0mBsQeMjaLKu u+71J16LdUk1poX3UPHzyhOX+N/OgZQ/hZLV9U+K5u/YgVeCxBGJevnJL7AKRFkc4ABR BdNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c6KJR1dXWQfbUVvWqz3TDKFjYpVTl3dj4ftXimlQA7Q=; b=N7KJEUPEs7fHBtYKU1fRVuYS+c9K1LbiPtLazo1VCFQCoIhH3kYiAY0adiQsQfhZvr arFxeWjWfkuD515S0JNmBafOXX/3vo5mKNG+Evl43P5YqE1SBBvfwWpTe9p5XG76GtSF uIFiD/2D8wnl0olHuFOxVqb1eC3TQ2iGHyWidxqU2CnEO4cF4yV6pG5ON9k4Clmy6E8q ZDxg7vOR2eF22n5053rkl8TArFycRwtEcabfbJMDkYlSzkpMzPSReM7TcDJpS4WitXIU N55MNUyovWCtzNEcvMRd9MK/fonqBKSJedsXlJWZpxNYC+J4drW7T78X4FNRrWZjDQ7+ smzg== X-Gm-Message-State: AO0yUKUyetytFAmq7yzkf5+TvVjkMcGBcYsf1KgVSeLb4nf04IHkzHXK 3mOB2dCug5PoEcyPjjvZcGKiDvGFdOp5rMVv X-Received: by 2002:a17:902:e0c5:b0:194:9324:7084 with SMTP id e5-20020a170902e0c500b0019493247084mr2458791pla.36.1675259958592; Wed, 01 Feb 2023 05:59:18 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:18 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 01/14] qcs404: sysmap: Don't map reserved memory ranges Date: Wed, 1 Feb 2023 19:28:48 +0530 Message-Id: <20230201135901.482671-2-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Currently u-boot maps whole of 1G RAM but there reserved memory ranges on QCS404 which are reserved for TrustZone, various firmware components etc. Any access to these reserved memory ranges causes a bus hang issue. So disable mapping for reserved memory ranges in u-boot. Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/sysmap-qcs404.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c index b7409031a0..64ca4adf1b 100644 --- a/arch/arm/mach-snapdragon/sysmap-qcs404.c +++ b/arch/arm/mach-snapdragon/sysmap-qcs404.c @@ -19,7 +19,19 @@ static struct mm_region qcs404_mem_map[] = { }, { .virt = 0x80000000UL, /* DDR */ .phys = 0x80000000UL, /* DDR */ - .size = 0x40000000UL, + .size = 0x05900000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x89600000UL, /* DDR */ + .phys = 0x89600000UL, /* DDR */ + .size = 0x162000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xa0000000UL, /* DDR */ + .phys = 0xa0000000UL, /* DDR */ + .size = 0x20000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { From patchwork Wed Feb 1 13:58:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649164 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp301366pva; Wed, 1 Feb 2023 06:02:36 -0800 (PST) X-Google-Smtp-Source: AK7set/3fGs0ZFkrlxW6K7YkarPq8jyRF2Tz/9aYb+mi/CYMPsmo2prU4+kc2ByDdMiIjzsy5HTy X-Received: by 2002:a05:6870:7386:b0:156:f2d1:14fc with SMTP id z6-20020a056870738600b00156f2d114fcmr1178602oam.34.1675260156698; Wed, 01 Feb 2023 06:02:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260156; cv=none; d=google.com; s=arc-20160816; b=Jzbh1uaoyaCzAiPJCP74pJQGseG2lZm7T+gI0uneQbBXh3DEWZkDgdgECdcjTBy71r QJHUUHVcijTEvJKbV6FX4VQgH3dFaKIoI02Dvqdl8IrMUvmDthWG090ZvGjF1EFyftbe OkaFfPzQzrOvd1lcDIaN7uq/gO12TR9W6pvScFTIoHDf+F3H8SAnBpQZWZI0UK4RAuFu h5hbv8nAn7inR/Y+d4whVUN4OA85TGnD9Xz6NIxNtWzxnI0qbH9tCgSon5s/P59YnAaT I+37xlm0tjYEW/ca7bURltE9fsaKksZrRYbVXDEYmJLAjSCP57qkFr5FM56bWB9ByyyG EIkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DnPqZxZKlu/mwL/JZ5NDglUAkFtE4vKdj9ILH6v2XIw=; b=zS4zhdwohSAaCSERxNzy+3oNMkd9r7bsFjUOBDkwn+zu+R12qicytYUrmFBL4KfCP4 pkWwFHSJXHAIo5X8pvkrelt22wMvz5geGnb5Bh7Fd24RcdSv8/DSYktEH1gV/jfZg4jf fWntwh97yX9POTzc9kFhOAEf8TNBGbyuoG17kXgZ9gkCDZKV7IVLPAfodiYoebTvmmxb shjfGR7FE90Ry8IhOUNdIA8AgVeCj4RH0vBaacFgUr+GR4eRU6D11Ybiix5+YaYKnnMO p3Q1rRcsh7xEQNFJ2Gh2pjem/ob4qQTNeXzlDcqJ5nu5DywD3k8Stnn/ona32ViCtiH+ wBtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EhVlihq+; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id z17-20020a05687042d100b001429ed359a5si5286096oah.202.2023.02.01.06.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:02:36 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EhVlihq+; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7522F85C92; Wed, 1 Feb 2023 15:00:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="EhVlihq+"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 470E985C71; Wed, 1 Feb 2023 14:59:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D852585C69 for ; Wed, 1 Feb 2023 14:59:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pl1-x632.google.com with SMTP id e6so10294651plg.12 for ; Wed, 01 Feb 2023 05:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DnPqZxZKlu/mwL/JZ5NDglUAkFtE4vKdj9ILH6v2XIw=; b=EhVlihq+WosHPHKKKCjNJXhaQFHITtp0SbLf23UWHRRBUDjN3FPnizfBbUpbRBMXJd 4aYJrHBfJcDQw0C6zMIth1klyaamcGkN2ie0PSBmMUguXFsb38SJV6vx6gyXCyYLp+XM VViz2+UH0M9kldwdDuy688H27DRtf1/8UzmvZ9jKRYbGkjwb5CKt5cvtJZxKXvdQL/zk G+fc6H2kURPD1vjWT4ORp1Stq2N6cQiH0AwOaFbowmvnakfLb4fBUUIyYv0VZ1qXZbAe 7xC3ogcTjhKj9KbFM0I5/GONTdSmrC4qY1WZP4crkgvbsDVbogpcykvnDflkbK7DbsWQ /9Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DnPqZxZKlu/mwL/JZ5NDglUAkFtE4vKdj9ILH6v2XIw=; b=1rY6H1BvxX7hwIr8FUtHQDj5iCCnnabKOwmMac9exb3/mVm4Fzh/ABYjnIwmASLsU9 fhT9Nqd4MeusCy7NyMQKySY9/LlJRu5coCF1eT6ndPNqC4f9Aet+f5/RVzosDqavzbqh 3Ut2ano3l2lYIi2t7QeS8gFq0Oju7T9sgUu3t0cLuwwl65tkfvEjmSZ3mHAEeU7pM0MV qy24tJnyVS++dU8UrHzrpp/iBCVNEtCfTTSgK8T8YehSiIRlyR0jC3o2xP0eogo4jwKd 3VZUzcM1QgUq+dTcOpzHHOOGrv7ZkNUgID4DHaciQMFqwkF+LGOU2Ta6ym5OaiSlgzM5 5dLQ== X-Gm-Message-State: AO0yUKXynmmGDKvta5BB/WA3I43w5CAniEALjFCAdoxVze9OYycVg+3P BiKjccta/C+WC4cEl9bMvEH6Ya05IUKjeZtT X-Received: by 2002:a17:903:2285:b0:196:5cb8:60e6 with SMTP id b5-20020a170903228500b001965cb860e6mr3704845plh.45.1675259962807; Wed, 01 Feb 2023 05:59:22 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:22 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 02/14] qcs404-evb: Enable msm_gpio driver support Date: Wed, 1 Feb 2023 19:28:49 +0530 Message-Id: <20230201135901.482671-3-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Sumit Garg --- arch/arm/dts/qcs404-evb.dts | 4 ++++ configs/qcs404evb_defconfig | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 0639af8fe3..c8bcf9f71d 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -40,6 +40,10 @@ pinctrl_north@1300000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x1300000 0x200000>; + gpio-controller; + gpio-count = <120>; + gpio-bank-name="soc"; + #gpio-cells = <2>; blsp1_uart2: uart { pins = "GPIO_17", "GPIO_18"; diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig index dae1551411..d64cd74269 100644 --- a/configs/qcs404evb_defconfig +++ b/configs/qcs404evb_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_DM_RESET=y CONFIG_MSM_SERIAL=y +CONFIG_MSM_GPIO=y CONFIG_SPMI_MSM=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y From patchwork Wed Feb 1 13:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649165 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp301769pva; Wed, 1 Feb 2023 06:03:03 -0800 (PST) X-Google-Smtp-Source: AK7set/6RJjwZc4GkynZM+rRQMNYEMLNjeWu0YPpx8riV/ReMfp43iypO2DHGgqgF5klIm+B4S1w X-Received: by 2002:a05:6871:714:b0:163:49a0:5557 with SMTP id f20-20020a056871071400b0016349a05557mr1080103oap.6.1675260182885; Wed, 01 Feb 2023 06:03:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260182; cv=none; d=google.com; s=arc-20160816; b=eruTzlhhsxIT8G7SFBGC4zS6zPgEbotf9G9SBl0J1Oqm9z01T7QeKZxDKI4K0Y+x4+ qrPwFSA2t3hqysGeP7TwZOLU/LwJp4eXfKKFU/RE80+W3ubRX7o5OvXAodWbRl6iCwi6 JIf6193sZatQ5YxXZH/M41i1BtiLOUS7qXxU4xuI6Uvdtqu950wU678jcA86N2XhqWFB 2vfJugASeC35K770T4M9yg5HlfPQyN19jcBMkJ8HGXaI2I2yXXvTMRmjAv2aqUR+5j1V Ioc9I0htAT3RFZhfI/3/fF6FBe93q7j719OQ/Cj1Ee5kDD7+0QibcAl3i6fLUOmE5ZAI GBtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wh9FITta3C+uiujkN9yOlTx3uqHPS8M4Fiy7NsSWCpk=; b=bXNve58+jYWXl0Tjs8ruecX4cEU3ftn5f99tL1ELDBYX21rkOesqskioC/KmZ2j+hl dk/Pe6mhNKk/4HYqo5UUsfjFiq7NtB6k6+WyMZTsZ6pOy1PmnBJcPADi06i8IKtnjJSS MHYyYpAUdk2BtIZkjS3di8jxUquUTtS4fJBJJTJQDJLC44daWOgGNVeTXakR+1pNcgeC beXd7kvuE/Nu4a3IvIK5Jm7kSD4xEK3F0OLsPrMUCZwtkIPrs5D7r0WCdoCzHUPOc63p h6YdY2CyOQMLR4H/OPD46rv01yC0Jz16VWzf7tXg2pqlbi3TiG8TpcwtSYRs1fVDPduK p0Gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JC7DO1r0; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id oi15-20020a0568702e0f00b0013bc222044esi16569612oab.178.2023.02.01.06.03.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:03:02 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JC7DO1r0; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E4E4F85C7C; Wed, 1 Feb 2023 15:00:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="JC7DO1r0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D938285C7A; Wed, 1 Feb 2023 14:59:44 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A826485AA5 for ; Wed, 1 Feb 2023 14:59:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x1033.google.com with SMTP id ha3-20020a17090af3c300b00230222051a6so2077195pjb.2 for ; Wed, 01 Feb 2023 05:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wh9FITta3C+uiujkN9yOlTx3uqHPS8M4Fiy7NsSWCpk=; b=JC7DO1r0kBc3NmQropa6tG2Lx3PXIZB+zIMrpjMAtkqQ629PZ3HEPx/WGVFPVnOo9I cmpE/ZRnc1zD+gT+oiq3OtwIGZF0ElyHG8AzrI9Jz3JzXTAmepJurAe8HAFDkmhjUr56 ZNTb2zohErBR+3uexT2tegCHbkeaEtKXo5j8fbUYQWwU+f0/gIV+U6cugo8WXW4X31MX +5J4Zkar0rQHvIcxPVtlkDCEP+lrsgPvAnAKZvBwQIzWGE9q4TJPHJYktCoC1IztCbCb zVVIxkYMbXQYTZY2xRzy24HxBOKJFSdVCRIzzrbLPtrLlVwtNSpKWPEDskqQr1fPmlBB X35w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wh9FITta3C+uiujkN9yOlTx3uqHPS8M4Fiy7NsSWCpk=; b=OqYwKjlHuXGhOydw6v3139kmGxAqoFRICuDniANSFJPHX4A3rxyFg9TDlyVUIk4skt toTPx9JgQFTLXMAg6/9bn1kLoq4l0jZ4vKvhelKZiAN/vsiTRunMJMd26O7H19gojG1d nG+RkI05nbZ/GglULmukAm4KSCh9U7qR2vmyz+7ikLAGwLtu2u9k9QixdXwcGYxh11+M /Tj/QOCq9NGBGjx7uajDDS+S/ExOEwp0SSj4swAx5PC+gSc6UAZw434ASqkZVmh25Mee 059T/STLveZW3bNcI0H6sC9ToE+jXCXzy6r5rSTw8tS0QuLGnYOKmxMGnLvt76PsAYra k80Q== X-Gm-Message-State: AO0yUKUZ3unU6vXcZvI3KvTIDVb1GOHbP3rjPB4BdBvTu3R/9DmCcc8m oozXkoS/2AXwpom6z2cp3kezj9oBVLdIECSi X-Received: by 2002:a17:903:22c3:b0:198:a49b:9f53 with SMTP id y3-20020a17090322c300b00198a49b9f53mr3110970plg.10.1675259967021; Wed, 01 Feb 2023 05:59:27 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:26 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 03/14] clocks: qcs404: Add support for ethernet clocks Date: Wed, 1 Feb 2023 19:28:50 +0530 Message-Id: <20230201135901.482671-4-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/clock-qcs404.c | 60 +++++++++++++++++++ .../include/mach/sysmap-qcs404.h | 14 +++++ 2 files changed, 74 insertions(+) diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c index 6fe92afe8d..b8f5691aae 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -18,6 +18,9 @@ /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(31) +#define CFG_CLK_SRC_GPLL1 BIT(8) +#define GPLL1_STATUS_ACTIVE BIT(31) + static struct vote_clk gcc_blsp1_ahb_clk = { .cbcr_reg = BLSP1_AHB_CBCR, .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, @@ -47,6 +50,13 @@ static struct pll_vote_clk gpll0_vote_clk = { .vote_bit = BIT(0), }; +static struct pll_vote_clk gpll1_vote_clk = { + .status = GPLL1_STATUS, + .status_bit = GPLL1_STATUS_ACTIVE, + .ena_vote = APCS_GPLL_ENA_VOTE, + .vote_bit = BIT(1), +}; + static const struct bcr_regs usb30_master_regs = { .cfg_rcgr = USB30_MASTER_CFG_RCGR, .cmd_rcgr = USB30_MASTER_CMD_RCGR, @@ -55,6 +65,22 @@ static const struct bcr_regs usb30_master_regs = { .D = USB30_MASTER_D, }; +static const struct bcr_regs emac_regs = { + .cfg_rcgr = EMAC_CFG_RCGR, + .cmd_rcgr = EMAC_CMD_RCGR, + .M = EMAC_M, + .N = EMAC_N, + .D = EMAC_D, +}; + +static const struct bcr_regs emac_ptp_regs = { + .cfg_rcgr = EMAC_PTP_CFG_RCGR, + .cmd_rcgr = EMAC_PTP_CMD_RCGR, + .M = EMAC_M, + .N = EMAC_N, + .D = EMAC_D, +}; + ulong msm_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -79,6 +105,20 @@ ulong msm_set_rate(struct clk *clk, ulong rate) case GCC_SDCC1_AHB_CLK: clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); break; + case GCC_ETH_RGMII_CLK: + if (rate == 250000000) + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0, + CFG_CLK_SRC_GPLL1); + else if (rate == 125000000) + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0, + CFG_CLK_SRC_GPLL1); + else if (rate == 50000000) + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0, + CFG_CLK_SRC_GPLL1); + else if (rate == 5000000) + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50, + CFG_CLK_SRC_GPLL1); + break; default: return 0; } @@ -111,6 +151,26 @@ int msm_enable(struct clk *clk) case GCC_USB2A_PHY_SLEEP_CLK: clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR); break; + case GCC_ETH_PTP_CLK: + /* SPEED_1000: freq -> 250MHz */ + clk_enable_cbc(priv->base + ETH_PTP_CBCR); + clk_enable_gpll0(priv->base, &gpll1_vote_clk); + clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0, + CFG_CLK_SRC_GPLL1); + break; + case GCC_ETH_RGMII_CLK: + /* SPEED_1000: freq -> 250MHz */ + clk_enable_cbc(priv->base + ETH_RGMII_CBCR); + clk_enable_gpll0(priv->base, &gpll1_vote_clk); + clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0, + CFG_CLK_SRC_GPLL1); + break; + case GCC_ETH_SLAVE_AHB_CLK: + clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR); + break; + case GCC_ETH_AXI_CLK: + clk_enable_cbc(priv->base + ETH_AXI_CBCR); + break; default: return 0; } diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h index e448faad2d..8920c4ee8f 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h @@ -12,6 +12,7 @@ /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x21000) +#define GPLL1_STATUS (0x20000) #define APCS_GPLL_ENA_VOTE (0x45000) #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) @@ -54,4 +55,17 @@ #define USB2A_PHY_SLEEP_CBCR (0x4102C) #define USB_HS_PHY_CFG_AHB_CBCR (0x41030) +/* ETH controller clock control registers */ +#define ETH_PTP_CBCR (0x4e004) +#define ETH_RGMII_CBCR (0x4e008) +#define ETH_SLAVE_AHB_CBCR (0x4e00c) +#define ETH_AXI_CBCR (0x4e010) +#define EMAC_PTP_CMD_RCGR (0x4e014) +#define EMAC_PTP_CFG_RCGR (0x4e018) +#define EMAC_CMD_RCGR (0x4e01c) +#define EMAC_CFG_RCGR (0x4e020) +#define EMAC_M (0x4e024) +#define EMAC_N (0x4e028) +#define EMAC_D (0x4e02c) + #endif From patchwork Wed Feb 1 13:58:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649166 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp302126pva; Wed, 1 Feb 2023 06:03:29 -0800 (PST) X-Google-Smtp-Source: AK7set92zOssFaLDCFw3sWptgBR83kw8bUddshr2KMnXg1AQjd+ZUBLesh4VtjjpGL7JMEnYqnX6 X-Received: by 2002:a9d:65c2:0:b0:68b:bc6c:d955 with SMTP id z2-20020a9d65c2000000b0068bbc6cd955mr1277914oth.17.1675260209459; Wed, 01 Feb 2023 06:03:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260209; cv=none; d=google.com; s=arc-20160816; b=X+WSgB1GXGc8d7XoSc0+dIialYov6klNZIOnQXVWt4a8kybHiRjdVaSpQakPmwkORq 3Ut7M87bhzx6PBIAh9lPvTQGNCdESJp39i1PDa2TTjJqNqFzEth2dMMlEggYz+WpVsI8 zL19NrLC5PMW8FcV8BV5ER5nVjqUkiNR0V/HysBvoKpekW3LXNY86vccsORBRApmnXZI 6v53rzDacBGEJJU1YmOCGNPHzRDNnS6Ofbxqqxau8zvKMvzb15QbiMjkIICNsLfAgj4t 1bomdCw4btFE/dGosF6KtX6y0sf+AwC2vWJXISbTCnG9PyM7LlEblrA4x22HwfDIClNK G23w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Uf0JUp0WOyuAxl1CUsKprRoREAUbOiStWI2VOsSFB6c=; b=bs9HGQhFq8lBHiW8BwclbYDUMJzUC3b9E9T6SKJ5Cq7BfKTsZuYGlnnSLoKdzlJygw WgSH7hRItALi8ZYfFlkAHS7Do5hWwCuq39P78skgyo5avH8yg0Bsc5C3dK1AxMsFmcsh N2d84jmBbrkezPnF67MkRK6t9/1yw0GfTcfln1EMfKv7EsSnfqyVTYm2IlKxf9cKmjO8 B3CkHZHMrmaSXPbuVjxY7zHMbsptEghsSPYyEZfWv81EOt08uCs0cjhkP6G8q55P64Ai 9brbZlVu+8Ca5z1i8y+govIyPsc7UjiYwX8iT++DjIWKpxMIUhz6noxF8oyRXeqFEH6K UK4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YkjnpVDI; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id cg3-20020a056830630300b0068bac2ed5cfsi14515457otb.240.2023.02.01.06.03.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:03:29 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YkjnpVDI; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 52CC885C83; Wed, 1 Feb 2023 15:02:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="YkjnpVDI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 47CBC85C79; Wed, 1 Feb 2023 14:59:43 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6985D854C7 for ; Wed, 1 Feb 2023 14:59:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pl1-x62e.google.com with SMTP id 5so18533849plo.3 for ; Wed, 01 Feb 2023 05:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uf0JUp0WOyuAxl1CUsKprRoREAUbOiStWI2VOsSFB6c=; b=YkjnpVDI7v2D6M1gT16zVguq5Ey+R3s2Cr3vuhuIhuONmfBOeT7gqx9Cp5KxAcaq7f hFWKqkmi96xXKiljcEauaVikJKmpykfDVFzP6cajKLrfqFg+WbNmLwoZ9m7WO/qTWXd4 lkwbC1J1Y27g08/RfWmzQY2ey9nPbU6xr4ij3FTrrGdxb8MCRz/jQKoCa+2/qJZj+DzW IARewkOcqrLJg6Y08SXLwWfohZA7OxxsRLKvn7u8norwTymi7SmRNCnF+QO0wiZIUHpz R6KkKlGfHZulCBvzh4Mww/PRE3G8QGjzTVE77+s9hcDKjEbDkC8CPGzorsA+6F/LJUPk 2Ymw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uf0JUp0WOyuAxl1CUsKprRoREAUbOiStWI2VOsSFB6c=; b=R2rJn53P9D3kAmYS1rlacgy5SgXGKuGfXwjEzHn6JQPJotl90pv4ZHQf0aAVyPK1F/ 8ITHg1tMPK4W5KeMdKylEC4LejlMHT1HGbm2GkJcBbxtzGYjPTuS0aG6mM5uHvW6LUdl GhaGtPpYXFiqvE9bUXzp8HcjJushmXvaY7oTtmvGKDxWngrpHl35Es9IRSbGQ+228djD R1o3eh9L3tZgRRBO+hpoe3MEYF7Q+65LxmHNxXMqvTsnx6RE7OuSE4il1KTqBjWwwH7H flw090ki3n8Sp/R8LCtEAGl2qcJ3ltQnsWidATeVyYAYRlAh6vbbCV2/42WTJEoIe9LD q2Ww== X-Gm-Message-State: AO0yUKXzDyz3YWp5JQytwRcBE9z3xt1dSetZpyLNOIc+MKVvr4KCIhsJ 2Y7kb8EjSnH5ZozUHK2KVhqRLjz0xVtHDCO/ X-Received: by 2002:a17:902:c943:b0:196:1cc3:74fb with SMTP id i3-20020a170902c94300b001961cc374fbmr2997025pla.50.1675259971237; Wed, 01 Feb 2023 05:59:31 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:30 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 04/14] pinctrl: qcs404: Enable ethernet pinmux options Date: Wed, 1 Feb 2023 19:28:51 +0530 Message-Id: <20230201135901.482671-5-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/pinctrl-qcs404.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c index 889ead0f57..5a7fbfd441 100644 --- a/arch/arm/mach-snapdragon/pinctrl-qcs404.c +++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c @@ -22,6 +22,13 @@ static const char * const msm_pinctrl_pins[] = { static const struct pinctrl_function msm_pinctrl_functions[] = { {"blsp_uart2", 1}, + {"rgmii_int", 1}, + {"rgmii_ck", 1}, + {"rgmii_tx", 1}, + {"rgmii_ctl", 1}, + {"rgmii_rx", 1}, + {"rgmii_mdio", 1}, + {"rgmii_mdc", 1}, }; static const char *qcs404_get_function_name(struct udevice *dev, From patchwork Wed Feb 1 13:58:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649167 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp302683pva; Wed, 1 Feb 2023 06:04:12 -0800 (PST) X-Google-Smtp-Source: AK7set+bYKD/3u7i6ctk/N8aSlkfWDkkxgiA2xjZEJ1m7Do2lj8TTvEFyVmJiDUZj3DOFj4omOXs X-Received: by 2002:a05:6830:1c72:b0:68d:3fc8:7c0b with SMTP id o50-20020a0568301c7200b0068d3fc87c0bmr645161otg.6.1675260252542; Wed, 01 Feb 2023 06:04:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260252; cv=none; d=google.com; s=arc-20160816; b=VBXHSD24sQlruO3wdsk5+78b90wEDI7RjdeQPXcUzE3/0hN0CTBK/XdVIaQgF+BoAY 8Y8UaUQbgZrfBYkeSPF9rwGxi90v60/3oNeRAv8oTWQ5EH2mfZeGJ5qPUnlHVY1ZTR80 oaPVcfFqid5IWI8G68B5NLSs5a5a306XlJRMWGzs+6GObc+10noe0uXrYFXSuAEXCTDc hreAUd6dX/dd8kcVK4m+5jrhn/GGNcbFtbg2aVKNXZTN65PUWbQozxAX6O6bkTOHH62b 3mw8UvQDBqP18P4gVu5WoQ0hTA062pZiIhPjGhxnqR8IrM7oygsJmXl8kmcRQGyuGxwm o5jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p4QXbhIBEYEVJTr0EjAPuGhsfyb+2nd1b+W+Go2gHcc=; b=ftKf0YFO9i076gwXX+YD9B0K1F+ELTFmnrumHpf0/K5wUQ6oIbxcPYyrSl0r4+dOyI PolMPkMZ4O8hJcEOqEOm+66VRO6D+1kPASxnBIRg9DLnIwXzOeTmZthD/m/yLYeaWhcz u4Ta1OvpBVDj6uTtnA4n9o3EpMfzLPy0GAMUdYWXEE1OSUBsCvmhXiuuZ/dZHlclJXfx YFkYG/yVgMSM3Akzjfr4OwPSfdkkvw/Y7D5Kdo+vABPHxr2J0kG3Wg01zr5rwjcvcl9C Cu57V/aef91utTCxftZtBcUBVVppTeIneCSngM5/WsZbL+3c4Hz+8Tmcbez8QkWFJBre jI+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lQWsPvJV; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id hl20-20020a0568701b1400b0016399c37e42si11113937oab.172.2023.02.01.06.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:04:12 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lQWsPvJV; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 809C185C8E; Wed, 1 Feb 2023 15:02:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="lQWsPvJV"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 86AF085C9E; Wed, 1 Feb 2023 15:00:15 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 730BE85C76 for ; Wed, 1 Feb 2023 14:59:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x1035.google.com with SMTP id rm7-20020a17090b3ec700b0022c05558d22so2065893pjb.5 for ; Wed, 01 Feb 2023 05:59:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p4QXbhIBEYEVJTr0EjAPuGhsfyb+2nd1b+W+Go2gHcc=; b=lQWsPvJVO0Ba983K0EudssG3FyuY1KSeDyvUtctJ5qD75SDw5ZSycI5f50Pdvl2bqC hb75sFBuQHj6g4M4LK9nntTNfw6DRyJNLp2xXE+HheVAiJF3GMJed/tdTlzomty6SHps pDtyuUBlX9egtyTArwJT9Fm0Aa2dNuFUE/HfnULmMogbTlKoWuaiT5awibrT67QGxiyr HEF02LIhzgbthkojaOJEOYeG+hrUhSA2nwcL+j/RxzxzzsVeV8V1e0bniiPrcKD4rbLk uO4SkgOv0Q4z1IHfkb2cpjdtE2OmCVvz6WaXzytQgxPKP+eht2ITZH8HmcHCOcunD8Ea cUEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p4QXbhIBEYEVJTr0EjAPuGhsfyb+2nd1b+W+Go2gHcc=; b=Smn31ZVxWvxZ3UQ0G/bMNbbVyGADsP/K6nwn5e6BwoHTXH2zlrRRAc8wiXFql3QPSr 0n1Z9KdxPLTKo9MyGtCsMyi3E6uE8VVrC5syOnAbbuoZLAoq+BLkS/iSMJa5rZZiSLir YFD6l5wGgDKs7sByZJ7G2X4yU1ATmSieQUWD2KjsKWlpORYL/xII+ejLkpJt6Nwhq0h3 FYfC0so0PeJrJwIKLeSr0d4TO2HtC7nyqbkGgH1qu5a5OODtDZxTJomjSDuOKgmzNmea PqoL4foiBA8jYn/tGLFqqjA5AvkJ/6ZByjIbt6Udcp+x+CdvJ8UDFQR5CBBjVWmxDCjN gzUg== X-Gm-Message-State: AO0yUKWg8JO2cYzk+3Bg/7n0rdmfC1RxaKJUdjljEn+UIidxfM8xw5NC CbCugFbZYK/PLDQQYzDHl25VTFJIjonZZ5xs X-Received: by 2002:a05:6a20:3d02:b0:bc:abc6:c7b with SMTP id y2-20020a056a203d0200b000bcabc60c7bmr19339775pzi.17.1675259975478; Wed, 01 Feb 2023 05:59:35 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:35 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 05/14] pinctrl-snapdragon: Get rid of custom drive-strength values Date: Wed, 1 Feb 2023 19:28:52 +0530 Message-Id: <20230201135901.482671-6-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Use standard pinconf drive-strength values from Linux DT bindings rather than ones based on custom u-boot header. These changes are in direction to make u-boot DTs for Qcom SoCs to be compatible with standard Linux DT bindings. Also, add support for pinconf bias-pull-up. Signed-off-by: Sumit Garg --- arch/arm/dts/dragonboard410c.dts | 3 +-- arch/arm/dts/dragonboard820c.dts | 3 +-- arch/arm/dts/qcom-ipq4019.dtsi | 1 - arch/arm/dts/qcs404-evb.dts | 1 - arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 8 ++++++- .../dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 ------------------- 6 files changed, 9 insertions(+), 29 deletions(-) delete mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index 59cf45eb17..9230dd3fd9 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -9,7 +9,6 @@ #include "skeleton64.dtsi" #include -#include / { model = "Qualcomm Technologies, Inc. Dragonboard 410c"; @@ -71,7 +70,7 @@ blsp1_uart: uart { function = "blsp1_uart"; pins = "GPIO_4", "GPIO_5"; - drive-strength = ; + drive-strength = <8>; bias-disable; }; }; diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index aaca681d2e..ad201d4874 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -8,7 +8,6 @@ /dts-v1/; #include "skeleton64.dtsi" -#include / { model = "Qualcomm Technologies, Inc. DB820c"; @@ -71,7 +70,7 @@ blsp8_uart: uart { function = "blsp_uart8"; pins = "GPIO_4", "GPIO_5"; - drive-strength = ; + drive-strength = <8>; bias-disable; }; }; diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi index 181732d262..6edc69da67 100644 --- a/arch/arm/dts/qcom-ipq4019.dtsi +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -9,7 +9,6 @@ #include "skeleton.dtsi" #include -#include #include #include diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index c8bcf9f71d..cc70afa4c8 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -9,7 +9,6 @@ #include "skeleton64.dtsi" #include -#include #include / { diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index ab884ab6bf..826dc51486 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -28,8 +28,9 @@ struct msm_pinctrl_priv { #define TLMM_GPIO_DISABLE BIT(9) static const struct pinconf_param msm_conf_params[] = { - { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, }; static int msm_get_functions_count(struct udevice *dev) @@ -89,6 +90,7 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: + argument = (argument / 2) - 1; clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), TLMM_DRV_STRENGTH_MASK, argument << 6); break; @@ -96,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), TLMM_GPIO_PULL_MASK); break; + case PIN_CONFIG_BIAS_PULL_UP: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK, argument); + break; default: return 0; } diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h deleted file mode 100644 index 615affb6f2..0000000000 --- a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * This header provides constants for Qualcomm Snapdragon pinctrl bindings. - * - * (C) Copyright 2018 Ramon Fried - * - */ - -#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H -#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H - -/* GPIO Drive Strength */ -#define DRIVE_STRENGTH_2MA 0 -#define DRIVE_STRENGTH_4MA 1 -#define DRIVE_STRENGTH_6MA 2 -#define DRIVE_STRENGTH_8MA 3 -#define DRIVE_STRENGTH_10MA 4 -#define DRIVE_STRENGTH_12MA 5 -#define DRIVE_STRENGTH_14MA 6 -#define DRIVE_STRENGTH_16MA 7 - -#endif From patchwork Wed Feb 1 13:58:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649168 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp303219pva; Wed, 1 Feb 2023 06:05:01 -0800 (PST) X-Google-Smtp-Source: AK7set+jFAR3x9yKCTiR1mWNmwj1V6bGAFef75KdBMLOBRMbrxxMZLdTaJIIWIL6FizpAJ+Rl1Nk X-Received: by 2002:a9d:1b66:0:b0:68b:b534:c8e4 with SMTP id l93-20020a9d1b66000000b0068bb534c8e4mr1422373otl.7.1675260301480; Wed, 01 Feb 2023 06:05:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260301; cv=none; d=google.com; s=arc-20160816; b=q9ETyfk+5WUJkgxcen3F8MQsCz1yVZFziaD2xbcImVwbPOFShVg1tlhm5dL8yh8VSO cQdWESE9eL48ZM4PBHZ4DazyYPjswE47Zt+77LV6ykCk3C46m5A1sulhLtSzhuG2u/tW RvJPglFvPGY0DTaHzGskKp78LcqIbdNjKBBjRJGZI6OHog4L0gKTFUYbvYLdWhJ7T/tu w/+w21zPlvKDQgCrLMXgseBTW2SFPUs7tjv3V2acUw9Yt4vGD1ls5eetrm+vwTVp/HSX 6N2j1JUttqYXwwgebDBdaUQ3iFb5z3m2pbt694iQjF0vbDbGVe5mJ8OLJTMoXXF/WWO8 bAgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nQ4N2iEXD19K17SmVs7Q6jYkWQq8B8obtRDPStpvTrA=; b=UfBJPfAnp9zvA6ajsrbq4SVIpNl9sWemzjIT4KEFX2GZBPJZ9SJRlgQEXCqwy8sxro 2zFCkZqHbaV90XZaWwhTyBipNiNXr7rxa7ppeaH2ea3Niyvi2k7wzVLw6XMkGEEMD+d1 C3ZtyGF7JdV6QivhlzDDWpG1ld1IWQR+SidJXN4wN1gVHFP4PbEk0kRDRk4PubS35gd8 oNOk5i1CEJj4L5dDjaTdLv/2ArvbfO+cZTYu83RIiQqmb5J9yjN3PSuhr04Q7vf/KPqR f7yPZrj8kP5QlkcPrNmufOzIa1cnhO9WfDs+y98zDrtB/wUZcEGNGcuiqWLptmE982mp qGjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rAaetirJ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id y1-20020a0568302a0100b0068be5783976si3826787otu.51.2023.02.01.06.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:05:01 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rAaetirJ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D3F8C85C9D; Wed, 1 Feb 2023 15:03:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="rAaetirJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 12DA485C52; Wed, 1 Feb 2023 15:00:48 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4AFE485C75 for ; Wed, 1 Feb 2023 14:59:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pl1-x632.google.com with SMTP id be8so18514824plb.7 for ; Wed, 01 Feb 2023 05:59:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nQ4N2iEXD19K17SmVs7Q6jYkWQq8B8obtRDPStpvTrA=; b=rAaetirJqBvIr/p8cDYKwoyrtahbriwVUL0Bf6emPuqapbCDGMMelpK4hJp8p/0VCa BaXG9GWy0J/RZA6eCQzSJd/mv4Wdir5eizX0N9ef2PE7pA774jKHb2bsXg2WJtH+Gapv 0XGOXFlY+8eN4Q7W6aF104z9BmMNGKLiACNhB0RwzNSAALe7jDqQqKzrdnHJKujARPQ2 g6xsqwy2dxvMmcFsuACfy3YNssuZiuOrvVZOXkdylJt7wR/TgKbpYN3Tvnm46ZKjULHt wQBSguT+XP9HL9t8u6OpthA9YRQcSG7jW4txIgxp7uxSJBlXb4pPncjCHa3n90aiK7px SU5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nQ4N2iEXD19K17SmVs7Q6jYkWQq8B8obtRDPStpvTrA=; b=w4dtpbtO1Shvx3t3FmyS+NIdEcjlBlUcxxHwOoUNmMrCvY65Vb/tnxb8Yh2dMpu8rJ PO5h2xhddf2Cf2sYxSCTxxamZp1ljz99inoBVPcZ0IGywAZJdDdOO5jtwDxv/qSgjbPW KvaPrkfDtz7JKeOxdLr6rOhlABqmslMB1HVUFBIeayvSQ+fDZUDGOIyqgY5l+bRwxGnP bvmQCyRu2Su3smWjrdw53jZI67+1sZwp5z0ZHhDG+SQbMt0sE63ocFzgnlpGwt1fDMr0 GRVjjUN+bq/uSwPpPohMzRWMTQIjKdnF4bteuWXAEP/YA/Z24CFLIwpfMDhyw6ualPAU mL6w== X-Gm-Message-State: AO0yUKUkHjdy5m11W3fBnBT+hvvuREj5x7icTAC0CpGsLVu/bNOe6EC4 9Vil2UiJXqCl2VAhz/Qzef96UMttjaG7Ph0F X-Received: by 2002:a17:902:c652:b0:196:35cf:3b11 with SMTP id s18-20020a170902c65200b0019635cf3b11mr2394519pls.55.1675259979708; Wed, 01 Feb 2023 05:59:39 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:39 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 06/14] net: dwc_eth_qos: Make eqos_get_tick_clk_rate callback optional Date: Wed, 1 Feb 2023 19:28:53 +0530 Message-Id: <20230201135901.482671-7-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- drivers/net/dwc_eth_qos.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index afc47b56ff..753a912607 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -774,10 +774,13 @@ static int eqos_start(struct udevice *dev) pr_err("eqos_calibrate_pads() failed: %d", ret); goto err_stop_resets; } - rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); - val = (rate / 1000000) - 1; - writel(val, &eqos->mac_regs->us_tic_counter); + if (eqos->config->ops->eqos_get_tick_clk_rate) { + rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); + + val = (rate / 1000000) - 1; + writel(val, &eqos->mac_regs->us_tic_counter); + } /* * if PHY was already connected and configured, From patchwork Wed Feb 1 13:58:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649169 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp303784pva; Wed, 1 Feb 2023 06:05:54 -0800 (PST) X-Google-Smtp-Source: AK7set/SdWANI+u7v7fIDV2sOpViJV6/uYOapMWd2OSzlQjFe9jqbXdoGjGBZHYQVVFY+JHicoW0 X-Received: by 2002:aca:3e45:0:b0:368:8745:70a8 with SMTP id l66-20020aca3e45000000b00368874570a8mr1003251oia.50.1675260353827; Wed, 01 Feb 2023 06:05:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260353; cv=none; d=google.com; s=arc-20160816; b=L6YwiKSp0g/xt2fBVM1jq4tnJ8dfOV5lI9B9chqyYRqqOyEw9rjUBPsZHaS04SvrjW idmGmiK3J217Vr2D0yL6gvDxwiMst3nLVHMOw+3wt2um9sYGTYrfdwXjJtZsh+gYKWPi AbpnqUfS+WVppvvcNZsKhY6Db+KwBt9FaYHr9o8zZeIpWLR2hNY0hCPDcSZ0TtI7DGuz SnXkiTuWFGnz6IgA3u9lQvJR8YLjx1iHoacutAwL1BOYRG2rMQvs57MlGh7gofHbBJLa 7xUtaa2opu7tgsHq3dFyCdNqAzUrYB137nd90TUKKxdeVM/s0l45Nc1+GZ3976kmdKq0 24fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EykesWwKz9OUTCa4KBwIKHRquT8YbapR9SO1jwz0yT0=; b=a5BPBQatVyI0W9swepfee7f2xOwBC+TBgrz+N62IjCUtSNs+CmcvA55m3P0WiUpXdf 7InnJwuWv5pPU0C/h+suultugoHpxzP12W180EiPbSBBX0H7x3BS+EcEUM+E2OI4q3My xlO/74n1nlO1vsRJlOknEcrj8yO0jk5ufs+iqzE/hyvHONjKXnz+usJlhqakGHDoLpjC JmUcRy3XzAkSFRKPi3bWVmddJxxhZZEaitxuWdMglfQ/uMxivbrMZYmYt4cCIbBjkIQ5 APSgIarRu15oiODu9n8k/+hehJpU1AG2prywjOVYYv9IXG40M7B2q4CSVh4g4kp+Az+r ESQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xTwKq2xs; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id v23-20020acaac17000000b003787ab9820fsi5315203oie.265.2023.02.01.06.05.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:05:53 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xTwKq2xs; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2F2E185CBA; Wed, 1 Feb 2023 15:04:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="xTwKq2xs"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 427FB85C94; Wed, 1 Feb 2023 15:01:24 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 24E8C85C7E for ; Wed, 1 Feb 2023 14:59:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pl1-x629.google.com with SMTP id m13so6617206plx.13 for ; Wed, 01 Feb 2023 05:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EykesWwKz9OUTCa4KBwIKHRquT8YbapR9SO1jwz0yT0=; b=xTwKq2xs7aqzNWaTEbCWY8N44jtrgJoEnIR5FfCOIj1OGdCJZ+8QAICR3V7UZro4lY 30TdEHmVPVmmsxBHdK2Xn9Ss6I5FBSch4a01370mec0kn6F5VFAYq4iPoTu+bLnoBqto xTXwmkcY99giXKGE3GWJFgCUjsHtDai4nQolIwxfsrj5wBkBbli7savOfejlUAD7YGsh 97yo7uLuq8aTrzhwnBNDKDZRVeIotOB5fyGfbh9fngYYCYPB9HvoFbwBfe1nITQD7gJe ko0L26rdmmz+deBTERFtRjyBpGcoGXXGBZydi2dSD/OzOXmOgYQNCIXVmebednD+BNIM kKIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EykesWwKz9OUTCa4KBwIKHRquT8YbapR9SO1jwz0yT0=; b=h2DWoheEsw5w4efoleu4eW0Xr5pSYDYg616zPwEbQJ98cASErOsr7LerjepJeYSevW GhE4X295nmLc3euxOeBccYKKLWIuejxH4N6BVJj+rUfJ2VKITJd8dUAixTbKfJ1tfVNv 9XOXbebSaMLjHxZGMIzwLIvd739In16aTo5oF4h5dsNGuQxerLDbdFt5/xC6pIWSDeVa b1msdfJC0nE7zItUBEl5N19NG09b9NlybXYmV37baaPfd734Itjy35/8KDE9TPhCu20v I4Budq8j9zE89dACmInjOuE00jO++53NlCrFuyhRwEr1rw9Oz9FuyzO4kfc/CadXi6B3 B/Kg== X-Gm-Message-State: AO0yUKUaKAkJjvbNhy6lVKegqgU+v5G9dr/bk7Ql4S+29guLsoiTEXM9 kvcCNWG0rxMXOQ6qZavAm7hffRmc3UnNM1Wd X-Received: by 2002:a17:902:d4ce:b0:198:9bf8:298c with SMTP id o14-20020a170902d4ce00b001989bf8298cmr3617202plg.65.1675259983955; Wed, 01 Feb 2023 05:59:43 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:43 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 07/14] net: dwc_eth_qos: Allow platform to override tx/rx_fifo_sz Date: Wed, 1 Feb 2023 19:28:54 +0530 Message-Id: <20230201135901.482671-8-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The GMAC controller on QCS404 SoC (support added by upcoming patch) fails to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So allow platforms to override FIFO size using corresponding DT node properties. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- drivers/net/dwc_eth_qos.c | 19 +++++++++++++------ drivers/net/dwc_eth_qos.h | 1 + 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 753a912607..65b8556be2 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -852,12 +852,19 @@ static int eqos_start(struct udevice *dev) rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; - /* - * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. - * r/tqs is encoded as (n / 256) - 1. - */ - tqs = (128 << tx_fifo_sz) / 256 - 1; - rqs = (128 << rx_fifo_sz) / 256 - 1; + /* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */ + tx_fifo_sz = 128 << tx_fifo_sz; + rx_fifo_sz = 128 << rx_fifo_sz; + + /* Allow platform to override TX/RX fifo size */ + if (eqos->tx_fifo_sz) + tx_fifo_sz = eqos->tx_fifo_sz; + if (eqos->rx_fifo_sz) + rx_fifo_sz = eqos->rx_fifo_sz; + + /* r/tqs is encoded as (n / 256) - 1 */ + tqs = tx_fifo_sz / 256 - 1; + rqs = rx_fifo_sz / 256 - 1; clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK << diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 8fccd6f057..466a792de7 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -276,6 +276,7 @@ struct eqos_priv { bool started; bool reg_access_ok; bool clk_ck_enabled; + unsigned int tx_fifo_sz, rx_fifo_sz; }; void eqos_inval_desc_generic(void *desc); From patchwork Wed Feb 1 13:58:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649171 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp304188pva; Wed, 1 Feb 2023 06:06:26 -0800 (PST) X-Google-Smtp-Source: AK7set8pT1Yp3eGRCXPHdt9Y1fhGZJYbmL3xsP0YyZW07BalZPouoyFRNaVl1yAGxtzx5+p8LCc4 X-Received: by 2002:a05:6870:6587:b0:163:af13:c4e1 with SMTP id fp7-20020a056870658700b00163af13c4e1mr1066974oab.46.1675260385925; Wed, 01 Feb 2023 06:06:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260385; cv=none; d=google.com; s=arc-20160816; b=gFRV+SfoDYR+YNvjTwum8S7PpO4BVnvPbcmIIBZLG8b8YCzBfVFzVBVBys5IjoZ9ZW Q/+mGAJD6cTMdLM0+kwYOZlq1quEzEtKUETanR0Ojqfb/gYF9D9Mkh/QrGa7yJ0BZ1DN 0ND1WbFFh5GsLj/SLYbRHsissX08iBCHywDcJSnFjL59rk3l8TRvGaN3J/apVoMoabJg tfqAtvzUM2VJoFnupCtAerxO8NZNJelRj7Jy1vDv4SXoTW566aXmXlUB9vN+fStlSPGU hK2FroqCRAn3RUeRNdMHl5OCgU050oxnL9ZdkK3PnorjYe7ERANiNehOORFXfGLxarwR i5yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=802uP/qYFsXNpFPpKtLgraFSP3GdBPd001BAT0HwI10=; b=kuCLC//vWAd4MEhgBiadOW8ScTT5y4kWpOrDD15zX4trDcFpQIyX4AqdWZfJppLlm8 743nB/C4xBUjNYL9mgmEpmO46315jILDY7vubK8v42ySoOVMbMxIvDOwC5rnWjFLASOW 28tceUCtGQP8KchPBhbdLdnejWibk/kKc03YAfCxOkH7UAldn/PzopaegyILLbVvkPqt 2Z7n9r43yBqzaqiVFjvcmDxipXEk1aug7u8l+DETwAJxyhOUXXnzSKrByrnh8scLY8Z4 xjip74O7X/BnoRnskK+/8r9wuxPU30vzlD1dYCtHyiWbVas+ckSanQzS5hVVEvbWOMW6 FHzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UZNe5RMG; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id p23-20020a4a8e97000000b004d8c7860f85si15828691ook.59.2023.02.01.06.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:06:25 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UZNe5RMG; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5CCA085CB5; Wed, 1 Feb 2023 15:05:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UZNe5RMG"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7681385CAA; Wed, 1 Feb 2023 15:02:44 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8965585C7F for ; Wed, 1 Feb 2023 14:59:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x1034.google.com with SMTP id nm12-20020a17090b19cc00b0022c2155cc0bso2072876pjb.4 for ; Wed, 01 Feb 2023 05:59:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=802uP/qYFsXNpFPpKtLgraFSP3GdBPd001BAT0HwI10=; b=UZNe5RMGPscq5qrArIgxz75eOP9v6+E0Pp+4H/tO6g2NRzgeDdj9YeuiP2AYORBq3o BZwDSB/aKOvhjh8aXvVcpOa9Dw4Itdgl6AwiAAySfSwxL47f5FyLRdZ0rMh4knZ5NYd9 +Aojhd6oACsFnS+FICBANneQ5FAFTkeUDIh5cTibUadIAg9P+91/cqD2wazkkPEeAJx0 qAlONfXL5LW1faSI8FMlA2ufMgk1D4c+FRq+RKJGR1ScGG6qVol4/p9B+GJFbqvb+xnE 9thUGoCOuSFX9vgQgszHdlwQvKrOXt5zrOSiB059gDUY1EztZrnunPtWQ2TYQENWLA2B B6bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=802uP/qYFsXNpFPpKtLgraFSP3GdBPd001BAT0HwI10=; b=1pssOxtrtA7sHoyDcIMY+sIeUWvdTsHw0Zt8CYCQvQ8fFD39AP9zzHeonLDqjOgc9r FZr0r85p+8xTZQaMpTy5xQhQMZk86iG2q6aaZyVIfmbhOiuMtIJiZMRwmfQQ8DYnWP5q ow+We3Mr/1zGD4G3Qd82h9kJJEzjQbstzSRowoiUx2ps++XqEEn3d/qR5iQHhgwIrfq7 PsQt+LHiYVTIbLgWlO/Ak7PNiBRjlEzd7WgUWGg7NpCcU1THDj12ibohGsyVe7541vcm +HZgo4KhN4dlfaEs/yzrqs9HmR1NucWQXDPFjT0kIrIkT5+v4C8BlYtfHhsv5RjsIpYX +GYw== X-Gm-Message-State: AO0yUKXIDPsP4mfMLidUbiAmkxKQIBiq2dNh7BUWqWeAUPjNczmUfTvb oAKNk4bImCcViKHgSvVFMcl3Zjcz/PqNyjG0 X-Received: by 2002:a05:6a20:6aa1:b0:b8:6fe8:5ed7 with SMTP id bi33-20020a056a206aa100b000b86fe85ed7mr2236563pzb.44.1675259988229; Wed, 01 Feb 2023 05:59:48 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:47 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 08/14] net: dwc_eth_qos: Add Qcom ethernet driver glue layer Date: Wed, 1 Feb 2023 19:28:55 +0530 Message-Id: <20230201135901.482671-9-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The Qualcom ETHQOS hardware supports an RGMII macro which needs to be configured according to following link speeds: - SPEED_1000 - SPEED_100 - SPEED_10 So add a corresponding glue driver to configure RGMII macro. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 7 + drivers/net/dwc_eth_qos.h | 3 + drivers/net/dwc_eth_qos_qcom.c | 612 +++++++++++++++++++++++++++++++++ 5 files changed, 630 insertions(+) create mode 100644 drivers/net/dwc_eth_qos_qcom.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7873538cc2..815e1f9248 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -242,6 +242,13 @@ config DWC_ETH_QOS_TEGRA186 The Synopsys Designware Ethernet QOS IP block with specific configuration used in NVIDIA's Tegra186 chip. +config DWC_ETH_QOS_QCOM + bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with specific + configuration used in Qcom QCS404 SoC. + config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" depends on PCI diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5b4e60eea3..b009b10aca 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o +obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 65b8556be2..112deb546d 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1712,6 +1712,13 @@ static const struct udevice_id eqos_ids[] = { }, #endif +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM) + { + .compatible = "qcom,qcs404-ethqos", + .data = (ulong)&eqos_qcom_config + }, +#endif + { } }; diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 466a792de7..fddbe9336c 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -253,6 +253,7 @@ struct eqos_priv { struct eqos_mtl_regs *mtl_regs; struct eqos_dma_regs *dma_regs; struct eqos_tegra186_regs *tegra186_regs; + void *eqos_qcom_rgmii_regs; struct reset_ctl reset_ctl; struct gpio_desc phy_reset_gpio; struct clk clk_master_bus; @@ -277,6 +278,7 @@ struct eqos_priv { bool reg_access_ok; bool clk_ck_enabled; unsigned int tx_fifo_sz, rx_fifo_sz; + u32 reset_delays[3]; }; void eqos_inval_desc_generic(void *desc); @@ -286,3 +288,4 @@ void eqos_flush_buffer_generic(void *buf, size_t size); int eqos_null_ops(struct udevice *dev); extern struct eqos_config eqos_imx_config; +extern struct eqos_config eqos_qcom_config; diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c new file mode 100644 index 0000000000..df83f1c5f9 --- /dev/null +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022-2023 Sumit Garg + * + * Qcom DWMAC specific glue layer + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dwc_eth_qos.h" + +/* RGMII_IO_MACRO_CONFIG fields */ +#define RGMII_CONFIG_FUNC_CLK_EN BIT(30) +#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) +#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) +#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) +#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) +#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) +#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) +#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) +#define RGMII_CONFIG_LOOPBACK_EN BIT(2) +#define RGMII_CONFIG_PROG_SWAP BIT(1) +#define RGMII_CONFIG_DDR_MODE BIT(0) + +/* SDCC_HC_REG_DLL_CONFIG fields */ +#define SDCC_DLL_CONFIG_DLL_RST BIT(30) +#define SDCC_DLL_CONFIG_PDN BIT(29) +#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) +#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) +#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) +#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) +#define SDCC_DLL_CONFIG_CDR_EN BIT(17) +#define SDCC_DLL_CONFIG_DLL_EN BIT(16) +#define SDCC_DLL_MCLK_GATING_EN BIT(5) +#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) + +/* SDCC_HC_REG_DDR_CONFIG fields */ +#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) +#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) +#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) +#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) +#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) + +/* SDCC_HC_REG_DLL_CONFIG2 fields */ +#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) +#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) +#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) +#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) +#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) + +/* SDC4_STATUS bits */ +#define SDC4_STATUS_DLL_LOCK BIT(7) + +/* RGMII_IO_MACRO_CONFIG2 fields */ +#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) +#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) +#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) +#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) +#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) +#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) +#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) + +struct dwmac_rgmii_regs { + u32 io_macro_config; /* 0x00 */ + u32 sdcc_hc_dll_config; /* 0x04 */ + u32 reserved_1; /* 0x08 */ + u32 sdcc_hc_ddr_config; /* 0x0c */ + u32 sdcc_hc_dll_config2; /* 0x10 */ + u32 sdc4_status; /* 0x14 */ + u32 sdcc_usr_ctl; /* 0x18 */ + u32 io_macro_config2; /* 0x1c */ + u32 io_macro_debug1; /* 0x20 */ + u32 reserved_2; /* 0x24 */ + u32 emac_sys_low_power_dbg; /* 0x28 */ + u32 reserved_3[53]; /* upto 0x100 */ +}; + +static struct dwmac_rgmii_regs emac_v2_3_0_por = { + .io_macro_config = 0x00C01343, + .sdcc_hc_dll_config = 0x2004642C, + .sdcc_hc_ddr_config = 0x00000000, + .sdcc_hc_dll_config2 = 0x00200000, + .sdcc_usr_ctl = 0x00010800, + .io_macro_config2 = 0x00002060 +}; + +static void ethqos_set_func_clk_en(struct dwmac_rgmii_regs *regs) +{ + setbits_le32(®s->io_macro_config, RGMII_CONFIG_FUNC_CLK_EN); +} + +static int ethqos_dll_configure(struct udevice *dev, + struct dwmac_rgmii_regs *regs) +{ + unsigned int val; + int retry = 1000; + + /* Set CDR_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EN); + + /* Set CDR_EXT_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EXT_EN); + + /* Clear CK_OUT_EN */ + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN); + + /* Set DLL_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN); + + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_MCLK_GATING_EN); + + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CDR_FINE_PHASE); + + /* Wait for CK_OUT_EN clear */ + do { + val = readl(®s->sdcc_hc_dll_config); + val &= SDCC_DLL_CONFIG_CK_OUT_EN; + if (!val) + break; + mdelay(1); + retry--; + } while (retry > 0); + if (!retry) + dev_err(dev, "Clear CK_OUT_EN timedout\n"); + + /* Set CK_OUT_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN); + + /* Wait for CK_OUT_EN set */ + retry = 1000; + do { + val = readl(®s->sdcc_hc_dll_config); + val &= SDCC_DLL_CONFIG_CK_OUT_EN; + if (val) + break; + mdelay(1); + retry--; + } while (retry > 0); + if (!retry) + dev_err(dev, "Set CK_OUT_EN timedout\n"); + + /* Set DDR_CAL_EN */ + setbits_le32(®s->sdcc_hc_dll_config2, SDCC_DLL_CONFIG2_DDR_CAL_EN); + + clrbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_DLL_CLOCK_DIS); + + clrsetbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 0x1A << 10); + + clrsetbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, BIT(2)); + + setbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW); + + return 0; +} + +static int ethqos_rgmii_macro_init(struct udevice *dev, + struct dwmac_rgmii_regs *regs, + unsigned long speed) +{ + /* Disable loopback mode */ + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN); + + /* Select RGMII, write 0 to interface select */ + clrbits_le32(®s->io_macro_config, RGMII_CONFIG_INTF_SEL); + + switch (speed) { + case SPEED_1000: + setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE); + clrbits_le32(®s->io_macro_config, + RGMII_CONFIG_BYPASS_TX_ID_EN); + setbits_le32(®s->io_macro_config, + RGMII_CONFIG_POS_NEG_DATA_SEL); + setbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP); + + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL); + setbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RSVD_CONFIG15); + setbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RX_PROG_SWAP); + + /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */ + clrsetbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_PRG_RCLK_DLY, 57); + setbits_le32(®s->sdcc_hc_ddr_config, SDCC_DDR_CONFIG_PRG_DLY_EN); + + setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN); + break; + + case SPEED_100: + setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE); + setbits_le32(®s->io_macro_config, + RGMII_CONFIG_BYPASS_TX_ID_EN); + clrbits_le32(®s->io_macro_config, + RGMII_CONFIG_POS_NEG_DATA_SEL); + clrbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP); + clrsetbits_le32(®s->io_macro_config, + RGMII_CONFIG_MAX_SPD_PRG_2, BIT(6)); + + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL); + setbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RSVD_CONFIG15); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RX_PROG_SWAP); + + /* Write 0x5 to PRG_RCLK_DLY_CODE */ + clrsetbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, + (BIT(29) | BIT(27))); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN); + + setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN); + break; + + case SPEED_10: + setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE); + setbits_le32(®s->io_macro_config, + RGMII_CONFIG_BYPASS_TX_ID_EN); + clrbits_le32(®s->io_macro_config, + RGMII_CONFIG_POS_NEG_DATA_SEL); + clrbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP); + clrsetbits_le32(®s->io_macro_config, + RGMII_CONFIG_MAX_SPD_PRG_9, + BIT(12) | GENMASK(9, 8)); + + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RSVD_CONFIG15); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RX_PROG_SWAP); + + /* Write 0x5 to PRG_RCLK_DLY_CODE */ + clrsetbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, + (BIT(29) | BIT(27))); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN); + + setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN); + break; + + default: + dev_err(dev, "Invalid speed %ld\n", speed); + return -EINVAL; + } + + return 0; +} + +static int ethqos_configure(struct udevice *dev, + struct dwmac_rgmii_regs *regs, + unsigned long speed) +{ + unsigned int retry = 1000; + + /* Reset to POR values and enable clk */ + writel(emac_v2_3_0_por.io_macro_config, ®s->io_macro_config); + writel(emac_v2_3_0_por.sdcc_hc_dll_config, ®s->sdcc_hc_dll_config); + writel(emac_v2_3_0_por.sdcc_hc_ddr_config, ®s->sdcc_hc_ddr_config); + writel(emac_v2_3_0_por.sdcc_hc_dll_config2, ®s->sdcc_hc_dll_config2); + writel(emac_v2_3_0_por.sdcc_usr_ctl, ®s->sdcc_usr_ctl); + writel(emac_v2_3_0_por.io_macro_config2, ®s->io_macro_config2); + + ethqos_set_func_clk_en(regs); + + /* Initialize the DLL first */ + + /* Set DLL_RST */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST); + + /* Set PDN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN); + + /* Clear DLL_RST */ + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST); + + /* Clear PDN */ + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN); + + if (speed == SPEED_1000) { + /* Set DLL_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN); + + /* Set CK_OUT_EN */ + setbits_le32(®s->sdcc_hc_dll_config, + SDCC_DLL_CONFIG_CK_OUT_EN); + + /* Set USR_CTL bit 26 with mask of 3 bits */ + clrsetbits_le32(®s->sdcc_usr_ctl, GENMASK(26, 24), BIT(26)); + + /* wait for DLL LOCK */ + do { + mdelay(1); + if (readl(®s->sdc4_status) & SDC4_STATUS_DLL_LOCK) + break; + retry--; + } while (retry > 0); + if (!retry) + dev_err(dev, "Timeout while waiting for DLL lock\n"); + + ethqos_dll_configure(dev, regs); + } + + ethqos_rgmii_macro_init(dev, regs, speed); + + return 0; +} + +static void ethqos_rgmii_dump(struct udevice *dev, + struct dwmac_rgmii_regs *regs) +{ + dev_dbg(dev, "Rgmii register dump\n"); + dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %08x\n", + readl(®s->io_macro_config)); + dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %08x\n", + readl(®s->sdcc_hc_dll_config)); + dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %08x\n", + readl(®s->sdcc_hc_ddr_config)); + dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %08x\n", + readl(®s->sdcc_hc_dll_config2)); + dev_dbg(dev, "SDC4_STATUS: %08x\n", + readl(®s->sdc4_status)); + dev_dbg(dev, "SDCC_USR_CTL: %08x\n", + readl(®s->sdcc_usr_ctl)); + dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %08x\n", + readl(®s->io_macro_config2)); + dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %08x\n", + readl(®s->io_macro_debug1)); + dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %08x\n", + readl(®s->emac_sys_low_power_dbg)); +} + +static int qcom_eqos_rgmii_set_speed(struct udevice *dev, + void *rgmii_regs, + unsigned long speed) +{ + int ret; + + ethqos_rgmii_dump(dev, rgmii_regs); + + ret = ethqos_configure(dev, rgmii_regs, speed); + if (ret) + return ret; + + ethqos_rgmii_dump(dev, rgmii_regs); + + return 0; +} + +static int qcom_eqos_rgmii_reset(struct udevice *dev, void *rgmii_regs) +{ + ethqos_set_func_clk_en(rgmii_regs); + + return 0; +} + +static int eqos_start_clks_qcom(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_CLK)) { + struct clk_bulk clocks; + int ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_stop_clks_qcom(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_CLK)) { + struct clk_bulk clocks; + int ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_disable_bulk(&clocks); + if (ret) + return ret; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_start_resets_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + if (!eqos->phy) { + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret); + return ret; + } + + udelay(eqos->reset_delays[0]); + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + return ret; + } + + udelay(eqos->reset_delays[1]); + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + return ret; + } + + udelay(eqos->reset_delays[2]); + } + + ret = reset_deassert(&eqos->reset_ctl); + if (ret < 0) { + pr_err("reset_deassert() failed: %d", ret); + return ret; + } + + ret = qcom_eqos_rgmii_reset(dev, eqos->eqos_qcom_rgmii_regs); + if (ret < 0) { + pr_err("qcom rgmii_reset failed: %d", ret); + return ret; + } + + debug("%s: OK\n", __func__); + return 0; +} + +/* Clock rates */ +#define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) +#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) +#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) + +static int eqos_set_tx_clk_speed_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + ulong rate; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + switch (eqos->phy->speed) { + case SPEED_1000: + rate = RGMII_1000_NOM_CLK_FREQ; + break; + case SPEED_100: + rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; + break; + case SPEED_10: + rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; + break; + default: + pr_err("invalid speed %d", eqos->phy->speed); + return -EINVAL; + } + + ret = clk_set_rate(&eqos->clk_tx, rate); + if (ret < 0) { + pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret); + return ret; + } + + ret = qcom_eqos_rgmii_set_speed(dev, eqos->eqos_qcom_rgmii_regs, + eqos->phy->speed); + if (ret < 0) { + pr_err("qcom set_speed: %d, failed: %d", eqos->phy->speed, ret); + return ret; + } + + return 0; +} + +static int eqos_probe_resources_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + phy_interface_t interface; + int reset_flags = GPIOD_IS_OUT; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + interface = eqos->config->interface(dev); + + if (interface == PHY_INTERFACE_MODE_NA) { + pr_err("Invalid PHY interface\n"); + return -EINVAL; + } + + eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); + + eqos->tx_fifo_sz = dev_read_u32_default(dev, "tx-fifo-depth", 0); + eqos->rx_fifo_sz = dev_read_u32_default(dev, "rx-fifo-depth", 0); + + ret = reset_get_by_name(dev, "emac", &eqos->reset_ctl); + if (ret) { + pr_err("reset_get_by_name(rst) failed: %d", ret); + return ret; + } + + if (dev_read_bool(dev, "snps,reset-active-low")) + reset_flags |= GPIOD_ACTIVE_LOW; + + ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, + &eqos->phy_reset_gpio, reset_flags); + if (ret == 0) { + ret = dev_read_u32_array(dev, "snps,reset-delays-us", + eqos->reset_delays, 3); + } else if (ret == -ENOENT) { + ret = 0; + } + + eqos->eqos_qcom_rgmii_regs = (void *)dev_read_addr_name(dev, "rgmii"); + if ((fdt_addr_t)eqos->eqos_qcom_rgmii_regs == FDT_ADDR_T_NONE) { + pr_err("Invalid RGMII address\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev, "rgmii", &eqos->clk_tx); + if (ret) { + pr_err("clk_get_by_name(tx) failed: %d", ret); + return -EINVAL; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_remove_resources_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_free(&eqos->clk_tx); + dm_gpio_free(dev, &eqos->phy_reset_gpio); + reset_free(&eqos->reset_ctl); + + debug("%s: OK\n", __func__); + return 0; +} + +static struct eqos_ops eqos_qcom_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_resources_qcom, + .eqos_remove_resources = eqos_remove_resources_qcom, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_qcom, + .eqos_stop_clks = eqos_stop_clks_qcom, + .eqos_start_clks = eqos_start_clks_qcom, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_qcom, + .eqos_get_enetaddr = eqos_null_ops, +}; + +struct eqos_config __maybe_unused eqos_qcom_config = { + .reg_access_always_ok = false, + .mdio_wait = 10, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &eqos_qcom_ops +}; From patchwork Wed Feb 1 13:58:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649170 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp303988pva; Wed, 1 Feb 2023 06:06:09 -0800 (PST) X-Google-Smtp-Source: AK7set/sbPUrSXJpuNyw9BvGEH0AOHjXK6BGVBF1YjlVqZsTe204xuLgjgMY4tojZzynhnC5Idmk X-Received: by 2002:a05:6830:6582:b0:68c:5082:b5c8 with SMTP id cn2-20020a056830658200b0068c5082b5c8mr1347342otb.5.1675260369639; Wed, 01 Feb 2023 06:06:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260369; cv=none; d=google.com; s=arc-20160816; b=ubPYzn/HX8zDhgDH5mEaj33I0UfP3A4zDsx8MTyvvzj1FyrdtI9A7MJ9EA/rWeqQOp fV4EPzWNbRhAsjn2grs+cNXInIYCeAEkhXCcABx6ZUa9/TXe2Hbejq8b9utdCCfICbCt kc3VkLnY0HFHjgllWYwxxfkLvuQhxA+IOQ67HxDH7+S3EhOorJYyBOrjHYWyRuNBsM6V xasOwmPqRdjBdcPrAOcan6CsgWxa+hcR8590k+faXn4CZFCn2P1FQq5foeMesKxmdvxi f+i7w+BXEt03REgEmwajJNI20UDB6pLZ/1AVMP72N8OlkkoLDXqZl4Gn5I+kopWSMbdr 7DBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yfvp1gUUP//SmMVEed5zgIAdTdTyK6Ynwsoz/X58s40=; b=MEitl9m5NnEBNNlcbp4Q5L1wAESPaz6kDJ/8i3AK95i3uiuuaF07G6cf40yyrM/v3f lIPdbFICr9RL+Xw27sYjtfsnCLtEjrlBrPia3QPN8Accs/jLorY4pFS7KCFeIgtM49EE gp0IZi2IQm1antv7xet7eLZawo//WYw+tXQvfJLaUNmW/KhUi7QDc/RjBUe8wygi/AvA /QgyrwjZ7aLMp6n8sKuHNriwHrOLoWzDcsgLV/vjznY8IJL2MG7fRxvsi5wjxcNzmFu+ rsSq6OH+/N3XVoMd0adPAsdq6mG/734WEqPFAPU40Q6cgm+kyeLGIZvKT6jSOH5AWhJA XLLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=enQuUvxa; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id l25-20020a05683004b900b0068bddbf976csi5173510otd.191.2023.02.01.06.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:06:09 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=enQuUvxa; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 399C3856DE; Wed, 1 Feb 2023 15:05:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="enQuUvxa"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5CD4685AA5; Wed, 1 Feb 2023 15:02:26 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5B98985C83 for ; Wed, 1 Feb 2023 14:59:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x1029.google.com with SMTP id mi9so8234501pjb.4 for ; Wed, 01 Feb 2023 05:59:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yfvp1gUUP//SmMVEed5zgIAdTdTyK6Ynwsoz/X58s40=; b=enQuUvxaXmr0ddUMUteFjrlb2yt1UnSMoIaBwQJcL48bFxjvPLmSNu4HyGP7Pi2RCT UgsOwlBAtFrZwnO6pyYrz/y4i74DdxQCESGYQRCtYmZ/GImC0x7dthVwAyYTmala75FC GkWZ72UOIEmGI49BVlVkwfjqL+a/b+0Ep+97otvO2/fQ7ft2KVk4TyL1oEL9zEBRuFLf /g3KPqvxXcDKbZ6g9hmleG9pfDrrxb+9uymZm9jJQPjww/UmDX8Il+CI+S/s4nN82hYw OIrI7kpZtqI1YOtcfh1F+bV3KkBYoR+pt1pPYuFKh7C0axxpWYN384wlnTZVkr8OzMrX Lqlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yfvp1gUUP//SmMVEed5zgIAdTdTyK6Ynwsoz/X58s40=; b=K4TDzVXztSgFebEkKAeSqa4NH9G5u7BoxWH8CjJgwzpRvFTAwcYP4Ihn1tjUwyJhWb Eab+jxsRy/KeaMLn0Btt5tsglrmtEQBeBHdrfAsL1KkaIb43JG9ErTIHwRJqaS70bpWv BfULkpl9QXUlJXEwQAvWb705LMUO31BNyOQeAv0qfDuFnt4VdmnXBUpCLsvGNvZj8wKV dV7CZQj3BZ212AqPNmE/ZH2m8kfDkxXCPmdfha3kIKcMrmPgUlyKBmZX18Nt9CVtkdwr kEMGPQUsgrb1Rc08OTJo139OpsYvQ0TIT8EgdbGndrb0h9sjrPEb4HIKf2W41U2pKzhP OpOQ== X-Gm-Message-State: AO0yUKVHGGdRwlfhUZk9p6Dn5Q/trFTwa8risyHuby1LaWDuSMWUtxf1 VvXwQsZURgj2mdo+fzu2sfNsy2eMHVcf2Esk X-Received: by 2002:a17:902:d4c3:b0:196:3ae3:4ffe with SMTP id o3-20020a170902d4c300b001963ae34ffemr3323703plg.41.1675259992551; Wed, 01 Feb 2023 05:59:52 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:52 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 09/14] dts: qcs404-evb: Add ethernet controller node Date: Wed, 1 Feb 2023 19:28:56 +0530 Message-Id: <20230201135901.482671-10-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Sumit Garg --- arch/arm/dts/qcs404-evb.dts | 98 ++++++++++++++++++++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index cc70afa4c8..2de0e7537b 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -36,7 +36,7 @@ ranges = <0x0 0x0 0x0 0xffffffff>; compatible = "simple-bus"; - pinctrl_north@1300000 { + soc_gpios: pinctrl_north@1300000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x1300000 0x200000>; gpio-controller; @@ -48,6 +48,61 @@ pins = "GPIO_17", "GPIO_18"; function = "blsp_uart2"; }; + + ethernet_defaults: ethernet-defaults { + int { + pins = "GPIO_61"; + function = "rgmii_int"; + bias-disable; + drive-strength = <2>; + }; + mdc { + pins = "GPIO_76"; + function = "rgmii_mdc"; + bias-pull-up; + }; + mdio { + pins = "GPIO_75"; + function = "rgmii_mdio"; + bias-pull-up; + }; + tx { + pins = "GPIO_67", "GPIO_66", "GPIO_65", "GPIO_64"; + function = "rgmii_tx"; + bias-pull-up; + drive-strength = <16>; + }; + rx { + pins = "GPIO_73", "GPIO_72", "GPIO_71", "GPIO_70"; + function = "rgmii_rx"; + bias-disable; + drive-strength = <2>; + }; + tx-ctl { + pins = "GPIO_68"; + function = "rgmii_ctl"; + bias-pull-up; + drive-strength = <16>; + }; + rx-ctl { + pins = "GPIO_74"; + function = "rgmii_ctl"; + bias-disable; + drive-strength = <2>; + }; + tx-ck { + pins = "GPIO_63"; + function = "rgmii_ck"; + bias-pull-up; + drive-strength = <16>; + }; + rx-ck { + pins = "GPIO_69"; + function = "rgmii_ck"; + bias-disable; + drive-strength = <2>; + }; + }; }; gcc: clock-controller@1800000 { @@ -172,6 +227,47 @@ }; }; + ethernet: ethernet@7a80000 { + compatible = "qcom,qcs404-ethqos"; + reg = <0x07a80000 0x10000>, + <0x07a96000 0x100>; + reg-names = "stmmaceth", "rgmii"; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + clocks = <&gcc GCC_ETH_AXI_CLK>, + <&gcc GCC_ETH_SLAVE_AHB_CLK>, + <&gcc GCC_ETH_PTP_CLK>, + <&gcc GCC_ETH_RGMII_CLK>; + + resets = <&reset GCC_EMAC_BCR>; + reset-names = "emac"; + + snps,tso; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + snps,reset-gpio = <&soc_gpios 60 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet_defaults>; + + phy-handle = <&phy1>; + phy-mode = "rgmii"; + max-speed = <1000>; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; + phy1: phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x3>; + }; + }; + }; + spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000 From patchwork Wed Feb 1 13:58:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649172 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp304403pva; Wed, 1 Feb 2023 06:06:44 -0800 (PST) X-Google-Smtp-Source: AK7set/cWdy/os0alVsV6M0NQtVITEVtLXNOirl4VDtSuSW7ztF0ntfkrnIPIn55/m0uihRLlMaX X-Received: by 2002:a4a:c70f:0:b0:517:bd25:216a with SMTP id n15-20020a4ac70f000000b00517bd25216amr1287749ooq.3.1675260404117; Wed, 01 Feb 2023 06:06:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260404; cv=none; d=google.com; s=arc-20160816; b=m4imABDF5dnO7ttoy3tn/LvGJPUL2+KZe5VwrypoFoLbmPQJH5JzMPjJfc/cz/nce1 R7R70bc7ekhC2k/5IohuOVdwPtYQWaYIF4OOoy4VUx+/5YGvlNSCkZR+/ew2Vrq/J+8W 88fcPWR6IzZ2n2phCRhrDVVW+IkNb++pBJ3RwvB/AgIM2je4th5n0JkmytHHCmzhgi8T hUC9hS7pha/8bOkfdrYA8MGwkwJZePgz3MA54pOgoRmeLCE40Irk+m+hmbQLbB43kDsj R9fiG8gb4KcL+G000OvhmngzyyqNrwoQMtU+zjHrM9W8Hdq/m3yopDjSJDLop88gfIQc 40vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=H7l5e1Mk6NBap2n4RtHZEWgpKHTeaD3uETXTC3h5PBs=; b=oMmg1HbRm7m10m8B5iz2V/iTysxAZnJGfoDs3xqmdBpxQulghrMeIuRrWmJXGLOZrl bbJq12+WXBOH+57FHTl1kOHmwtcbSRCkeHMZSd7HLTB0LqJ9YP/tSmWCsOH59JrQAH33 xhqUHK2vnWy/OwiDS8SE4Z7uop6m3PlgWfPY0RHcFvJB6UW5XYNzJXufUDVcd4aWgykg LU2kAK6+01My4XD4+pHv+XTmdANsyy6zxl0cCHOVqZsiToPxq2cPGSux92qh66U85XLD 69uas7vufwKbzhhkvp5vW4ifa5jlLZ20tuzJPAhsuFHatu9PYoWJ6jqVHPvioyYwqBWK RJCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j8RGyNRN; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id i12-20020a4ab24c000000b004de1b23d821si16265627ooo.14.2023.02.01.06.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:06:43 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j8RGyNRN; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9A80885CCC; Wed, 1 Feb 2023 15:05:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="j8RGyNRN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5978D85CAF; Wed, 1 Feb 2023 15:02:54 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8C58A85C8E for ; Wed, 1 Feb 2023 14:59:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x1029.google.com with SMTP id pj3so4556049pjb.1 for ; Wed, 01 Feb 2023 05:59:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H7l5e1Mk6NBap2n4RtHZEWgpKHTeaD3uETXTC3h5PBs=; b=j8RGyNRNA6iIvmBV/pmSAP0hPw3JHMRVpefQ4CZuyg1vCsXxAoGlGGrkuRBhRQZqOd UVIP/XK4kkM2uONA1j86PseDlkOSoDhiNX9lX+v6neXnE69qboKpHkDsEfrLR5ZXsuOe G8STpjFMkwi/DZBzvlJE7iW6IMQozzd6RCI69qxZ99Qpu/suXmts4ok0oFPGsDbyfbxG CQ3wfVrPLU8yl8gtyzx/WeRARAvfLeck9/6vDll7lSxf0m3NTK8dHUlPlCtPrq5Fn31z vpbkCIxvMQJbSpomfgUX9XldFMbR42Zbs0muG1BCZAxCMiSbCCR2PLqw2mkZYAAOg+vs 5WQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H7l5e1Mk6NBap2n4RtHZEWgpKHTeaD3uETXTC3h5PBs=; b=TTKn3f/gdm5+gTFcOyrZMBXvTizNboQaDZFiRESRuTi4T/QMfz6iHn9QTQggc37P45 RL4O7Pi8QIbAGU+jtIljeio25luTSUrsjpRdilgtXWqCktSWRuwARf7pyCOOqq2PqQp9 MzZ/UczcD5NaYaV+TxWo7b6Bb/jHXoQBdLIonU3Q/J4R7LZuCvskN6l03dU1jXglh1d1 SosGP2olmHwHE6KPyBWitA9BC40vGhV8SrU9gS6soTwKEifHF7LjuuunjM+AM6U0SI8N mNuloMMl0mN8yZJ1U455BGGD9BGLDLvEJuEGsHF/0InWrsRKaqdgz69O8ulGaviD53yg 99vQ== X-Gm-Message-State: AO0yUKUgvc5obWqLYlqoHxl7hdGxQujGkhikdHWgmh/mrGMfO3UO2xPZ esTOfi7vMBx9qIRwZiKeLglVPegqXOydNvVE X-Received: by 2002:a17:902:d08b:b0:196:132c:5b7 with SMTP id v11-20020a170902d08b00b00196132c05b7mr2523431plv.1.1675259996758; Wed, 01 Feb 2023 05:59:56 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:56 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 10/14] clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0 Date: Wed, 1 Feb 2023 19:28:57 +0530 Message-Id: <20230201135901.482671-11-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add clk_rcg_set_rate() which allows to configure clocks without programming MND values. This is required for configuring I2C clocks on QCS404. Co-developed-by: Mike Worsfold Signed-off-by: Mike Worsfold Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/clock-snapdragon.c | 24 +++++++++++++++++++++ arch/arm/mach-snapdragon/clock-snapdragon.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index fda7098274..0ac45dce9a 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -111,6 +111,30 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, clk_bcr_update(base + regs->cmd_rcgr); } +/* root set rate for clocks with half integer and mnd_width=0 */ +void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, + int source) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + regs->cfg_rcgr); + cfg &= ~CFG_MASK; + cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ + + /* + * Set the divider; HW permits fraction dividers (+0.5), but + * for simplicity, we will support integers only + */ + if (div) + cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; + + writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + + /* Inform h/w to start using the new config. */ + clk_bcr_update(base + regs->cmd_rcgr); +} + static int msm_clk_probe(struct udevice *dev) { struct msm_clk_priv *priv = dev_get_priv(dev); diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 2ac53b538d..c90bbefa58 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -42,5 +42,7 @@ void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source); +void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, + int source); #endif From patchwork Wed Feb 1 13:58:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649173 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp304581pva; Wed, 1 Feb 2023 06:06:58 -0800 (PST) X-Google-Smtp-Source: AK7set8kDfi7NaRExtK17ZlcuzdH6FaJgcMkJDq7GGsyDbRIN6UdmJTy2R0H8fZXPepbHU7jm7pY X-Received: by 2002:a05:6870:e0cb:b0:163:a1a3:912b with SMTP id a11-20020a056870e0cb00b00163a1a3912bmr1049021oab.56.1675260418583; Wed, 01 Feb 2023 06:06:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260418; cv=none; d=google.com; s=arc-20160816; b=mujXmwxvzg7SfsMp+qvdGtbwi0frhsRj+JHhJyIeiCo4fF0XDmWj83bScOyAEsK9nw Ak3OO5pRZ9EN8YlO3QWNqOSVNtbGE/KSHXQ0Ake5rsoYHIfdOpsWCbLdrhikvYjRQy0/ w04qHBCpTiZ1YxOnXq/hYyzF3Tk05Luaz5T4X7F8zbD4mpw1gnDuOOjUhSDkgHcC5b3s kba/hU0oU/TMtZqPPmljwQlCKRL8x/MCR3y43Hkd1OhdLOB4jPF5ujeOiyDOX1TyLLCk CR0lJfssaMRgriL/pX7/DF1eGvRv6X1j256zVxZqJkbT2nk2eS9W3TfHc+9JA+wzFNlp C7uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Xdf8I24my+RES1hqOGFcOF5sho33tW39rnt5z28aa9A=; b=oxxPVDlcHFMzokXomaGnoWSmQl0CVW5vmmePCr6PWKpDGIjEEOVot9nuV6tYGldqj8 bzVQwiX/6rZS6Tjq6Volm0LQ5L2lftru9d0CTr5MY7oA2t7/zi0Ad2/Y/3Ie6HZEzNfP gdmx4luxs8uct8uYTRFkb5nriv4ki3y6GFjGwQz7rBopmGRUQ7QwIlQNme4w91wXxCSv DkufJO4ttwzJy2877Dmu1apg3fn5yrfgaRWXejn9cGpe5W58Y2Bckdp4qIPUh7+lcPwL K9lUxGbDP5Pd4AOLq+cX/19pbJXgDaRM4lx9WM0GhBq3gXG/v5M0vTPU/S1ZDALKt41t /htQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kmfrW663; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id w65-20020a4a5d44000000b005111f2a9ad4si8126389ooa.69.2023.02.01.06.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:06:58 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kmfrW663; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 95CF085C75; Wed, 1 Feb 2023 15:06:10 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="kmfrW663"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 133E285CB6; Wed, 1 Feb 2023 15:03:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 57FA285CA3 for ; Wed, 1 Feb 2023 15:00:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x102d.google.com with SMTP id n20-20020a17090aab9400b00229ca6a4636so2307608pjq.0 for ; Wed, 01 Feb 2023 06:00:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xdf8I24my+RES1hqOGFcOF5sho33tW39rnt5z28aa9A=; b=kmfrW6639y33yzxAhkLKoX4wtLfs/dZoK7wgKE09m7QX4Rgr5ym9iVAX333iGBVaRy e3z7fwTqFkm+9vgHtVVJXVO/dLVE1mze3XpFEfnnq/+bYJsM91WLJ8VFihpFwB3vsyNO VIOWP2frcWpPO+2P09YHUf/B+KGPb6gGS3+EIzeejVU+jmIwWh/MgMVbuMpYfkPE42hp 19rKX2iSy5OE/baL8xlTvfXYwB6pLojKE5P4MWt2VG9/uwfnD7zd/6lbhORiy3mKR8/F MMLsfhjGPP5uGBpy5vJqICh/plIl5QmjfJeyaHAL5BGN0nM06pxuxKYS2Kx/e4s/nlpK kQkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xdf8I24my+RES1hqOGFcOF5sho33tW39rnt5z28aa9A=; b=QT67xPpURCmyyGUtSml7o3NWwSQY/8eWmYUfaaJQ+sDU1auaZjxfhIEQkNONvpCpKB owwZvPhZFg2KHioC5iEQYmbEdEEe8T+rgrtKuFAO/W3f893WnV4smatgxxozb6s2UfpY gIijCy8Pb3mZsl7zaGy7bMcGq2zVbgO3zm67aeq5MCgYB8pt5i7J+UakXJpwtX8q7HYn M9g7TCLhppNIEnp9H/MbMPHRScVDja//pfaHtwWN8QFtEPdM325ZYz40czLc/2HyT1Wo 5B/1m8MW9G9aaBYsNYxx/bFnQPVWPFyH2VnknjgTiVRnTFD3pJknajtk8LBlYMGTclyO zLyg== X-Gm-Message-State: AO0yUKWwN/Zva6PADQwSfuSelsxGwXDMIgMGZAv2v1cylBmcnvBTGuqk UySRJEODGEEFCuRZatrtSbG5EauBnt8NX/9z X-Received: by 2002:a17:902:d506:b0:198:9e29:cc4f with SMTP id b6-20020a170902d50600b001989e29cc4fmr3520245plg.43.1675260005128; Wed, 01 Feb 2023 06:00:05 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.06.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:00:04 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 12/14] pinctrl: qcs404: Enable I2C pinmux options Date: Wed, 1 Feb 2023 19:28:59 +0530 Message-Id: <20230201135901.482671-13-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Co-developed-by: Mike Worsfold Signed-off-by: Mike Worsfold Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/pinctrl-qcs404.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c index 5a7fbfd441..a6e53c4412 100644 --- a/arch/arm/mach-snapdragon/pinctrl-qcs404.c +++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c @@ -29,6 +29,12 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"rgmii_rx", 1}, {"rgmii_mdio", 1}, {"rgmii_mdc", 1}, + {"blsp_i2c0", 3}, + {"blsp_i2c1", 2}, + {"blsp_i2c_sda_a2", 3}, + {"blsp_i2c_scl_a2", 3}, + {"blsp_i2c3", 2}, + {"blsp_i2c4", 1}, }; static const char *qcs404_get_function_name(struct udevice *dev, From patchwork Wed Feb 1 13:59:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649175 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp304880pva; Wed, 1 Feb 2023 06:07:28 -0800 (PST) X-Google-Smtp-Source: AK7set8qqksCVIOZJSGZsWotF0wP3V1EZMxgpXW/aVwcRNa1bB9fT9zOfQacHA10dIqI9xrNAcm9 X-Received: by 2002:aca:a8cb:0:b0:35e:7ef8:d85b with SMTP id r194-20020acaa8cb000000b0035e7ef8d85bmr1071246oie.37.1675260447868; Wed, 01 Feb 2023 06:07:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260447; cv=none; d=google.com; s=arc-20160816; b=HDGlucI/uc8qJLibcom3SgbqIaejIk0HEFiBXb5lK+YlKwZNNYQmmvdWdHptCtx/Gf +Wqd17LKFuvkhmPndtl7DfpAzHXMfiwL6iAd4IyFMakvcUWUn1W0iWvVjW1gIdMLTcjH lY1AoqvEFDh2KuMXphznyvWWczGFiHITUlACvrUJp7suL15ISBhZgjQ59vviM4ygr8bI dQyb0Rp9/wopeUdGVtmBwGaxlSiKEAzXN4Dvbi2CFDsL5q2dx1WEtJBuuPc3jyMZO8h9 rZvnarY6CLxoame78GeCf0NpCLM/OWMXQN+KArxgO2lQ/6df7GVaNICt/zDKQPrXiEkF Sv4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UHlWLMtyeDh41phYEKkvqW3ZLvlrB/kngr2q9k5p9zg=; b=HtqlTBDo5b9r37LKb8nAuuqMxuTRyDkXSI5GKSHvWbn9z0is5Te2lRjxijugCgcNig vZ/ys+tseaAK4gqI94efTZCAVw684/Js792VrdHnOgvfUXq0xKs7gtXeMOzKM28TQKsb 7qya9PD9w4ObZNMxm0aRvB5EBeHTnqfLsdRgaO6eJK5XLrA70jS6W6768Pid9veCjwQQ 3OgBMggqzP3PoxpSAiOCsoIz9m0dwt1DzPID4PD1EbQThrWRQ8RFW1/dp08KqOtmLZ4D mOhzn5Usm9nFABhrc6JfiaAMTVYUTjHYECJhqQLwfOEoZKgUYfmq5RoJVNDkfJ1fhFzl c3ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sYhBFbZ0; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id i127-20020acab885000000b0036cfb62aacasi16307256oif.269.2023.02.01.06.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:07:27 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sYhBFbZ0; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 278EB85CBD; Wed, 1 Feb 2023 15:06:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="sYhBFbZ0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EB02A85CC0; Wed, 1 Feb 2023 15:05:02 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5A40D85C76 for ; Wed, 1 Feb 2023 15:00:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pl1-x632.google.com with SMTP id n13so3027544plf.11 for ; Wed, 01 Feb 2023 06:00:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UHlWLMtyeDh41phYEKkvqW3ZLvlrB/kngr2q9k5p9zg=; b=sYhBFbZ0NB2oHPmICuqEqOzwJ/fNpDu6HweLUrlKVIjjtAauFTAPczdzSo3rwn19Db RVFsa2eKOAtxQeyfcK5Jxx0W+u+R4+v5LIWsq7Ghuk0Nx4tyVckbMHe42bsWy4uJrJKm acjTgdAr50nr9HqFzrRJ2KHAESL+qDO8jcFylmivjTUrkWgjKobtu1A/OmJslCbn8GyO kOFap3BKO7UYGq0ZaeAtHXJqpi41O+wRuK7ELMdem1HkaZlAPgB/QFrQ8pvOJAyPAEmp nAu6JtOtN46gv/aGI+BvIix4ZXFAOxCs8uKvt5wKPybOYTYAqIElHmuam64NmmmHi0Ij W54g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UHlWLMtyeDh41phYEKkvqW3ZLvlrB/kngr2q9k5p9zg=; b=IPb9G+Ox7KPcOX0tUNMudxgMIa1elFaYfxXtaRtWbnPDqMFYlKxGToJ2goJh3nGlrV 8BKJnnBsucYKDk8s860DpR6jmWsUztoEgXm9yniWKwbJa6Mk/V77nXugPxip48NC/PRB lDMghEwgmQ1Z31uT+xd8stbfSdZrS0Sk0SE+NCXhhNMDXllRxcjrbjiF+bueHZ8n/289 EDJOpTFCxIct+qAmJPs+fJL/8wOeQ3tWM65FIvbioeTxAtxn0M+lUAugBa4OHkZMdaxM In98mKwaBVth3AOh4ZHbnVSYMPv3kLLq+szaJkZH0nGYa3f8bmd88hpsGm8akoiDuopJ fhWA== X-Gm-Message-State: AO0yUKW2/MEJwDt+iZ7RF9Ir6GP/0aPt/cRJrHDoxNtOpwC6oExi21jd eEhztS5SzzuU4wXDBvA2817f5oNC3m0pSb+Q X-Received: by 2002:a17:902:c3c5:b0:196:433e:2384 with SMTP id j5-20020a170902c3c500b00196433e2384mr2703232plj.57.1675260009719; Wed, 01 Feb 2023 06:00:09 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.06.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:00:09 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 13/14] i2c: Add support for Qualcomm I2C driver Date: Wed, 1 Feb 2023 19:29:00 +0530 Message-Id: <20230201135901.482671-14-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add support for Qualcomm I2C QUP driver which is inspired from corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c. Currently this driver only support FIFO polling mode which is sufficient to support devices like eeprom, rtc etc. Co-developed-by: Mike Worsfold Signed-off-by: Mike Worsfold Signed-off-by: Sumit Garg --- drivers/i2c/Kconfig | 12 + drivers/i2c/Makefile | 1 + drivers/i2c/qup_i2c.c | 579 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 592 insertions(+) create mode 100644 drivers/i2c/qup_i2c.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 76e19918aa..427074bff8 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -580,6 +580,18 @@ config SYS_I2C_OCTEON chips have several I2C ports and all are provided, controlled by the device tree. +config SYS_I2C_QUP + bool "Qualcomm QUP I2C controller" + depends on ARCH_SNAPDRAGON + help + Support for Qualcomm QUP I2C controller based on Qualcomm Universal + Peripherals (QUP) engine. The QUP engine is an advanced high + performance slave port that provides a common data path (an output + FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP + controller is publicly documented in the Snapdragon 410E (APQ8016E) + Technical Reference Manual, chapter "6.1 Qualcomm Universal + Peripherals Engine (QUP)". + config SYS_I2C_S3C24X0 bool "Samsung I2C driver" depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 920aafb91c..b024547959 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_SYS_I2C_NPCM) += npcm_i2c.o obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o +obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o diff --git a/drivers/i2c/qup_i2c.c b/drivers/i2c/qup_i2c.c new file mode 100644 index 0000000000..5ae3cccd4a --- /dev/null +++ b/drivers/i2c/qup_i2c.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, Sony Mobile Communications AB. + * Copyright (c) 2022-2023, Sumit Garg + * + * Inspired by corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* QUP Registers */ +#define QUP_CONFIG 0x000 +#define QUP_STATE 0x004 +#define QUP_IO_MODE 0x008 +#define QUP_SW_RESET 0x00c +#define QUP_OPERATIONAL 0x018 +#define QUP_ERROR_FLAGS 0x01c /* NOT USED */ +#define QUP_ERROR_FLAGS_EN 0x020 /* NOT USED */ +#define QUP_TEST_CTRL 0x024 /* NOT USED */ +#define QUP_OPERATIONAL_MASK 0x028 /* NOT USED */ +#define QUP_HW_VERSION 0x030 +#define QUP_MX_OUTPUT_CNT 0x100 +#define QUP_OUT_DEBUG 0x108 /* NOT USED */ +#define QUP_OUT_FIFO_CNT 0x10C /* NOT USED */ +#define QUP_OUT_FIFO_BASE 0x110 +#define QUP_MX_WRITE_CNT 0x150 +#define QUP_MX_INPUT_CNT 0x200 +#define QUP_MX_READ_CNT 0x208 +#define QUP_IN_READ_CUR 0x20C /* NOT USED */ +#define QUP_IN_DEBUG 0x210 /* NOT USED */ +#define QUP_IN_FIFO_CNT 0x214 /* NOT USED */ +#define QUP_IN_FIFO_BASE 0x218 +#define QUP_I2C_CLK_CTL 0x400 +#define QUP_I2C_STATUS 0x404 /* NOT USED */ +#define QUP_I2C_MASTER_GEN 0x408 +#define QUP_I2C_MASTER_BUS_CLR 0x40C /* NOT USED */ + +/* QUP States and reset values */ +#define QUP_RESET_STATE 0 +#define QUP_RUN_STATE 1 +#define QUP_PAUSE_STATE 3 +#define QUP_STATE_MASK 3 + +#define QUP_STATE_VALID BIT(2) +#define QUP_I2C_MAST_GEN BIT(4) +#define QUP_I2C_FLUSH BIT(6) + +#define QUP_OPERATIONAL_RESET 0x000ff0 +#define QUP_I2C_STATUS_RESET 0xfffffc + +/* QUP OPERATIONAL FLAGS */ +#define QUP_I2C_NACK_FLAG BIT(3) +#define QUP_OUT_NOT_EMPTY BIT(4) +#define QUP_IN_NOT_EMPTY BIT(5) +#define QUP_OUT_FULL BIT(6) +#define QUP_OUT_SVC_FLAG BIT(8) +#define QUP_IN_SVC_FLAG BIT(9) +#define QUP_MX_OUTPUT_DONE BIT(10) +#define QUP_MX_INPUT_DONE BIT(11) +#define OUT_BLOCK_WRITE_REQ BIT(12) +#define IN_BLOCK_READ_REQ BIT(13) + +/* + * QUP engine acting as I2C controller is referred to as + * I2C mini core, following are related macros. + */ +#define QUP_NO_OUTPUT BIT(6) +#define QUP_NO_INPUT BIT(7) +#define QUP_CLOCK_AUTO_GATE BIT(13) +#define QUP_I2C_MINI_CORE (2 << 8) +#define QUP_I2C_N_VAL_V2 7 + +/* Packing/Unpacking words in FIFOs, and IO modes */ +#define QUP_OUTPUT_BLK_MODE BIT(10) +#define QUP_OUTPUT_BAM_MODE (BIT(10) | BIT(11)) +#define QUP_INPUT_BLK_MODE BIT(12) +#define QUP_INPUT_BAM_MODE (BIT(12) | BIT(13)) +#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE) +#define QUP_BLK_MODE (QUP_OUTPUT_BLK_MODE | QUP_INPUT_BLK_MODE) +#define QUP_UNPACK_EN BIT(14) +#define QUP_PACK_EN BIT(15) + +#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN) +#define QUP_V2_TAGS_EN 1 + +#define QUP_OUTPUT_BLOCK_SIZE(x) (((x) >> 0) & 0x03) +#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07) +#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03) +#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07) + +/* QUP v2 tags */ +#define QUP_TAG_V2_START 0x81 +#define QUP_TAG_V2_DATAWR 0x82 +#define QUP_TAG_V2_DATAWR_STOP 0x83 +#define QUP_TAG_V2_DATARD 0x85 +#define QUP_TAG_V2_DATARD_NACK 0x86 +#define QUP_TAG_V2_DATARD_STOP 0x87 + +#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31) + +/* Minimum transfer timeout for i2c transfers in micro seconds */ +#define TOUT_CNT (2 * 1000 * 1000) + +/* Default values. Use these if FW query fails */ +#define DEFAULT_CLK_FREQ I2C_SPEED_STANDARD_RATE +#define DEFAULT_SRC_CLK 19200000 + +/* + * Max tags length (start, stop and maximum 2 bytes address) for each QUP + * data transfer + */ +#define QUP_MAX_TAGS_LEN 4 +/* Max data length for each DATARD tags */ +#define RECV_MAX_DATA_LEN 254 +/* TAG length for DATA READ in RX FIFO */ +#define READ_RX_TAGS_LEN 2 + +struct qup_i2c_priv { + phys_addr_t base; + struct clk core; + struct clk iface; + u32 in_fifo_sz; + u32 out_fifo_sz; + u32 clk_ctl; + u32 config_run; +}; + +static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg) +{ + return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0); +} + +static int qup_i2c_poll_state_mask(struct qup_i2c_priv *qup, + u32 req_state, u32 req_mask) +{ + int retries = 1; + u32 state; + + /* + * State transition takes 3 AHB clocks cycles + 3 I2C master clock + * cycles. So retry once after a 1uS delay. + */ + do { + state = readl(qup->base + QUP_STATE); + + if (state & QUP_STATE_VALID && + (state & req_mask) == req_state) + return 0; + + udelay(1); + } while (retries--); + + return -ETIMEDOUT; +} + +static int qup_i2c_poll_state(struct qup_i2c_priv *qup, u32 req_state) +{ + return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); +} + +static int qup_i2c_poll_state_valid(struct qup_i2c_priv *qup) +{ + return qup_i2c_poll_state_mask(qup, 0, 0); +} + +static int qup_i2c_poll_state_i2c_master(struct qup_i2c_priv *qup) +{ + return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); +} + +static int qup_i2c_change_state(struct qup_i2c_priv *qup, u32 state) +{ + if (qup_i2c_poll_state_valid(qup) != 0) + return -EIO; + + writel(state, qup->base + QUP_STATE); + + if (qup_i2c_poll_state(qup, state) != 0) + return -EIO; + return 0; +} + +/* + * Function to check wheather Input or Output FIFO + * has data to be serviced + */ +static int qup_i2c_check_fifo_status(struct qup_i2c_priv *qup, u32 reg_addr, + u32 flags) +{ + unsigned long count = TOUT_CNT; + u32 val, status_flag; + int ret = 0; + + do { + val = readl(qup->base + reg_addr); + status_flag = val & flags; + + if (!count) { + printf("%s, timeout\n", __func__); + ret = -ETIMEDOUT; + break; + } + + count--; + udelay(1); + } while (!status_flag); + + return ret; +} + +/* + * Function to configure Input and Output enable/disable + */ +static void qup_i2c_enable_io_config(struct qup_i2c_priv *qup, u32 write_cnt, + u32 read_cnt) +{ + u32 qup_config = QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2; + + writel(qup->config_run | write_cnt, qup->base + QUP_MX_WRITE_CNT); + + if (read_cnt) + writel(qup->config_run | read_cnt, qup->base + QUP_MX_READ_CNT); + else + qup_config |= QUP_NO_INPUT; + + writel(qup_config, qup->base + QUP_CONFIG); +} + +static unsigned int qup_i2c_read_word(struct qup_i2c_priv *qup) +{ + return readl(qup->base + QUP_IN_FIFO_BASE); +} + +static void qup_i2c_write_word(struct qup_i2c_priv *qup, u32 word) +{ + writel(word, qup->base + QUP_OUT_FIFO_BASE); +} + +static int qup_i2c_blsp_read(struct qup_i2c_priv *qup, unsigned int addr, + bool last, u8 *buffer, unsigned int bytes) +{ + unsigned int i, j, word; + int ret = 0; + + /* FIFO mode size limitation, for larger size implement block mode */ + if (bytes > (qup->in_fifo_sz - READ_RX_TAGS_LEN)) + return -EINVAL; + + qup_i2c_enable_io_config(qup, QUP_MAX_TAGS_LEN, + bytes + READ_RX_TAGS_LEN); + + if (last) + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATARD_STOP << 16 | + bytes << 24); + else + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATARD << 16 | bytes << 24); + + ret = qup_i2c_change_state(qup, QUP_RUN_STATE); + if (ret) + return ret; + + ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG); + if (ret) + return ret; + writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); + + ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_IN_SVC_FLAG); + if (ret) + return ret; + writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); + + word = qup_i2c_read_word(qup); + *(buffer++) = (word >> (8 * READ_RX_TAGS_LEN)) & 0xff; + if (bytes > 1) + *(buffer++) = (word >> (8 * (READ_RX_TAGS_LEN + 1))) & 0xff; + + for (i = 2; i < bytes; i += 4) { + word = qup_i2c_read_word(qup); + + for (j = 0; j < 4; j++) { + if ((i + j) == bytes) + break; + *buffer = (word >> (j * 8)) & 0xff; + buffer++; + } + } + + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); + return ret; +} + +static int qup_i2c_blsp_write(struct qup_i2c_priv *qup, unsigned int addr, + bool first, bool last, const u8 *buffer, + unsigned int bytes) +{ + unsigned int i; + u32 word = 0; + int ret = 0; + + /* FIFO mode size limitation, for larger size implement block mode */ + if (bytes > (qup->out_fifo_sz - QUP_MAX_TAGS_LEN)) + return -EINVAL; + + qup_i2c_enable_io_config(qup, bytes + QUP_MAX_TAGS_LEN, 0); + + if (first) { + ret = qup_i2c_change_state(qup, QUP_RUN_STATE); + if (ret) + return ret; + + writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); + + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); + if (ret) + return ret; + } + + if (last) + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATAWR_STOP << 16 | + bytes << 24); + else + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATAWR << 16 | bytes << 24); + + for (i = 0; i < bytes; i++) { + /* Write the byte of data */ + word |= *buffer << ((i % 4) * 8); + if ((i % 4) == 3) { + qup_i2c_write_word(qup, word); + word = 0; + } + buffer++; + } + + if ((i % 4) != 0) + qup_i2c_write_word(qup, word); + + ret = qup_i2c_change_state(qup, QUP_RUN_STATE); + if (ret) + return ret; + + ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG); + if (ret) + return ret; + writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); + + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); + return ret; +} + +static void qup_i2c_conf_mode_v2(struct qup_i2c_priv *qup) +{ + u32 io_mode = QUP_REPACK_EN; + + writel(0, qup->base + QUP_MX_OUTPUT_CNT); + writel(0, qup->base + QUP_MX_INPUT_CNT); + + writel(io_mode, qup->base + QUP_IO_MODE); +} + +static int qup_i2c_xfer_v2(struct udevice *bus, struct i2c_msg msgs[], int num) +{ + struct qup_i2c_priv *qup = dev_get_priv(bus); + int ret, idx = 0; + u32 i2c_addr; + + writel(1, qup->base + QUP_SW_RESET); + ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); + if (ret) + goto out; + + /* Configure QUP as I2C mini core */ + writel(QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2 | QUP_NO_INPUT, + qup->base + QUP_CONFIG); + writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); + + if (qup_i2c_poll_state_i2c_master(qup)) { + ret = -EIO; + goto out; + } + + qup_i2c_conf_mode_v2(qup); + + for (idx = 0; idx < num; idx++) { + struct i2c_msg *m = &msgs[idx]; + + qup->config_run = !idx ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; + i2c_addr = i2c_8bit_addr_from_msg(m); + + if (m->flags & I2C_M_RD) + ret = qup_i2c_blsp_read(qup, i2c_addr, idx == (num - 1), + m->buf, m->len); + else + ret = qup_i2c_blsp_write(qup, i2c_addr, idx == 0, + idx == (num - 1), m->buf, + m->len); + if (ret) + break; + } +out: + qup_i2c_change_state(qup, QUP_RESET_STATE); + return ret; +} + +static int qup_i2c_enable_clocks(struct udevice *dev, struct qup_i2c_priv *qup) +{ + int ret; + + ret = clk_enable(&qup->core); + if (ret) { + dev_err(dev, "clk_enable failed %d\n", ret); + return ret; + } + + ret = clk_enable(&qup->iface); + if (ret) { + dev_err(dev, "clk_enable failed %d\n", ret); + return ret; + } + + return 0; +} + +static int qup_i2c_probe(struct udevice *dev) +{ + static const int blk_sizes[] = {4, 16, 32}; + struct qup_i2c_priv *qup = dev_get_priv(dev); + u32 io_mode, hw_ver, size, size_idx; + int ret; + + qup->base = (phys_addr_t)dev_read_addr_ptr(dev); + if (!qup->base) + return -EINVAL; + + ret = clk_get_by_name(dev, "core", &qup->core); + if (ret) { + pr_err("clk_get_by_name(core) failed: %d\n", ret); + return ret; + } + ret = clk_get_by_name(dev, "iface", &qup->iface); + if (ret) { + pr_err("clk_get_by_name(iface) failed: %d\n", ret); + return ret; + } + qup_i2c_enable_clocks(dev, qup); + + writel(1, qup->base + QUP_SW_RESET); + ret = qup_i2c_poll_state_valid(qup); + if (ret) + return ret; + + hw_ver = readl(qup->base + QUP_HW_VERSION); + dev_dbg(dev, "Revision %x\n", hw_ver); + + io_mode = readl(qup->base + QUP_IO_MODE); + + /* + * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' + * associated with each byte written/received + */ + size_idx = QUP_OUTPUT_BLOCK_SIZE(io_mode); + if (size_idx >= ARRAY_SIZE(blk_sizes)) { + ret = -EIO; + return ret; + } + size = QUP_OUTPUT_FIFO_SIZE(io_mode); + qup->out_fifo_sz = blk_sizes[size_idx] * (2 << size); + + size_idx = QUP_INPUT_BLOCK_SIZE(io_mode); + if (size_idx >= ARRAY_SIZE(blk_sizes)) { + ret = -EIO; + return ret; + } + size = QUP_INPUT_FIFO_SIZE(io_mode); + qup->in_fifo_sz = blk_sizes[size_idx] * (2 << size); + + dev_dbg(dev, "IN:fifo:%d, OUT:fifo:%d\n", qup->in_fifo_sz, + qup->out_fifo_sz); + + return 0; +} + +static int qup_i2c_set_bus_speed(struct udevice *dev, unsigned int clk_freq) +{ + struct qup_i2c_priv *qup = dev_get_priv(dev); + unsigned int src_clk_freq; + int fs_div, hs_div; + + /* We support frequencies up to FAST Mode Plus (1MHz) */ + if (!clk_freq || clk_freq > I2C_SPEED_FAST_PLUS_RATE) { + dev_err(dev, "clock frequency not supported %d\n", clk_freq); + return -EINVAL; + } + + src_clk_freq = clk_get_rate(&qup->iface); + if ((int)src_clk_freq < 0) { + src_clk_freq = DEFAULT_SRC_CLK; + dev_dbg(dev, "using default core freq %d\n", src_clk_freq); + } + + dev_dbg(dev, "src_clk_freq %u\n", src_clk_freq); + dev_dbg(dev, "clk_freq %u\n", clk_freq); + + hs_div = 3; + if (clk_freq <= I2C_SPEED_STANDARD_RATE) { + fs_div = ((src_clk_freq / clk_freq) / 2) - 3; + qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); + } else { + /* 33%/66% duty cycle */ + fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; + qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); + } + + dev_dbg(dev, "clk_ctl %u\n", qup->clk_ctl); + + return 0; +} + +/* Probe to see if a chip is present. */ +static int qup_i2c_probe_chip(struct udevice *dev, uint chip_addr, + uint chip_flags) +{ + struct qup_i2c_priv *qup = dev_get_priv(dev); + u32 hw_ver = readl(qup->base + QUP_HW_VERSION); + + return hw_ver ? 0 : -1; +} + +static const struct dm_i2c_ops qup_i2c_ops = { + .xfer = qup_i2c_xfer_v2, + .probe_chip = qup_i2c_probe_chip, + .set_bus_speed = qup_i2c_set_bus_speed, +}; + +/* + * Currently this driver only supports v2.x of QUP I2C controller, hence + * functions above are named with a _v2 suffix. So when we have the + * v1.1.1 support added as per the Linux counterpart then it should be easy + * to add corresponding functions named with a _v1 suffix. + */ +static const struct udevice_id qup_i2c_ids[] = { + { .compatible = "qcom,i2c-qup-v2.1.1" }, + { .compatible = "qcom,i2c-qup-v2.2.1" }, + {} +}; + +U_BOOT_DRIVER(i2c_qup) = { + .name = "i2c_qup", + .id = UCLASS_I2C, + .of_match = qup_i2c_ids, + .probe = qup_i2c_probe, + .priv_auto = sizeof(struct qup_i2c_priv), + .ops = &qup_i2c_ops, +}; From patchwork Wed Feb 1 13:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 649174 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp304745pva; Wed, 1 Feb 2023 06:07:15 -0800 (PST) X-Google-Smtp-Source: AK7set/MECw5M2VloeqTHOt+onyN/oda6ynAwF8wAf1wo7Apjn7NVfcuxVTk+LkK2v82Dkg3Bt86 X-Received: by 2002:a4a:4155:0:b0:517:968f:73c0 with SMTP id x82-20020a4a4155000000b00517968f73c0mr957882ooa.0.1675260435042; Wed, 01 Feb 2023 06:07:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675260435; cv=none; d=google.com; s=arc-20160816; b=opl7ydnUc2wdoe4lZYi+8UJDJAlOWVTOP/R8rF5y9dCZ1mFG3a2lpHJHCf4UwGIr1d OF/xNGSfhha/BrHQjzcZAOk9pNNnhimU4ARQ/KhaWT/uK/5lxnXVb285LfpFFCGhOJy8 2TA4RpNdjNMpYxGkZK2nByDsctNTUttSCWhVtKMeAIelUPaZTbKaJpAp61SXf3p0/8DQ a176RfZcPPPqWmF8sG6nDbYFuYSpqfI+J+E4tc1+nxwr4PlT7kbWcUMGbkI58hvrturB 87smQGzvIBDBrIIJ61ZYZfGmvRoyytNPrZhhukCd+/oruQpfqZULwSI0LGkQS8mzU73+ 70hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6kr/g6m/4ZltE8jqlhDtEwO8Fv1oew34oK40awNbuVI=; b=QbAQsToWDf05U/EmLlwoXhniE+hwjWn/pvs0SSH8bkKNAyGLtSO+eo1bMza+t8TScj nxLVkF7KhAvkjestztASb8bh7sZPjJNlCESND/ykUzBZpUJRQWMoxM7iqRKkPxzVhdOu Arp9zvUDId3UVY672/lZtuNm5+UDZJoS0zq7ghsrx/jwgAIz3nSY3swl2vVeuQU/D/GQ B7DQi/bTVcQuDlXrwNuoQ66E4AyhRNE2+UHg27UlW2qaJ/8+ojb1Z2NNkIQ6CdPVXyAT wYYK2htJy47yiqXicUho48dAdyScKUa75H0z4NcUTPueb4zdZij7OyEzTAacvz15XJ2V uQ4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G5WJNO3q; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id p1-20020a4a95c1000000b00517810e5daasi8006829ooi.5.2023.02.01.06.07.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:07:15 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G5WJNO3q; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 553AC85C93; Wed, 1 Feb 2023 15:06:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="G5WJNO3q"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A6C0685C97; Wed, 1 Feb 2023 15:03:58 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BL_SPAMCOP_NET, SPF_HELO_NONE,T_SPF_TEMPERROR autolearn=no autolearn_force=no version=3.4.2 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 02B9B85CA1 for ; Wed, 1 Feb 2023 15:00:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x1029.google.com with SMTP id pj3so4556924pjb.1 for ; Wed, 01 Feb 2023 06:00:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6kr/g6m/4ZltE8jqlhDtEwO8Fv1oew34oK40awNbuVI=; b=G5WJNO3qzIAHRVcPbhKnCYuOTTdwZTrlF7qK0PEz0CfrTwKw5dWr0HicYIW/5B3XhY 2BquO6QtPxLdvtBssPMS7ovthVtoYsJnlRP7tc5Umd4xuJKS219raAVHYnF5CZVVs5UX kk8iALqGqGwkFTP27v9tvjNfXj+tgfX0kzGr5LbjvRc4kAJ9PuO0gPl5KlYioTwLpNUj O5DSaHOm/yean0s3hxEGqGbM3PgOWIcBj10wAUW1NjPIOOHwyX4efxBiKH1kPvuONCXx c6Uk46CC5iuL8Nh0uVJwXUm6IQJWcxHVWCh/VHly2cAkhhZ/JHwtVKqwS9jaNM2fQB2s /sZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6kr/g6m/4ZltE8jqlhDtEwO8Fv1oew34oK40awNbuVI=; b=5uolBP+pR0VrbHZGD66Gh9sZcJZgWXCzpDxhojcwE3RVquv57v7DRShyFGCGY3zPeV HxMkS6R57/BlwyaQ1ZX02KbhSSth/5cDD35GMLIgTGyp+1IMfHo2gwToaAZZ2wjb7XE6 1ULQhMeLpm4IIW6zWjqMiJTI/FafDf/R6Zt5R9P2UnWBWAHafRnZtj4ey1wOyQ17J2hF iiFstCtbf5bWXieANREOwN9BKAPvO+9XVOZMcf+lNV3nzfpfFHiMMNvja5s68DAWzUdd LNMeU8TGP1GracAab4WUD9CWk4uEdAcf/3EHgccWWMe+UEaH+97a1IDvohqpjt02ciIb DZPg== X-Gm-Message-State: AO0yUKV7ajpdV1kC4Qj4hEVNLdEVW+62FVTs5P4Q9yBgCQMjVZBnIIo2 NZwls3X/Kp3jdNA/kOn30cm29gcJ51SmtlQj X-Received: by 2002:a05:6a20:d691:b0:ae:47a6:e6d9 with SMTP id it17-20020a056a20d69100b000ae47a6e6d9mr2789335pzb.6.1675260013995; Wed, 01 Feb 2023 06:00:13 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.06.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 06:00:13 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 14/14] dts: qcs404-evb: Add I2C controller nodes Date: Wed, 1 Feb 2023 19:29:01 +0530 Message-Id: <20230201135901.482671-15-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Sumit Garg --- arch/arm/dts/qcs404-evb.dts | 97 +++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 2de0e7537b..8d7893c116 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -23,6 +23,11 @@ aliases { serial0 = &debug_uart; + i2c0 = &blsp1_i2c0; + i2c1 = &blsp1_i2c1; + i2c2 = &blsp1_i2c2; + i2c3 = &blsp1_i2c3; + i2c4 = &blsp1_i2c4; }; memory { @@ -49,6 +54,38 @@ function = "blsp_uart2"; }; + blsp1_i2c0_default: blsp1-i2c0-default { + pins = "GPIO_32", "GPIO_33"; + function = "blsp_i2c0"; + }; + + blsp1_i2c1_default: blsp1-i2c1-default { + pins = "GPIO_24", "GPIO_25"; + function = "blsp_i2c1"; + }; + + blsp1_i2c2_default: blsp1-i2c2-default { + sda { + pins = "GPIO_19"; + function = "blsp_i2c_sda_a2"; + }; + + scl { + pins = "GPIO_20"; + function = "blsp_i2c_scl_a2"; + }; + }; + + blsp1_i2c3_default: blsp1-i2c3-default { + pins = "GPIO_84", "GPIO_85"; + function = "blsp_i2c3"; + }; + + blsp1_i2c4_default: blsp1-i2c4-default { + pins = "GPIO_117", "GPIO_118"; + function = "blsp_i2c4"; + }; + ethernet_defaults: ethernet-defaults { int { pins = "GPIO_61"; @@ -105,6 +142,66 @@ }; }; + blsp1_i2c0: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c0_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c1_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c2: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c2_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c3: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c3_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_i2c4: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_i2c4_default>; + #address-cells = <1>; + #size-cells = <0>; + }; + gcc: clock-controller@1800000 { compatible = "qcom,gcc-qcs404"; reg = <0x1800000 0x80000>;