From patchwork Wed Feb 1 18:36:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 649267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7593C636D4 for ; Wed, 1 Feb 2023 18:37:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232014AbjBAShH (ORCPT ); Wed, 1 Feb 2023 13:37:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbjBAShF (ORCPT ); Wed, 1 Feb 2023 13:37:05 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6CC080154 for ; Wed, 1 Feb 2023 10:36:33 -0800 (PST) Received: by mail-ed1-x52d.google.com with SMTP id q19so8710091edd.2 for ; Wed, 01 Feb 2023 10:36:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pDicGkl+5x/PXSx3Dad29Z0zKYmJ8UAe01LZn9BX9P0=; b=lgatjYCVYPzRwVfKLWY0TbmS/6NaTm3qJxDaz+9esYJTY2atIDNJW5P+PvnrBmkuoP PJIjR6y5RscfxilsEijJ5S6XK/ozSce/dShr0Z1cdxBus5mtmVxe8reJwdkYQbEj7Uhs irGlD9UO2FEm2YJUriY6EnY7tqRJmerb2hdXKFppLyhIqfh5/CVABupPoOUXGAfvwhKR Qqb0jTbVarpsIwGeA/Ga7X4ttifcAmmlXFcF5BQJQ1+6mtbIgtV4jLalogay5i5UODtB ziKBng7yJfNtFh5VDjxCGMqGhQDsiX3dRc2j5OAot2bDYG3GMWd4wjmSGdR2Mvyu4qA8 QJdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pDicGkl+5x/PXSx3Dad29Z0zKYmJ8UAe01LZn9BX9P0=; b=C+nKkJ5W0zgGqeE+hB39zslrACza3NY46fz4lHtT+3LJ+RfEaMYtI55Q5E42nfErDn VybNvdcy96tp/gGOxQemoIMAnd2UJiYZh1cwV1coswe/W6AQWaEUbf9n6x7ropsF6sE3 LE0LWe7gefULCfiR1SY3miyq0Go3il47Qjtzx/CEis6sHNf9PikoCcgOM34tGd5nvzid jmAT3w3XCltmFUw0wKjL+esaoPt9WTtaIpTYlwVChEzGuFeMbrm9K+JZOt8LIj+jZiBN 4CWvGqsvsSm4jNMG+K8Sz1HzLsvYZ/RUgS14c36heu5hMa+LMBaEI9mte95cdsFiqTu/ UyaQ== X-Gm-Message-State: AO0yUKXXtY3N+gYicxzrkxBzgZOWxN0HIULw+cSIo28+EbaeyWueV+Tp 0HFfSjUr1iNTP7f2tD2U6gcUYMssL2iqCQ1H X-Google-Smtp-Source: AK7set9JGY1MR1r8KkizFypTJD/0/NyT4I6S6iUmAHWh1KbkYcTW9e2q5lqjie6NgWNoNsxLvRL8Ng== X-Received: by 2002:a05:6402:1bcc:b0:499:b672:ee30 with SMTP id ch12-20020a0564021bcc00b00499b672ee30mr3154277edb.11.1675276591697; Wed, 01 Feb 2023 10:36:31 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:31 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 01/10] clk: qcom: branch: Add helper functions for setting retain bits Date: Wed, 1 Feb 2023 19:36:17 +0100 Message-Id: <20230201183626.351211-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Most Qualcomm branch clocks come with a pretty usual set of bits that can enable memory retention by means of not turning off parts of the memory logic. Add them to the common header file and introduce helper functions for setting them instead of using magic writes. Signed-off-by: Konrad Dybcio --- v4 -> v5: - Make the helpers accept clk_branch instead of u64 reg drivers/clk/qcom/clk-branch.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 17a58119165e..55b3a2c3afed 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -37,6 +37,32 @@ struct clk_branch { struct clk_regmap clkr; }; +/* Branch clock common bits for HLOS-owned clocks */ +#define CBCR_FORCE_MEM_CORE_ON BIT(14) +#define CBCR_FORCE_MEM_PERIPH_ON BIT(13) +#define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) + +static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, + struct clk_branch clk, bool on) +{ + regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_CORE_ON, + on ? CBCR_FORCE_MEM_CORE_ON : 0); +} + +static inline void qcom_branch_set_force_periph_on(struct regmap *regmap, + struct clk_branch clk, bool on) +{ + regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_ON, + on ? CBCR_FORCE_MEM_PERIPH_ON : 0); +} + +static inline void qcom_branch_set_force_periph_off(struct regmap *regmap, + struct clk_branch clk, bool on) +{ + regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_OFF, + on ? CBCR_FORCE_MEM_PERIPH_OFF : 0); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; From patchwork Wed Feb 1 18:36:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 650318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC2A6C38142 for ; Wed, 1 Feb 2023 18:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232063AbjBAShN (ORCPT ); Wed, 1 Feb 2023 13:37:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232058AbjBAShL (ORCPT ); Wed, 1 Feb 2023 13:37:11 -0500 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ED8D8016D for ; Wed, 1 Feb 2023 10:36:39 -0800 (PST) Received: by mail-ed1-x531.google.com with SMTP id n6so16003570edo.9 for ; Wed, 01 Feb 2023 10:36:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=El1AVRsQ6D1MqifIni9EpinXyr4efhm++D3OufFjYP4=; b=ly6dETHjzRa3Mg4uA8RGluvZ0Z6g7wigR0NdtxHggKWXXPpvGYo8ET89DUdbzgnXTt XJ5+rXU9PSoBxNn5gBh4pmHNCs1rikeKa2FkI5qU8yNHp3h7zhrPz7vAwivbC3oZk/4q MkqfjcI/0U0PYwu92ruOi3LPYr5oiEwMLPSSUko5SRwMufwcE1g0FxFp4TzohVGr6EcB mRmfbTk1enXM86qoiMMsVrRkP8c/cQGy82MIsh70FwxsoJCJlmPuKFQVIYGoOa+kbp7D zGaIFdQ80TOG13TxNLv1RtlQt4jKUwEAJ0lQtHRZXQPjm8xt8fFk8QswlnsSLP/baxCa IrbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=El1AVRsQ6D1MqifIni9EpinXyr4efhm++D3OufFjYP4=; b=aefjhdvx5z+Wee/DObScFZJLf4Tice9jz1j8/CInHzp+3ysE9wB4pz288JHsmk6+Fo lSwehZrgoa0WTfPd7VFjrM1JMY418og4h+PqclYkmVbemvFkXkyow8SBVddc2wX5RdUF sWbb8IKdty614rgfe1YlCpOyVV8rwZQx+gMcA1w70TxhNgdxorVoOu9g8OCOLe8A7Xdr BldjgNFcD1EingOmV68/aGCypwQWkFQ/AoH1NjmAefCuMjSNBlUDWX3fHqHuvssiu2FU Cg0c/yw+ovqFDWoARGiUo6maOlR/kUqb5tTRUNDN4xNajKVgOTTZ299u2e6WmvwMoI/x GLqw== X-Gm-Message-State: AO0yUKXFfIVGjf0FagMX/cLOYfsIYyEOsW39edC3rbWM+DJSCFNiPKZ7 frYwF7/8KbZeNHhwLdgyYZPmUwDG9Z2kdnBS X-Google-Smtp-Source: AK7set9q3uP3SBemadz+F9KkGslcV4+CfVNGuzTtXrjHXVs+qRfNNKLI9VldjJz5jNUEwmD725D2kA== X-Received: by 2002:aa7:ca42:0:b0:492:8207:f2ba with SMTP id j2-20020aa7ca42000000b004928207f2bamr7319238edt.1.1675276593387; Wed, 01 Feb 2023 10:36:33 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:33 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/10] clk: qcom: branch: Add helper functions for setting SLEEP/WAKE bits Date: Wed, 1 Feb 2023 19:36:18 +0100 Message-Id: <20230201183626.351211-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org HLOS-controlled branch clocks on non-ancient Qualcomm platforms feature SLEEP and WAKE fields which can be written to to configure how long the clock hardware should wait internally before being (un)gated. Some very sensitive clocks need to have these values programmed to prevent putting the hardware in a not-exactly-good state. Add definitions of these fields and introduce helpers for setting them inside clock drivers. Signed-off-by: Konrad Dybcio --- v4 -> v5: - Introduce helpers that shift the value for you drivers/clk/qcom/clk-branch.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 55b3a2c3afed..fa90e150853b 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -41,6 +41,8 @@ struct clk_branch { #define CBCR_FORCE_MEM_CORE_ON BIT(14) #define CBCR_FORCE_MEM_PERIPH_ON BIT(13) #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) +#define CBCR_WAKEUP GENMASK(11, 8) +#define CBCR_SLEEP GENMASK(7, 4) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) @@ -63,6 +65,18 @@ static inline void qcom_branch_set_force_periph_off(struct regmap *regmap, on ? CBCR_FORCE_MEM_PERIPH_OFF : 0); } +static inline void qcom_branch_set_wakeup(struct regmap *regmap, struct clk_branch clk, u32 val) +{ + regmap_update_bits(regmap, clk.halt_reg, CBCR_WAKEUP, + FIELD_PREP(CBCR_WAKEUP, val)); +} + +static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branch clk, u32 val) +{ + regmap_update_bits(regmap, clk.halt_reg, CBCR_SLEEP, + FIELD_PREP(CBCR_SLEEP, val)); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; From patchwork Wed Feb 1 18:36:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 649266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72AB0C05027 for ; Wed, 1 Feb 2023 18:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232124AbjBAShV (ORCPT ); Wed, 1 Feb 2023 13:37:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232089AbjBAShR (ORCPT ); Wed, 1 Feb 2023 13:37:17 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8837D7EFC1 for ; Wed, 1 Feb 2023 10:36:44 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id v10so18640312edi.8 for ; Wed, 01 Feb 2023 10:36:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z6IkYBzHRtP78kfNNlfDDoZLESVj7tG9rKk+4Qd2VXM=; b=KegFK2U/B4RmndOABI9a19JnrGK7nSS6Tc9XCPCEzK8Weeo6nle5akFanIEPCZ8L5/ /g4mdwbHw2jhToCgyOHDPnUjvDaW5Zx6V2bFsFUTROxs4tbg2JfbKU+0TjBbYnP951oI gik1lD+Is6F7bj2z6ze2lrhxXFxwbkwM9HBLqD/K/P0JU/q8JymFN5U5nSFgBU5EC2Ry P9sLjDnX7Tva+/iUhTbt0l2lLCMe0deR95raWSS0SmrGSv0UGv7na9xPjfBgH6xcFcte admvL6QDxMqH5hnfUxH+dRRvxuSnANwoYK+U66ldI/mgsxvgpN8geON5p4qIs6dQHh+2 zpZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z6IkYBzHRtP78kfNNlfDDoZLESVj7tG9rKk+4Qd2VXM=; b=WtgEnDmK5kbNfnNQ/RPtyMfcihpmWikjg+M/R4VPGkZFWspJW92B/Rv4+kcZlaayIh 5FXZV5voWCstRNBhC4SSJ/s6+YUubvKgfe1s/WZYQhHaFpZhpZ4vtGUKJcssHHMXTyIl m+ggitgHLkQGmlfkPWtesMB9TuY9HLE3cKfeEYj1gpNUZaN5CofrL7XaYMYeQeGvGQ6X lJ34ydqZFHyvR+J9YJcqzO2GhopQ2YJqu/aqFnEuynvKJWkmT8gr8kXpuXxjRwRkYzqI 8oeMMm7/Qew5nkA23YOsRPc2uGB6eRuQx/0OtHDchW/FpBYNNRFuLX3P4Y26ZdHa/3Nx jhbg== X-Gm-Message-State: AO0yUKXbDKqtk3S9qShYLlU8KBqz9i0ItTWINhtQ5p5RdAzbhsBGQQVz oJ4RRDq3SLQI9Q9Dc9tDS1k9oOGblqcgITD4 X-Google-Smtp-Source: AK7set/OSp3bTSpScRiuoz93pZ+OMFRFsPgu7NtaeIA7jnL3rY6kaW+n5yFBntYk4y4jdQ04uyNTTg== X-Received: by 2002:aa7:d417:0:b0:4a0:dadc:c0c2 with SMTP id z23-20020aa7d417000000b004a0dadcc0c2mr3444923edq.27.1675276594967; Wed, 01 Feb 2023 10:36:34 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:34 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 03/10] clk: qcom: branch: Move CBCR bits definitions to the header file Date: Wed, 1 Feb 2023 19:36:19 +0100 Message-Id: <20230201183626.351211-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the definitions of CBCR bits to the branch header file. Signed-off-by: Konrad Dybcio --- v4 -> v5: - New patch drivers/clk/qcom/clk-branch.c | 5 ----- drivers/clk/qcom/clk-branch.h | 4 ++++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index f869fc6aaed6..f2b577b07b7e 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -39,11 +39,6 @@ static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling) return !!val == !enabling; } -#define BRANCH_CLK_OFF BIT(31) -#define BRANCH_NOC_FSM_STATUS_SHIFT 28 -#define BRANCH_NOC_FSM_STATUS_MASK 0x7 -#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT) - static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling) { u32 val; diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index fa90e150853b..cff9ed6653b8 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -38,6 +38,10 @@ struct clk_branch { }; /* Branch clock common bits for HLOS-owned clocks */ +#define BRANCH_CLK_OFF BIT(31) +#define BRANCH_NOC_FSM_STATUS_SHIFT 28 +#define BRANCH_NOC_FSM_STATUS_MASK 0x7 +#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT) #define CBCR_FORCE_MEM_CORE_ON BIT(14) #define CBCR_FORCE_MEM_PERIPH_ON BIT(13) #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) From patchwork Wed Feb 1 18:36:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 650317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99DDAC636D7 for ; Wed, 1 Feb 2023 18:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231717AbjBAShV (ORCPT ); Wed, 1 Feb 2023 13:37:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232090AbjBAShU (ORCPT ); Wed, 1 Feb 2023 13:37:20 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24BB37FA20 for ; Wed, 1 Feb 2023 10:36:45 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id mf7so35400931ejc.6 for ; Wed, 01 Feb 2023 10:36:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CXCf2QEFiI/UaJA4L2hQetVotYkWuOmRjSs3LoUx6JE=; b=zY3iUDbikuUlCz2+bgIMc1ycTaMuwKI7PI5fZbAZjudVlEaR22XjCYMTGA+E7hjC8v O2SBgPtUivnoFg+nNhUMG3sI5EXNtDFpTZsnjwjvkH2BGzGTJvroZ6qmsH6a11/CFGfE zPPDU3wG1ScTF+1bUTIZfmH50LFTac7ZDHWttc0UcFJMWfBnBc7GJzrsAMueNSBJTO1h Eh0cpDG5s+WKaIh8wgeZopJPtOdJgyKqrVqtTgX6pmK48UwHP9XEUe0DyZ8DQmli8LCM Cs8Srlr2GxcP2yRcSl7TUHkm92dcJ8Y4tvGRnpadxRQ9tHVZjFaJGbtSfZyiwyA1ABXB IzxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CXCf2QEFiI/UaJA4L2hQetVotYkWuOmRjSs3LoUx6JE=; b=3jx3MBTUF1Dxf/01mlTG+jRGzTh1FnEw1NIzc7m4vwKRx1/Qfm9WNhSxxarEKj5fhH ICoSt0MeL+J2Ke9qTNRVeE9Y3Emq0PnpbIttCMIgjH6I33CQHe+7jer6MWSn9o32ko4I CEyeYTJxpe6Hkpg32bbHqTNTACeVUOzq6PWnLd70W7x9xF8A8fpye6smeYD6Ki6W6yOd Ri70pfNuvGTTkD4/f7SnNsuXxjq3TXU8wyV4BNen8UTff0wN0iVrsV/Mmb+DNAAiAOFx HZuGQN5ExbTdxXLmn4XkR9XbcG7whajznEwHvJN2ZW4i7WBatccfmcExiZrYtO8orJSt SMWA== X-Gm-Message-State: AO0yUKV4Dx80AxQzZYFJolx67upFVt7pxy6apdf8UR9trNa67q8tt0xv hrDSk3XGzSmYEIfUXaG76SmA5tFYdMz1+AzY X-Google-Smtp-Source: AK7set+g6R5KH1B7A2ADa+1nbxa2R1ZUk0Ft5BfSO+EbNOnhLHDwVWt+kv+lCXDycCX4VUslNcPeAg== X-Received: by 2002:a17:906:49da:b0:88a:8e57:f063 with SMTP id w26-20020a17090649da00b0088a8e57f063mr3433423ejv.62.1675276596833; Wed, 01 Feb 2023 10:36:36 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:36 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 04/10] clk: qcom: branch: Clean up branch enable registers Date: Wed, 1 Feb 2023 19:36:20 +0100 Message-Id: <20230201183626.351211-5-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Prefix the "branch enable" registers with CBCR_ to be closer to what they are actually called in Qualcomm terms, use GENMASK instead of shifting values around and adjust their usage accordingly. Signed-off-by: Konrad Dybcio --- v4 -> v5: - New patch drivers/clk/qcom/clk-branch.c | 10 +++++----- drivers/clk/qcom/clk-branch.h | 7 +++---- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index f2b577b07b7e..ca896ebf7e1b 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -44,17 +44,17 @@ static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling) u32 val; u32 mask; - mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT; - mask |= BRANCH_CLK_OFF; + mask = CBCR_NOC_FSM_STATUS; + mask |= CBCR_CLK_OFF; regmap_read(br->clkr.regmap, br->halt_reg, &val); if (enabling) { val &= mask; - return (val & BRANCH_CLK_OFF) == 0 || - val == BRANCH_NOC_FSM_STATUS_ON; + return (val & CBCR_CLK_OFF) == 0 || + FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON; } else { - return val & BRANCH_CLK_OFF; + return val & CBCR_CLK_OFF; } } diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index cff9ed6653b8..43cd41947ef5 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -38,10 +38,9 @@ struct clk_branch { }; /* Branch clock common bits for HLOS-owned clocks */ -#define BRANCH_CLK_OFF BIT(31) -#define BRANCH_NOC_FSM_STATUS_SHIFT 28 -#define BRANCH_NOC_FSM_STATUS_MASK 0x7 -#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT) +#define CBCR_CLK_OFF BIT(31) +#define CBCR_NOC_FSM_STATUS GENMASK(30, 28) + #define FSM_STATUS_ON BIT(1) #define CBCR_FORCE_MEM_CORE_ON BIT(14) #define CBCR_FORCE_MEM_PERIPH_ON BIT(13) #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) From patchwork Wed Feb 1 18:36:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 649265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D67EC05027 for ; Wed, 1 Feb 2023 18:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232098AbjBASh0 (ORCPT ); Wed, 1 Feb 2023 13:37:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232081AbjBAShU (ORCPT ); Wed, 1 Feb 2023 13:37:20 -0500 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 354AD7EFFA for ; Wed, 1 Feb 2023 10:36:49 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id v13so18618157eda.11 for ; Wed, 01 Feb 2023 10:36:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KGnNtC4Awi0nUMpoeI3htL1/o9C3zMSo8k9y9gT/K8g=; b=Jj0uDyoSYSc2BG3cMNXHfjyAOBmIv/eEYOsj/Msz/PnGphWpGJ/t3f6aRZ9Q7DDiLH UqKzqnkDFLuh+OaemZGHyYvIlDCLls/Yrwr/1ihkecOxLxY4E0zd4MLRP5MEbiApWnKt z0qiawxyqghQSqB9TMJEtoYE+CXZc7jYZUpFym58yrQvc0tOMXh4C3r7JRZ2e1wPbDAe 7b3r9IpT3NDdRSOCd20w2UJHpP4X1AvMBpAO/PaDigoYcOQfjTsOHJ55XbhVP06vHaV5 s/TaIPvFhHMOKtlKKMsuJeId5b4uIIikubJHZLLLSw+D5Ml4WNZRHtDJTZoIga3IDe5P 4IaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KGnNtC4Awi0nUMpoeI3htL1/o9C3zMSo8k9y9gT/K8g=; b=ZxB78OPn1edv1aGcR0EEwxmk1d8utzwtDuG9p73LhdKFuBn99tjL1qo7oc488Kq+jZ 7jJ43y2P3mhNpepqTV/YxPpjZJJHQW73VdFQ6Anv3DBagEj1PJZV4aoHpltqn/tcmfg7 AIojMz3936UZDpvG37hCkU5ffUDTWLX2kUMOMvRmqFpwUbSH7YIMHgWEVHK3zsTkzgXn uE2tTe7v8yMi4pYPFxtidlpj639uOGwK8taGR1i+9A/N0S6O+pcxvwoeeQEQG2kDTpsB QifUW6JQrZx39HcfzXhEKavbDAy75/F+1zWdWdqnxDQL+Zeu6JlE2qI4p9S11R3xd7fj I6Dg== X-Gm-Message-State: AO0yUKX9q4SKrcbG5/n/UmKRTzupCsfRbCMfi9yT84KFwzxQqeLUlnHI dCqmkMAYjo84KA2SQa/HwmdGVtPrIyTtP4T7 X-Google-Smtp-Source: AK7set+FU15vjgJJQfGO499QbgtRoVzoW7swVQmcRwWOdIskzBSUlwSqoXQwGWZvQ+VYCIn4lQ4zNg== X-Received: by 2002:a05:6402:40d3:b0:4a2:4269:6dff with SMTP id z19-20020a05640240d300b004a242696dffmr3605518edb.21.1675276599470; Wed, 01 Feb 2023 10:36:39 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:39 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 05/10] dt-bindings: clock: Add Qcom SM6125 GPUCC Date: Wed, 1 Feb 2023 19:36:21 +0100 Message-Id: <20230201183626.351211-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6125 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- v4 -> v5: No changes .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 +++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6125-gpucc.h b/include/dt-bindings/clock/qcom,sm6125-gpucc.h new file mode 100644 index 000000000000..ce5bd920f2c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6125-gpucc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H + +/* Clocks */ +#define GPU_CC_PLL0_OUT_AUX2 0 +#define GPU_CC_PLL1_OUT_AUX2 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GFX3D_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_SLEEP_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_AHB_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Wed Feb 1 18:36:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 650316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D651C636D4 for ; Wed, 1 Feb 2023 18:37:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232079AbjBASh1 (ORCPT ); Wed, 1 Feb 2023 13:37:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232130AbjBAShW (ORCPT ); Wed, 1 Feb 2023 13:37:22 -0500 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EA488003B for ; Wed, 1 Feb 2023 10:36:49 -0800 (PST) Received: by mail-ed1-x536.google.com with SMTP id n6so16003971edo.9 for ; Wed, 01 Feb 2023 10:36:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Og3Oc91UlBG1GlMV+EWWkVOrWZ/L02m4dPMjrXYNZyw=; b=BN3Sawj+KgXWxL4tPCNWbYiwEBd9parliypO6KAZZyvUX09v8zffqF0H/hF6BH6k3+ h99061XYs8SolRXuy36c/hen7Hm0DReN4UZysXhFk9yHdl4Ekcp8cOJoK3yicG+68itC hmyzBx4+nO9nHonpUIt7qdtGMTeT8McfLodvlJ2J7iJEtVjIyGDKxSsD662QGJgL8Gm2 a3JaH/n4XrgApXXzDOi0LJ52PXnxtuNh8V26Ze0GC+qLgztDCOAsrJi4GUg1s5pzT7Sp QN952mwekQNoSMh868CkYjAfhDWtjb2+eVyqTb/OkvkAVwCqzbfVD3b5fYyRec1+52Mv /CAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Og3Oc91UlBG1GlMV+EWWkVOrWZ/L02m4dPMjrXYNZyw=; b=NW3YJHCR9OKEcMB1m+pEug6EXOOizbUpDnGiz170+JuDpxwjLYuDl5ueZpNlW/CF22 TxTTGx1wrROERiibk60Ejd+TY4V0ut02YhC4NFlzlB3J5pBXnDGRA6NTd5jxifcyNoFz mIPIjET8sF57Lm9TiAADHWEgeBQV/BR3mxKEQ4jDinlB6QUf/abLzDtnmdBRz5uyW1Li XX173s2wPXZx2LLuGLK+O6EXbMZHShvQVI1C751I5tZVmwpjDzokaovz92apxrkZuAOD 8XuAno0pYHh9Rjt+aiCwkqTsL2pV+UbFdjxpVkXqX5ixLxRv6g6Y6pX3WvXW8Q3GupvZ Mh/Q== X-Gm-Message-State: AO0yUKWcrpoojGfjRUx+Tne4mHxxkrCBQZCgqWQixWvcjEo2sEOQaHRQ PfxdpIUcsDrqkLQ7SPDMxGmV9M/8LCA520tL X-Google-Smtp-Source: AK7set9yumJUFQD/JmZWtdEoNcFRaHR1HskltEhIeMMgyMwDVL8QeTNJcsQQjMxe79SSs6Hfj7y1LQ== X-Received: by 2002:a05:6402:160e:b0:4a2:4abb:8d2b with SMTP id f14-20020a056402160e00b004a24abb8d2bmr2929038edv.6.1675276601730; Wed, 01 Feb 2023 10:36:41 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:41 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 06/10] clk: qcom: Add GPU clock controller driver for SM6125 Date: Wed, 1 Feb 2023 19:36:22 +0100 Message-Id: <20230201183626.351211-7-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the GPU clock controller found on SM6125. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- v4 -> v5: - Use the new SLEEP/WAKE helpers drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6125.c | 424 ++++++++++++++++++++++++++++++++ 3 files changed, 434 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6125.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ca6c7d2ada6c..4ee1bf151ee2 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -798,6 +798,15 @@ config SM_GCC_8550 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GPUCC_6125 + tristate "SM6125 Graphics Clock Controller" + select SM_GCC_6125 + depends on ARM64 || COMPILE_TEST + help + Support for the graphics clock controller on SM6125 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6350 tristate "SM6350 Graphics Clock Controller" select SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e41ea0efe8c4..14405ccf1992 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o +obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c new file mode 100644 index 000000000000..d4f1296a48ef --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6125.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPU_CC_PLL0_2X_CLK, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL1_OUT_AUX, + P_GPU_CC_PLL1_OUT_AUX2, +}; + +static struct pll_vco gpu_cc_pll_vco[] = { + { 1000000000, 2000000000, 0 }, + { 500000000, 1000000000, 2 }, +}; + +/* 1020MHz configuration */ +static const struct alpha_pll_config gpu_pll0_config = { + .l = 0x35, + .config_ctl_val = 0x4001055b, + .alpha_hi = 0x20, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x0 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +/* 930MHz configuration */ +static const struct alpha_pll_config gpu_pll1_config = { + .l = 0x30, + .config_ctl_val = 0x4001055b, + .alpha_hi = 0x70, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { + .offset = 0x0, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_aux2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = { + .offset = 0x100, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1_out_aux2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX2, 4 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0_out_aux2.clkr.hw }, + { .hw = &gpu_cc_pll1_out_aux2.clkr.hw }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x1088, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .pd = { + .name = "gpu_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm6125_clocks[] = { + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr, + [GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static struct gdsc *gpucc_sm6125_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm6125_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm6125_desc = { + .config = &gpu_cc_sm6125_regmap_config, + .clks = gpu_cc_sm6125_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks), + .gdscs = gpucc_sm6125_gdscs, + .num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs), +}; + +static const struct of_device_id gpu_cc_sm6125_match_table[] = { + { .compatible = "qcom,sm6125-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table); + +static int gpu_cc_sm6125_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config); + clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config); + + /* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf); + qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf); + + qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); + qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap); +} + +static struct platform_driver gpu_cc_sm6125_driver = { + .probe = gpu_cc_sm6125_probe, + .driver = { + .name = "gpucc-sm6125", + .of_match_table = gpu_cc_sm6125_match_table, + }, +}; +module_platform_driver(gpu_cc_sm6125_driver); + +MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 1 18:36:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 650315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50477C05027 for ; Wed, 1 Feb 2023 18:37:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232218AbjBAShd (ORCPT ); Wed, 1 Feb 2023 13:37:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232103AbjBAShX (ORCPT ); Wed, 1 Feb 2023 13:37:23 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1988B80174 for ; Wed, 1 Feb 2023 10:36:51 -0800 (PST) Received: by mail-ed1-x52c.google.com with SMTP id n6so16004067edo.9 for ; Wed, 01 Feb 2023 10:36:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VugfDnbVGJaahf/oLca3GRkNKUdU4yMW4xYQ5pl9Ev0=; b=tGXEf0inP2Pw2LnTDwfZX+RwJPE8gldwNQdsQUvGROSrMyUhghrRkhLpWkonoZud9j OVu1QwLfJ3gzGv89ngV/2b9oV1XAlg+IDEN2gWGcC4VyljgoMrLjBEyqeglngEKn6/UE trH4EHO8omg0eMz5HUjwcoVVLGxWkQcufoHsmV2Us2R2pgkRruXxPOsfVGfKMea03U7J DLljkWoi2nBdWh5H45PMLNhztUsovu41DhzDCsi95VtjfNfPVNI2/NuArXXyJDY5gw58 8oaCtf3GPf7olyawupf+ymoLZFpRKnLIBcQtN3ceuy4HQWIf7W9HOthAMhAjlGjOjplr RVKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VugfDnbVGJaahf/oLca3GRkNKUdU4yMW4xYQ5pl9Ev0=; b=lF3X0fdX5aF4e7oGTiFgKCQk7VvVgf5NFTrKgBqEineGK9UCjbl45c/9NfvRIb1BJv SdqixUAMG9ki7fqrHNo598nqb5HVnr8XQL1hmTy2uF6HJ7k/ZIipcNQkE1kIVo336ER3 8CNAWgpskSf9C94QDa+skWPkYJb/BnZOuOIpSWZWqmELuH0OKkSwAUztlUNQ/Yi8kpMT mUaGvrMkCPt0racmlPrPJW/r/kZS3R2zk5fSxrrXlfQzEJKPE7yQr79nX2VEePz6FSPy IbUr5diR7HXy08bYPCZyvzsMExuBs2ZySQaala3NDNGx8Sq4UMq2BR0yxoSxp32lHK/r KCqw== X-Gm-Message-State: AO0yUKWYPXiTKWI93Uh88HpMgaDH+JqLSsnujyFn1dnxh+0kz2dDDGm1 +6N7AdkqyAeoOCGIYwLIsht12ROTZm2r2670 X-Google-Smtp-Source: AK7set9G3jxPsrG9cX2HVsEL1eeL5hJQSY0PxOxqYyOMU6X8doqvlObb5DJgMHOjPs52btuNWS/RXw== X-Received: by 2002:a50:9304:0:b0:4a2:7489:a70a with SMTP id m4-20020a509304000000b004a27489a70amr3564955eda.22.1675276604184; Wed, 01 Feb 2023 10:36:44 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:43 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 07/10] dt-bindings: clock: Add Qcom SM6375 GPUCC Date: Wed, 1 Feb 2023 19:36:23 +0100 Message-Id: <20230201183626.351211-8-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- v4 -> v5: No changes .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 +++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..b480ead5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-gpucc.h b/include/dt-bindings/clock/qcom,sm6375-gpucc.h new file mode 100644 index 000000000000..0887ac03825e --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H + +/* GPU CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +/* Resets */ +#define GPU_GX_BCR 0 +#define GPU_ACD_BCR 1 +#define GPU_GX_ACD_MISC_BCR 2 + +#endif From patchwork Wed Feb 1 18:36:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 649263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07CD7C38142 for ; Wed, 1 Feb 2023 18:37:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232234AbjBAShd (ORCPT ); Wed, 1 Feb 2023 13:37:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232112AbjBAShY (ORCPT ); Wed, 1 Feb 2023 13:37:24 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 231CB8017B for ; Wed, 1 Feb 2023 10:36:51 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id q19so8710730edd.2 for ; Wed, 01 Feb 2023 10:36:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RUx8jIbRQCiBSngvcTRQiyqBzdbbv8puC2IXuoEpTPA=; b=ulFSn2TlexHZn+Uu7Yo/jkahQDUrTD4fIYa0VdK9TPpddFrwRCOsMsK5oBQ+0qXmD5 nWQ14GyZU8BtZLSF44sHgjTcdx955I1hQjG5ZtXkuWHROXtlPIAyAYzgxoR2HySekz0X o1yeAMqt6jUvSI44g8vXhpJ2MKdF3o7fSQusm5y2y0Jdrwok3pzMChDm9JGSuSZ23H66 vQV/LGbYQEHR7BuoUsPyXuhQvJWo7VJT3f5x4oAzHbhye8RhJj9qp4vzOX2CK0959pxW a6F3yvjLVtI3zcQTTQoZBoSjRpSiN7kVbvct4UuqosMSHLp9vuXJECtsnPXpuJTQarHb 1XSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RUx8jIbRQCiBSngvcTRQiyqBzdbbv8puC2IXuoEpTPA=; b=EjuLCwgm1meO4zuLmOKHHqzrVWLZw9xU4mf+HEbLhCWYt5PXGnu69Fek3sGC7PTxCA 5mOkJ6UtRbibTEz1j7p3R/+1JKW0psegTh0GuU2v2aIFwd1WSKB7N8CNADf6ZmZaOCNn k8o/skPyMXDWnrflYBDBuoGUjaUnhXb5u5R0KmPeo7HaaU9+1AP1xlS4NRgJoEy2+dQQ X7UpEhn9kj1o8Tji248PFxE4xSqFjFbmqPTGJtJN32kBV+D1MIul91bY4yeKv7us1gGw 8ElkU8ojbxIT+AefZAntNpAHd+c0C8yV4MWh6mKiCkG0udPa+8D8THxZbhqf3PbEs31H 6pZA== X-Gm-Message-State: AO0yUKWbfa7xpffwDfWmz5WTVAVuguaUiYGyrDEw+ebp8wvwZN/R4Eme utwS7Xf/8PYWL4cafdQzXpefZ2bWeZZMQ/1Q X-Google-Smtp-Source: AK7set8zfOJ/pvHEsKE6Br207HwptvkWjMbYp3pxU3oAqUQzLo5aIhfeD2l8zLie2r25HwE7kuNWoQ== X-Received: by 2002:aa7:d7d0:0:b0:49f:a3d7:b84d with SMTP id e16-20020aa7d7d0000000b0049fa3d7b84dmr2931611eds.34.1675276606433; Wed, 01 Feb 2023 10:36:46 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:46 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 08/10] clk: qcom: Add GPU clock controller driver for SM6375 Date: Wed, 1 Feb 2023 19:36:24 +0100 Message-Id: <20230201183626.351211-9-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the GPU clock controller found on SM6375. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- v4 -> v5: - pick up rb drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6375.c | 469 ++++++++++++++++++++++++++++++++ 3 files changed, 479 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6375.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 4ee1bf151ee2..a5995ede04e9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -807,6 +807,15 @@ config SM_GPUCC_6125 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_6375 + tristate "SM6375 Graphics Clock Controller" + select SM_GCC_6375 + depends on ARM64 || COMPILE_TEST + help + Support for the graphics clock controller on SM6375 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6350 tristate "SM6350 Graphics Clock Controller" select SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 14405ccf1992..5a1b65b2ac05 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -114,6 +114,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o +obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c new file mode 100644 index 000000000000..eb9ffa956950 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, + DT_GCC_GPU_SNOC_DVM_GFX_CLK, +}; + +enum { + P_BI_TCXO, + P_GCC_GPU_GPLL0_CLK_SRC, + P_GCC_GPU_GPLL0_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, + P_GPU_CC_PLL1_OUT_EVEN, + P_GPU_CC_PLL1_OUT_MAIN, + P_GPU_CC_PLL1_OUT_ODD, +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 532MHz Configuration */ +static const struct alpha_pll_config gpucc_pll0_config = { + .l = 0x1b, + .alpha = 0xb555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329a299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpucc_pll0 = { + .offset = 0x0, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpucc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = P_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +/* 514MHz Configuration */ +static const struct alpha_pll_config gpucc_pll1_config = { + .l = 0x1a, + .alpha = 0xc555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329a299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpucc_pll1 = { + .offset = 0x100, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpucc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = P_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct parent_map gpucc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, + { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, +}; + +static const struct clk_parent_data gpucc_parent_data_0[] = { + { .index = P_BI_TCXO }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpucc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_EVEN, 1 }, + { P_GPU_CC_PLL0_OUT_ODD, 2 }, + { P_GPU_CC_PLL1_OUT_EVEN, 3 }, + { P_GPU_CC_PLL1_OUT_ODD, 4 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, +}; + +static const struct clk_parent_data gpucc_parent_data_1[] = { + { .index = P_BI_TCXO }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct parent_map gpucc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, + { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, +}; + +static const struct clk_parent_data gpucc_parent_data_2[] = { + { .index = P_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct freq_tbl ftbl_gpucc_gmu_clk_src[] = { + F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpucc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_0, + .freq_tbl = ftbl_gpucc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpucc_gmu_clk_src", + .parent_data = gpucc_parent_data_0, + .num_parents = ARRAY_SIZE(gpucc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpucc_gx_gfx3d_clk_src[] = { + F(266000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_1, + .freq_tbl = ftbl_gpucc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gfx3d_clk_src", + .parent_data = gpucc_parent_data_1, + .num_parents = ARRAY_SIZE(gpucc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpucc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gfx3d_slv_clk = { + .halt_reg = 0x10a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gfx3d_slv_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_snoc_dvm_clk", + .parent_data = &(const struct clk_parent_data){ + .index = DT_GCC_GPU_SNOC_DVM_GFX_CLK, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_cxo_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_cxo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_gmu_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR, GPU_ACD_BCR, GPU_GX_ACD_MISC_BCR }, + .reset_count = 3, + .pd = { + .name = "gpu_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | SW_RESET | AON_RESET, +}; + +static struct clk_regmap *gpucc_sm6375_clocks[] = { + [GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpucc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr, + [GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr, + [GPU_CC_PLL0] = &gpucc_pll0.clkr, + [GPU_CC_PLL1] = &gpucc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpucc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpucc_sm6375_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, + [GPU_ACD_BCR] = { 0x1160 }, + [GPU_GX_ACD_MISC_BCR] = { 0x8004 }, +}; + +static struct gdsc *gpucc_sm6375_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpucc_sm6375_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpucc_sm6375_desc = { + .config = &gpucc_sm6375_regmap_config, + .clks = gpucc_sm6375_clocks, + .num_clks = ARRAY_SIZE(gpucc_sm6375_clocks), + .resets = gpucc_sm6375_resets, + .num_resets = ARRAY_SIZE(gpucc_sm6375_resets), + .gdscs = gpucc_sm6375_gdscs, + .num_gdscs = ARRAY_SIZE(gpucc_sm6375_gdscs), +}; + +static const struct of_device_id gpucc_sm6375_match_table[] = { + { .compatible = "qcom,sm6375-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table); + +static int gpucc_sm6375_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); + clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); +} + +static struct platform_driver gpucc_sm6375_driver = { + .probe = gpucc_sm6375_probe, + .driver = { + .name = "gpucc-sm6375", + .of_match_table = gpucc_sm6375_match_table, + }, +}; +module_platform_driver(gpucc_sm6375_driver); + +MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 1 18:36:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 649264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A528C38142 for ; Wed, 1 Feb 2023 18:37:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232196AbjBASha (ORCPT ); Wed, 1 Feb 2023 13:37:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232094AbjBAShW (ORCPT ); Wed, 1 Feb 2023 13:37:22 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 214EF8017A for ; Wed, 1 Feb 2023 10:36:51 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id m8so9433693edd.10 for ; Wed, 01 Feb 2023 10:36:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MA67TLxXEvH5vo53lgHeUwnhZhAWkiUA2se0bT0//1c=; b=wV8KuSEVvssP/fEzU3F7EhtJaUre6atA3VUbaqj96igtqmgWhsXowwklDYU/JzZw/x Tle3hGCuT+2uXdCPv2Yy/l9yROotXYEDG93aiJJp08ujvyg8Sk7vQk64OQswdLdIbGTg sYPurJNYYp1BIdZMjfaF4dbYKjIipcILLraMpHaF7G/o+4KjGwuU7OExwOxTnmhuObmG KGTFKmFGQvNPrRuI6dnEIWIgBfFs/yosCIq0KCgwkRFI/jMbz72Eivq4bj/J4QALPyty P0POLMzEV4A1086bzcQazRIA8s+2dFRUr73xoXY3Wb2e62J08rSG/0OUCrKvb1wAeLyN L0ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MA67TLxXEvH5vo53lgHeUwnhZhAWkiUA2se0bT0//1c=; b=FWzmI74+vboZAtfBDKSKDp2w63NLd0oeaVmoL16dzY6zogyFmfUq75ASeaLSxbVgYE qm4kveInAMXQy2QSllHBv4I3gunokIeCEs01O5ih++HtCDOMcnLdcIf90JsRkzye/UBT Y9lba5sNDB1IzD+RxySaAM+kobrHvz/dHdHkd7zxX24hTSenohkOPifQ1D3Pkkx/V1zL XS9jbLQ80Y/8HjrYqa5xwl7558nPN3sWaHfWJdnXSkB4sbbv/lvGeQKQdPRf+0zCwDDw nOOAs65KslP66EpBT5YvCI9b4FbXE/k8foHHK/y9oJdD5z1fFFXWN0N6XHC6+9rVq65m mnlg== X-Gm-Message-State: AO0yUKUTUMjRl6fBtvMKjTLz0SONNW8orC11hbHTDUpnqZHiA13fYPRG 7qx+g3e5tynhvC/yl+kG5udA3Ls8y42eUylI X-Google-Smtp-Source: AK7set9BY+ASrlAVSPZqiT5NTlGfv3MX2UUK3N2NJ13b0LlPA+1zmyRTQcy7OrkidnR7I6Jxcj9SrQ== X-Received: by 2002:a05:6402:500c:b0:49e:6bf1:5399 with SMTP id p12-20020a056402500c00b0049e6bf15399mr3378241eda.8.1675276609259; Wed, 01 Feb 2023 10:36:49 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:48 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/10] dt-bindings: clock: Add Qcom SM6115 GPUCC Date: Wed, 1 Feb 2023 19:36:25 +0100 Message-Id: <20230201183626.351211-10-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- v4 -> v5: - pick up rb .../bindings/clock/qcom,sm6115-gpucc.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..cf19f44af774 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Wed Feb 1 18:36:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 650314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55F98C636D4 for ; Wed, 1 Feb 2023 18:38:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232141AbjBASh7 (ORCPT ); Wed, 1 Feb 2023 13:37:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232241AbjBAShe (ORCPT ); Wed, 1 Feb 2023 13:37:34 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C63E7F334 for ; Wed, 1 Feb 2023 10:36:58 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id cw4so13514719edb.13 for ; Wed, 01 Feb 2023 10:36:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XLtLdPRWSgZacRyT66yu3XX23m1pMiw/Q9ZIEMzd6ww=; b=xqNZHviQ1HBZGF2HvVGhL4Xcf6rB3q+R0rA3CNqCTbZc5MDD7YE0V75OF5WWUIjQNX 6xgfPzN5Q+grMmFTiQ/Ed7JDpNXPEWPGY4KmFFYEHST/70Ijdh2/mL73evHSs98gxCDM mqKKFJnH8XkNZE197HwI0zyOXVxmTQ4LUzoAdl3YBONS9ydsRCom88+4FDMwQM4VyUZQ d0n2/UtMJHReLVhP9JAzpBh9vBr9nHX812pB+i4S1W0mrdJPZUVNd/UYpi4cipQjg4Mp jT7w/l4ZXWsxG0LxVMXIc08TdX9eq/YmGjaiQc3olaL6sM+P1566G9P1n6Qa+Ff/9Dm0 71wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XLtLdPRWSgZacRyT66yu3XX23m1pMiw/Q9ZIEMzd6ww=; b=wWQHb3TF07MVgGQDJdsVL8oRzjZCiAcSo7bh61GqwnHTMcZGCOz6e77MdbyS/L/Msp o8YSynRtaouWVrITqllqsD5c/pHbPtOSUkhtvJptl2tl8WRUq4fvkPqAoDtcEZIktoAf bE9DH6LLP56+xdFp9Sx9+1KCiLfXdRqoBbzKcZR2ZDmHL60Ynx2NALNdsm3jXDzwO6A4 B3JQfYO8Bsrp5niVyXTkCOv1M7FJfZXCoVtThig8wx3rFP+Szvn949Ko5XZgohGpfj3Q erVzi/iKSSbQ88Qkl0M4rWGC/6DvlIvw6YxxEgRC9juqZelj1xMfejKGVQo63w/RNJlZ NyTQ== X-Gm-Message-State: AO0yUKULihpkgcf6amnZj+VeQc9KHBx9qBOe21YjVTHf+kEoFdShLSRI 8pLc0b2bMBXtJM8iuYIEOZJMyuW/2MAL4Lna X-Google-Smtp-Source: AK7set8E/a04n1N79P+kXSXfoYNx0Dsv0k3xyYkMl8GJAbb7280nO8pMw5CV3q7LgofH+fTclv5vnA== X-Received: by 2002:a05:6402:1bc6:b0:499:bcd7:a968 with SMTP id ch6-20020a0564021bc600b00499bcd7a968mr3187295edb.22.1675276611459; Wed, 01 Feb 2023 10:36:51 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id t13-20020a50d70d000000b00458b41d9460sm10297508edi.92.2023.02.01.10.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 10:36:51 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v5 10/10] clk: qcom: Add GPU clock controller driver for SM6115 Date: Wed, 1 Feb 2023 19:36:26 +0100 Message-Id: <20230201183626.351211-11-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201183626.351211-1-konrad.dybcio@linaro.org> References: <20230201183626.351211-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the GPU clock controller found on SM6115. Signed-off-by: Konrad Dybcio --- v4 -> v5: - Use new SLEEP/WAKE helpers drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6115.c | 503 ++++++++++++++++++++++++++++++++ 3 files changed, 513 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6115.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a5995ede04e9..825701084323 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -798,6 +798,15 @@ config SM_GCC_8550 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GPUCC_6115 + tristate "SM6125 Graphics Clock Controller" + select SM_GCC_6115 + depends on ARM64 || COMPILE_TEST + help + Support for the graphics clock controller on SM6115 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6125 tristate "SM6125 Graphics Clock Controller" select SM_GCC_6125 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 5a1b65b2ac05..9f6b93698ef2 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o +obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c new file mode 100644 index 000000000000..c84727e8352d --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_AUX, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco default_vco[] = { + { 1000000000, 2000000000, 0 }, +}; + +static struct pll_vco pll1_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x3e, + .alpha = 0, + .alpha_hi = 0x80, + .vco_val = 0x0 << 20, + .vco_mask = GENMASK(21, 20), + .alpha_en_mask = BIT(24), + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .aux2_output_mask = BIT(2), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +/* 1200MHz configuration */ +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = default_vco, + .num_vco = ARRAY_SIZE(default_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = { + { 0x0, 1 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpu_cc_pll0_out_aux2, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_aux2", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +/* 640MHz configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x21, + .alpha = 0x55555555, + .alpha_hi = 0x55, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = pll1_vco, + .num_vco = ARRAY_SIZE(pll1_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = { + { 0x0, 1 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = { + .offset = 0x100, + .post_div_shift = 15, + .post_div_table = post_div_table_gpu_cc_pll1_out_aux, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux), + .width = 3, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1_out_aux", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = P_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = P_BI_TCXO }, + { .hw = &gpu_cc_pll0_out_aux2.clkr.hw }, + { .hw = &gpu_cc_pll1_out_aux.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0), + F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_cxo_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_cxo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR }, + .reset_count = 1, + .pd = { + .name = "gpu_gx_gdsc", + }, + .parent = &gpu_cx_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | SW_RESET | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm6115_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm6115_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, +}; + +static struct gdsc *gpu_cc_sm6115_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm6115_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm6115_desc = { + .config = &gpu_cc_sm6115_regmap_config, + .clks = gpu_cc_sm6115_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm6115_clocks), + .resets = gpu_cc_sm6115_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm6115_resets), + .gdscs = gpu_cc_sm6115_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm6115_gdscs), +}; + +static const struct of_device_id gpu_cc_sm6115_match_table[] = { + { .compatible = "qcom,sm6115-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); + +static int gpu_cc_sm6115_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf); + qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf); + + qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); + qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); +} + +static struct platform_driver gpu_cc_sm6115_driver = { + .probe = gpu_cc_sm6115_probe, + .driver = { + .name = "sm6115-gpucc", + .of_match_table = gpu_cc_sm6115_match_table, + }, +}; +module_platform_driver(gpu_cc_sm6115_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM6115 Driver"); +MODULE_LICENSE("GPL");