From patchwork Thu Apr 25 12:55:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 162849 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1898853jan; Thu, 25 Apr 2019 05:55:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqx0gNR+ytrUAhoLQe0ijeF87ekugC9HHb6SmXoP52lqkvpNiISAQQPBWZl5CyB5EIv4y6vO X-Received: by 2002:a63:e850:: with SMTP id a16mr37331804pgk.195.1556196926324; Thu, 25 Apr 2019 05:55:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556196926; cv=none; d=google.com; s=arc-20160816; b=MkUJhuDUjSNe7IBFlS/Qk3FbIBEB16Wh3EuVKwn7fK/5pI1Cvzd73S9rmhou215+Ih OMebCEkx9qvJK5UUhWUUm6rQGDeOW+zuM1WhpI8vX/LPZO1pZkbgSFoV+ml2Tsx/ArM2 vct2BYXS8Kyf+TNg/ivhlbywE+OUjKZDodwlEJ0xamA0xASdHSL6D4pRUD7dDD8H1hYX R52w1MBETTdMSoWcgMog1NG3t19BFGPVIghi/zSMMrePXFs8OeeJLXAarwWxt4hbZSl4 4TXi7/tj/OLRxchGQngjF1qELBUnXCURZgehYtF7aSe0IqOMXW8LhnHA9/99l1TBq8x1 6IvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=6hXOfflPIrcfGTPZaCTIS2JfePySj2SNkBJwDrcdy2M=; b=noV3OjpOQo4aa2Tkhn9fqyYgUkw3AFClK4kK+NpBesRGos/WfA7xHtbc3UxUIrcyLj cefykkrfWb7wNj38qX3CKEmKtJKpyKRoNiXYah7cUFI8jeWYgm8XRF27DZvgUU3Y6/ag y/VWET2u1F2bb+zq0VHTD/XLA0RDpvQn2n+sk5RaiLCh4Fci3fNWLClRfeZoHnYcQVmj 75j/Hj6Eew6iRRWOwk7OPiOkgLCjlTdNXPnLkvJxLoiuaUe0bieENr5dprtJLb2OpzoA hvGOLPrjYj3/Ni23CwHI12c4WsJmAvX7sdZFHZMwgg1rcBkdkW4cnUNOj20DrdXTbaim Rq3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K1EtZdHR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d1si15130743plo.9.2019.04.25.05.55.25; Thu, 25 Apr 2019 05:55:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K1EtZdHR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728794AbfDYMzZ (ORCPT + 30 others); Thu, 25 Apr 2019 08:55:25 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:44762 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726272AbfDYMzY (ORCPT ); Thu, 25 Apr 2019 08:55:24 -0400 Received: by mail-pl1-f195.google.com with SMTP id y12so8504569plk.11 for ; Thu, 25 Apr 2019 05:55:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6hXOfflPIrcfGTPZaCTIS2JfePySj2SNkBJwDrcdy2M=; b=K1EtZdHR2+sdReH896jE8wtOjZVeBKH+qTEvPUC+dxQIL68C1Jj7+WXgxfaf5ExpkJ v/qvsF9n906LA/+mz6deh36sKPtW6rJnNDQoAtW87L+M3U/xZTtdQLr7hcjc202rLPjA +00NxaiLPalDKXKiX8wYt4oUcrOZeQc/Z5IAsEY5MsMqIqJIj/M8IBTh/qor/yUvW4dg Pe11tO3MgtMbObOT307zjugAmch4BNKsIhIEKFTPSI/VTCJoVmatzO1qRsAQhhVKHs4O AiPaR1AB4C0r8NpGOIk4gqjN8CVExiPV0U1v6JtaLAdj5zPHX3BPZPxgduVrDHk0jygu bPLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6hXOfflPIrcfGTPZaCTIS2JfePySj2SNkBJwDrcdy2M=; b=WaOzRWgbF5wntiZ573VmZ2WhpGG4MjpquVzRVtN9XcZRFMNEIEQRgdYDEA96iVkIsh 2VdrCK9rmyajYF9LQXGcGog/TASe8V3Lq76gG9Tf1OGJWoiWeYEisrrUZqk3KERjnrp1 oKBxQei+DPGUJQ6338okdQGX3sW97us+EmBm4T9C2ZXXRQNUXNBxNiMhZxL+bQGevXob 5pAYdOVJHfthqsVKTBNEXxrxSsQCmwdVs5wptKtO7tPktC7ea0g8OesTsls7ayvjGPIZ TmXIOg+85l6xXTlYtFQmC2+IaE2s2wKXG6e3W3DTV0J3cHMlyDFvIIMytraN83VyyWEZ UAeg== X-Gm-Message-State: APjAAAUd0g0uyfJhpX6BWr4dzQfevsPybeUPh86f0l90XsfGtqnNWzEu L2uv7bniogyJcloOMxX8cSho X-Received: by 2002:a17:902:8a8a:: with SMTP id p10mr39624532plo.8.1556196923677; Thu, 25 Apr 2019 05:55:23 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:81e:2691:7d48:1fca:4d86:743]) by smtp.gmail.com with ESMTPSA id c18sm50507983pfc.0.2019.04.25.05.55.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 05:55:22 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 1/3] dt-bindings: reset: Add devicetree binding for BM1880 reset controller Date: Thu, 25 Apr 2019 18:25:06 +0530 Message-Id: <20190425125508.5965-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425125508.5965-1-manivannan.sadhasivam@linaro.org> References: <20190425125508.5965-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree binding for Bitmain BM1880 SoC reset controller. This SoC has two reset controllers each controlling reset lines of different peripherals. Signed-off-by: Manivannan Sadhasivam --- .../bindings/reset/bitmain,bm1880-reset.txt | 18 +++ .../dt-bindings/reset/bitmain,bm1880-reset.h | 106 ++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt create mode 100644 include/dt-bindings/reset/bitmain,bm1880-reset.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt b/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt new file mode 100644 index 000000000000..0674ae904b19 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt @@ -0,0 +1,18 @@ +Bitmain BM1880 SoC Reset Controller +=================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "bitmain,bm1880-reset" +- reg: Offset and length of reset controller space in SCTRL. +- #reset-cells: Must be 1. + +Example: + + reset: reset-controller@800 { + compatible = "bitmain,bm1880-reset"; + reg = <0x800 0x8>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/bitmain,bm1880-reset.h b/include/dt-bindings/reset/bitmain,bm1880-reset.h new file mode 100644 index 000000000000..e8103ce6f4d6 --- /dev/null +++ b/include/dt-bindings/reset/bitmain,bm1880-reset.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2018 Bitmain Ltd. + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_BM1880_RESET_H +#define _DT_BINDINGS_BM1880_RESET_H + +#define BM1880_RST_MAIN_AP 0 +#define BM1880_RST_SECOND_AP 1 +#define BM1880_RST_DDR 2 +#define BM1880_RST_VIDEO 3 +#define BM1880_RST_JPEG 4 +#define BM1880_RST_VPP 5 +#define BM1880_RST_GDMA 6 +#define BM1880_RST_AXI_SRAM 7 +#define BM1880_RST_TPU 8 +#define BM1880_RST_USB 9 +#define BM1880_RST_ETH0 10 +#define BM1880_RST_ETH1 11 +#define BM1880_RST_NAND 12 +#define BM1880_RST_EMMC 13 +#define BM1880_RST_SD 14 +#define BM1880_RST_SDMA 15 +#define BM1880_RST_I2S0 16 +#define BM1880_RST_I2S1 17 +#define BM1880_RST_UART0_1_CLK 18 +#define BM1880_RST_UART0_1_ACLK 19 +#define BM1880_RST_UART2_3_CLK 20 +#define BM1880_RST_UART2_3_ACLK 21 +#define BM1880_RST_MINER 22 +#define BM1880_RST_I2C0 23 +#define BM1880_RST_I2C1 24 +#define BM1880_RST_I2C2 25 +#define BM1880_RST_I2C3 26 +#define BM1880_RST_I2C4 27 +#define BM1880_RST_PWM0 28 +#define BM1880_RST_PWM1 29 +#define BM1880_RST_PWM2 30 +#define BM1880_RST_PWM3 31 +#define BM1880_RST_SPI 32 +#define BM1880_RST_GPIO0 33 +#define BM1880_RST_GPIO1 34 +#define BM1880_RST_GPIO2 35 +#define BM1880_RST_EFUSE 36 +#define BM1880_RST_WDT 37 +#define BM1880_RST_AHB_ROM 38 +#define BM1880_RST_SPIC 39 + +#define BM1880_CLK_RST_A53 0 +#define BM1880_CLK_RST_50M_A53 1 +#define BM1880_CLK_RST_AHB_ROM 2 +#define BM1880_CLK_RST_AXI_SRAM 3 +#define BM1880_CLK_RST_DDR_AXI 4 +#define BM1880_CLK_RST_EFUSE 5 +#define BM1880_CLK_RST_APB_EFUSE 6 +#define BM1880_CLK_RST_AXI_EMMC 7 +#define BM1880_CLK_RST_EMMC 8 +#define BM1880_CLK_RST_100K_EMMC 9 +#define BM1880_CLK_RST_AXI_SD 10 +#define BM1880_CLK_RST_SD 11 +#define BM1880_CLK_RST_100K_SD 12 +#define BM1880_CLK_RST_500M_ETH0 13 +#define BM1880_CLK_RST_AXI_ETH0 14 +#define BM1880_CLK_RST_500M_ETH1 15 +#define BM1880_CLK_RST_AXI_ETH1 16 +#define BM1880_CLK_RST_AXI_GDMA 17 +#define BM1880_CLK_RST_APB_GPIO 18 +#define BM1880_CLK_RST_APB_GPIO_INTR 19 +#define BM1880_CLK_RST_GPIO_DB 20 +#define BM1880_CLK_RST_AXI_MINER 21 +#define BM1880_CLK_RST_AHB_SF 22 +#define BM1880_CLK_RST_SDMA_AXI 23 +#define BM1880_CLK_RST_SDMA_AUD 24 +#define BM1880_CLK_RST_APB_I2C 25 +#define BM1880_CLK_RST_APB_WDT 26 +#define BM1880_CLK_RST_APB_JPEG 27 +#define BM1880_CLK_RST_JPEG_AXI 28 +#define BM1880_CLK_RST_AXI_NF 29 +#define BM1880_CLK_RST_APB_NF 30 +#define BM1880_CLK_RST_NF 31 +#define BM1880_CLK_RST_APB_PWM 32 +#define BM1880_CLK_RST_RV 33 +#define BM1880_CLK_RST_APB_SPI 34 +#define BM1880_CLK_RST_TPU_AXI 35 +#define BM1880_CLK_RST_UART_500M 36 +#define BM1880_CLK_RST_APB_UART 37 +#define BM1880_CLK_RST_APB_I2S 38 +#define BM1880_CLK_RST_AXI_USB 39 +#define BM1880_CLK_RST_APB_USB 40 +#define BM1880_CLK_RST_125M_USB 41 +#define BM1880_CLK_RST_33K_USB 42 +#define BM1880_CLK_RST_12M_USB 43 +#define BM1880_CLK_RST_APB_VIDEO 44 +#define BM1880_CLK_RST_VIDEO_AXI 45 +#define BM1880_CLK_RST_VPP_AXI 46 +#define BM1880_CLK_RST_APB_VPP 47 +#define BM1880_CLK_RST_AXI1 48 +#define BM1880_CLK_RST_AXI2 49 +#define BM1880_CLK_RST_AXI3 50 +#define BM1880_CLK_RST_AXI4 51 +#define BM1880_CLK_RST_AXI5 52 +#define BM1880_CLK_RST_AXI6 53 + +#endif /* _DT_BINDINGS_BM1880_RESET_H */ From patchwork Thu Apr 25 12:55:07 2019 Content-Type: text/plain; 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This SoC has two reset controllers, each controlling reset lines of different peripherals. This commit also adds reset support to UART peripherals. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index fdfdc65d29ef..37ecb760a2d2 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "bitmain,bm1880"; @@ -92,6 +93,18 @@ compatible = "bitmain,bm1880-pinctrl"; reg = <0x50 0x4B0>; }; + + clk_rst: reset-controller@800 { + compatible = "bitmain,bm1880-reset"; + reg = <0x800 0x8>; + #reset-cells = <1>; + }; + + rst: reset-controller@C00 { + compatible = "bitmain,bm1880-reset"; + reg = <0xC00 0x8>; + #reset-cells = <1>; + }; }; uart0: serial@58018000 { @@ -100,6 +113,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART0_1_CLK>; status = "disabled"; }; @@ -109,6 +123,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART0_1_ACLK>; status = "disabled"; }; @@ -118,6 +133,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART2_3_CLK>; status = "disabled"; }; @@ -127,6 +143,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART2_3_ACLK>; status = "disabled"; }; }; From patchwork Thu Apr 25 12:55:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 162851 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1899028jan; Thu, 25 Apr 2019 05:55:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqwOgnGDZLirSlvw5N0rNE7N9RmFo7egpsJBzkWr5bbK5R70Vm8BPQzC4WNe24mwDjgudMWX X-Received: by 2002:aa7:8019:: with SMTP id j25mr40738012pfi.77.1556196935451; Thu, 25 Apr 2019 05:55:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556196935; cv=none; d=google.com; s=arc-20160816; b=pXQAgKbnv0pN0ivFwoYH44SMCsrydo+LLs9L97Jnny1mdYkMS4fe7HMyIaEQjm7pGw DKjrHDnL+aojOUDSi1SAF9KJwQMGV0sgiRdf4fplJ8oU3R4VWgNf1+s8dU0ZUgB9M3Bw 4xDhgrJs367C9slHdVfhJAc3UhZZJovYsNa+IW7rRw1sB2SU0zoyBf1du2lDDTLEUSVS AkXagytIIWMmzDHTjU7QK2OAWXL24TEQZK+b8TTfHDGULCdlQVvelMEe3bkCyC88RtHY wud/MUlbEeszF1/uXzr9AFhruTDtKvAmFtpCHjJE6Cco9U6z2OBdKXD93LPiHGhe+a82 Ptwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=8wBY4DrJYGHWrcFUmZjiCL1GZae6MKSXg88kMv8qUJs=; b=OkSudDBfK4KsqkjoaVuGVYGFdTvCgllKHt8PWL5AJvr7/Ev/zIuHZEyWXuupWH2Pu6 ZYkIPvs8OBAdeNLjQ0vgR8H4wBwsf2r/mnRAUroSCdjQWuXL+0goTLvqDuHg4i3VtX9w 4fLgz2ztYH1zifv40dq76BAVw5s0qmob9ZF/hvko6lv181J7P15jpLLHlOPKG3aX2hsK WGmF0Mmh3t8P/P/gV2ma8J7Vu7B7cKPeWuonInJf/jUWi82uJc+AlL1twFzBisTOwZSQ 5CydJd1EYiJciBTbdfF1Ygko9wnFsGUzTz6eFopqIgr4oT6AiTefI2BZ7a1yzhy57sQp T1qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="kpt/0gZ4"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g19si11840406pgk.532.2019.04.25.05.55.35; Thu, 25 Apr 2019 05:55:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="kpt/0gZ4"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729078AbfDYMzd (ORCPT + 30 others); Thu, 25 Apr 2019 08:55:33 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41973 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728921AbfDYMzc (ORCPT ); Thu, 25 Apr 2019 08:55:32 -0400 Received: by mail-pf1-f195.google.com with SMTP id 188so11139634pfd.8 for ; Thu, 25 Apr 2019 05:55:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8wBY4DrJYGHWrcFUmZjiCL1GZae6MKSXg88kMv8qUJs=; b=kpt/0gZ4WrV9SiGhJ7LUvRdANxf1yoZCJH59nBxbGmEN87lgZU0zmDaK0zbjhO7BLG utf6gA5paYqhvOPoQZULRLLHoxbGrpcyjoo0Srwg28SpomupgdlyfEaGXKM4E4WWPzMD d9vSpUAbWJzG7yM6wfKaL7fMtHgfuZMBGLtOUYvGF0YHuMDzBWmPxOPVH8Hch8x0pxU8 8FceKSLo+h0ie0C2V3G3NuCXwi9y66ENXD9yCaoeg07jiJWERnqUDi116toaFfMHz+a7 Snx7/z1M4B+tBKqT+ijdrEWcYvU7/UgzI0eA7GMb40edMPbxfit+kG2Xmf5VhDmE+TJF QB1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8wBY4DrJYGHWrcFUmZjiCL1GZae6MKSXg88kMv8qUJs=; b=fuIxkGjEsMEteivHCJstfNsUO6cNFoXGF6/Wmev01pW4rrGUw708YTXIsPwCrKOU9i HgbAypgSj94HvQdqd0NAh+DIXAlSvO58mPXCoBTzlLIXcEdVY5G5qtqD/xjx3SmBcdG9 HwmzHtuzcfubRd27mNyK+cxGyh0+bjCMGJjIZ/ZgDKgHAGw3rdNvHxZQHc3hL0wd+Z9r gTXoBZy1HmO6MfOu/cSrKS/OTHxxLaifl+gg4Ro7J5NiHF1Ld0ns8d3VMrcEsUJdAvHN qIcxK+sYJ52v0t374m70sQA80DPkLHM9cyIchtya3zp3zsEmwlh8Wu4CPmhGvg9r1/kb wHaQ== X-Gm-Message-State: APjAAAViDQIPEG9+4u3ha8B1WeFTTmp+hWpIhdH7lQ4UvtF/afYQfdg4 nX/rgUhYYr8U7MDUk+xDosy5 X-Received: by 2002:a65:424d:: with SMTP id d13mr37022632pgq.318.1556196931990; Thu, 25 Apr 2019 05:55:31 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:81e:2691:7d48:1fca:4d86:743]) by smtp.gmail.com with ESMTPSA id c18sm50507983pfc.0.2019.04.25.05.55.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 05:55:31 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 3/3] reset: Add reset controller support for BM1880 SoC Date: Thu, 25 Apr 2019 18:25:08 +0530 Message-Id: <20190425125508.5965-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425125508.5965-1-manivannan.sadhasivam@linaro.org> References: <20190425125508.5965-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset controller support for Bitmain BM1880 SoC reusing the reset-simple driver. While we are at it, this driver has also been modified to make use of the SPDX license identifier. Signed-off-by: Manivannan Sadhasivam --- drivers/reset/Kconfig | 3 ++- drivers/reset/Makefile | 1 + drivers/reset/reset-simple.c | 16 +++++++++++----- 3 files changed, 14 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2c8c23db92fb..b25e8d139f0d 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -117,7 +117,7 @@ config RESET_QCOM_PDC config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, @@ -129,6 +129,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - Bitmain BM1880 SoC config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 61456b8f659c..b87968771166 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_ATH79) += reset-ath79.o obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o +#obj-$(CONFIG_RESET_BM1880) += reset-bm1880.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 77fbba3100c8..fd1fa4984d76 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Simple Reset Controller Driver * @@ -8,11 +9,6 @@ * Copyright 2013 Maxime Ripard * * Maxime Ripard - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #include @@ -119,6 +115,14 @@ static const struct reset_simple_devdata reset_simple_active_low = { .status_active_low = true, }; +#define BM1880_NR_BANKS 2 + +static const struct reset_simple_devdata reset_simple_bm1880 = { + .nr_resets = BM1880_NR_BANKS * 32, + .active_low = true, + .status_active_low = true, +}; + static const struct of_device_id reset_simple_dt_ids[] = { { .compatible = "altr,stratix10-rst-mgr", .data = &reset_simple_socfpga }, @@ -129,6 +133,8 @@ static const struct of_device_id reset_simple_dt_ids[] = { .data = &reset_simple_active_low }, { .compatible = "aspeed,ast2400-lpc-reset" }, { .compatible = "aspeed,ast2500-lpc-reset" }, + { .compatible = "bitmain,bm1880-reset", + .data = &reset_simple_bm1880 }, { /* sentinel */ }, };