From patchwork Mon Feb 6 22:34:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650960 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2531283pva; Mon, 6 Feb 2023 14:38:46 -0800 (PST) X-Google-Smtp-Source: AK7set8AVV4Xkm958U2mCu/OaYZK/ToXFdm9SLCjDYq8+Eud15JBenwK3iYWU9Adp/bwMCam83MN X-Received: by 2002:ac8:7c54:0:b0:3b8:461b:4134 with SMTP id o20-20020ac87c54000000b003b8461b4134mr1503691qtv.68.1675723125863; Mon, 06 Feb 2023 14:38:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723125; cv=none; d=google.com; s=arc-20160816; b=ZVh/FRysEMKdHW64VQ+Gh0lsR81jmNjHWpg835Dn9FEx1oTRRjDjDEjPanhu7nus0R eARmQuRbJugdIVO5j0fTaKZxp7iFD7I0iRVcmmI7m4Pn4LJqhb+idP0Mf+Du/3YeQS5A 3iAhC9iEzTH7nWFd8EpG2P8xESJ2EUCpU7Tz+ckuDuMj2QG6FlmOh8xzGXRXgkwbsQa/ Bo97q65LuI8zPWxici14fyf5VxfxP4tfLy2jz+3ms/xnvtJVZ/W89jV3+3iG8RRwICUj +I968idz2+dAtk6eHqtaf4ZI/TBH/UQg3ifU8NCtErU97+0lthfEVX0xUTTJ8aM635Kl e/xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p4gyS8VSD6RIzTedBzt7OIRvLu1nwoR5LZytAL+qtYA=; b=a5Ht7qQqqnihk9eWWtbmMXeAFiwY/oSmdOyMnN3mxDWdo9k1hA4l8/+T+9K3fclNDU tSKjVCNfyL4jWHq//hB0lvSk9jrL68KLj1krTAR8kkv4yZNncJx/AuYu3/vvFjR4t6AN /kUDuzAgSqeKmqPC3qQG7GVH9pTBySZjkNNDyPMDnIsBNh53JJdY/IEXe6OcCQb5aTb8 t4XyPjfvFqlv3mvXgWpNfWFf2O3M0RK7Q5j38fYOAdFwfyHQhKUPSGO3Js5VwwNufgbG Stdch7Rfrqn5lXYw4S6uDb5l6vHjif72BK3cruXyzjFfEfCFBrzAdPU64jhBsWyekflW lNDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M0jkkyt+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n11-20020ac85a0b000000b003ba1da18a39si5127281qta.589.2023.02.06.14.38.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:38:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M0jkkyt+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5M-0001q0-EH; Mon, 06 Feb 2023 17:35:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA4y-0001i5-Or for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:26 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA4w-0004QP-1s for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:16 -0500 Received: by mail-wm1-x333.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so11920018wmb.2 for ; Mon, 06 Feb 2023 14:35:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p4gyS8VSD6RIzTedBzt7OIRvLu1nwoR5LZytAL+qtYA=; b=M0jkkyt+5OA03Ycl5VLUGKKEtqBl6coUbdTH6Dxixe+6IAEiK7xLR6nDhOkjDL41Oy P0zwEHgnfmurEJ17sVxDvcrBtPTbiKOiNroNcydc8oY721IEnr7Gs/g+y+vNwmHLBWIp UAWRkacDWwLyxGTM7uhCmotCHHg1VYE4XREeuOkPBNr8OPSz37x3MSam5Pn6VGeFsHRX qc+YWiPGLicw8SqkappHHWVNN//ANKcblzJcRxx4PVdiouZ/kx90XnH1Vh9NgEf1srsB pHe+yBR/1IGXZ5umvvftuCCsqZ524+vFUDgX6V0qZn9YCl4iAWswT/RafqrsRHfpShHh 7u6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p4gyS8VSD6RIzTedBzt7OIRvLu1nwoR5LZytAL+qtYA=; b=jeNwkItHWCr4+UDu1+vBNcNajqdOMCtYvsxu16lNovkmed3mVdrLpVGMYjrf5Z5bhI 5UKYw2yDFhwht2ITxuf4dx55bcHNkkLJZvTPXSYCObveeTDMKqZWcvUnVWdEPGgCWae3 02q0Gwsr2XzhHh5GUPjWHicWVqiEJsLVsjdyYTMSIf5ml8iQhjXOqgGOp9k1gjJkJfVL k/f2FPuCoigIamQXmQnwNyUdu3/R7YeTbdr45i6X7VQUyPfhCywVJktZ5tmUUZYiw/2q zYBEdVwqgbCAlYqhN6NZ7M31z86zhgwQe4VCLcnYnOxL2TsbfQ7y3TiQGRoeeJqcKfM3 1aoQ== X-Gm-Message-State: AO0yUKUXCnU3aVwuypioxMnNf/0GxrYwP2ol/RnX+Zj5J/mEfJi46SjI v5d/EIlNvcWnW9pFOZWLQ73eFp9Ssfz9FnjV X-Received: by 2002:a05:600c:1613:b0:3df:b5ae:5289 with SMTP id m19-20020a05600c161300b003dfb5ae5289mr1115598wmn.8.1675722910146; Mon, 06 Feb 2023 14:35:10 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id o37-20020a05600c512500b003c6bbe910fdsm18922037wms.9.2023.02.06.14.35.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 01/11] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro Date: Mon, 6 Feb 2023 23:34:52 +0100 Message-Id: <20230206223502.25122-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, similarly to automatic conversion from commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/intc/armv7m_nvic.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 0180c7b0ca..07f9c21a5f 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -16,10 +16,7 @@ #include "qom/object.h" #define TYPE_NVIC "armv7m_nvic" - -typedef struct NVICState NVICState; -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, - TYPE_NVIC) +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) /* Highest permitted number of exceptions (architectural limit) */ #define NVIC_MAX_VECTORS 512 From patchwork Mon Feb 6 22:34:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650955 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2530365pva; Mon, 6 Feb 2023 14:36:16 -0800 (PST) X-Google-Smtp-Source: AK7set9sTfKwuabK7MF7F7ujpkX8k4kTIPnioTnoNc/bYv2aCZio3rCSxGZNWdkifM1Cc9zrPvQB X-Received: by 2002:ac8:7fcd:0:b0:3ba:19e5:3e45 with SMTP id b13-20020ac87fcd000000b003ba19e53e45mr1911213qtk.13.1675722976183; Mon, 06 Feb 2023 14:36:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675722976; cv=none; d=google.com; s=arc-20160816; b=S6a1vgZyAB3FoECn2j8/6nr5cAMxSRyYPpkiMRXCHA5K12jZZ9mCESmOTNzcsp1bg+ rglVwKJu1Wu3KchOV1ZpdmAcMWODlo675YQtEjEEYb2FGclllbv58l39S7miJKpbVMXn CrRlEfagrQm0InSfpYcRsr2UNZxuo+uk954wlcnOB4RYqP3PWHo9mto6FK9MpBj3Kx2p XSm4x+2ui6gHkKKWD8cPO7Ju76LxCsDUQCGLJvkI6/rKgXE/LPgSbRqE3xukBE0T929C BIbztwUo7mpHZ25tHJFZF4KwsLVUeEFH94ZqZ4k2o8C+HeD4129n0FKEDo4hBzFFHPb5 X93A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PqS8f1SsLczkqeP2a5G3rABOyp0fVyhf7LwTVRK5JbM=; b=eo+NiUSp/qi7jVHpVC34MJS+dr/y3Yico2Yobd5zoFZa8WXe4cvpDz66/2Rb+7Ps43 24GTC/Q63EkMBRYjJdLMQfPOSpENrR9/gyT7vD6yti3aNzfhQ7r1PH4MXfGf4xbQ+H98 ivHl/tzxsbrxbjAuwCTWRVCk5/WxnCaMXao4oP0uMuo+/0rRGFjx6S9FlBVTg10/66k3 RRCPy2KaQoL5Ym3ebosl8okOoVOaZ9WvB7NZZkFA6ZXEAi4/arnvfhG+sdmNT50cNMea 6GnYMLG0jlyLqHiUP28IKQFq316aKJzCJLn92gVwyyDAYmOs5bsdXDtSgB5erBERBclk TzcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VcQPq29o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t30-20020a05622a181e00b003ba23fbfe75si4034425qtc.398.2023.02.06.14.36.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:36:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VcQPq29o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5M-0001qA-Hg; Mon, 06 Feb 2023 17:35:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA52-0001ip-VV for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:28 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA4z-0004R2-EN for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:19 -0500 Received: by mail-wm1-x336.google.com with SMTP id f47-20020a05600c492f00b003dc584a7b7eso11901937wmp.3 for ; Mon, 06 Feb 2023 14:35:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PqS8f1SsLczkqeP2a5G3rABOyp0fVyhf7LwTVRK5JbM=; b=VcQPq29oDvlBhGLhvTpTQy6lsGEwc5fzIWcgFrIwcL7y40SCRV3nzJgeKMA9/eQBWJ 2DpTKvrqN6NPihFphi6F7VXDSBrKr9FEAwURq8EOD2m/bP0suDzfdwj8SyDQvnvckRfx a17SdDEX1QJhQ1tUWB8B+CeO2kA7nDeP5d/1+hV3XBaaBlCBTjDIAPMBWwl/nrKb8dRo 4M01yK3ZvgZO6H+dJwk9YMUcbDI3nUDHxPqwSkIQTWvZ+YRf98WtgglsFZfPCAvIiGZM RHZENNbKa13TCEvS9rEIQLHVl8eq4vkW0h4/0leM8wzU80CyYFD/N2QhX7qhO0GuPsdj 0SVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PqS8f1SsLczkqeP2a5G3rABOyp0fVyhf7LwTVRK5JbM=; b=sUwLxRkprYr7DRBQ5CxdQ/hRTrS13ssn+OFH9F/G0rh4rg5SI37u1LniEv3iI5RrEO loZB5am1zUgh7aC0XpWhv86KiomBmo7I4tQ2Kbq+7hcfwFDcV6CgFv6nbd1ntFlREVgD gXXqAWnUiDHZtovlo0fHu7F6EB4KWbTpVypFj8G1EsBUDhbK6/Yj4pjldDYxxdhQpaLf xsk8ASr2nRiGRie0irjpc8Zo/zO1Qfs94wut4w/lP/RVb3oQ60oFc0AngFZ30eHCaG/h +kuKMwbgu4ifMwxkAk+FbFYL8WbeTGGaTOo9zIHCNyrIted8HWMcGOrK/6Evg03vwUD7 4Fyg== X-Gm-Message-State: AO0yUKUeOWwKVN+z2z/cuBHYU9rX+Z1q8StexbKIT36sElBI9irXklR/ tfo1xBlGVep73d/k8OLUNQ5yJ3A4mgisiz5a X-Received: by 2002:a05:600c:4d21:b0:3dc:3398:cf87 with SMTP id u33-20020a05600c4d2100b003dc3398cf87mr1149674wmp.11.1675722915674; Mon, 06 Feb 2023 14:35:15 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id o14-20020a05600c4fce00b003dc1a525f22sm12732030wmq.25.2023.02.06.14.35.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 02/11] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation Date: Mon, 6 Feb 2023 23:34:53 +0100 Message-Id: <20230206223502.25122-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/m_helper.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index e7e746ea18..76239c9abe 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -150,7 +150,12 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return 0; } -#else +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + return ARMMMUIdx_MUser; +} + +#else /* !CONFIG_USER_ONLY */ /* * What kind of stack write are we doing? This affects how exceptions @@ -2854,8 +2859,6 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return tt_resp; } -#endif /* !CONFIG_USER_ONLY */ - ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, bool secstate, bool priv, bool negpri) { @@ -2892,3 +2895,5 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } + +#endif /* !CONFIG_USER_ONLY */ From patchwork Mon Feb 6 22:34:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650964 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2531437pva; Mon, 6 Feb 2023 14:39:09 -0800 (PST) X-Google-Smtp-Source: AK7set91x0rGq1bcraoyX/ltCnpoOjnicTzDzsdB1OtjPUix2KNCX2Dh3oehrPW1lgAtZuqiZcNg X-Received: by 2002:adf:ee52:0:b0:2bd:e7a0:6b5e with SMTP id w18-20020adfee52000000b002bde7a06b5emr614398wro.40.1675723149023; Mon, 06 Feb 2023 14:39:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723149; cv=none; d=google.com; s=arc-20160816; b=yYHnTySrSrwSWPyHkKhrfx7mtVCug3JqAO6Zayj1haR+8etmKchXhzBqAJRwbanuxR Psq+n+58c8UzxHmUqQqyFcjKmoX9f1EA36C+C5ofqP9/p5DGGnAdlhr19P59LXS95Gfi V+26N41GRM3ramWJ68/EDlyVjyYxY1bFCPeNe4vHW2t/JOZhGMTFtkRKo/zsqC6e0uOv 2lP25uPK0F5BJp9NrGnZ3Rg/wkVubWLyI1gXdaFvU941UxkbDRcy1vUmDH7Xan0kdcA8 UDcu0mWuM/7SR+0ICGkdgOQS2Ae2jcGxdBO1XsWXM/tN+Y93n1G9DM1XuX4xkWGbuglA oAdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=A95YCGa6JM5usJ8r5LH9ThRro8jldDCk7TyXyCW7Wr0=; b=h3ziZWeDuQzPwb/S9c6h67W9+EEhqEQwnyNz6ytdB217PfhoV+Px1hCzP4fRrEe8x/ dzzAMIipcI3JR76nfvkOwtI+4zygfkF/qrwtoImLBXaCHYCMRMDfussY9Re1IWax0ReQ 6B0y/b906jxbL5dyuhq9vDfdOYrpvDgUCPVJCnWRU62/8nJA+kFKYupa8K2lh86jyWax /xKIzwIl3nnvdKxPeoMqoU9bvlk5dz0QYC5pB2hPanOOuEAOf0uBnr8uGYHzWqnpW2rQ lcPMV5pAoP8wCpPA5Djmv1W8bFFu0RlwzABnUdm8IHXJQo+A9aiFA20rnnA9BhUjDqG8 jziQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r/yrr937"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g1-20020adfd1e1000000b00293b54e4f0bsi14929369wrd.382.2023.02.06.14.39.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:39:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r/yrr937"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5L-0001pn-O1; Mon, 06 Feb 2023 17:35:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA58-0001jj-Ci for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:28 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA56-0004Rt-Oj for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:26 -0500 Received: by mail-wr1-x42f.google.com with SMTP id o18so11895300wrj.3 for ; Mon, 06 Feb 2023 14:35:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A95YCGa6JM5usJ8r5LH9ThRro8jldDCk7TyXyCW7Wr0=; b=r/yrr937Nb9XGVEVXlDO8JoLMkqy5W+rWgGSuxz6xwh92VT16Iy9LFmvKr5QPhl2hS l7oib5TBVPahjANY+zFcuYFKsjYIdP58B3L+I3YPnmWNZ0JSJqTJ0DvEA6QaNCKfpotT 0gChsHDcI2avLSKsa7OZRD0gTFKOf9m/2+njh/mbsxeoyrQowtTQAog/CztxLeOU49Vw mivHUKJt7j0BkcicVLgnmLs+5WplDbIcB4aANjhqV3Q9VKLHeRmxZxxhHSUOVFQfYwln 9AUAqApUBSgAqwRluLRSGkleQdu7fDaJZCCpaTNsPRfUaj3lUcMGTUiaimqOm6Sa5O02 la9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A95YCGa6JM5usJ8r5LH9ThRro8jldDCk7TyXyCW7Wr0=; b=j3rW9bmpaAe57u/HIuO9wRT3XwZH+tC37O8KbSy5kRA+YMl2uDU2gyAsObnRvt/EQE cNdO9pTntmKCBa8faP5TgiL2NIVLqlC1Dt8kvtfOvYj2gN+CuLb+0CJn0sM0uZOoSaou /hWS1l3bA3i7fiO8wniHg04SCzIIUWhcUQXQd6+pIqzts4e5mKOBI4vJJJ7vfGWmkiD5 woSPgt3uwKFMzibV0o/WSq9mx+xepSu7AIYZwamQJ4155wIpOqveqrSrn821uB2YmUsO Syxs84+fiwdAZHlquzccIJd33MKrc+MUZ9Q2t92+aDIvgQUefZxtVEVBgsiRFGC2OHBM 2Rdg== X-Gm-Message-State: AO0yUKX0COzJUwbuntG19rLyNzUEC2xXHdIzxBksjQyqWMlnvFpl6rje 1vVxSqpFhM/LX6MhaNbbcAgoTN5iUCzK79vA X-Received: by 2002:a5d:6307:0:b0:2c3:e993:9d81 with SMTP id i7-20020a5d6307000000b002c3e9939d81mr622961wru.66.1675722921371; Mon, 06 Feb 2023 14:35:21 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id h12-20020a5d688c000000b002b9b9445149sm9797132wru.54.2023.02.06.14.35.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 03/11] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope Date: Mon, 6 Feb 2023 23:34:54 +0100 Message-Id: <20230206223502.25122-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() are only used for system emulation in m_helper.c. Move the definitions to avoid prototype forward declarations. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/internals.h | 14 -------- target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- 2 files changed, 37 insertions(+), 51 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e1e018da46..759b70c646 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -597,20 +597,6 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); -/* - * Return the MMU index for a v7M CPU with all relevant information - * manually specified. - */ -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, - bool secstate, bool priv, bool negpri); - -/* - * Return the MMU index for a v7M CPU in the specified security and - * privilege state. - */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv); - /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 76239c9abe..b4964dca8a 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -157,6 +157,43 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) #else /* !CONFIG_USER_ONLY */ +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, + bool secstate, bool priv, bool negpri) +{ + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |= ARM_MMU_IDX_M_PRIV; + } + + if (negpri) { + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |= ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); + + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv = arm_v7m_is_handler_mode(env) || + !(env->v7m.control[secstate] & 1); + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + /* * What kind of stack write are we doing? This affects how exceptions * generated during the stacking are treated. @@ -2859,41 +2896,4 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return tt_resp; } -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, - bool secstate, bool priv, bool negpri) -{ - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; - - if (priv) { - mmu_idx |= ARM_MMU_IDX_M_PRIV; - } - - if (negpri) { - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; - } - - if (secstate) { - mmu_idx |= ARM_MMU_IDX_M_S; - } - - return mmu_idx; -} - -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, - bool secstate, bool priv) -{ - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); - - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); -} - -/* Return the MMU index for a v7M CPU in the specified security state */ -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) -{ - bool priv = arm_v7m_is_handler_mode(env) || - !(env->v7m.control[secstate] & 1); - - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); -} - #endif /* !CONFIG_USER_ONLY */ From patchwork Mon Feb 6 22:34:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650956 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2530565pva; Mon, 6 Feb 2023 14:36:47 -0800 (PST) X-Google-Smtp-Source: AK7set9tsJZKBPYDh+QvAYIUGxMF86MGcjF2R871oc6xpKU0dpVZHKn3R69ADfS498glzeDoZlkp X-Received: by 2002:a05:6214:5094:b0:567:d3cf:65a6 with SMTP id kk20-20020a056214509400b00567d3cf65a6mr1207925qvb.4.1675723007692; Mon, 06 Feb 2023 14:36:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723007; cv=none; d=google.com; s=arc-20160816; b=e2R2wjJd5JMlwAJ4O07URZhrqlUJrXailxgZrOmOj9jjih5ae9s3AJVxLTKEOoIIrs Vjtp8gW+reR8jaLyxpZeksR0euleeh43+eKQKaTTbzYtz4U+ZoJdisNkEHD4jED2aJ1z g92pPjG+LCIxy4k8AurVhJHiBc2MB7lFZAwNuyg/hmkUnpaSfJN0kPQePqnq5CDUAUEb 2zA+VQ7Ae7S7qCfWYwrghXPkrVT+z2aAuzTPwGNtZh5wwGYPpIekZHmyBQdq7o00qGWp gYO1eSNcXSNyYdQPXPSZWppZlOjXfTryuwUD6v1OgPD0mH/umAIQ7EBLsNsSJaBDA/Ip 318g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=19uwBfdpAT1fRxylT2Hyf84R7eD4Io8guMa3+/7IF5E=; b=n31UjRNLuhq2U8h0XkFcmthx3WjDdsUjtBru1qihwBm1TB/gdfvvs0hvb7wqJ5v6tQ fxWxjC19Vst/Lxq2OQtTXF8CHmlYimNGGOO8ls6aHUtPHt32U7aTHu5xR5P8rcijDpx5 RFFBZ7oL5hcgVf75U35A62CT0LhBR95id6w+DyyQi5YFHTlfAGyXkGAw8/YoWZVVruFG Lbczlcl6j3+AgxUXvUEfls0Vsv4pZaD4WyBnLJL3qU3JmDpg3eJPn5lh8FzavL1TuQJo ehEzF7T/K3doo+eENjkvky9aUHM8WWIrkYjr+mHoxatFZeU4Rfq5HnWrALzloYFKAMCz y58w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CGJ8bxT2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k13-20020a0cc78d000000b0053773334bbasi8546142qvj.360.2023.02.06.14.36.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:36:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CGJ8bxT2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5K-0001op-UJ; Mon, 06 Feb 2023 17:35:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5B-0001kk-MD for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:31 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5A-0004TC-6W for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:29 -0500 Received: by mail-wr1-x429.google.com with SMTP id j25so8350758wrc.4 for ; Mon, 06 Feb 2023 14:35:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=19uwBfdpAT1fRxylT2Hyf84R7eD4Io8guMa3+/7IF5E=; b=CGJ8bxT2P13F5mXwid42JRnMFxipx7ovw7vNTLmbt+wq0xGlmfQ8fwqhsOY/s9PV28 hTbgFnbZytKVDxHEjC14d4u0bLZ56SrMQ5XmEPYACSMTqlqbzJiSzDcLGgZN1iTG5FOs Kemjol8J+ZOfuul+XIierj7z0DQmCiYmMSIg9eHOPIQSF71P0drCMGFNtEU1Z4nb4wFt z/eOSusBITbRaT9MTK/O+pq3miYOQ1sPOsobOqDLje+Xo604BgQiQwW0NvgiwaqTKtbG jTq9twDNIPiyVL098S1fELJtWXmBODyUsd1vMCoezRuaqEltOD6Q1FR3oLMoQfTLYCVV kRlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=19uwBfdpAT1fRxylT2Hyf84R7eD4Io8guMa3+/7IF5E=; b=tGRTTk7VT5oFA/+X5XIMj45/h7hnqI5VweS8rXM+/ou6eDQw5pn4STq7RV7KW4XGdT YEOJ0x31r6P6a7SIGrjhhpVLJWp6hiwWm4WSsJtReUPJmTZtpNKFBQ8d02gI57M2eVfl m4lr4UvsIgg/8BDyALAhHK9zaR9Y+jkY1wfndPJlQ47t9dCg6rZPkSoc/AuT5fRW/DPj Y0k6hYs+XPnO9GGapjteD7BUhvNIs2X4Jrg9DIv4qROpV2F6KdlCYMcykCUXyz4W0TK2 QH+S27Lqw7VhbR2SJKnLX3s+786KTVJKdljl2DYTLnGx0lHKujECJPqP4zLmj65o6QwZ MatA== X-Gm-Message-State: AO0yUKXgMOyp7N+heW2MXPhgvUA2JdEH0KAHjXVtItfvUU8NcSAgvRAG NL1zcv1ji+kz7POrrqKIkUaw/p5JuBJ1WQA6 X-Received: by 2002:adf:efce:0:b0:2c3:db9e:4afe with SMTP id i14-20020adfefce000000b002c3db9e4afemr384789wrp.60.1675722926561; Mon, 06 Feb 2023 14:35:26 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id e6-20020a5d6d06000000b002be099f78c0sm10224886wrq.69.2023.02.06.14.35.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 04/11] target/arm: Constify ID_PFR1 on user emulation Date: Mon, 6 Feb 2023 23:34:55 +0100 Message-Id: <20230206223502.25122-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c62ed05c12..22670c20c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7021,6 +7021,7 @@ static void define_pmu_regs(ARMCPU *cpu) } } +#ifndef CONFIG_USER_ONLY /* * We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. @@ -7038,7 +7039,6 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } -#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -7998,8 +7998,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, .access = PL1_R, .type = ARM_CP_NO_RAW, .accessfn = access_aa32_tid3, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_pfr1, +#else + .type = ARM_CP_NO_RAW, + .accessfn = access_aa32_tid3, .readfn = id_pfr1_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, From patchwork Mon Feb 6 22:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650962 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2531386pva; Mon, 6 Feb 2023 14:39:00 -0800 (PST) X-Google-Smtp-Source: AK7set+BJbGhkH0SmVFrCJ1nI2YdkQPfF8hcOb//ezcHG5k6+h+QZ5FwV9WMzPx8l168uw7EisGl X-Received: by 2002:a05:600c:18a6:b0:3dd:1a8b:7374 with SMTP id x38-20020a05600c18a600b003dd1a8b7374mr1176856wmp.5.1675723140804; Mon, 06 Feb 2023 14:39:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723140; cv=none; d=google.com; s=arc-20160816; b=HZ5cgZwbroKKRMn6fu/z5ipn/9225/HNIpiZZc4Tl7AWzph/QHwEc5HUTVBZstqGms 10OyNt4XjFfRIqkZ4zBPTLSRTiiMB6NRGhkV4vVkQCVhAfHVbxsYXg64Nm9zpjkLsiAR lVUQknrYwNLS/Zn02ge258V5fpHcpotY9UDPXq0bJ0E+jUN4PwYVZ0/3Rq3f1Dg+U5th SeLk4OKBYYyJU9wzyELQ0SqLaMRegKfJzmSUzEfLZCcVBnruZMExVf8HX5y2MLyvj8z/ G/vmwUpXBkCZ5GzA0e1miIu+V+R6xGssHe745T1yfmXFB1rtuoDUCJ41ZHkI+sS/FMqq 5JrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=blxTJd5Tx9NIUQZO/x0aKGGdE7GU/DbRJ0PEKLke2ts=; b=hXD+XvKMf1dUhOnhCtP4/H1uZ5hdbSXJtQIhrhD/HV+i4ws1or9JlnYHvjCGECBlaQ v4kvKdrRHJvxted9oKZ9XqDnRC4pwgoqO6CEAaj63PZujNEyoVNjdhhM4y/yY4cKKq/1 QgFFBAnUqE3WHEqAR/437h7Ey4KLGGfjxrvJefMyvKDHssT0xdor1utMzyk2oZj3a375 azN0hdsVvEJoH7oPFqpl1JwVK6fYM8UzUSunva+QD5FvzYoiFXpafpz5xMj54gtKHN2q T9DA8CrXEyWnYrAI2IQCN/0z2vNDHtlcmBfAzIPm18py7lwV9Z2pefau19l0ZPugDtYx C1qQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O0v/mntk"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l8-20020a05600c4f0800b003da10b4a918si13985810wmq.58.2023.02.06.14.39.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:39:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O0v/mntk"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5L-0001pI-6V; Mon, 06 Feb 2023 17:35:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5H-0001lk-Qt for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:36 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5F-0004Tu-Ha for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:35 -0500 Received: by mail-wr1-x436.google.com with SMTP id i5so4715920wrc.0 for ; Mon, 06 Feb 2023 14:35:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=blxTJd5Tx9NIUQZO/x0aKGGdE7GU/DbRJ0PEKLke2ts=; b=O0v/mntkLzsAwHjb/nhX4yl/zVm8bN+5Pa5mzJVvu642xpmgEbfXxmO5QktMbPnwTa FDdLZKmL5u+PUBRidLc/slaVJ/YWNFQlH68bsLYuiF9ZP+My18MhDM64zcVakMJddaAS tS3/WInDY8JAspYoDznqDPbiutDScMJ5NpuOtC6LSgiI7214SDRINdzC4kWMXB7v5LJm DAMR5yGMmECHelSHznGjsbG8bD3yovzHm76Q7EiqN84H0P+Cbe0iUCYAizx3WG2TSAqY AHa+BpdwL6XpnWm2HwUXb1zXaoGCqgKTDk6jdGt/PBle8ssh80HXkl0WHYnawdeL4gPt 37TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=blxTJd5Tx9NIUQZO/x0aKGGdE7GU/DbRJ0PEKLke2ts=; b=TMLAIquybA9E0UVqj6InY7M4yhm3QMZg8yETcZie1P5NfMujHSiDKRvR7nShFWjPLl ujhNk5VNPakfB+Dg2P/iVGM/chx2ooB+dnlXyom/8K+q5nzPuDeFBdTSAUhy+2S2EWeL CLnYjBmpezMQhP61VSCfHm9WQUlR/FGy0VbL3Rz8D+XGFv5HhHp0tJKQA0oiQM+8E6nQ 2029cHis5qePWDf/225qsMWEFngLhK39+16XzSDvjgX/OnfmrDgTnHGhbliqsF/HSR1N QOxUdWYtm6iVQSvBNOm1NQpwjWffrtUjMbxvlDX3GkZ/xOxG4ayY3jM87dK0L0BLN7We r6Kg== X-Gm-Message-State: AO0yUKWLSLSoMM+R5drLMz+r6aZsuKNlBKgOTDTM8RPVyd+83m2J2OyE Xtc4AKFlovoQCMoT2k4vWFyP+gBPNZ+l0d8R X-Received: by 2002:a05:6000:1287:b0:2bf:bb71:dc55 with SMTP id f7-20020a056000128700b002bfbb71dc55mr422119wrx.52.1675722932088; Mon, 06 Feb 2023 14:35:32 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id s7-20020adfeb07000000b002bff1de8d4bsm9769030wrn.49.2023.02.06.14.35.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 05/11] target/arm: Convert CPUARMState::eabi to boolean Date: Mon, 6 Feb 2023 23:34:56 +0100 Message-Id: <20230206223502.25122-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 4 ++-- linux-user/user-internals.h | 2 +- target/arm/cpu.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index c0790f3246..a992423257 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -356,7 +356,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_SWI: { - env->eabi = 1; + env->eabi = true; /* system call */ if (env->thumb) { /* Thumb is always EABI style with syscall number in r7 */ @@ -382,7 +382,7 @@ void cpu_loop(CPUARMState *env) * > 0xfffff and are handled below as out-of-range. */ n ^= ARM_SYSCALL_BASE; - env->eabi = 0; + env->eabi = false; } } diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index 0280e76add..3576da413f 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -135,7 +135,7 @@ void print_termios(void *arg); #ifdef TARGET_ARM static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { - return cpu_env->eabi == 1; + return cpu_env->eabi; } #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7bc97fece9..05b9012cee 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -723,7 +723,7 @@ typedef struct CPUArchState { #if defined(CONFIG_USER_ONLY) /* For usermode syscall translation. */ - int eabi; + bool eabi; #endif struct CPUBreakpoint *cpu_breakpoint[16]; From patchwork Mon Feb 6 22:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650957 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2530569pva; Mon, 6 Feb 2023 14:36:48 -0800 (PST) X-Google-Smtp-Source: AK7set+8CpoFBwmIpqtH3eCnSxZ87yLJaz+MAI6ZppThzUmRI4sQkWNLS+VvKFcjoJu2q1GgkxhO X-Received: by 2002:a05:622a:40b:b0:3b8:2838:97b9 with SMTP id n11-20020a05622a040b00b003b8283897b9mr2037106qtx.15.1675723007901; Mon, 06 Feb 2023 14:36:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723007; cv=none; d=google.com; s=arc-20160816; b=iTUAIAGUmk7eIL3g4BvX2ZRe/NGBjktAgMVteY4E0Gh/hom/yU8shBA3MN0FapA3Hm d3aIZDTRmZoYq2rDGtqnkIUs+1lZVN73uYyoF5H6oP+xviW7SjqaEJS1P2hhLk1jXo2T JPPqv6mVAGa0TqA+4l/BxVq+SXJgrPlFPi/xcEftzTtTRqXyR8Rn3ggi8EfyKzZjB8O6 v8Yf3lDztNf1eN+tVbU6ORFVewEG3gaGHVQ7Nz4FoT3gz2+6sD0GmruIcekPkClFQWVd SmNFHyVec38remUmIX7d4PVT7hfBBWe78xgc8sZ8PgnKn3eGriCM7TTgROCRW3Yy6ofL WFMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hkXbL8y61939hNYH0ESs0TMwg7eANZ0/D9elcJnMLJc=; b=sgkctaIFyAL4Q5BR840EnFXqVnwDCYpw+Tk9WtAenETRVP/DiV9D4cMj/q7X2HKO7R YgvPmGCUacWxT3qEEqUK1BQG5oDpIhUvIjrtElxgBRyeRSnL6IDuV37Q2WIRBJN11Gue uyZUbkIt5JYLRTWaVCvAgK7o4MUvEujKbOKYspBirAkeKYrFuCiPcsRBQlDpd62lJwdi yZdOfpB6Ojg5m54Bxr9BewWEGOEPDsKmFDnv6D/L9qBB7NOWG93eamKzXcS8buf+/sR/ Kklcgkgr+5q0tOMDZoAw0eZB66RJHOEnng9Ze4MFxPZ6u+6OpBy4SB9/w3R77+bwEQIM +bKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kXy245hs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 16-20020ac85910000000b003b9b7f67cb5si9211061qty.294.2023.02.06.14.36.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:36:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kXy245hs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5P-0001tG-1m; Mon, 06 Feb 2023 17:35:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5N-0001rE-8E for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:41 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5L-0004Uy-Jp for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:41 -0500 Received: by mail-wr1-x431.google.com with SMTP id ba1so7825155wrb.5 for ; Mon, 06 Feb 2023 14:35:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hkXbL8y61939hNYH0ESs0TMwg7eANZ0/D9elcJnMLJc=; b=kXy245hsMKQfadouVZLsj8GRcGW/9K3Q3+eoLVcx6EYiNkvECEPRdFdZVq/NBdgLkc S8y9qE7K7P/jEpLghMETO12yS02us5hJG5R86CCNd8wo5ElsMOqvIIk6a1oaBHkUqBfK q+z1lLXlRnKKbTGosaMPTJZB6zd4D0lj6cXR+SN59ev+V8g9nwnkbq3IMs805ldh+svN /aLNBPFnR6w2QQQEqwh4DrfV5cFbmqFlvmYhEt/f+ziPUZ7LS6F8LH1AJ0i3MZReJuXQ crhNdNeyRyhsRfNQOis7POp10ZqYyB2CRI5GgOe0Ty9udRGDOXtZEC15k9EYTxQMyMgC 9msQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hkXbL8y61939hNYH0ESs0TMwg7eANZ0/D9elcJnMLJc=; b=bzrPTIHgSGhp7WMlMIQvJxjCgtHtDpaZJWoNhNXZTcXwOU5Z9OpQ6mZ+EfKWXMv8Zm tRg460YGWPa/9J0toAOI1Z+FQgiYdkJW5IDg+gsrIFSqxpxIQbavU9T8bX9RCW8NHAL7 NJzwCrbHYHqMSbOtMariI6mu9AO4yahTqHHrn7FqVhErMvUuym0EHX75EFWyyzuaFett P6tZJ/b4M19V2FiuyhvBLqY/seSjal91gAY31OebnCm4cZLaRkopqvCQRWRW57vJRSpk KiFUEb6p0NhAaHcZC2bPuNszBs8zDHW+eaAdynJfb56D3CaUTndIDz24v+PG2Wzxnh3F 7E4g== X-Gm-Message-State: AO0yUKX2T2FhnszxZ4RewCMWU4BfmvomRc6Pb+XelgR483zrVyMjdIyd Bk2JQ3qNoyK3T7qDqa9LY8SlXjp+fM4yxESd X-Received: by 2002:a5d:4cc6:0:b0:2c3:d657:e951 with SMTP id c6-20020a5d4cc6000000b002c3d657e951mr425799wrt.29.1675722938070; Mon, 06 Feb 2023 14:35:38 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id g10-20020a05600c310a00b003de77597f16sm12753148wmo.21.2023.02.06.14.35.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 06/11] target/arm: Avoid resetting CPUARMState::eabi field Date: Mon, 6 Feb 2023 23:34:57 +0100 Message-Id: <20230206223502.25122-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Although the 'eabi' field is only used in user emulation where CPU reset doesn't occur, it doesn't belong to the area to reset. Move it after the 'end_reset_fields' for consistency. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05b9012cee..1c1e0334f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,11 +721,6 @@ typedef struct CPUArchState { ARMVectorReg zarray[ARM_MAX_VQ * 16]; #endif -#if defined(CONFIG_USER_ONLY) - /* For usermode syscall translation. */ - bool eabi; -#endif - struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; @@ -776,6 +771,10 @@ typedef struct CPUArchState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; +#if defined(CONFIG_USER_ONLY) + /* For usermode syscall translation. */ + bool eabi; +#endif /* CONFIG_USER_ONLY */ #ifdef TARGET_TAGGED_ADDRESSES /* Linux syscall tagged address support */ From patchwork Mon Feb 6 22:34:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650954 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2530362pva; Mon, 6 Feb 2023 14:36:16 -0800 (PST) X-Google-Smtp-Source: AK7set/cfMqfJqKPkED+xH6IDMf4YtZoC+JnPaI3UQgpIzfrxB4VqD7NuQ5fc6+mOprh71pYBUiy X-Received: by 2002:a05:622a:1314:b0:3b9:a586:374e with SMTP id v20-20020a05622a131400b003b9a586374emr1496998qtk.67.1675722976042; Mon, 06 Feb 2023 14:36:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675722976; cv=none; d=google.com; s=arc-20160816; b=RJlrCwz0Ci/aeucJFPtGqxHySwBaMu7cOcClX6Es8fz/NV+XK+vmAM48/2WMhycbB3 vEaSPA2OOlKCg8+NIfC3+juJyoxlTZ8DfR/GpNJ1Y5/UUFbfHiev0ef4jJCd8n36hNvY c7++xEKmNEM5Q/sECszH8bFlKp2W8UUm3UymDyYyEhqz6c9xVbbecXLeE9blcokEsTzG 9mq4CBWWDynO7I4w7a6Y5H5PknqDg71Vw39GX7WuSNsMleYTYi+gzWvfQseRSYq6q+pS EqVn2NJWsl3Hk6ibHlG7lmNy4VAZP/uoZTqQzVbbLgbxZknQaZeNnhkLIsjW7JHwRv1z k+hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tq6DPJouguMrWtZeeVmDD2Re+mYoIDnT0PaG7kqN/mg=; b=SiH24i9Rj3LdcIbvlGGzRSyc3HCKeBsUrft7LHn6JyUOrRja6VcAPSAzvSYaorOBuU +SOvoOwrr2tYFDipsawDqVDQBcSDT2yh4aDwxVZk7GWHQ2ikdgt7h4znldvREfHIdvVG 6qPI9iXjUUUJFViBfuNm4Bx2GoTrvyN4V3n04geFDhWeEOAYiZv3DPXbCyOV+4V4Kbhn gtVU+ERz1b/tHtIl7MhBhhE34fHD+pDlr2o+NBKghB5dyCTfspXo86lcKYD/vULYV+NW koOg4WPj1NTEEvg2alRGpOlXXBK1BX96OI0+EM0SBrnmSqJcNzZnN697+TujpAjBBWob +GGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mek3dnXt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e15-20020ac8598f000000b003ab72ecdec0si9442853qte.59.2023.02.06.14.36.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:36:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mek3dnXt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5T-0001uK-8P; Mon, 06 Feb 2023 17:35:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5R-0001te-NI for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:45 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5Q-0004QP-42 for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:45 -0500 Received: by mail-wm1-x333.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so11920715wmb.2 for ; Mon, 06 Feb 2023 14:35:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tq6DPJouguMrWtZeeVmDD2Re+mYoIDnT0PaG7kqN/mg=; b=Mek3dnXtIUsl1ep7k31ICMi0nee9DTCTRphEZbvt9Mqke9VUlh3Ka2Jy4qTXD9HOXn cEOZ3GH9dv1fw9LUQB0j113HA6zRXOuRfB+j33Vv2Nkwocyfs5Q1XE4wFOG8pUd67V7b rOs5Co5ziRFjuqm6PkSaUtgutU7SgPKxYissaaGUMlN2evYs+g9Y/i4mR/8L27vQubRj +zbtNdYROkk74UogvuHQ425jQI7Ar+d+oGZhj5MOs7HKsQ9G4OjqEtA3xAyXm4Bb1Onm 1AGRfwXRp1vwme+eE/Sa73ETLso1jP+KrmITyoiVpt9YevghxkuwHCoQlWi0flM4yH5w a/rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tq6DPJouguMrWtZeeVmDD2Re+mYoIDnT0PaG7kqN/mg=; b=p9XFUEeSkEGI2DRQzp9/g/DjbetGwUcs3V3/zlvy6+GjBJWQEwMKODq85F/paVJ48E fO1QytdGuurq1XZoOVlJqvGdI5YRDpfdp49RPvBpaGctrC0FFUPyGvaX4TUBEYsNHLuQ wYmdgJQwGciTt66UQizui2+v9Ycj1Njhzdb/efRePr/yCNXF01IghlvFXYt0IPdSTvaY TPJUuVl/MuGiBuRQt6XdBFKa4NDwadDqMVgB1evvfut/M2/4pYmNwiGbbZ8YpcAn/GMM Vff4i5z4bnl/7Ae/Y3Pc5khMHnYso59FfnQ2mTkyMWSyu4h2F5Rjpq5KhO3w998qJ2jV 01mw== X-Gm-Message-State: AO0yUKVOzV80nwDk7BdeQizV3pC++PBdzfixY2kMk9xPgJlFYEh8Zut+ P37mMFHD03ngbwc/S0QA4VnwkvhvH9L7LHLV X-Received: by 2002:a05:600c:35c6:b0:3df:9858:c034 with SMTP id r6-20020a05600c35c600b003df9858c034mr12591508wmq.9.1675722943215; Mon, 06 Feb 2023 14:35:43 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id h27-20020a05600c2cbb00b003db12112fcfsm13356593wmc.4.2023.02.06.14.35.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 07/11] target/arm: Restrict CPUARMState::gicv3state to sysemu Date: Mon, 6 Feb 2023 23:34:58 +0100 Message-Id: <20230206223502.25122-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1c1e0334f0..002082eb5b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -769,9 +769,10 @@ typedef struct CPUArchState { void *nvic; const struct arm_boot_info *boot_info; +#if !defined(CONFIG_USER_ONLY) /* Store GICv3CPUState to access from this struct */ void *gicv3state; -#if defined(CONFIG_USER_ONLY) +#else /* CONFIG_USER_ONLY */ /* For usermode syscall translation. */ bool eabi; #endif /* CONFIG_USER_ONLY */ From patchwork Mon Feb 6 22:34:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650958 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2530615pva; Mon, 6 Feb 2023 14:36:55 -0800 (PST) X-Google-Smtp-Source: AK7set8nr/egqKT2M+OF+H+z0rKr48yN/xPTjDwJYIeMh24ogMevOWBHNebdB+rUpZlfNsXJMdzg X-Received: by 2002:a05:622a:11d4:b0:3b9:b436:4c6f with SMTP id n20-20020a05622a11d400b003b9b4364c6fmr1909967qtk.39.1675723014915; Mon, 06 Feb 2023 14:36:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723014; cv=none; d=google.com; s=arc-20160816; b=MAoj286RgwYf4HqdDgxDa0DMMEGspO2vPIHU9vyCMnLJ9TgwfX6nb11dpRI56Y7u+g /a0YDLIsUMnCPNregrSD3eFrax7rg4D7Fji8vx1DiZ1Aiy0kZasi+U/YFq9XF/JPUxJx UvvPG7QOSDEsR/QkHgife7lQdEjp1cNu20EIMDf6RygB74SGYzck3pYSZSyZK8v95TiD xyxicHYp/tj0w0NiGoKGsam9k83c6TrVb8vRX/6JrPd8TdFemKuub86daNqT7t51WD+R eflt2h8iuUFasTrhoMMnqe8F7VsXEM5r22tesWYG3btRaNtVehmx4JCiJY4fowCURhZu GRnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E4wwJ9rgwf3OGu6ruHO5E3WC10MpsXTe+i4WOyzlxyQ=; b=xt6+YoGWIDrnLbdfLutcRHH0V1PyZjr/Nn3kEhiTkjz/1diZoL7tJzo7Cs4ygRjsnG ljlEWZ+8v2nzBeD0fcECUmZbmDnoe35jm2NcpPgDMfjlEAmEzgLlPMtM1sCWPYQsFFKE tEzjGDvITm1OKRa8HyOTTH76Mo33oE4IO/EJoGR+QaSfyHNLChcAnvNA4v0QFxsIZsT2 AOo6V6uOr9+7QDEGyUvSy86vyKFIuwPLK2+iY/HCx8Efskwrht3xhKyIBrV98Xf0fgQf CfS7e+aWArGMIw4DfFfEcg5rDI+RrXChhcH2IfVTAd0JzGizzhkEVzD6vIVeE6IKMw3I uqUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uiJC8y6S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f18-20020a05620a281200b006f7fae571a3si5308305qkp.118.2023.02.06.14.36.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:36:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uiJC8y6S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5e-0001wu-Dd; Mon, 06 Feb 2023 17:36:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5X-0001uw-EP for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:54 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5V-0004XC-TC for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:51 -0500 Received: by mail-wm1-x336.google.com with SMTP id k8-20020a05600c1c8800b003dc57ea0dfeso11935537wms.0 for ; Mon, 06 Feb 2023 14:35:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E4wwJ9rgwf3OGu6ruHO5E3WC10MpsXTe+i4WOyzlxyQ=; b=uiJC8y6Scd+xH5k6JhmB1Txo0p0Al4I43GaNRNM1U1OoqQZUHDELm4AWJjDOlYpiJ1 ksqh1SE4wUDIluR7RVkTB3BQ2w8QmVlqNu9AOFeUqfB0vQj/zslF+vWiaKfGk4asAOgE zNqs1ZG4dma4urO/4+kgM9bRJEazewBlNP/EWXySmrJOMv4qs6eKRdz0EV7UZecUyzTp B5dGuBIds/LA/gd9xHTW3WyMcRn98g2UTQuD75hkhJuCinNLqubBQ6CB+ooQ99HtAjxM iCjSNr+SkTpg9p9MwZnjaP7gprQ+jJ5A5hpe7Qi5Wh5AxiHDaAOXr9xPlYAvXKGh18+r dXsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E4wwJ9rgwf3OGu6ruHO5E3WC10MpsXTe+i4WOyzlxyQ=; b=wJfZeY8B2LuGCz7AAZmQr6VEU11HJNrPgs3aLFe+XQj6oLhQaOh+NGVPfTpG1UUW5S /VbNqad+0c9VyMJBP9Ey6WVyV0kwR7Jpym+yey3iITAgDZfJ88li5EwfdfEWML/UfVH4 5v17C23tj9/0EsKrdcZtlYfQ6/hrmCikdyViBXuiAEy0yydbiVIDFbFWu1BUyiWBSzTX fm4NYSuBEEyJjKZqWnY/03Mf+jbA32SYKZ1E7p8zGVLAntFvEbpMyo4t8bu3S7INj0Nq E9C55RBxKHYL9mmXk6wkDMHWpmT73EVt7mEviNR9vrXIDVfd4SaN+IzN6ENMgVNd/oyV fVow== X-Gm-Message-State: AO0yUKUiaHZewQjpJf8EmA19Q8L//3x/CeSSiCbFw7TUpS7inF+E3Kl9 p1IkasvrYDdynOdJRM8W4AWxhrgdFQUfI+i3 X-Received: by 2002:a05:600c:319d:b0:3dc:5950:b358 with SMTP id s29-20020a05600c319d00b003dc5950b358mr1160116wmp.14.1675722948488; Mon, 06 Feb 2023 14:35:48 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id z17-20020a7bc7d1000000b003dc3f07c876sm17500100wmk.46.2023.02.06.14.35.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 08/11] target/arm: Restrict CPUARMState::arm_boot_info to sysemu Date: Mon, 6 Feb 2023 23:34:59 +0100 Message-Id: <20230206223502.25122-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 002082eb5b..a574e85b76 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -768,8 +768,8 @@ typedef struct CPUArchState { } sau; void *nvic; - const struct arm_boot_info *boot_info; #if !defined(CONFIG_USER_ONLY) + const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; #else /* CONFIG_USER_ONLY */ From patchwork Mon Feb 6 22:35:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650961 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2531301pva; Mon, 6 Feb 2023 14:38:47 -0800 (PST) X-Google-Smtp-Source: AK7set/3Ex01S1/QySIzGWYK5ausK98tchKfj9rQXEwfoJBulqRlnknXG86AyIFJceV36PjLVQrn X-Received: by 2002:a05:622a:287:b0:3b9:beca:8d79 with SMTP id z7-20020a05622a028700b003b9beca8d79mr2198478qtw.12.1675723127567; Mon, 06 Feb 2023 14:38:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723127; cv=none; d=google.com; s=arc-20160816; b=J1PGMVXmJpEdiyQqblS/Dd4n33MHnRPQeiCz9juVSObk5jQLY1uPxiQwmDuaCcpE50 /ZiLEZpoD88SGFa3ckT52uwd5YBTs6e+UemVXd5yzT1ebUDpHIISpDb5MNiuJIxCH8cw fEhVrzB/Jg6J61Gb9pd+wdb4yTbCUr2gdKVtjycvF7RpUylh8HM2US6aonozGOPUl0Db 2GdIz75zyxV6ukGYP4iUVrWkeocSAzCTaSAui8GLSlsFVjHI4SP8FHaqYLBWBNaqF7Ez Lkej7BEnH5bLgSl4s+PErNf9o/FqPTgVZMQrIvHQSudpLENscPAgY9tq3Zq1Nn9xDqE/ tiIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/k7Xuyi4yDhm+JEx9OBf9mhnkAiRR8pR4vzYzacLnP8=; b=ij5qcJZQOljvKxkEgwvKA6KD4vbOvugKFey23abWGIzYmC1eSpEQ4zyN5rJ4i7yCY3 Ede2UEWIlSaogVk80vMC5fhZrEQ7NkNontnkUDiuVyrRHK6aKVy1yf+yqd15N1vxKhSN 2jahrPgb43k1mSBdFL6HIVGXAnC2Oe82488iptRc8JjGK1QQ6d2pesIxfq1RN6ZFgQc8 AXx3mTtxUWd+luaD9vKR+YjLzjZiCiQltmisheqYR+PkAlsVNd1xLu351qw2OnVpNGO/ la7ElYFlgh0BPBX8EL6cNK91RGyVvADrDGEIMYqG+bXSCY7/0Qxik7udXu7nHQl22iHl V1wQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U3eTCcOy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h12-20020a05620a244c00b0072c19806f79si11828825qkn.662.2023.02.06.14.38.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:38:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U3eTCcOy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA5w-00023V-NE; Mon, 06 Feb 2023 17:36:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5c-0001wD-5t for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:56 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5a-0004Rt-ID for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:35:55 -0500 Received: by mail-wr1-x42f.google.com with SMTP id o18so11896371wrj.3 for ; Mon, 06 Feb 2023 14:35:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/k7Xuyi4yDhm+JEx9OBf9mhnkAiRR8pR4vzYzacLnP8=; b=U3eTCcOy6zdmk2vKJvcQTKLuIHvtaW174JDHL80aevYN+nwHs5E+BdMrtJVPqP/EQc OgybLpw+f2wCkx5A+c1I14efpk6ZobychfMRbOlX/0IWex64SpRXhWxqdkA6Jk8/L2aM p8ibcfO/fLS8wWos/Sj/lkYb1YFMIsBy9M7Mw3lXXrnbkweq5lbNnrC/4d/RopkOz+WK sHE5Oe30RL8r+Z9Q30NXD6oT0/klhmR85/LXaTf+3z63Hgr1FCjkaIC5ttgi6r2HTvy6 68xdGOgJncQ1oV8NhK6OY3ADxb88UYZ2Gx2ScGoXSjHFosTrZT1nmK3W3zGWMOZZ6wie 3E7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/k7Xuyi4yDhm+JEx9OBf9mhnkAiRR8pR4vzYzacLnP8=; b=XrmlnAeNLf+n09ahUry2Jy81sLe0/kPHp83IPBBu0nEKgHGGYxFdpiIrLmZ2LlhJ0c FgqeRVtJoUn9ziRkYBcOOCKRmZ/NZBmmopRT3ACHX4oIi1T6s6w6KPxcUitHpJfoOA8C 0wfk74cny+JLx08Qjtc+WgcUV64caV6twlQLY6oc/LPt/bjN8wtmvayCi/lsu3h22RKU 4nNqqwgF1daLpONaJKitXgovwAW4lwkAPAK0EkicyhVgQ0SYgsFwoFYcJr4Rqvm52480 R/da+2OmHpJ/UdfWMEU1mJ0h23QnhgHWrRMkaYDd1dY0SDBSZwpRlWTxA8FPAUX+f3UH qlCA== X-Gm-Message-State: AO0yUKVBUIbNn6IgHRCTVbfyCfE47FSI+Qi8pzunkkFRZID4X6bzmkIV W/30vh5zWR41OEYkBP9cerboNkcH8meK67Aj X-Received: by 2002:adf:db88:0:b0:2bf:d776:1c9a with SMTP id u8-20020adfdb88000000b002bfd7761c9amr505199wri.4.1675722953688; Mon, 06 Feb 2023 14:35:53 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id d5-20020adfef85000000b002c3e600d1a8sm4481597wro.95.2023.02.06.14.35.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 09/11] target/arm: Restrict CPUARMState::nvic to sysemu Date: Mon, 6 Feb 2023 23:35:00 +0100 Message-Id: <20230206223502.25122-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a574e85b76..01f9566a1b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -767,8 +767,8 @@ typedef struct CPUArchState { uint32_t ctrl; } sau; - void *nvic; #if !defined(CONFIG_USER_ONLY) + void *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; From patchwork Mon Feb 6 22:35:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650959 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2531243pva; Mon, 6 Feb 2023 14:38:39 -0800 (PST) X-Google-Smtp-Source: AK7set/OrspZGXNCRdVdjdFsCpqhVetMO26TRQAMWIrAVaXTxip9jzDJH/3/xbLor4QjTzq3wxO3 X-Received: by 2002:a05:622a:34b:b0:3b8:6ae7:1757 with SMTP id r11-20020a05622a034b00b003b86ae71757mr1783867qtw.38.1675723119688; Mon, 06 Feb 2023 14:38:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723119; cv=none; d=google.com; s=arc-20160816; b=M1yDOmdleguMOBvxoUyTTQ3OQlf/i9Y/qn8VaA1kC6xl3wOfk56EoRvxIspQTIm9jt Sm9tq4sAWPYAtjeC1KjxJFku2WVuVXhW2sIXzvxmwA2MC1arsKxXVacjb0RdxCtbc5sM /vKGhSPhPCY2utQbXuTGE3AVpOPcC8Q23ap0DdgE9GGxIM69Vdzjow7JDb6Qo+dWb84k fBG2MraM0hr9ghorQdWYszjSWpQCm/GcGyMaNSF+QCnXL/ITbbSJcfb64KbWMVvbrKcf FaNd4DMDePMQYyoWGYXNltrQerk7R+yWyae7YLb3w+ZBBX0E/7ALIYAA8YTjna1OAAEv tfnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uXew3WIFLBzNY/R9haO5NzeKd4QdCH/e2ycwfYhObHY=; b=Dqh5Ex4dac4st6o2oYWzVzewRXHGcsUZzVVzonnxqcPZ9vLXzP9OzlHdKko3qZbjtn P/DF01FiMBeMpxs0qSvgJx3cTvASy4/Q7WzcjJabeTiXlCdhVLTTVTXbNMizdQW/qhk5 11EM2Hi+dVmGRP6qzShkTBGS+3voVH69otITnXyPa/PgzzdP+3Y/AKauJMquzoPQFZQr p/t0DgX1qC6Kb9pxKQ/AZ3A5VqLJa/yuTUWTJhDvgESUtFUhWiaD+ew6gOgcsOeqSz6J m2B76fenmkRXgbKp1ueQj84SHa837Jbi9TkloCq0R+a3ktk60tV0x6hMerjbam/n3eHw /rLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ak9v7YHi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x3-20020a05620a448300b0071ed9bb6ec4si10779800qkp.110.2023.02.06.14.38.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:38:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ak9v7YHi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA6P-0002fC-2N; Mon, 06 Feb 2023 17:36:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5k-0001zm-Vo for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:36:07 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5i-0004Rt-N1 for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:36:04 -0500 Received: by mail-wr1-x42f.google.com with SMTP id o18so11896551wrj.3 for ; Mon, 06 Feb 2023 14:35:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uXew3WIFLBzNY/R9haO5NzeKd4QdCH/e2ycwfYhObHY=; b=ak9v7YHiTVxHsNVl/iltQSCcCrfGeA0snuyBoVt1ceiEmzMt6x9/ky6GwlPPOu3u7I 7z8L/lF4IKks9maHYWw/SP/HIeZDTbpqNFsT4nb5hwGbJizpuQkTqMqAigzq6D3yUenw C/z2GhPSD6t3uqZKapWbCC4qKsYdPAAELv/6Zavq+qAAbs76EVdp9HjZ8qMJmIsG+/WI IcdELmUcuTS9S895mgR3OUxYPMRHCLugx1G4gMFi1OSaOIkG3JNtdNpvZsEdbFxzI8Bk hqpGDylnVCzkxOrAKtEbUOEyGtbNYQyPy4igb/U9OR9cApqApb+fUwHy71DMx1s63jOf NmlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uXew3WIFLBzNY/R9haO5NzeKd4QdCH/e2ycwfYhObHY=; b=5mgObfFjuoolAoQM41ED+4CwJVB0lUKQFXNk9y1ur8dRr3B+mrO2TlbsfPMOBi1aSu aBg0jDF4FVh2lTbEOrSz5QwShhRpcDukfJSMuQqTB6lIyhwCVXD9ucjO8vTvCA0Ca2uY iWXZvh+OSGKiemcZC1FWN4PeSsbfFyXRBOhw8dFxx82Gj80jeoZyQEqWNKXiM46NmKNG L3IVyW8pn9BWYD4RbTxLrHdK+kZoLr6ZfQGfOmjZDW1Nu4de8uCcJp0miSM3sSwgTC6s GGDQGsla6azCKDBfcGaixKq2MPDOSwZzmyuytX1T4khFZkx3DihZ8Of2z7fZbYg4WFn1 DWOQ== X-Gm-Message-State: AO0yUKVaRXWZgVeXRkfj4ZTUl2TMbnixIYCa4W02DM6Vf1WQmBgDwNJU gmZQu+iOhNa52+CHKKl3Yui1CBjYmq99Yibp X-Received: by 2002:a5d:47cc:0:b0:2c3:be89:7c2a with SMTP id o12-20020a5d47cc000000b002c3be897c2amr13614132wrc.13.1675722959101; Mon, 06 Feb 2023 14:35:59 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id u17-20020adfdb91000000b002bdd96d88b4sm9937430wri.75.2023.02.06.14.35.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:35:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 10/11] target/arm: Store CPUARMState::nvic as NVICState* Date: Mon, 6 Feb 2023 23:35:01 +0100 Message-Id: <20230206223502.25122-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- target/arm/cpu.c | 1 + target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- target/arm/m_helper.c | 2 +- 4 files changed, 39 insertions(+), 48 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1f7763964c..e54553283f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -389,7 +389,7 @@ static inline int nvic_exec_prio(NVICState *s) return MIN(running, s->exception_prio); } -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) { /* Return true if the requested execution priority is negative * for the specified security state, ie that security state @@ -399,8 +399,6 @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) * mean we don't allow FAULTMASK_NS to actually make the execution * priority negative). Compare pseudocode IsReqExcPriNeg(). */ - NVICState *s = opaque; - if (s->cpu->env.v7m.faultmask[secure]) { return true; } @@ -418,17 +416,13 @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) return false; } -bool armv7m_nvic_can_take_pending_exception(void *opaque) +bool armv7m_nvic_can_take_pending_exception(NVICState *s) { - NVICState *s = opaque; - return nvic_exec_prio(s) > nvic_pending_prio(s); } -int armv7m_nvic_raw_execution_priority(void *opaque) +int armv7m_nvic_raw_execution_priority(NVICState *s) { - NVICState *s = opaque; - return s->exception_prio; } @@ -506,9 +500,8 @@ static void nvic_irq_update(NVICState *s) * if @secure is true and @irq does not specify one of the fixed set * of architecturally banked exceptions. */ -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) { - NVICState *s = (NVICState *)opaque; VecInfo *vec; assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); @@ -666,17 +659,17 @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, } } -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) { - do_armv7m_nvic_set_pending(opaque, irq, secure, false); + do_armv7m_nvic_set_pending(s, irq, secure, false); } -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) { - do_armv7m_nvic_set_pending(opaque, irq, secure, true); + do_armv7m_nvic_set_pending(s, irq, secure, true); } -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) { /* * Pend an exception during lazy FP stacking. This differs @@ -684,7 +677,6 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) * whether we should escalate depends on the saved context * in the FPCCR register, not on the current state of the CPU/NVIC. */ - NVICState *s = (NVICState *)opaque; bool banked = exc_is_banked(irq); VecInfo *vec; bool targets_secure; @@ -773,9 +765,8 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) } /* Make pending IRQ active. */ -void armv7m_nvic_acknowledge_irq(void *opaque) +void armv7m_nvic_acknowledge_irq(NVICState *s) { - NVICState *s = (NVICState *)opaque; CPUARMState *env = &s->cpu->env; const int pending = s->vectpending; const int running = nvic_exec_prio(s); @@ -814,10 +805,9 @@ static bool vectpending_targets_secure(NVICState *s) exc_targets_secure(s, s->vectpending); } -void armv7m_nvic_get_pending_irq_info(void *opaque, +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, bool *ptargets_secure) { - NVICState *s = (NVICState *)opaque; const int pending = s->vectpending; bool targets_secure; @@ -831,9 +821,8 @@ void armv7m_nvic_get_pending_irq_info(void *opaque, *pirq = pending; } -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) { - NVICState *s = (NVICState *)opaque; VecInfo *vec = NULL; int ret = 0; @@ -915,7 +904,7 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) return ret; } -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) { /* * Return whether an exception is "ready", i.e. it is enabled and is @@ -926,7 +915,6 @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) * for non-banked exceptions secure is always false; for banked exceptions * it indicates which of the exceptions is required. */ - NVICState *s = (NVICState *)opaque; bool banked = exc_is_banked(irq); VecInfo *vec; int running = nvic_exec_prio(s); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5f63316dbf..b3a2275b08 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -36,6 +36,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" +#include "hw/intc/armv7m_nvic.h" #endif #include "sysemu/tcg.h" #include "sysemu/qtest.h" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 01f9566a1b..9a80819d8d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -227,6 +227,8 @@ typedef struct CPUARMTBFlags { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; +typedef struct NVICState NVICState; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -768,7 +770,7 @@ typedef struct CPUArchState { } sau; #if !defined(CONFIG_USER_ONLY) - void *nvic; + NVICState *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; @@ -2559,16 +2561,16 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, /* Interface between CPU and Interrupt controller. */ #ifndef CONFIG_USER_ONLY -bool armv7m_nvic_can_take_pending_exception(void *opaque); +bool armv7m_nvic_can_take_pending_exception(NVICState *s); #else -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) { return true; } #endif /** * armv7m_nvic_set_pending: mark the specified exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2578,10 +2580,10 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) * if @secure is true and @irq does not specify one of the fixed set * of architecturally banked exceptions. */ -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); /** * armv7m_nvic_set_pending_derived: mark this derived exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2591,10 +2593,10 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); * exceptions (exceptions generated in the course of trying to take * a different exception). */ -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); /** * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2603,11 +2605,11 @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); * Similar to armv7m_nvic_set_pending(), but specifically for exceptions * generated in the course of lazy stacking of FP registers. */ -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); /** * armv7m_nvic_get_pending_irq_info: return highest priority pending * exception, and whether it targets Secure state - * @opaque: the NVIC + * @s: the NVIC * @pirq: set to pending exception number * @ptargets_secure: set to whether pending exception targets Secure * @@ -2617,20 +2619,20 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); * to true if the current highest priority pending exception should * be taken to Secure state, false for NS. */ -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, bool *ptargets_secure); /** * armv7m_nvic_acknowledge_irq: make highest priority pending exception active - * @opaque: the NVIC + * @s: the NVIC * * Move the current highest priority pending exception from the pending * state to the active state, and update v7m.exception to indicate that * it is the exception currently being handled. */ -void armv7m_nvic_acknowledge_irq(void *opaque); +void armv7m_nvic_acknowledge_irq(NVICState *s); /** * armv7m_nvic_complete_irq: complete specified interrupt or exception - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to complete * @secure: true if this exception was secure * @@ -2639,10 +2641,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque); * 0 if there is still an irq active after this one was completed * (Ignoring -1, this is the same as the RETTOBASE value before completion.) */ -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); /** * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2653,28 +2655,28 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); * interrupt the current execution priority. This controls whether the * RDY bit for it in the FPCCR is set. */ -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); /** * armv7m_nvic_raw_execution_priority: return the raw execution priority - * @opaque: the NVIC + * @s: the NVIC * * Returns: the raw execution priority as defined by the v8M architecture. * This is the execution priority minus the effects of AIRCR.PRIS, * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. * (v8M ARM ARM I_PKLD.) */ -int armv7m_nvic_raw_execution_priority(void *opaque); +int armv7m_nvic_raw_execution_priority(NVICState *s); /** * armv7m_nvic_neg_prio_requested: return true if the requested execution * priority is negative for the specified security state. - * @opaque: the NVIC + * @s: the NVIC * @secure: the security state to test * This corresponds to the pseudocode IsReqExecPriNeg(). */ #ifndef CONFIG_USER_ONLY -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); #else -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) { return false; } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index b4964dca8a..25de64c43c 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1015,7 +1015,7 @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, * that we will need later in order to do lazy FP reg stacking. */ bool is_secure = env->v7m.secure; - void *nvic = env->nvic; + NVICState *nvic = env->nvic; /* * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits * are banked and we want to update the bit in the bank for the From patchwork Mon Feb 6 22:35:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650963 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2531425pva; Mon, 6 Feb 2023 14:39:06 -0800 (PST) X-Google-Smtp-Source: AK7set9AzMArmU9HuMHMrRzfQLdm6J9xqO7dW7i1sIGPUGWw90MtHrfdcWuHl7xbGCHszm6YcZJH X-Received: by 2002:a5d:5583:0:b0:2c3:da89:bc50 with SMTP id i3-20020a5d5583000000b002c3da89bc50mr396907wrv.52.1675723146389; Mon, 06 Feb 2023 14:39:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675723146; cv=none; d=google.com; s=arc-20160816; b=cJIpJpue9Rfe60qcKvMjJ8g+ionFzDWd/pUcyoBcR+NSLKrsCj9stQjqAfnSZMSh+b gIMaQ8tycM2g2VlZcnvIBe3yYbUV6EzbfcvDgxSywjT8zh62DloJNPQRlDbF+D3mt4aa VWHk+0eLsxiHLGo1qYK9CjhrWth84AYvKCU74P5ryqbse0DA2KO9ZVuwQtoznEHNa6lU 2agMOAVRHXniRpYq7Y5siIb4vqhLS9AlhDblXhXXWqN9+r9IQVDaLeHBsuHZifE8chjn lIxE/eNAaWBmSP5sXJPuBkeoGSDrg0s6t/BTUSVtidCGp4NCa/23hy/sFkGP2qXMWt+6 QhJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Th29SQNs7/l87a43ReKMZy6K5gSwY95yoc+dQl25fFo=; b=wEDF62ryuLFJGYYHrN0skEGTWOvV3BmSi2VHboT3aKHiRkMqwNCe/ywU5ZiD5BsLuj IDtNWzzFtsb+ILTfK/kWPDdvbp1yhJrUHhERgJ3smi7j3Pz6t0csEEH6wv+57y7813cN Nni0rJaZs/LvWlCyWCVWjfiGz2rE0jAizkPh02x8NAgQ/l2EcyBVLWZgslSn0MDv08wa rLJHWdWJaDo54ukCPWdRxlvC7tTLDj1O3JsrepB8j+SoqVPhbIZS+Vw/G0BptOsOPvW0 8kW748BTXtusKJ58z04kPyW9087DUBWw0yqMRpZZtI7qXn+ZbvCskFST0nbfStSw/Fcw FnJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UZLAGAHV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w2-20020adfcd02000000b002c3daf89ff6si9252933wrm.92.2023.02.06.14.39.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 14:39:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UZLAGAHV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPA6O-0002bG-1P; Mon, 06 Feb 2023 17:36:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPA5q-00023R-Qx for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:36:11 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pPA5n-0004QP-EF for qemu-devel@nongnu.org; Mon, 06 Feb 2023 17:36:09 -0500 Received: by mail-wm1-x333.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so11921204wmb.2 for ; Mon, 06 Feb 2023 14:36:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Th29SQNs7/l87a43ReKMZy6K5gSwY95yoc+dQl25fFo=; b=UZLAGAHV9ptv26hSJWLRvMGmiMhBXL6bkMNNDsg5323vbcbLf0nTrFG6XCPkhlrB/J Wdarnnonw6ZDtTxnr/MspxQjknz9FFPRLMlPpHr12Yaz4YqLpfua9+wAVgQwrPvNIF0Z 4iCbHG1Q4+0x0cl6enPYDrE8ZIVDsamW4q1qvfHUJfOsQmFev1X5cgB1+Ot2Onj2Hs+P CgbeWmCsP+SrCrtYCgG2Gj7HDsFrbPLaK0s99Lw3Wt5aA1/FRVuSQikzkc6NqsR1iNBp teuFWk2g41vIsI/FRkK28g3GLvwSsUh52H4BBUUa8qyBeHOffTfsaTZPpcae7HBgcqNG 6r3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Th29SQNs7/l87a43ReKMZy6K5gSwY95yoc+dQl25fFo=; b=xLlW6nsUPFjgzI5+66wRIaHG6nYZdPOgBcMAX614bQeToxHdqDWg38s/qhq+Pzwh7n zaj3Yq01DHpM/4GTLT5t6eFO/z4P8beDCnoCB8VCESpr78fFYguqmjj52ef39MFtpNZH UZ4XA53xM20gY4hcsjLyuCR4+KbhD4AtA8h4cmNQbXdqnwtbf8iLFRWerhFK7BK60ups zIskEuT7WMNZe9xJE9V7OdyZf3x/tf1V0r7+Y8rTP3wBijT4YnHkkpZv/RbWubHP9n27 DAAWABdj+M9MYcZy8uHT9QxhMU5H6i3PeydRHn4Ru6i7MfTVrmBS0KPL8QR7JX9TEODY iRMg== X-Gm-Message-State: AO0yUKXB3r0dztArQEu9GBn0pDrkoaPN6OCXphpeGryjudAQbwfC77yC 0WgwrjmdxNlrAPsckKa8l4O6dmsE9JmHIJkl X-Received: by 2002:a05:600c:160a:b0:3df:ffab:a391 with SMTP id m10-20020a05600c160a00b003dfffaba391mr1076324wmn.24.1675722966382; Mon, 06 Feb 2023 14:36:06 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id l21-20020a05600c1d1500b003dc59d6f2f8sm13238785wms.17.2023.02.06.14.36.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 14:36:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 11/11] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' Date: Mon, 6 Feb 2023 23:35:02 +0100 Message-Id: <20230206223502.25122-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206223502.25122-1-philmd@linaro.org> References: <20230206223502.25122-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While dozens of files include "cpu.h", only 3 files require these NVIC helper declarations. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 4 +- target/arm/cpu.h | 123 ---------------------------------- target/arm/cpu_tcg.c | 3 + target/arm/m_helper.c | 3 + 5 files changed, 132 insertions(+), 124 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 07f9c21a5f..1ca262fbf8 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,4 +83,127 @@ struct NVICState { qemu_irq sysresetreq; }; +/* Interface between CPU and Interrupt controller. */ +/** + * armv7m_nvic_set_pending: mark the specified exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Marks the specified exception as pending. Note that we will assert() + * if @secure is true and @irq does not specify one of the fixed set + * of architecturally banked exceptions. + */ +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_set_pending_derived: mark this derived exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Similar to armv7m_nvic_set_pending(), but specifically for derived + * exceptions (exceptions generated in the course of trying to take + * a different exception). + */ +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions + * generated in the course of lazy stacking of FP registers. + */ +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_get_pending_irq_info: return highest priority pending + * exception, and whether it targets Secure state + * @s: the NVIC + * @pirq: set to pending exception number + * @ptargets_secure: set to whether pending exception targets Secure + * + * This function writes the number of the highest priority pending + * exception (the one which would be made active by + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure + * to true if the current highest priority pending exception should + * be taken to Secure state, false for NS. + */ +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, + bool *ptargets_secure); +/** + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active + * @s: the NVIC + * + * Move the current highest priority pending exception from the pending + * state to the active state, and update v7m.exception to indicate that + * it is the exception currently being handled. + */ +void armv7m_nvic_acknowledge_irq(NVICState *s); +/** + * armv7m_nvic_complete_irq: complete specified interrupt or exception + * @s: the NVIC + * @irq: the exception number to complete + * @secure: true if this exception was secure + * + * Returns: -1 if the irq was not active + * 1 if completing this irq brought us back to base (no active irqs) + * 0 if there is still an irq active after this one was completed + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) + */ +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Return whether an exception is "ready", i.e. whether the exception is + * enabled and is configured at a priority which would allow it to + * interrupt the current execution priority. This controls whether the + * RDY bit for it in the FPCCR is set. + */ +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_raw_execution_priority: return the raw execution priority + * @s: the NVIC + * + * Returns: the raw execution priority as defined by the v8M architecture. + * This is the execution priority minus the effects of AIRCR.PRIS, + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. + * (v8M ARM ARM I_PKLD.) + */ +int armv7m_nvic_raw_execution_priority(NVICState *s); +/** + * armv7m_nvic_neg_prio_requested: return true if the requested execution + * priority is negative for the specified security state. + * @s: the NVIC + * @secure: the security state to test + * This corresponds to the pseudocode IsReqExecPriNeg(). + */ +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); +#else +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) +{ + return false; +} +#endif +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_can_take_pending_exception(NVICState *s); +#else +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) +{ + return true; +} +#endif + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b3a2275b08..876ab8f3bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -36,8 +36,10 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" +#ifdef CONFIG_TCG #include "hw/intc/armv7m_nvic.h" -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ #include "sysemu/tcg.h" #include "sysemu/qtest.h" #include "sysemu/hw_accel.h" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a80819d8d..d623afe84a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2559,129 +2559,6 @@ void arm_cpu_list(void); uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); -/* Interface between CPU and Interrupt controller. */ -#ifndef CONFIG_USER_ONLY -bool armv7m_nvic_can_take_pending_exception(NVICState *s); -#else -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) -{ - return true; -} -#endif -/** - * armv7m_nvic_set_pending: mark the specified exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Marks the specified exception as pending. Note that we will assert() - * if @secure is true and @irq does not specify one of the fixed set - * of architecturally banked exceptions. - */ -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_set_pending_derived: mark this derived exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Similar to armv7m_nvic_set_pending(), but specifically for derived - * exceptions (exceptions generated in the course of trying to take - * a different exception). - */ -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions - * generated in the course of lazy stacking of FP registers. - */ -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_get_pending_irq_info: return highest priority pending - * exception, and whether it targets Secure state - * @s: the NVIC - * @pirq: set to pending exception number - * @ptargets_secure: set to whether pending exception targets Secure - * - * This function writes the number of the highest priority pending - * exception (the one which would be made active by - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure - * to true if the current highest priority pending exception should - * be taken to Secure state, false for NS. - */ -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, - bool *ptargets_secure); -/** - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active - * @s: the NVIC - * - * Move the current highest priority pending exception from the pending - * state to the active state, and update v7m.exception to indicate that - * it is the exception currently being handled. - */ -void armv7m_nvic_acknowledge_irq(NVICState *s); -/** - * armv7m_nvic_complete_irq: complete specified interrupt or exception - * @s: the NVIC - * @irq: the exception number to complete - * @secure: true if this exception was secure - * - * Returns: -1 if the irq was not active - * 1 if completing this irq brought us back to base (no active irqs) - * 0 if there is still an irq active after this one was completed - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) - */ -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Return whether an exception is "ready", i.e. whether the exception is - * enabled and is configured at a priority which would allow it to - * interrupt the current execution priority. This controls whether the - * RDY bit for it in the FPCCR is set. - */ -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_raw_execution_priority: return the raw execution priority - * @s: the NVIC - * - * Returns: the raw execution priority as defined by the v8M architecture. - * This is the execution priority minus the effects of AIRCR.PRIS, - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. - * (v8M ARM ARM I_PKLD.) - */ -int armv7m_nvic_raw_execution_priority(NVICState *s); -/** - * armv7m_nvic_neg_prio_requested: return true if the requested execution - * priority is negative for the specified security state. - * @s: the NVIC - * @secure: the security state to test - * This corresponds to the pseudocode IsReqExecPriNeg(). - */ -#ifndef CONFIG_USER_ONLY -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); -#else -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) -{ - return false; -} -#endif - /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs * which are passed to define_arm_cp_regs(). diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ccde5080eb..df0c45e523 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -19,6 +19,9 @@ #include "hw/boards.h" #endif #include "cpregs.h" +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#include "hw/intc/armv7m_nvic.h" +#endif /* Share AArch32 -cpu max features with AArch64. */ diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 25de64c43c..f94e87e728 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -18,6 +18,9 @@ #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif +#if !defined(CONFIG_USER_ONLY) +#include "hw/intc/armv7m_nvic.h" +#endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val)