From patchwork Sat Feb 11 03:18:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 653052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9D86C05027 for ; Sat, 11 Feb 2023 03:19:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229721AbjBKDTB (ORCPT ); Fri, 10 Feb 2023 22:19:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229698AbjBKDSk (ORCPT ); Fri, 10 Feb 2023 22:18:40 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16A0323113; Fri, 10 Feb 2023 19:18:39 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5630F6602114; Sat, 11 Feb 2023 03:18:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085518; bh=Qz2BvAFfeR2pDH8idXft8j3/6B8ejfNa6vswzgvImNI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GHzfI5rdTu9/UZQWhAxLUwT9InbdtWjYgD9KO+/XqXr3fY4lXHlyWhChStvUQR01m xRLs4k3bnjFo8PWBFh51vKusUx9xj/uvL1FNUKDZXF6f9TCCX2LQ3ULqnJT1TZ0Tyo Rz2D4/dDd9ddU/gHRWbfF5cH8VA38de5O2pTkRwv9EqmpIRkh9frNe8X/026R1N8V4 Tq9vVpS9hVB1I6Osa42muP8FW4Evlh11PlZ2njTaino7d+ojKQlCzS8vR7PsyWDO92 Wss6o1LNqXIDWpvrF/z0PG5pbHmgejn/aF+Ufr5DMyRRDfMUSQF2ud2JT48tfS+Qgu v1uC6CLBuhwsQ== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 02/12] dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property Date: Sat, 11 Feb 2023 05:18:11 +0200 Message-Id: <20230211031821.976408-3-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the 'uncached-offset' property to be used for specifying the uncached memory offset required for handling non-coherent DMA transactions. Signed-off-by: Cristian Ciocaltea --- Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index 2b864b2f12c9..60cd87a2810a 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -82,6 +82,11 @@ properties: next-level-cache: true + uncached-offset: + $ref: /schemas/types.yaml#/definitions/uint64 + description: | + Uncached memory offset for handling non-coherent DMA transactions. + memory-region: maxItems: 1 description: | From patchwork Sat Feb 11 03:18:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 653051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 223DCC636D4 for ; Sat, 11 Feb 2023 03:19:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229784AbjBKDTH (ORCPT ); Fri, 10 Feb 2023 22:19:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229741AbjBKDTB (ORCPT ); Fri, 10 Feb 2023 22:19:01 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DC08880D6; Fri, 10 Feb 2023 19:18:45 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1719D6602112; Sat, 11 Feb 2023 03:18:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085524; bh=dWT0RanDNiM3R2DCgFc/XbzaC63mZATcL9ooscBLbYQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OEECfIzkegZFxQGlNbEk0xpVXMYbfsjuxNV0jzVV+mhag3vfoFisKqwcwAejSdADU c2tk68Yksshis0/Wo96/mdHLwprlFo1d7gT4NWnVZo4FhmuA3vb8qRWnxx5jPtgXWv b/pV/VG5UGPafKrQc9OH4xX5/PaK4lgE+77yMgpU1Bz0QdUXAVG4RG5L9OgAoYqk8P iQzRVEev8TgYOSWRcZ+nLYNmv7Ycrz7LIMBI0fVjR8NpLZy9o8IZDtO3Y2KKPhWK6X asyOruKtVqPgbh/86k8oWarMwscItXxCD4n4rBW0WRhCtDtEcFkJUN2o7DMhhM26VZ Q2BNo4v2uF72Q== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling Date: Sat, 11 Feb 2023 05:18:13 +0200 Message-Id: <20230211031821.976408-5-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Emil Renner Berthing Add functions to flush the caches and handle non-coherent DMA. Signed-off-by: Emil Renner Berthing [replace with ] Signed-off-by: Cristian Ciocaltea --- drivers/soc/sifive/sifive_ccache.c | 60 +++++++++++++++++++++++++++++- include/soc/sifive/sifive_ccache.h | 21 +++++++++++ 2 files changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 676468c35859..0062635d845f 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -8,13 +8,16 @@ #define pr_fmt(fmt) "CCACHE: " fmt +#include #include #include #include #include #include #include +#include #include +#include #include #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 @@ -39,10 +42,14 @@ #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) +#define SIFIVE_CCACHE_FLUSH64 0x200 +#define SIFIVE_CCACHE_FLUSH32 0x240 + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 #define SIFIVE_CCACHE_MAX_ECCINTR 4 +#define SIFIVE_CCACHE_LINE_SIZE 64 static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; @@ -125,6 +132,47 @@ int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +static phys_addr_t uncached_offset; +DEFINE_STATIC_KEY_FALSE(sifive_ccache_handle_noncoherent_key); + +void sifive_ccache_flush_range(phys_addr_t start, size_t len) +{ + phys_addr_t end = start + len; + phys_addr_t line; + + if (!len) + return; + + mb(); + for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end; + line += SIFIVE_CCACHE_LINE_SIZE) { +#ifdef CONFIG_32BIT + writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); +#else + writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64); +#endif + mb(); + } +} +EXPORT_SYMBOL_GPL(sifive_ccache_flush_range); + +void *sifive_ccache_set_uncached(void *addr, size_t size) +{ + phys_addr_t phys_addr = __pa(addr) + uncached_offset; + void *mem_base; + + mem_base = memremap(phys_addr, size, MEMREMAP_WT); + if (!mem_base) { + pr_err("%s memremap failed for addr %p\n", __func__, addr); + return ERR_PTR(-EINVAL); + } + + return mem_base; +} +EXPORT_SYMBOL_GPL(sifive_ccache_set_uncached); +#endif /* CONFIG_RISCV_DMA_NONCOHERENT */ + static int ccache_largest_wayenabled(void) { return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; @@ -213,6 +261,7 @@ static int __init sifive_ccache_init(void) int i, rc, intr_num; const struct of_device_id *match; unsigned long broken_irqs; + u64 __maybe_unused offset; np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match); if (!np) @@ -258,6 +307,15 @@ static int __init sifive_ccache_init(void) } of_node_put(np); +#ifdef CONFIG_RISCV_DMA_NONCOHERENT + if (!of_property_read_u64(np, "uncached-offset", &offset)) { + uncached_offset = offset; + static_branch_enable(&sifive_ccache_handle_noncoherent_key); + riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE; + riscv_noncoherent_supported(); + } +#endif + ccache_config_read(); ccache_cache_ops.get_priv_group = ccache_get_priv_group; @@ -278,4 +336,4 @@ static int __init sifive_ccache_init(void) return rc; } -device_initcall(sifive_ccache_init); +arch_initcall(sifive_ccache_init); diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h index 4d4ed49388a0..d349ccb3969b 100644 --- a/include/soc/sifive/sifive_ccache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -7,10 +7,31 @@ #ifndef __SOC_SIFIVE_CCACHE_H #define __SOC_SIFIVE_CCACHE_H +#include +#include + extern int register_sifive_ccache_error_notifier(struct notifier_block *nb); extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb); #define SIFIVE_CCACHE_ERR_TYPE_CE 0 #define SIFIVE_CCACHE_ERR_TYPE_UE 1 +DECLARE_STATIC_KEY_FALSE(sifive_ccache_handle_noncoherent_key); + +static inline bool sifive_ccache_handle_noncoherent(void) +{ +#ifdef CONFIG_SIFIVE_CCACHE + return static_branch_unlikely(&sifive_ccache_handle_noncoherent_key); +#else + return false; +#endif +} + +void sifive_ccache_flush_range(phys_addr_t start, size_t len); +void *sifive_ccache_set_uncached(void *addr, size_t size); +static inline void sifive_ccache_clear_uncached(void *addr, size_t size) +{ + memunmap(addr); +} + #endif /* __SOC_SIFIVE_CCACHE_H */ From patchwork Sat Feb 11 03:18:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 653050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B65D7C636D3 for ; Sat, 11 Feb 2023 03:19:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229780AbjBKDT0 (ORCPT ); Fri, 10 Feb 2023 22:19:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229777AbjBKDTH (ORCPT ); Fri, 10 Feb 2023 22:19:07 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCEBB84F42; Fri, 10 Feb 2023 19:18:50 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 452C46602116; Sat, 11 Feb 2023 03:18:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085529; bh=Ogmcu0djiCm10ycXgbUuJ7cEbzi156f9C1KsCx+q2FI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nN13tQTAM5JWAD7C8n8ylR+HsLi/Z1YQ1vwzeCV78eigKOq5MyWsW7yY4s09lgPfx smj3EctbM5vW27EAnfeFp4PcVUWKrr618YXZIgi5iocIEqAA+gwIHuBiJzN+zrLVT7 fNBAx4iTnqtPDNXBpakG4TOakUKOw7Qc3EnFjsWMYamdWu9C3ce//NUCHwomRpI4tw jDL30mNX4RuKEYHgIVtvifgpy+Y+yvFbtuYweBpM80bvbAcGdBBvK1gRqroCETAVD3 SXFs8mUcpUY/yens+0waJ0SggLIDFFABfzEax2jAnSbwdqqZH9yIF9aaqBejtM+8WS pX3cvWP3J2Xfw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 06/12] dt-bindings: mfd: syscon: Add StarFive JH7100 sysmain compatible Date: Sat, 11 Feb 2023 05:18:15 +0200 Message-Id: <20230211031821.976408-7-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Emil Renner Berthing Document StarFive JH7100 SoC compatible for sysmain registers. Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index c828c4f5e4a7..43f564be709f 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -67,6 +67,7 @@ properties: - rockchip,rk3568-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - starfive,jh7100-sysmain - const: syscon From patchwork Sat Feb 11 03:18:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 653049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D865C636D3 for ; Sat, 11 Feb 2023 03:19:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229933AbjBKDTm (ORCPT ); Fri, 10 Feb 2023 22:19:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229845AbjBKDTY (ORCPT ); Fri, 10 Feb 2023 22:19:24 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD97F85B09; Fri, 10 Feb 2023 19:18:56 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 46C9F6602116; Sat, 11 Feb 2023 03:18:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085535; bh=TwwenY6La9ML4nip9B8ZX+9fLGGbM4jAo/uXYp0Qk4g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OKKkxrnUMuOi0Jh4iaoScbQdgxmTpT21oDKQCOanqE8R1krG6V9W13cJ50yrqcsVo +ucoeJ7OsadEO/0r4YYaXdoMCiUprTqbLHRIbmesNRuTkWJZcGF4WHwNEWFlMiDv7V cOX+NXcfXAB8TL+niHinGc5huEX+FnSVX89Jlvock4vuc54MDerKLyeQxlPSplwOFB N6fGJaqAHupHho1yyqlmwZqx+xRY2NkM3BM1zTh8UFFWe8KdmkWU2iYgbibZ3yPwmX om419IAXnIh0hH6Nq1tCvUHRsdq/OvvC60e6GbktI11Ny1+1hSiprEMCd0UVRLRt31 ukA0TQq82HJYw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 08/12] net: stmmac: Add glue layer for StarFive JH7100 SoC Date: Sat, 11 Feb 2023 05:18:17 +0200 Message-Id: <20230211031821.976408-9-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Emil Renner Berthing This adds a glue layer for the Synopsys DesignWare MAC IP core on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing [drop references to JH7110, update JH7100 compatible string] Signed-off-by: Cristian Ciocaltea --- MAINTAINERS | 1 + drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-starfive.c | 155 ++++++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index d48468b81b94..defedaff6041 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19820,6 +19820,7 @@ STARFIVE DWMAC GLUE LAYER M: Emil Renner Berthing S: Maintained F: Documentation/devicetree/bindings/net/starfive,jh7100-dwmac.yaml +F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c STARFIVE JH7100 CLOCK DRIVERS M: Emil Renner Berthing diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index f77511fe4e87..2c81aa594291 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -165,6 +165,18 @@ config DWMAC_SOCFPGA for the stmmac device driver. This driver is used for arria5 and cyclone5 FPGA SoCs. +config DWMAC_STARFIVE + tristate "StarFive DWMAC support" + default m if SOC_STARFIVE + depends on SOC_STARFIVE || COMPILE_TEST + select MFD_SYSCON + help + Support for ethernet controller on StarFive SOCs. + + This selects StarFive SoC glue layer support for the stmmac device + driver. This driver is used for the JH71x0 series GMAC ethernet + controller. + config DWMAC_STI tristate "STi GMAC support" default ARCH_STI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 057e4bab5c08..8738fdbb4b2d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o +obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c new file mode 100644 index 000000000000..d4c81f1a5482 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dwmac-starfive.c - DWMAC glue layer for StarFive JH7100 SoC + * + * Copyright (C) 2021 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define JH7100_SYSMAIN_REGISTER28 0x70 +/* The value below is not a typo, just really bad naming by StarFive ¯\_(ツ)_/¯ */ +#define JH7100_SYSMAIN_REGISTER49 0xc8 + +struct dwmac_starfive { + struct device *dev; + struct clk *gtxc; +}; + +static int dwmac_starfive_jh7100_syscon_init(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *sysmain; + u32 gtxclk_dlychain; + int ret; + + sysmain = syscon_regmap_lookup_by_phandle(np, "starfive,syscon"); + if (IS_ERR(sysmain)) + return dev_err_probe(dev, PTR_ERR(sysmain), + "error getting sysmain registers\n"); + + /* Choose RGMII interface to the phy. + * TODO: support other interfaces once we know the meaning of other + * values in the register + */ + ret = regmap_update_bits(sysmain, JH7100_SYSMAIN_REGISTER28, 0x7, 1); + if (ret) + return dev_err_probe(dev, ret, "error selecting gmac interface\n"); + + if (!of_property_read_u32(np, "starfive,gtxclk-dlychain", >xclk_dlychain)) { + ret = regmap_write(sysmain, JH7100_SYSMAIN_REGISTER49, gtxclk_dlychain); + if (ret) + return dev_err_probe(dev, ret, "error selecting gtxclk delay chain\n"); + } + + return 0; +} + +static void dwmac_starfive_fix_mac_speed(void *data, unsigned int speed) +{ + struct dwmac_starfive *dwmac = data; + unsigned long rate; + int ret; + + switch (speed) { + case SPEED_1000: + rate = 125000000; + break; + case SPEED_100: + rate = 25000000; + break; + case SPEED_10: + rate = 2500000; + break; + default: + dev_warn(dwmac->dev, "unsupported link speed %u\n", speed); + return; + } + + ret = clk_set_rate(dwmac->gtxc, rate); + if (ret) + dev_err(dwmac->dev, "error setting gtx clock rate: %d\n", ret); +} + +static int dwmac_starfive_probe(struct platform_device *pdev) +{ + struct stmmac_resources stmmac_res; + struct plat_stmmacenet_data *plat; + struct dwmac_starfive *dwmac; + struct clk *txclk; + int (*syscon_init)(struct device *dev); + int ret; + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + syscon_init = of_device_get_match_data(&pdev->dev); + if (syscon_init) { + ret = syscon_init(&pdev->dev); + if (ret) + return ret; + } + + dwmac->gtxc = devm_clk_get_enabled(&pdev->dev, "gtxc"); + if (IS_ERR(dwmac->gtxc)) + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->gtxc), + "error getting/enabling gtxc clock\n"); + + txclk = devm_clk_get_enabled(&pdev->dev, "tx"); + if (IS_ERR(txclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(txclk), + "error getting/enabling tx clock\n"); + + plat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat), + "dt configuration failed\n"); + + dwmac->dev = &pdev->dev; + plat->bsp_priv = dwmac; + plat->fix_mac_speed = dwmac_starfive_fix_mac_speed; + + ret = stmmac_dvr_probe(&pdev->dev, plat, &stmmac_res); + if (ret) { + stmmac_remove_config_dt(pdev, plat); + return ret; + } + + return 0; +} + +static const struct of_device_id dwmac_starfive_match[] = { + { + .compatible = "starfive,jh7100-dwmac", + .data = dwmac_starfive_jh7100_syscon_init, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dwmac_starfive_match); + +static struct platform_driver dwmac_starfive_driver = { + .probe = dwmac_starfive_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "dwmac-starfive", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = dwmac_starfive_match, + }, +}; +module_platform_driver(dwmac_starfive_driver); + +MODULE_AUTHOR("Emil Renner Berthing "); +MODULE_DESCRIPTION("StarFive DWMAC Glue Layer"); +MODULE_LICENSE("GPL"); From patchwork Sat Feb 11 03:18:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 653048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4B8EC636D4 for ; Sat, 11 Feb 2023 03:19:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229892AbjBKDTy (ORCPT ); Fri, 10 Feb 2023 22:19:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbjBKDT2 (ORCPT ); Fri, 10 Feb 2023 22:19:28 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E09A885B2F; Fri, 10 Feb 2023 19:19:02 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 80E466602127; Sat, 11 Feb 2023 03:19:01 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085541; bh=XW8rElFUTfgsJr1jtp6+bs1URQt5kqLzyalOrXtwnI0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QRSffU9SmuyvwYAm+UPE3h0oUhI+XYMgdzYG7GG38kA0e0174udJj1lzuUqTkTAW5 jJqKpWZ512dZgilIhNYQiB72no9UdbhJKRDCSU+ckWSBhW0NyvxAjkvC/8C0qyxK8e LFdZngHPm/fTyHwN8rONF8yB2RvwxPnTtwxTtIX0QoVsGCCr0dbtGF72hVIEcMJBlg 83PRBJ822Q2NEowQn1EwN4+L4YRQG/ZPxscIT5XhGFC3xtO28HnnVxnIF++/evL3/Q lh9cxBQYChoB2YQUfa+g1a6o/IwTo8CgvVaThXXaQszH7k4cp8oHKUD7aRoofocVQi egZmlE6B9+bnw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 10/12] riscv: dts: starfive: jh7100: Add ccache DT node Date: Sat, 11 Feb 2023 05:18:19 +0200 Message-Id: <20230211031821.976408-11-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Provide a DT node for the Sifive Composable Cache controller found on the StarFive JH7100 SoC. Note this is also used to support non-coherent DMA. Signed-off-by: Cristian Ciocaltea --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 7109e70fdab8..88f91bc5753b 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -32,6 +32,7 @@ U74_0: cpu@0 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; tlb-split; @@ -57,6 +58,7 @@ U74_1: cpu@1 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; tlb-split; @@ -116,6 +118,20 @@ soc { ranges; dma-noncoherent; + ccache: cache-controller@2010000 { + compatible = "starfive,jh7100-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>, + <0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + interrupts = <128>, <130>, <131>, <129>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + uncached-offset = <0xf 0x80000000>; + }; + clint: clint@2000000 { compatible = "starfive,jh7100-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; From patchwork Sat Feb 11 03:18:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 653047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0515C636D3 for ; Sat, 11 Feb 2023 03:20:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229772AbjBKDUR (ORCPT ); Fri, 10 Feb 2023 22:20:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229942AbjBKDTm (ORCPT ); Fri, 10 Feb 2023 22:19:42 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36031BDE5; Fri, 10 Feb 2023 19:19:09 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id ADB21660211A; Sat, 11 Feb 2023 03:19:07 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085547; bh=FVwCMHp81rng2JtkEJwcV2RSVh1OgfTEUNvp1icmEos=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dexWFXzTRq4fY6EDM50+F7V73z2VMXWhD7QBI80JWZJcfL9WLO95pS5knaTIet4Bn LHRer0o/Sa4OYjCRDAaJxSohSsPgyPOIQ7IrQd7CRqilfOlmiSyiLDLznR97+Lvvze RdFxvm8ZhJlP6GtGQ4BuqXjan1XgBR03B9Ab0HfLNWH1MMAEC7aacNMc639Jd69SU7 cgseOHhJHk8yzf9GuiMTytsJdiK265EvK5oNkiJW3iYeiIei/h+OAD7jIZU8PWwkFh UXNcMN+O4qHGI6Xmxf7Dn1rhHru20cxjOBkWQLJ7kSF2LNPGz4VXwuaOoLipGJI79J 6oPlNU5ku7JTw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 12/12] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac Date: Sat, 11 Feb 2023 05:18:21 +0200 Message-Id: <20230211031821.976408-13-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinmux configuration for the DWMAC found on the JH7100 based boards and enable the gmac DT node. Signed-off-by: Cristian Ciocaltea --- .../boot/dts/starfive/jh7100-common.dtsi | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..9927e7462e9f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -41,7 +41,85 @@ led-ack { }; }; +&gmac { + starfive,gtxclk-dlychain = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins>; + status = "okay"; +}; + &gpio { + gmac_pins: gmac-0 { + gtxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <35>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + miitxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + tx-pins { + pins = , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + rxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <6>; + }; + rxer-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + rx-pins { + pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux =